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    Searched refs:mmGB_TILE_MODE0 (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vi.c 503 {mmGB_TILE_MODE0},
596 case mmGB_TILE_MODE0:
628 idx = (reg_offset - mmGB_TILE_MODE0);
amdgpu_cik.c 997 {mmGB_TILE_MODE0},
1091 case mmGB_TILE_MODE0:
1123 idx = (reg_offset - mmGB_TILE_MODE0);
amdgpu_gfx_v6_0.c 646 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
852 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1076 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1300 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
amdgpu_gfx_v8_0.c 2280 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2470 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2659 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
2862 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3064 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3235 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
3412 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);
amdgpu_si.c 1071 case mmGB_TILE_MODE0:
1103 idx = (reg_offset - mmGB_TILE_MODE0);
amdgpu_gfx_v7_0.c 1224 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1407 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1577 WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 660 #define mmGB_TILE_MODE0 0x2644
gfx_7_0_d.h 694 #define mmGB_TILE_MODE0 0x2644
gfx_7_2_d.h 707 #define mmGB_TILE_MODE0 0x2644
gfx_8_0_d.h 779 #define mmGB_TILE_MODE0 0x2644
gfx_8_1_d.h 779 #define mmGB_TILE_MODE0 0x2644
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 944 #define mmGB_TILE_MODE0 0x0644
gc_9_1_offset.h 914 #define mmGB_TILE_MODE0 0x0644
gc_9_2_1_offset.h 880 #define mmGB_TILE_MODE0 0x0644
gc_10_1_0_offset.h 2858 #define mmGB_TILE_MODE0 0x13e4
    [all...]

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