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Searched refs:mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_7_0_offset.h	`74 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_offset.h	`164 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x03ed`
vcn_2_0_0_offset.h	`828 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x05ad`
vcn_2_5_offset.h	`873 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 0x0469`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c	`421 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 487 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 495 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 1200 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),`
amdgpu_vcn_v2_0.c	`337 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 404 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 412 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);`
amdgpu_uvd_v7_0.c	`691 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 834 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),`
amdgpu_vcn_v1_0.c	`325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 395 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,`

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