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    Searched refs:pll_id (Results 1 - 25 of 26) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_pll.c 279 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
280 pll_in_use |= (1 << test_amdgpu_crtc->pll_id);
307 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
308 return test_amdgpu_crtc->pll_id;
345 if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)
346 return test_amdgpu_crtc->pll_id;
353 (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID))
354 return test_amdgpu_crtc->pll_id;
amdgpu_atombios_crtc.c 249 int pll_id,
272 pll_id == adev->mode_info.crtcs[i]->pll_id) {
286 switch (pll_id) {
570 static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
573 if (pll_id < ATOM_EXT_PLL1)
584 int pll_id,
619 args.v1.ucPpll = pll_id;
629 args.v2.ucPpll = pll_id;
639 args.v3.ucPpll = pll_id;
    [all...]
atombios_crtc.h 46 int pll_id,
amdgpu_dce_virtual.c 178 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
243 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
amdgpu_dce_v11_0.c 2667 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2675 switch (amdgpu_crtc->pll_id) {
2680 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2690 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2697 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2726 amdgpu_crtc->pll_id,
2770 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2772 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2845 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID
    [all...]
amdgpu_atombios_encoders.c 779 int pll_id = 0; local in function:amdgpu_atombios_encoder_setup_dig_transmitter
810 pll_id = amdgpu_crtc->pll_id;
978 args.v3.acConfig.ucRefClkSource = pll_id;
1040 args.v4.acConfig.ucRefClkSource = pll_id;
1105 args.v5.asConfig.ucPhyClkSrcId = pll_id;
amdgpu_dce_v8_0.c 2489 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2497 switch (amdgpu_crtc->pll_id) {
2501 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2509 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2516 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2570 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc);
2572 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2625 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
amdgpu_mode.h 404 u32 pll_id; member in struct:amdgpu_crtc
amdgpu_dce_v10_0.c 2588 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2596 switch (amdgpu_crtc->pll_id) {
2601 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2608 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2662 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2664 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2737 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
amdgpu_dce_v6_0.c 2478 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2486 switch (amdgpu_crtc->pll_id) {
2490 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2497 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2552 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2554 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2607 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
bios_parser_types.h 146 enum clock_source_id pll_id; /* needed for DCE 4.0 */ member in struct:bp_transmitter_control
212 enum clock_source_id pll_id; /* Clock Source Id */ member in struct:bp_pixel_clock_parameters
260 enum clock_source_id pll_id; /* Clock Source Id */ member in struct:bp_set_dce_clock_parameters
287 enum clock_source_id pll_id; member in struct:bp_spread_spectrum_parameters
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce112/
amdgpu_dce112_clk_mgr.c 92 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
111 (dce_clk_params.pll_id ==
146 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
183 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
187 (dce_clk_params.pll_id ==
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/
amdgpu_command_table.c 527 uint32_t pll_id; local in function:transmitter_control_v3
549 if (!cmd->clock_source_id_to_atom(cntl->pll_id, &pll_id))
645 params.acConfig.ucRefClkSource = (uint8_t)pll_id;
681 if (!cmd->clock_source_id_to_ref_clk_src(cntl->pll_id, &ref_clk_src_id))
795 cmd->clock_source_id_to_atom_phy_clk_src_id(cntl->pll_id);
954 if (CLOCK_SOURCE_ID_PLL1 == bp_params->pll_id)
956 else if (CLOCK_SOURCE_ID_PLL2 == bp_params->pll_id)
1023 uint32_t pll_id; local in function:set_pixel_clock_v5
1027 if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id
1080 uint32_t pll_id; local in function:set_pixel_clock_v6
1158 uint32_t pll_id; local in function:set_pixel_clock_v7
    [all...]
amdgpu_command_table2.c 365 uint32_t pll_id; local in function:set_pixel_clock_v7
369 if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id)
392 clk.pll_id = (uint8_t) pll_id;
412 pll_id, bp_params->color_depth);
808 if (!cmd->clock_source_id_to_atom(bp_params->pll_id, &atom_pll_id) ||
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_atombios_crtc.c 401 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
406 switch (pll_id) {
422 switch (pll_id) {
451 int pll_id,
474 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
489 switch (pll_id) {
508 switch (pll_id) {
530 args.v1.ucPpll = pll_id;
535 atombios_disable_ss(rdev, pll_id);
    [all...]
radeon_atombios_encoders.c 1032 int pll_id = 0; local in function:atombios_dig_transmitter_setup2
1064 pll_id = radeon_crtc->pll_id;
1232 args.v3.acConfig.ucRefClkSource = pll_id;
1294 args.v4.acConfig.ucRefClkSource = pll_id;
1359 args.v5.asConfig.ucPhyClkSrcId = pll_id;
radeon_mode.h 353 int pll_id; member in struct:radeon_crtc
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_clock_source.c 640 bp_ss_params.pll_id = clk_src->base.id;
742 bp_params.pll_id = clk_src->base.id;
865 bp_pc_params.pll_id = clock_source->id;
939 bp_pc_params.pll_id = clock_source->id;
979 bp_pixel_clock_params.pll_id = clk_src->id;
amdgpu_dce_link_encoder.c 936 cntl.pll_id = clock_source;
972 cntl.pll_id = clock_source;
1010 cntl.pll_id = clock_source;
1049 cntl.pll_id = clock_source;
dce_clk_mgr.c 268 pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
310 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
327 (dce_clk_params.pll_id ==
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/
amdgpu_dce_clk_mgr.c 251 pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_link_encoder.c 930 cntl.pll_id = clock_source;
972 cntl.pll_id = clock_source;
1011 cntl.pll_id = clock_source;
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpll_mgr.c 854 enum intel_dpll_id pll_id; local in function:hsw_ddi_dp_get_dpll
859 pll_id = DPLL_ID_LCPLL_810;
862 pll_id = DPLL_ID_LCPLL_1350;
865 pll_id = DPLL_ID_LCPLL_2700;
872 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
intel_ddi.c 1563 enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, local in function:icl_ddi_clock_get
1566 if (pll_id == DPLL_ID_ICL_TBTPLL)
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
atomfirmware.h 2681 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 member in struct:set_pixel_clock_parameter_v1_7

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