| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_pllgt215.c | 47 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq;
49 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq;
55 N = tmp / info->refclk;
56 fN = tmp % info->refclk;
59 if (fN >= info->refclk / 2)
62 if (fN < info->refclk / 2)
64 fN = tmp - (N * info->refclk);
72 err = abs(freq - (info->refclk * N / M / *P));
80 *pfN = ((fN << 13) + info->refclk / 2) / info->refclk;
[all...] |
| nouveau_nvkm_subdev_clk_nv04.c | 43 pv->refclk = info->refclk;
|
| nouveau_nvkm_subdev_clk_pllnv04.c | 53 int crystal = info->refclk;
154 int crystal = info->refclk;
|
| nouveau_nvkm_subdev_clk_mcp77.c | 182 pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href);
183 if (!pll.refclk)
|
| nouveau_nvkm_subdev_clk_gf100.c | 266 limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
267 if (!limits.refclk)
|
| nouveau_nvkm_subdev_clk_gk104.c | 279 limits.refclk = read_div(clk, idx, 0x137120, 0x137140);
280 if (!limits.refclk)
|
| nouveau_nvkm_subdev_clk_gt215.c | 71 /* refclk for the 0xe8xx plls is a fixed frequency */
227 * XXX: PLLs with refclk 810MHz? */
264 ret = gt215_clk_info(&clk->base, idx - 0x10, limits.refclk, info);
265 if (ret != limits.refclk)
|
| nouveau_nvkm_subdev_clk_nv50.c | 341 pll.refclk = read_pll_ref(clk, reg);
342 if (!pll.refclk)
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/bios/ |
| pll.h | 22 int refclk; member in struct:nvkm_pll_vals
49 u32 refclk; member in struct:nvbios_pll
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_cdclk.h | 21 u16 refclk; member in struct:intel_cdclk_vals
|
| intel_cdclk.c | 1171 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1172 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1173 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1174 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1175 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1180 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1181 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1182 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1187 { .refclk = 19200, .cdclk = 168000, .divider = 4, .ratio = 35 },
1188 { .refclk = 19200, .cdclk = 336000, .divider = 2, .ratio = 35 }
[all...] |
| vlv_dsi_pll.c | 268 int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; local
316 dsi_clock = (m * refclk) / (p * n);
|
| intel_display.c | 454 /* LVDS 100mhz refclk limits. */
580 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
586 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
597 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
603 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
609 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
615 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
621 int chv_calc_dpll_params(int refclk, struct dpll *clock)
627 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),
637 * Returns whether the given set of divisors are valid for a given refclk wit
1041 int refclk = 100000; local
8839 int refclk = 48000; local
8874 int refclk = 96000; local
8917 int refclk = 96000; local
8951 int refclk = 96000; local
8982 int refclk = 100000; local
9003 int refclk = 100000; local
9064 int refclk = 100000; local
9175 int refclk = 100000; local
10129 int refclk = 120000; local
11901 int refclk = i9xx_pll_refclk(dev, pipe_config); local
[all...] |
| intel_display.h | 589 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
|
| intel_ddi.c | 1278 int refclk; local
1292 refclk = 24;
1294 refclk = 135;
1304 refclk = 135;
1307 refclk = 2700;
1319 return (refclk * n * 100) / (p * r);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bios/ |
| nouveau_nvkm_subdev_bios_pll.c | 333 info->refclk = nvbios_rd32(bios, data + 31);
356 info->refclk = nvbios_rd32(bios, data + 28);
359 info->refclk = nvbios_rd16(bios, data + 9) * 1000;
374 info->refclk = nvbios_rd16(bios, data + 1) * 1000;
392 if (!info->refclk) {
393 info->refclk = device->crystal;
399 info->refclk = 200000;
401 info->refclk = 25000;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_nv04.c | 379 pv.refclk = info.refclk;
|
| /src/sys/dev/pci/ |
| radeonfb.c | 646 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d "
1620 int refclk = 0; local
1626 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff;
1640 if (refclk && refdiv && minpll && maxpll)
1648 refclk = refclk ? refclk : 1432;
1650 refclk = refclk ? refclk : 2700
[all...] |
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/allwinner/ |
| sun8i-a83t-cubietruck-plus.dts | 106 refclk-frequency = <19200000>;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_hw.c | 204 pllvals->refclk = pll_lim.refclk;
215 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| nouveau_nvkm_subdev_fb_ramgk104.c | 1050 int refclk, i; local
1068 refclk = next->freq;
1073 fuc->mempll.refclk = ret;
1082 ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1,
1084 fuc->mempll.refclk = ret;
|
| nouveau_nvkm_subdev_fb_ramgf100.c | 220 ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk,
|
