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    Searched refs:smc_state (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_ni_dpm.c 2300 NISLANDS_SMC_SWSTATE *smc_state)
2307 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
2309 smc_state->levels[ps->performance_level_count - 1].bSP =
2396 NISLANDS_SMC_SWSTATE *smc_state)
2411 smc_state->levels[0].aT = cpu_to_be32(a_t);
2415 smc_state->levels[0].aT = cpu_to_be32(0);
2440 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
2442 smc_state->levels[i].aT = cpu_to_be32(a_t);
2448 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
2456 NISLANDS_SMC_SWSTATE *smc_state)
2696 NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL); local in function:ni_upload_sw_state
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rv770_dpm.h 233 RV770_SMC_SWSTATE *smc_state);
236 RV770_SMC_SWSTATE *smc_state);
radeon_rv770_dpm.c 262 RV770_SMC_SWSTATE *smc_state)
294 smc_state->levels[i].aT = cpu_to_be32(a_t);
300 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT =
308 RV770_SMC_SWSTATE *smc_state)
314 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
316 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP =
680 RV770_SMC_SWSTATE *smc_state)
686 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
690 &smc_state->levels[0],
697 &smc_state->levels[1]
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radeon_cypress_dpm.c 770 RV770_SMC_SWSTATE *smc_state)
777 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
781 &smc_state->levels[0],
788 &smc_state->levels[1],
795 &smc_state->levels[2],
800 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
801 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
802 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
805 smc_state->levels[0].ACIndex = 2;
806 smc_state->levels[1].ACIndex = 3
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radeon_si_dpm.c 2294 SISLANDS_SMC_SWSTATE *smc_state)
2317 if (smc_state->levelCount != state->performance_level_count)
2322 smc_state->levels[0].dpm2.MaxPS = 0;
2323 smc_state->levels[0].dpm2.NearTDPDec = 0;
2324 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2325 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2326 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2376 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2377 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2378 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC
5283 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; local in function:si_upload_sw_state
5306 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; local in function:si_upload_ulv_state
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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dpm.c 2392 SISLANDS_SMC_SWSTATE *smc_state)
2415 if (smc_state->levelCount != state->performance_level_count)
2420 smc_state->levels[0].dpm2.MaxPS = 0;
2421 smc_state->levels[0].dpm2.NearTDPDec = 0;
2422 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2423 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2424 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2473 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2474 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2475 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC
5747 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; local in function:si_upload_sw_state
5768 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; local in function:si_upload_ulv_state
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