| /src/games/warp/ |
| score.c | 88 "last wave over.\r\n\n");
152 totalscore = smarts = cumsmarts = wave = 0;
162 wave = atoi(spbuf+36);
180 printf("\r\nSaved game: SCORE DIFF CUMDIFF ENTERPRISES BASES WAVE");
182 totalscore,smarts,cumsmarts,numents,numbases,wave);
404 wave++;
405 snprintf(spbuf, sizeof(spbuf), "Wave = %d, Difficulty = %d, cumulative difficulty = %d",
406 wave, smarts, cumsmarts);
656 totalscore = cumsmarts = wave = 0;
682 logname, totalscore, smarts, cumsmarts, numents, numbases, wave,
[all...] |
| warp.c | 333 numents, numbases, wave,
|
| warp.h | 406 EXT int wave; variable in typeref:typename:EXT int
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx.h | 198 uint32_t wave, uint32_t *dst, int *no_fields);
200 uint32_t wave, uint32_t thread, uint32_t start,
203 uint32_t wave, uint32_t start, uint32_t size,
|
| amdgpu_debugfs.c | 681 /** amdgpu_debugfs_wave_read - Read WAVE STATUS data
688 * The offset being sought changes which wave that the status data
695 * Bits 31..36: WAVE ID selector
699 * Followed by WAVE STATUS registers relevant to the GFX IP version
708 uint32_t offset, se, sh, cu, wave, simd, data[32]; local in function:amdgpu_debugfs_wave_read
718 wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
731 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
759 /** amdgpu_debugfs_gpr_read - Read wave gprs
766 * The offset being sought changes which wave that the status data
773 * Bits 36..43: WAVE ID selecto
787 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; local in function:amdgpu_debugfs_gpr_read
[all...] |
| amdgpu_gfx_v6_0.c | 2991 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2994 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3002 uint32_t wave, uint32_t thread,
3006 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3016 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3018 /* type 0 wave data */
3020 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3021 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3022 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3023 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO)
[all...] |
| amdgpu_gfx_v7_0.c | 2305 /* Currently, there is a high possibility to get wave ID mismatch
2307 * different wave IDs than the GDS expects. This situation happens
2309 * The wave IDs generated by ME are also wrong after suspend/resume.
2312 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
4149 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
4152 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4160 uint32_t wave, uint32_t thread,
4164 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4174 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4176 /* type 0 wave data *
[all...] |
| amdgpu_gfx_v10_0.c | 1110 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
1113 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1118 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
1123 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1131 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1138 /* type 2 wave data */
1140 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
1141 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
1142 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
1143 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO)
[all...] |
| amdgpu_gfx_v8_0.c | 5213 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
5216 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5224 uint32_t wave, uint32_t thread,
5228 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
5238 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
5240 /* type 0 wave data */
5242 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
5243 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
5244 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
5245 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO)
[all...] |
| amdgpu_gfx_v9_0.c | 1924 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1927 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1935 uint32_t wave, uint32_t thread,
1939 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1949 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1951 /* type 1 wave data */
1953 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1954 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1955 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1956 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO)
[all...] |
| /src/sys/arch/luna68k/dev/xplx/ |
| xplx.asm | 1518 ; output PAM wave = normal 5 + antinoise 1
1629 ; output PAM wave = 4
1722 ; output PAM wave = normal 5 + antinoise 1
1854 ; output PAM wave = 2
|
