| /src/sys/arch/powerpc/include/ |
| spr.h | 143 #define SPR_SPRG7 0x117 /* E4.. SPR General 7 */
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| instr.h | 327 #define OPC31_LHZX 0x117
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| /src/sys/arch/hpcmips/dev/ |
| ite8181reg.h | 98 #define ITE8181_GUI_CC1R3 0x117
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| /src/lib/libform/ |
| form.h | 113 #define REQ_BEG_FIELD (KEY_MAX + 0x117) /* go to the beginning of
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/fuc/ |
| macros.fuc | 32 #define GM107 0x117
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 200 #define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
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| smu7_ppsmc.h | 197 #define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
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| tonga_ppsmc.h | 221 #define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
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| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 364 #define BTN_TASK 0x117
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| /src/sys/external/bsd/drm2/dist/include/drm/ |
| drm_dp_helper.h | 521 #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ |
| bif_5_0_d.h | 425 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x117
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| /src/sys/arch/powerpc/powerpc/ |
| db_disasm.c | 443 { 0x117, "sprg7" },
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| /src/sys/dev/isa/ |
| aria.c | 348 aria_do_kludge(iot, ioh, ioh1, 0x117, 0x00, 0x88, 0x00);
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| /src/sys/dev/qbus/ |
| qfont.c | 97 ,0x00 ,0x00 ,0x112 ,0x113 ,0x114 ,0x115 ,0x116 ,0x117 /* 136 */
132 ,0x00 ,0x00 ,0x112 ,0x113 ,0x114 ,0x115 ,0x116 ,0x117 /* 136 */
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 407 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
1607 SC_GRP3_DYN_SCLK_BUSY = 0x117,
2564 SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117,
3569 #define SQ_DPP_ROW_SR7 0x117
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| gfx_8_1_enum.h | 407 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117,
1625 SC_GRP3_DYN_SCLK_BUSY = 0x117,
2582 SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117,
3587 #define SQ_DPP_ROW_SR7 0x117
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| gfx_7_2_enum.h | 1422 SC_GRP3_DYN_SCLK_BUSY = 0x117,
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1180 #define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117
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| gmc_8_1_d.h | 1284 #define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117
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| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1317 x117: sh1add %r26,%r26,%r1 ! sh2add %r1,%r26,%r1 ! b e_t0 ! sh3add %r1,%r1,%r1 label
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_base.c | 3186 case 0x117: device->chip = &nv117_chipset; break;
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| /src/sys/arch/sparc64/sparc64/ |
| locore.s | 817 STRAP(0x110); STRAP(0x111); STRAP(0x112); STRAP(0x113); STRAP(0x114); STRAP(0x115); STRAP(0x116); STRAP(0x117)
1028 STRAP(0x110); STRAP(0x111); STRAP(0x112); STRAP(0x113); STRAP(0x114); STRAP(0x115); STRAP(0x116); STRAP(0x117)
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/ |
| dce_8_0_d.h | 1072 #define mmSYMCLKG_CLOCK_ENABLE 0x117
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| dce_11_0_d.h | 1036 #define mmSYMCLKG_CLOCK_ENABLE 0x117
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