| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| omap4-kc1.dts | 54 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
|
| omap4-duovero-parlor.dts | 79 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
|
| omap4-var-om44customboard.dtsi | 67 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */
|
| omap4-panda-common.dtsi | 339 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
|
| omap4-sdp.dts | 310 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
|
| /src/sys/arch/amiga/amiga/ |
| cc_registers.h | 173 #define R_SPR1PTL 0x126
|
| /src/lib/libform/ |
| form.h | 136 #define REQ_CLR_EOL (KEY_MAX + 0x126) /* clear to the end of the line */
|
| /src/sys/arch/powerpc/include/ibm4xx/ |
| dcr4xx.h | 127 #define DCR_DMA0_POL 0x126 /* DMA Polarity Configuration Register */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 215 #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)
|
| smu7_ppsmc.h | 212 #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint32_t) 0x126)
|
| tonga_ppsmc.h | 239 #define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint16_t) 0x126)
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 373 #define BTN_BASE 0x126
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ |
| bif_5_0_d.h | 439 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2 0x126
|
| /src/sys/arch/powerpc/powerpc/ |
| db_disasm.c | 581 { 0x126, "dma0_pol" },
|
| /src/sys/dev/qbus/ |
| qfont.c | 99 ,0x125 ,0x126 ,0x127 ,0x128 ,0x129 ,0x12a ,0x12b ,0x12c /* 152 */
134 ,0x125 ,0x126 ,0x127 ,0x128 ,0x129 ,0x12a ,0x12b ,0x12c /* 152 */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1195 #define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126
|
| gmc_8_1_d.h | 1299 #define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 422 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
1622 SC_PA3_SC_DATA_FIFO_RD = 0x126,
3583 #define SQ_DPP_ROW_RR6 0x126
|
| gfx_8_1_enum.h | 422 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126,
1640 SC_PA3_SC_DATA_FIFO_RD = 0x126,
3601 #define SQ_DPP_ROW_RR6 0x126
|
| gfx_7_2_enum.h | 1437 SC_PA3_SC_DATA_FIFO_RD = 0x126,
|
| /src/sys/lib/libkern/arch/hppa/ |
| milli.S | 1335 x126: zdep %r26,25,26,%r1 ! sub %r1,%r26,%r1 ! b e_shift ! sh1add %r1,%r29,%r29 label
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_base.c | 3190 case 0x126: device->chip = &nv126_chipset; break;
|
| /src/sys/arch/sparc64/sparc64/ |
| locore.s | 819 STRAP(0x120); STRAP(0x121); STRAP(0x122); STRAP(0x123); STRAP(0x124); STRAP(0x125); STRAP(0x126); STRAP(0x127)
1030 STRAP(0x120); STRAP(0x121); STRAP(0x122); STRAP(0x123); STRAP(0x124); STRAP(0x125); STRAP(0x126); STRAP(0x127)
|
| /src/sys/dev/pci/cxgb/ |
| cxgb_regs.h | 4548 #define A_TP_RX_TRC_KEY3 0x126
|
