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  /src/sys/arch/arm/nvidia/
tegra_pciereg.h 40 0x134 + ((i) - 6) * 0x04)
tegra124_xusbpadreg.h 109 #define XUSB_PADCTL_USB3_PAD_MUX_REG 0x134
tegra210_pinmux.c 138 TEGRA_PIN("dap2_fs_paa0", 0x134, "i2s2", "rsvd1", "rsvd2", "rsvd3"),
tegra_hdmireg.h 141 #define HDMI_NV_PDISP_HDMI_EMU1_REG 0x134
  /src/sys/arch/mac68k/include/
psc.h 85 #define PSC_LEV3_IER 0x134 /* level 3 interrupt enable register */
  /src/sys/dev/pcmcia/
if_cnwreg.h 85 #define CNW_EREG_TSERW 0x134
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 156 #define CM_PLLTCNT0 0x134
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 115 #define I2O_OPC 0x134
  /src/sys/arch/sh3/include/
pcicreg.h 75 #define SH4_PCIAINTM (SH4_PCIC+0x134) /* 32bit */
  /src/sys/dev/eisa/
bha_eisa.c 86 port = 0x134;
  /src/sys/arch/amiga/amiga/
cc_registers.h 180 #define R_SPR5PTH 0x134
  /src/sys/arch/arm/footbridge/
dc21285reg.h 191 #define I2O_OUTBOUND_POST_COUNT 0x134
  /src/sys/arch/arm/sunxi/
sun5i_a13_ccu.c 60 #define CSI_CFG_REG 0x134
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 93 #define GPMC_CONFIG6_4 0x134
  /src/sys/dev/pci/
cs4281reg.h 99 #define CS4281_DCC2 0x134 /* DMA Engine 2 Current Count Register */
if_stgereg.h 440 #define STGE_EtherStatsOctets 0x134
  /src/sys/dev/sbus/
p9100reg.h 139 #define VID_SRADDR 0x134 /* screen repaint address */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 205 0x134 MODE_NITRO /* i2s_bitclk */
  /src/sys/dev/ic/
ahcisatareg.h 271 #define AHCI_P_SACT(p) (0x134 + AHCI_P_OFFSET(p)) /* Serial ATA active */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
omap4-var-om44customboard.dtsi 75 OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
vf610-pinfunc.h 499 #define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0
500 #define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0
501 #define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0
502 #define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0
503 #define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2
504 #define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/hisilicon/
hikey-pinctrl.dtsi 67 0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
77 0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
344 0x134 0x0 /* SDIO_CLK (IOCFG077) */
352 0x134 0x0 /* SDIO_CLK (IOCFG077) */
  /src/lib/libform/
form.h 160 #define REQ_SCR_HBLINE (KEY_MAX + 0x134) /* horizontal scroll
  /src/sys/arch/arm/imx/
imx23_digctlreg.h 254 #define HW_DIGCTL_OCRAM_STATUS2_SET 0x134
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mn-pinfunc.h 379 #define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
380 #define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0
381 #define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6
382 #define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3
383 #define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
384 #define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0

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