1 /* $NetBSD: psc.h,v 1.8 2019/07/23 15:19:07 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym (at) azeotrope.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 #include <sys/bus.h> /* XXX for bus_addr_t */ 29 30 /* 31 * Some register definitions for the PSC, present only on the 32 * Centris/Quadra 660av and the Quadra 840av. 33 */ 34 35 extern volatile u_int8_t *PSCBase; 36 37 #define psc_reg1(r) (*((volatile u_int8_t *)(PSCBase+r))) 38 #define psc_reg2(r) (*((volatile u_int16_t *)(PSCBase+r))) 39 #define psc_reg4(r) (*((volatile u_int32_t *)(PSCBase+r))) 40 41 void psc_init(void); 42 43 int add_psc_lev3_intr(void (*)(void *), void *); 44 int add_psc_lev4_intr(int, int (*)(void *), void *); 45 int add_psc_lev5_intr(int, void (*)(void *), void *); 46 int add_psc_lev6_intr(int, void (*)(void *), void *); 47 48 int remove_psc_lev3_intr(void); 49 int remove_psc_lev4_intr(int); 50 int remove_psc_lev5_intr(int); 51 int remove_psc_lev6_intr(int); 52 53 int start_psc_dma(int, int *, bus_addr_t, uint32_t, int); 54 int pause_psc_dma(int); 55 int wait_psc_dma(int, int, uint32_t *); 56 int stop_psc_dma(int, int, uint32_t *, int); 57 58 /* 59 * Reading an interrupt status register returns a mask of the 60 * currently interrupting devices (one bit per device). Reading an 61 * interrupt enable register returns a mask of the currently enabled 62 * devices. Writing an interrupt enable register with the MSB set 63 * enables the interrupts in the lower 4 bits, while writing with the 64 * MSB clear disables the corresponding interrupts. 65 * e.g. write 0x81 to enable device 0, write 0x86 to enable devices 1 66 * and 2, write 0x02 to disable device 1. 67 * 68 * Level 3 device 0 is MACE 69 * Level 4 device 0 is 3210 DSP? 70 * Level 4 device 1 is SCC channel A (modem port) 71 * Level 4 device 2 is SCC channel B (printer port) 72 * Level 4 device 3 is MACE DMA completion 73 * Level 5 device 0 is 3210 DSP? 74 * Level 5 device 1 is 3210 DSP? 75 * Level 6 device 0 is ? 76 * Level 6 device 1 is ? 77 * Level 6 device 2 is ? 78 */ 79 80 /* PSC interrupt registers */ 81 #define PSC_ISR_BASE 0x100 /* ISR is BASE + 0x10 * level */ 82 #define PSC_IER_BASE 0x104 /* IER is BASE + 0x10 * level */ 83 84 #define PSC_LEV3_ISR 0x130 /* level 3 interrupt status register */ 85 #define PSC_LEV3_IER 0x134 /* level 3 interrupt enable register */ 86 #define PSCINTR_ENET 0 /* Ethernet interrupt */ 87 88 #define PSC_LEV4_ISR 0x140 /* level 4 interrupt status register */ 89 #define PSC_LEV4_IER 0x144 /* level 4 interrupt enable register */ 90 #define PSCINTR_SCCA 1 /* SCC channel A interrupt */ 91 #define PSCINTR_SCCB 2 /* SCC channel B interrupt */ 92 #define PSCINTR_ENET_DMA 3 /* Ethernet DMA completion interrupt */ 93 94 #define PSC_LEV5_ISR 0x150 /* level 5 interrupt status register */ 95 #define PSC_LEV5_IER 0x154 /* level 5 interrupt enable register */ 96 97 #define PSC_LEV6_ISR 0x160 /* level 6 interrupt status register */ 98 #define PSC_LEV6_IER 0x164 /* level 6 interrupt enable register */ 99 100 /* PSC DMA channel control registers */ 101 #define PSC_CTLBASE 0xc00 102 103 #define PSC_SCSI_CTL 0xc00 /* SCSI control/status */ 104 #define PSC_ENETRD_CTL 0xc10 /* MACE receive DMA channel control/status */ 105 #define PSC_ENETWR_CTL 0xc20 /* MACE transmit DMA channel control/status */ 106 #define PSC_FDC_CTL 0xc30 /* Floppy disk */ 107 #define PSC_SCCA_CTL 0xc40 /* SCC channel A */ 108 #define PSC_SCCB_CTL 0xc50 /* SCC channel B */ 109 #define PSC_SCCATX_CTL 0xc60 /* SCC channel A transmit */ 110 111 /* PSC DMA channels */ 112 #define PSC_ADDRBASE 0x1000 113 #define PSC_LENBASE 0x1004 114 #define PSC_CMDBASE 0x1008 115 116 #define PSC_SCSI_ADDR 0x1000 /* SCSI DMA address register */ 117 #define PSC_SCSI_LEN 0x1004 /* SCSI DMA buffer count */ 118 #define PSC_SCSI_CMD 0x1008 /* SCSI DMA command register */ 119 #define PSC_ENETRD_ADDR 0x1020 /* MACE receive DMA address register */ 120 #define PSC_ENETRD_LEN 0x1024 /* MACE receive DMA buffer count */ 121 #define PSC_ENETRD_CMD 0x1028 /* MACE receive DMA command register */ 122 #define PSC_ENETWR_ADDR 0x1040 /* MACE transmit DMA address register */ 123 #define PSC_ENETWR_LEN 0x1044 /* MACE transmit DMA length */ 124 #define PSC_ENETWR_CMD 0x1048 /* MACE transmit DMA command register */ 125 126 /* 127 * PSC DMA channels are controlled by two sets of registers (see p.29 128 * of the Quadra 840av and Centris 660av Developer Note). Add the 129 * following offsets to get the desired register set. 130 */ 131 #define PSC_SET0 0x00 132 #define PSC_SET1 0x10 133 134 /* 135 * Pseudo channels for the dma control functions 136 */ 137 #define PSC_DMA_CHANNEL_SCSI 0 138 #define PSC_DMA_CHANNEL_ENETRD 1 139 #define PSC_DMA_CHANNEL_ENETWR 2 140 #define PSC_DMA_CHANNEL_FDC 3 141 #define PSC_DMA_CHANNEL_SCCA 4 142 #define PSC_DMA_CHANNEL_SCCB 5 143 #define PSC_DMA_CHANNEL_SCCATX 6 144
Indexes created Mon Sep 22 05:09:51 GMT 2025