| /src/sys/external/isc/libsodium/dist/test/default/ |
| core5.c | 12 0x3e, 0x90, 0x60, 0x52, 0x1e, 0x4b, 0xb3, 0x52
|
| core6.c | 12 0x3e, 0x90, 0x60, 0x52, 0x1e, 0x4b, 0xb3, 0x52
|
| stream4.c | 21 0x52, 0x28, 0xc5, 0x2a, 0x4c, 0x62, 0xcb, 0xd4, 0x4b, 0x66, 0x84, 0x9b,
28 0x48, 0xf5, 0x9f, 0xfd, 0x49, 0x24, 0xca, 0x1c, 0x60, 0x90, 0x2e, 0x52,
|
| box_easy.c | 24 0xeb, 0xeb, 0x0c, 0x7b, 0x52, 0x28, 0xc5, 0x2a, 0x4c, 0x62, 0xcb, 0xd4,
32 0x60, 0x90, 0x2e, 0x52, 0xf0, 0xa0, 0x89, 0xbc, 0x76, 0x89, 0x70, 0x40,
|
| secretbox.c | 22 0x52, 0x28, 0xc5, 0x2a, 0x4c, 0x62, 0xcb, 0xd4, 0x4b, 0x66, 0x84, 0x9b,
29 0x48, 0xf5, 0x9f, 0xfd, 0x49, 0x24, 0xca, 0x1c, 0x60, 0x90, 0x2e, 0x52,
|
| /src/sys/arch/vax/vax/ |
| db_disasm.h | 69 ((x) == 0xfdf6) ? 0x52 : \
|
| /src/sys/dev/podulebus/ |
| powerromreg.h | 38 #define PRID_HCCS_REDSHIFT 0x52 /* HCCS RedShift 16 bit SCSI-1 */
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| zynq-zc770-xm012.dts | 42 reg = <0x52>;
52 reg = <0x52>;
|
| imx6qdl-pico-nymph.dtsi | 22 reg = <0x52>;
|
| zynq-zc770-xm011.dts | 46 reg = <0x52>;
|
| imx27-phytec-phycard-s-som.dtsi | 40 reg = <0x52>;
|
| imx7d-pico-nymph.dts | 61 reg = <0x52>;
|
| zynq-zc770-xm010.dts | 58 reg = <0x52>;
|
| /src/sys/external/bsd/drm2/dist/include/drm/ |
| i915_drm.h | 50 #define INTEL_GMCH_CTRL 0x52
62 #define I830_GMCH_CTRL 0x52
|
| drm_scdc_helper.h | 65 #define SCDC_ERR_DET_1_L 0x52
|
| /src/sys/dev/pci/ |
| pciide_sis_reg.h | 66 #define SIS_MISC 0x52
75 #define SIS_REG_52 0x52
|
| pciide_hpt_reg.h | 68 #define HPT366_CTRL3(chan) (0x52 + ((chan) * 4))
88 #define HPT370_CTRL3(chan) (0x52 + ((chan) * 4))
|
| pciide_acer_reg.h | 58 #define ACER_FCS 0x52
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/ |
| r8a779a0-falcon-csi-dsi.dtsi | 33 reg = <0x52>;
|
| /src/sys/arch/pmax/tc/ |
| dtreg.h | 98 #define DT_ADDR_FIRST 0x52 /* first assignable address */
|
| /src/sys/arch/vax/include/ |
| ka630.h | 131 #define KA630_MAXCOL 0x52
|
| /src/sys/arch/sun3/dev/ |
| am9516.h | 33 #define UDC_ADR_CMR_LOW 0x52 /* channel mode reg, low word */
|
| /src/sys/dev/spi/ |
| spiflash.h | 72 #define SPIFLASH_CMD_ERASE2 0x52 /* sector erase (alternate) */
|
| /src/sys/dev/wscons/ |
| linux_keymap.c | 145 [103] /* KEY_UP */ = 0x52,
|
| /src/tests/crypto/opencrypto/ |
| h_aesctr2.c | 39 unsigned char key[20] = {0xae, 0x68, 0x52, 0xf8, 0x12, 0x10, 0x67, 0xcc,
|
