| /src/sys/arch/sh3/include/ |
| exception.h | 68 #define EXPEVT_FPU_SLOT_DISABLE 0x820 /* Slot FPU disabled */
113 #define SH7709_INTEVT2_DEI1 0x820
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| /src/games/bcd/ |
| bcd.c | 96 0x022, 0x900, 0x880, 0x840, 0x820, 0x810, 0x808, 0x804,
100 0x900, 0x880, 0x840, 0x820, 0x810, 0x808, 0x804, 0x802,
112 0x900, 0x880, 0x840, 0x820, 0x810, 0x808, 0x804, 0x802,
116 0x900, 0x880, 0x840, 0x820, 0x810, 0x808, 0x804, 0x802,
|
| /src/sys/arch/arm/nvidia/ |
| tegra_apbreg.h | 37 #define APB_MISC_GP_MIPI_PAD_CTRL_0_REG 0x820
|
| tegra_usbreg.h | 101 #define TEGRA_EHCI_UTMIP_TX_CFG0_REG 0x820
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| rv6xxd.h | 159 #define CG_SPLL_SPREAD_SPECTRUM_LOW 0x820
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/pinctrl/ |
| am33xx.h | 55 #define AM335X_PIN_GPMC_AD8 0x820
|
| /src/sys/arch/arm/imx/ |
| imx51reg.h | 236 #define USBOH3_UH1_PHY_CTRL_1 0x820
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| am437x-cm-t43.dts | 56 AM4372_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0 */
|
| am335x-guardian.dts | 380 AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
|
| imx6sl-pinfunc.h | 87 #define MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x070 0x360 0x820 0x6 0x0
118 #define MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x080 0x370 0x820 0x6 0x1
608 #define MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x1a0 0x4a8 0x820 0x6 0x2
1043 #define MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x290 0x598 0x820 0x6 0x3
|
| am437x-sk-evm.dts | 347 AM4372_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
|
| am43x-epos-evm.dts | 408 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
|
| stih407-family.dtsi | 447 st,syscfg = <0x11c 0x820>;
|
| am437x-gp-evm.dts | 268 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
|
| imx35-pinfunc.h | 523 #define MX35_PAD_LD21__ESDHC3_DAT1 0x204 0x668 0x820 0x3 0x0
681 #define MX35_PAD_ATA_DIOW__ESDHC3_DAT1 0x26c 0x6d0 0x820 0x1 0x1
|
| imx50-pinfunc.h | 197 #define MX50_PAD_UART3_RXD__EIM_WEIM_D_13 0x0a8 0x354 0x820 0x6 0x0
631 #define MX50_PAD_EPDC_D13__EIM_WEIM_D_13 0x1e4 0x580 0x820 0x2 0x1
|
| imx53-pinfunc.h | 76 #define MX53_PAD_KEY_ROW3__I2C2_SDA 0x040 0x368 0x820 0x4 0x0
449 #define MX53_PAD_EIM_D16__I2C2_SDA 0x118 0x460 0x820 0x5 0x1
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| imx6dl-pinfunc.h | 805 #define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0
920 #define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1
|
| imx6q-pinfunc.h | 297 #define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
480 #define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
|
| /src/sys/external/bsd/dwc2/dist/ |
| dwc2_hw.h | 487 #define DTKNQR1 HSOTG_REG(0x820)
|
| /src/sys/dev/ic/ |
| bwireg.h | 469 #define BWI_REGWIN_T_BUSPCIE 0x820
|
| rtwnreg.h | 734 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8)
739 #define R92C_FPGA0_XA_HSSIPARAM1 0x820
|
| rtwn_data.h | 145 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c,
542 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c,
651 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c,
765 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838,
|
| /src/sys/arch/mips/ralink/ |
| ralink_reg.h | 737 #define RA_FE_TX_BASE_PTR_2 0x820 /* TX Ring #2 Base Pointer */
1158 #define RA_USB_OTG_DV_IN_SEQ_RQ1 0x820
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| /src/sys/dev/usb/ |
| if_mue.c | 331 threshold = 0x820;
|
