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  /src/sys/arch/alpha/pci/
tsreg.h 82 #define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */
88 #define TS_C_MTR 0x101##a000##0040UL
90 #define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */
96 #define TS_C_MPD 0x101##a000##00c0UL
103 #define TS_C_AAR0 0x101##a000##0100UL
104 #define TS_C_AAR1 0x101##a000##0140UL
105 #define TS_C_AAR2 0x101##a000##0180UL
106 #define TS_C_AAR3 0x101##a000##01c0UL
111 #define TS_C_DIM0 0x101##a000##0200UL
112 #define TS_C_DIM1 0x101##a000##0240U
    [all...]
tsreg.h 82 #define TS_C_CSC 0x101##a000##0000UL /* Cchip System Configuration */
88 #define TS_C_MTR 0x101##a000##0040UL
90 #define TS_C_MISC 0x101##a000##0080UL /* Miscellaneous Register */
96 #define TS_C_MPD 0x101##a000##00c0UL
103 #define TS_C_AAR0 0x101##a000##0100UL
104 #define TS_C_AAR1 0x101##a000##0140UL
105 #define TS_C_AAR2 0x101##a000##0180UL
106 #define TS_C_AAR3 0x101##a000##01c0UL
111 #define TS_C_DIM0 0x101##a000##0200UL
112 #define TS_C_DIM1 0x101##a000##0240U
    [all...]
  /src/sys/arch/hp300/dev/
dioreg.h 47 #define DIOII_SIZEOFF 0x101 /* device size */
dioreg.h 47 #define DIOII_SIZEOFF 0x101 /* device size */
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
usb_a9g20-dab-mmx.dtsi 80 linux,code = <0x101>;
usb_a9g20-dab-mmx.dtsi 80 linux,code = <0x101>;
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/
armada-ap810-ap0-octa-core.dtsi 37 reg = <0x101>;
armada-ap810-ap0-octa-core.dtsi 37 reg = <0x101>;
armada-ap806-quad.dtsi 66 reg = <0x101>;
armada-ap807-quad.dtsi 66 reg = <0x101>;
  /src/sys/dev/isa/
gusreg.h 47 #define GUS_MIDI_READ (0x101-GUS_IOH4_OFFSET)
48 #define GUS_MIDI_WRITE (0x101-GUS_IOH4_OFFSET)
gusreg.h 47 #define GUS_MIDI_READ (0x101-GUS_IOH4_OFFSET)
48 #define GUS_MIDI_WRITE (0x101-GUS_IOH4_OFFSET)
  /src/sys/arch/i386/stand/lib/
vbe.h 29 #define VBE_DEFAULT_MODE 0x101 /* 640x480x8 */
vbe.h 29 #define VBE_DEFAULT_MODE 0x101 /* 640x480x8 */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_abm.c 262 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
264 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
265 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
amdgpu_dce_abm.c 262 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
264 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
265 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
  /src/sys/arch/sparc64/include/
trap.h 111 #define T_BREAKPOINT 0x101 /* breakpoint `instruction' */
trap.h 111 #define T_BREAKPOINT 0x101 /* breakpoint `instruction' */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
mt6755.dtsi 71 reg = <0x101>;
mt6795.dtsi 71 reg = <0x101>;
mt6755.dtsi 71 reg = <0x101>;
mt6795.dtsi 71 reg = <0x101>;
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/amlogic/
meson-g12b.dtsi 79 reg = <0x0 0x101>;
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pcie.dtsi 22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/
k3-am654.dtsi 80 reg = <0x101>;

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