| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/ |
| r200_blit.h | 36 struct radeon_bo *src_bo,
|
| r200_blit.c | 368 struct radeon_bo *src_bo,
376 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
452 * @param[in] src_bo source radeon buffer object
453 * @param[in] src_offset offset of the source image in the @a src_bo
473 struct radeon_bo *src_bo,
515 if (src_bo == dst_bo) {
529 src_bo);
541 if (!validate_buffers(r200, src_bo, dst_bo))
547 emit_tx_setup(r200, src_mesaformat, dst_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/ |
| radeon_blit.h | 36 struct radeon_bo *src_bo,
|
| radeon_blit.c | 217 struct radeon_bo *src_bo,
225 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
304 * @param[in] src_bo source radeon buffer object
305 * @param[in] src_offset offset of the source image in the @a src_bo
325 struct radeon_bo *src_bo,
367 if (src_bo == dst_bo) {
381 src_bo);
393 if (!validate_buffers(r100, src_bo, dst_bo))
399 emit_tx_setup(r100, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/ |
| r200_blit.h | 36 struct radeon_bo *src_bo,
|
| r200_blit.c | 378 struct radeon_bo *src_bo,
386 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
462 * @param[in] src_bo source radeon buffer object
463 * @param[in] src_offset offset of the source image in the @a src_bo
483 struct radeon_bo *src_bo,
525 if (src_bo == dst_bo) {
539 src_bo);
551 if (!validate_buffers(r200, src_bo, dst_bo))
557 emit_tx_setup(r200, src_mesaformat, dst_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/ |
| radeon_blit.h | 36 struct radeon_bo *src_bo,
|
| radeon_blit.c | 226 struct radeon_bo *src_bo,
234 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
313 * @param[in] src_bo source radeon buffer object
314 * @param[in] src_offset offset of the source image in the @a src_bo
334 struct radeon_bo *src_bo,
376 if (src_bo == dst_bo) {
390 src_bo);
402 if (!validate_buffers(r100, src_bo, dst_bo))
408 emit_tx_setup(r100, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch);
|
| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| sna_io.c | 226 void sna_read_boxes(struct sna *sna, PixmapPtr dst, struct kgem_bo *src_bo,
240 __FUNCTION__, nbox, src_bo->handle,
246 box[n].x2 * dst->drawable.bitsPerPixel/8 > src_bo->pitch ||
247 box[n].y2 * src_bo->pitch > kgem_bo_size(src_bo))
252 src_bo->pitch, kgem_bo_size(src_bo));
263 if (download_inplace(kgem, dst, src_bo, box, nbox)) {
265 read_boxes_inplace(kgem, dst, src_bo, box, nbox);
269 can_blt = kgem_bo_can_blt(kgem, src_bo) &
835 struct kgem_bo *src_bo; local
1343 struct kgem_bo *src_bo; local
1786 struct kgem_bo *src_bo; local
[all...] |
| sna_blt.c | 1655 struct kgem_bo *src_bo = op->u.blt.bo[0]; local
1705 b[7] = kgem_add_reloc(kgem, kgem->nbatch + 7, src_bo,
1719 kgem_bcs_set_tiling(&sna->kgem, src_bo, dst_bo);
1762 b[7] = kgem_add_reloc(kgem, kgem->nbatch + 7, src_bo,
1776 kgem_bcs_set_tiling(&sna->kgem, src_bo, dst_bo);
1793 struct kgem_bo *src_bo = op->u.blt.bo[0]; local
1845 kgem_add_reloc64(kgem, kgem->nbatch + 8, src_bo,
1859 kgem_bcs_set_tiling(&sna->kgem, src_bo, dst_bo);
1904 kgem_add_reloc64(kgem, kgem->nbatch + 8, src_bo,
1918 kgem_bcs_set_tiling(&sna->kgem, src_bo, dst_bo)
4238 assert(sna_pixmap((PixmapPtr)src)->gpu_bo == src_bo); local
4282 assert(sna_pixmap((PixmapPtr)src)->gpu_bo == src_bo); local
[all...] |
| sna_tiling.c | 788 struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
799 !kgem_bo_can_blt(&sna->kgem, src_bo) ||
804 kgem_bo_can_blt(&sna->kgem, src_bo),
809 max_size = sna_max_tile_copy_size(sna, src_bo, dst_bo);
871 src_bo, src_dx, src_dy,
1013 struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
1023 alu, kgem_bo_size(src_bo), kgem_bo_size(dst_bo)));
1026 !kgem_bo_can_blt(&sna->kgem, src_bo) ||
1031 kgem_bo_can_blt(&sna->kgem, src_bo),
1036 max_size = sna_max_tile_copy_size(sna, src_bo, dst_bo)
[all...] |
| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| sna_io.c | 224 void sna_read_boxes(struct sna *sna, PixmapPtr dst, struct kgem_bo *src_bo,
238 __FUNCTION__, nbox, src_bo->handle,
244 box[n].x2 * dst->drawable.bitsPerPixel/8 > src_bo->pitch ||
245 box[n].y2 * src_bo->pitch > kgem_bo_size(src_bo))
250 src_bo->pitch, kgem_bo_size(src_bo));
261 if (download_inplace(kgem, dst, src_bo, box, nbox)) {
263 read_boxes_inplace(kgem, dst, src_bo, box, nbox);
267 can_blt = kgem_bo_can_blt(kgem, src_bo) &
816 struct kgem_bo *src_bo; local
1319 struct kgem_bo *src_bo; local
1759 struct kgem_bo *src_bo; local
[all...] |
| sna_tiling.c | 788 struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
799 !kgem_bo_can_blt(&sna->kgem, src_bo) ||
804 kgem_bo_can_blt(&sna->kgem, src_bo),
809 max_size = sna_max_tile_copy_size(sna, src_bo, dst_bo);
871 src_bo, src_dx, src_dy,
1013 struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
1023 alu, kgem_bo_size(src_bo), kgem_bo_size(dst_bo)));
1026 !kgem_bo_can_blt(&sna->kgem, src_bo) ||
1031 kgem_bo_can_blt(&sna->kgem, src_bo),
1036 max_size = sna_max_tile_copy_size(sna, src_bo, dst_bo)
[all...] |
| sna_blt.c | 1607 struct kgem_bo *src_bo = op->u.blt.bo[0]; local
1657 b[7] = kgem_add_reloc(kgem, kgem->nbatch + 7, src_bo,
1713 b[7] = kgem_add_reloc(kgem, kgem->nbatch + 7, src_bo,
1743 struct kgem_bo *src_bo = op->u.blt.bo[0]; local
1795 kgem_add_reloc64(kgem, kgem->nbatch + 8, src_bo,
1853 kgem_add_reloc64(kgem, kgem->nbatch + 8, src_bo,
3668 struct kgem_bo *src_bo, int16_t src_dx, int16_t src_dy,
3681 src_bo->tiling, dst_bo->tiling,
3682 src_bo->pitch, dst_bo->pitch));
3685 if (wedged(sna) || !kgem_bo_can_blt(kgem, src_bo) || !kgem_bo_can_blt(kgem, dst_bo))
4201 assert(sna_pixmap((PixmapPtr)src)->gpu_bo == src_bo); local
4244 assert(sna_pixmap((PixmapPtr)src)->gpu_bo == src_bo); local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/ |
| intel_blit.h | 63 drm_intel_bo *src_bo,
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/ |
| intel_blit.h | 63 drm_intel_bo *src_bo,
|
| /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/ |
| radv_meta_buffer.c | 242 copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo,
254 radv_buffer_init(&src_buffer, cmd_buffer->device, src_bo, size, src_offset);
292 struct radeon_winsys_bo *src_bo, struct radeon_winsys_bo *dst_bo)
298 if ((src_bo && !(src_bo->initial_domain & RADEON_DOMAIN_VRAM)) ||
337 radv_copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *src_bo,
342 radv_prefer_compute_dma(cmd_buffer->device, size, src_bo, dst_bo);
345 copy_buffer_shader(cmd_buffer, src_bo, dst_bo, src_offset, dst_offset, size);
347 uint64_t src_va = radv_buffer_get_va(src_bo);
352 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo);
[all...] |
| /xsrc/external/mit/xf86-video-qxl/dist/src/ |
| qxl_mem.c | 519 struct qxl_ums_bo *src_bo = (struct qxl_ums_bo *)_src_bo; local
525 src_bo->refcnt++;
527 slot_id = src_bo->type == QXL_BO_SURF ? qxl->vram_mem_slot : qxl->main_mem_slot;
528 value = physical_address(qxl, src_bo->internal_virt_addr, slot_id);
536 struct qxl_ums_bo *src_bo = (struct qxl_ums_bo *)_src_bo; local
540 src_bo->refcnt++;
542 slot_id = src_bo->type == QXL_BO_SURF ? qxl->vram_mem_slot : qxl->main_mem_slot;
543 value = physical_address(qxl, src_bo->internal_virt_addr, slot_id);
|
| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| radeon_video.h | 63 struct radeon_bo *src_bo[2]; member in struct:__anon6939
|
| radeon_textured_video.c | 161 pPriv->src_bo[0] = NULL;
162 radeon_bo_unref(pPriv->src_bo[1]);
163 pPriv->src_bo[1] = NULL;
241 struct radeon_bo *src_bo; local
324 pPriv->src_bo[0] = pPriv->video_memory;
325 radeon_allocate_video_bo(pScrn, (void*)&pPriv->src_bo[1], size,
352 src_bo = pPriv->src_bo[pPriv->currentBuffer];
354 ret = radeon_bo_map(src_bo, 1);
358 pPriv->src_addr = src_bo->ptr
[all...] |
| radeon_exa_funcs.c | 66 has_src = info->state_2d.src_pitch_offset || info->state_2d.src_bo;
87 OUT_RING_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
170 info->state_2d.src_bo = NULL;
262 info->state_2d.src_bo = driver_priv->bo->bo.radeon;
324 RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo,
332 if (src_bo && dst_bo) {
334 } else if (src_bo && !dst_bo) {
350 if (src_bo) {
351 OUT_RING_RELOC(src_bo, src_domain, 0);
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/ |
| radv_meta_buffer.c | 340 struct radeon_winsys_bo *src_bo,
360 .bo = src_bo,
432 struct radeon_winsys_bo *src_bo,
438 copy_buffer_shader(cmd_buffer, src_bo, dst_bo,
441 uint64_t src_va = radv_buffer_get_va(src_bo);
446 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, src_bo);
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| brw_blorp.h | 64 struct brw_bo *src_bo,
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| brw_blorp.h | 64 struct brw_bo *src_bo,
|
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| radeon_exa_funcs.c | 100 has_src = info->state_2d.src_pitch_offset || (info->cs && info->state_2d.src_bo);
123 OUT_RELOC(info->state_2d.src_bo, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0);
211 info->state_2d.src_bo = NULL;
308 info->state_2d.src_bo = driver_priv->bo;
417 RADEONBlitChunk(ScrnInfoPtr pScrn, struct radeon_bo *src_bo,
426 if (src_bo && dst_bo) {
428 } else if (src_bo && dst_bo == NULL) {
444 if (src_bo) {
445 OUT_RELOC(src_bo, src_domain, 0);
|
