1/* 2 * Copyright (C) 2010 Advanced Micro Devices, Inc. 3 * 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sublicense, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial 16 * portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 */ 27 28#include "radeon_common.h" 29#include "radeon_context.h" 30#include "radeon_blit.h" 31#include "radeon_tex.h" 32 33static inline uint32_t cmdpacket0(struct radeon_screen *rscrn, 34 int reg, int count) 35{ 36 if (count) 37 return CP_PACKET0(reg, count - 1); 38 return CP_PACKET2; 39} 40 41/* common formats supported as both textures and render targets */ 42unsigned r100_check_blit(mesa_format mesa_format, uint32_t dst_pitch) 43{ 44 /* XXX others? */ 45 switch (mesa_format) { 46#if UTIL_ARCH_LITTLE_ENDIAN 47 case MESA_FORMAT_B8G8R8A8_UNORM: 48 case MESA_FORMAT_B8G8R8X8_UNORM: 49 case MESA_FORMAT_B5G6R5_UNORM: 50 case MESA_FORMAT_B4G4R4A4_UNORM: 51 case MESA_FORMAT_B5G5R5A1_UNORM: 52#else 53 case MESA_FORMAT_A8R8G8B8_UNORM: 54 case MESA_FORMAT_X8R8G8B8_UNORM: 55 case MESA_FORMAT_R5G6B5_UNORM: 56 case MESA_FORMAT_A4R4G4B4_UNORM: 57 case MESA_FORMAT_A1R5G5B5_UNORM: 58#endif 59 case MESA_FORMAT_A_UNORM8: 60 case MESA_FORMAT_L_UNORM8: 61 case MESA_FORMAT_I_UNORM8: 62 break; 63 default: 64 return 0; 65 } 66 67 /* Rendering to small buffer doesn't work. 68 * Looks like a hw limitation. 69 */ 70 if (dst_pitch < 32) 71 return 0; 72 73 /* ??? */ 74 if (_mesa_get_format_bits(mesa_format, GL_DEPTH_BITS) > 0) 75 return 0; 76 77 return 1; 78} 79 80static inline void emit_vtx_state(struct r100_context *r100) 81{ 82 BATCH_LOCALS(&r100->radeon); 83 84 BEGIN_BATCH(8); 85 if (r100->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) { 86 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, 0); 87 } else { 88 OUT_BATCH_REGVAL(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); 89 90 } 91 OUT_BATCH_REGVAL(RADEON_SE_COORD_FMT, (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 92 RADEON_TEX1_W_ROUTING_USE_W0)); 93 OUT_BATCH_REGVAL(RADEON_SE_VTX_FMT, RADEON_SE_VTX_FMT_XY | RADEON_SE_VTX_FMT_ST0); 94 OUT_BATCH_REGVAL(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 95 RADEON_BFACE_SOLID | 96 RADEON_FFACE_SOLID | 97 RADEON_VTX_PIX_CENTER_OGL | 98 RADEON_ROUND_MODE_ROUND | 99 RADEON_ROUND_PREC_4TH_PIX)); 100 END_BATCH(); 101} 102 103static void inline emit_tx_setup(struct r100_context *r100, 104 mesa_format mesa_format, 105 struct radeon_bo *bo, 106 intptr_t offset, 107 unsigned width, 108 unsigned height, 109 unsigned pitch) 110{ 111 uint32_t txformat = RADEON_TXFORMAT_NON_POWER2; 112 BATCH_LOCALS(&r100->radeon); 113 114 assert(width <= 2048); 115 assert(height <= 2048); 116 assert(offset % 32 == 0); 117 118 txformat |= tx_table[mesa_format].format; 119 120 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 121 offset |= RADEON_TXO_MACRO_TILE; 122 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 123 offset |= RADEON_TXO_MICRO_TILE_X2; 124 125 BEGIN_BATCH(18); 126 OUT_BATCH_REGVAL(RADEON_PP_CNTL, RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE); 127 OUT_BATCH_REGVAL(RADEON_PP_TXCBLEND_0, (RADEON_COLOR_ARG_A_ZERO | 128 RADEON_COLOR_ARG_B_ZERO | 129 RADEON_COLOR_ARG_C_T0_COLOR | 130 RADEON_BLEND_CTL_ADD | 131 RADEON_CLAMP_TX)); 132 OUT_BATCH_REGVAL(RADEON_PP_TXABLEND_0, (RADEON_ALPHA_ARG_A_ZERO | 133 RADEON_ALPHA_ARG_B_ZERO | 134 RADEON_ALPHA_ARG_C_T0_ALPHA | 135 RADEON_BLEND_CTL_ADD | 136 RADEON_CLAMP_TX)); 137 OUT_BATCH_REGVAL(RADEON_PP_TXFILTER_0, (RADEON_CLAMP_S_CLAMP_LAST | 138 RADEON_CLAMP_T_CLAMP_LAST | 139 RADEON_MAG_FILTER_NEAREST | 140 RADEON_MIN_FILTER_NEAREST)); 141 OUT_BATCH_REGVAL(RADEON_PP_TXFORMAT_0, txformat); 142 OUT_BATCH_REGVAL(RADEON_PP_TEX_SIZE_0, ((width - 1) | 143 ((height - 1) << RADEON_TEX_VSIZE_SHIFT))); 144 OUT_BATCH_REGVAL(RADEON_PP_TEX_PITCH_0, pitch * _mesa_get_format_bytes(mesa_format) - 32); 145 146 OUT_BATCH_REGSEQ(RADEON_PP_TXOFFSET_0, 1); 147 OUT_BATCH_RELOC(bo, offset, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0); 148 149 END_BATCH(); 150} 151 152static inline void emit_cb_setup(struct r100_context *r100, 153 struct radeon_bo *bo, 154 intptr_t offset, 155 mesa_format mesa_format, 156 unsigned pitch, 157 unsigned width, 158 unsigned height) 159{ 160 uint32_t dst_pitch = pitch; 161 uint32_t dst_format = 0; 162 BATCH_LOCALS(&r100->radeon); 163 164 /* XXX others? */ 165 switch (mesa_format) { 166 /* The first of each pair is for little, the second for big endian. */ 167 case MESA_FORMAT_B8G8R8A8_UNORM: 168 case MESA_FORMAT_A8R8G8B8_UNORM: 169 case MESA_FORMAT_B8G8R8X8_UNORM: 170 case MESA_FORMAT_X8R8G8B8_UNORM: 171 dst_format = RADEON_COLOR_FORMAT_ARGB8888; 172 break; 173 case MESA_FORMAT_B5G6R5_UNORM: 174 case MESA_FORMAT_R5G6B5_UNORM: 175 dst_format = RADEON_COLOR_FORMAT_RGB565; 176 break; 177 case MESA_FORMAT_B4G4R4A4_UNORM: 178 case MESA_FORMAT_A4R4G4B4_UNORM: 179 dst_format = RADEON_COLOR_FORMAT_ARGB4444; 180 break; 181 case MESA_FORMAT_B5G5R5A1_UNORM: 182 case MESA_FORMAT_A1R5G5B5_UNORM: 183 dst_format = RADEON_COLOR_FORMAT_ARGB1555; 184 break; 185 case MESA_FORMAT_A_UNORM8: 186 case MESA_FORMAT_L_UNORM8: 187 case MESA_FORMAT_I_UNORM8: 188 dst_format = RADEON_COLOR_FORMAT_RGB8; 189 break; 190 default: 191 break; 192 } 193 194 if (bo->flags & RADEON_BO_FLAGS_MACRO_TILE) 195 dst_pitch |= RADEON_COLOR_TILE_ENABLE; 196 197 if (bo->flags & RADEON_BO_FLAGS_MICRO_TILE) 198 dst_pitch |= RADEON_COLOR_MICROTILE_ENABLE; 199 200 BEGIN_BATCH(18); 201 OUT_BATCH_REGVAL(RADEON_RE_TOP_LEFT, 0); 202 OUT_BATCH_REGVAL(RADEON_RE_WIDTH_HEIGHT, (((width - 1) << RADEON_RE_WIDTH_SHIFT) | 203 ((height - 1) << RADEON_RE_HEIGHT_SHIFT))); 204 OUT_BATCH_REGVAL(RADEON_RB3D_PLANEMASK, 0xffffffff); 205 OUT_BATCH_REGVAL(RADEON_RB3D_BLENDCNTL, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO); 206 OUT_BATCH_REGVAL(RADEON_RB3D_CNTL, dst_format); 207 208 OUT_BATCH_REGSEQ(RADEON_RB3D_COLOROFFSET, 1); 209 OUT_BATCH_RELOC(bo, offset, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); 210 OUT_BATCH_REGSEQ(RADEON_RB3D_COLORPITCH, 1); 211 OUT_BATCH_RELOC(bo, dst_pitch, 0, RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0); 212 213 END_BATCH(); 214} 215 216static GLboolean validate_buffers(struct r100_context *r100, 217 struct radeon_bo *src_bo, 218 struct radeon_bo *dst_bo) 219{ 220 int ret; 221 222 radeon_cs_space_reset_bos(r100->radeon.cmdbuf.cs); 223 224 ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs, 225 src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0); 226 if (ret) 227 return GL_FALSE; 228 229 ret = radeon_cs_space_check_with_bo(r100->radeon.cmdbuf.cs, 230 dst_bo, 0, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT); 231 if (ret) 232 return GL_FALSE; 233 234 return GL_TRUE; 235} 236 237/** 238 * Calculate texcoords for given image region. 239 * Output values are [minx, maxx, miny, maxy] 240 */ 241static inline void calc_tex_coords(float img_width, float img_height, 242 float x, float y, 243 float reg_width, float reg_height, 244 unsigned flip_y, float *buf) 245{ 246 buf[0] = x / img_width; 247 buf[1] = buf[0] + reg_width / img_width; 248 buf[2] = y / img_height; 249 buf[3] = buf[2] + reg_height / img_height; 250 if (flip_y) 251 { 252 buf[2] = 1.0 - buf[2]; 253 buf[3] = 1.0 - buf[3]; 254 } 255} 256 257static inline void emit_draw_packet(struct r100_context *r100, 258 unsigned src_width, unsigned src_height, 259 unsigned src_x_offset, unsigned src_y_offset, 260 unsigned dst_x_offset, unsigned dst_y_offset, 261 unsigned reg_width, unsigned reg_height, 262 unsigned flip_y) 263{ 264 float texcoords[4]; 265 float verts[12]; 266 BATCH_LOCALS(&r100->radeon); 267 268 calc_tex_coords(src_width, src_height, 269 src_x_offset, src_y_offset, 270 reg_width, reg_height, 271 flip_y, texcoords); 272 273 verts[0] = dst_x_offset; 274 verts[1] = dst_y_offset + reg_height; 275 verts[2] = texcoords[0]; 276 verts[3] = texcoords[3]; 277 278 verts[4] = dst_x_offset + reg_width; 279 verts[5] = dst_y_offset + reg_height; 280 verts[6] = texcoords[1]; 281 verts[7] = texcoords[3]; 282 283 verts[8] = dst_x_offset + reg_width; 284 verts[9] = dst_y_offset; 285 verts[10] = texcoords[1]; 286 verts[11] = texcoords[2]; 287 288 BEGIN_BATCH(15); 289 OUT_BATCH(RADEON_CP_PACKET3_3D_DRAW_IMMD | (13 << 16)); 290 OUT_BATCH(RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_ST0); 291 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING | 292 RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST | 293 RADEON_CP_VC_CNTL_MAOS_ENABLE | 294 RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE | 295 (3 << 16)); 296 OUT_BATCH_TABLE(verts, 12); 297 END_BATCH(); 298} 299 300/** 301 * Copy a region of [@a width x @a height] pixels from source buffer 302 * to destination buffer. 303 * @param[in] r100 r100 context 304 * @param[in] src_bo source radeon buffer object 305 * @param[in] src_offset offset of the source image in the @a src_bo 306 * @param[in] src_mesaformat source image format 307 * @param[in] src_pitch aligned source image width 308 * @param[in] src_width source image width 309 * @param[in] src_height source image height 310 * @param[in] src_x_offset x offset in the source image 311 * @param[in] src_y_offset y offset in the source image 312 * @param[in] dst_bo destination radeon buffer object 313 * @param[in] dst_offset offset of the destination image in the @a dst_bo 314 * @param[in] dst_mesaformat destination image format 315 * @param[in] dst_pitch aligned destination image width 316 * @param[in] dst_width destination image width 317 * @param[in] dst_height destination image height 318 * @param[in] dst_x_offset x offset in the destination image 319 * @param[in] dst_y_offset y offset in the destination image 320 * @param[in] width region width 321 * @param[in] height region height 322 * @param[in] flip_y set if y coords of the source image need to be flipped 323 */ 324unsigned r100_blit(struct gl_context *ctx, 325 struct radeon_bo *src_bo, 326 intptr_t src_offset, 327 mesa_format src_mesaformat, 328 unsigned src_pitch, 329 unsigned src_width, 330 unsigned src_height, 331 unsigned src_x_offset, 332 unsigned src_y_offset, 333 struct radeon_bo *dst_bo, 334 intptr_t dst_offset, 335 mesa_format dst_mesaformat, 336 unsigned dst_pitch, 337 unsigned dst_width, 338 unsigned dst_height, 339 unsigned dst_x_offset, 340 unsigned dst_y_offset, 341 unsigned reg_width, 342 unsigned reg_height, 343 unsigned flip_y) 344{ 345 struct r100_context *r100 = R100_CONTEXT(ctx); 346 347 if (!r100_check_blit(dst_mesaformat, dst_pitch)) 348 return GL_FALSE; 349 350 /* Make sure that colorbuffer has even width - hw limitation */ 351 if (dst_pitch % 2 > 0) 352 ++dst_pitch; 353 354 /* Need to clamp the region size to make sure 355 * we don't read outside of the source buffer 356 * or write outside of the destination buffer. 357 */ 358 if (reg_width + src_x_offset > src_width) 359 reg_width = src_width - src_x_offset; 360 if (reg_height + src_y_offset > src_height) 361 reg_height = src_height - src_y_offset; 362 if (reg_width + dst_x_offset > dst_width) 363 reg_width = dst_width - dst_x_offset; 364 if (reg_height + dst_y_offset > dst_height) 365 reg_height = dst_height - dst_y_offset; 366 367 if (src_bo == dst_bo) { 368 return GL_FALSE; 369 } 370 371 if (src_offset % 32 || dst_offset % 32) { 372 return GL_FALSE; 373 } 374 375 if (0) { 376 fprintf(stderr, "src: size [%d x %d], pitch %d, offset %zd " 377 "offset [%d x %d], format %s, bo %p\n", 378 src_width, src_height, src_pitch, src_offset, 379 src_x_offset, src_y_offset, 380 _mesa_get_format_name(src_mesaformat), 381 src_bo); 382 fprintf(stderr, "dst: pitch %d offset %zd, offset[%d x %d], format %s, bo %p\n", 383 dst_pitch, dst_offset, dst_x_offset, dst_y_offset, 384 _mesa_get_format_name(dst_mesaformat), dst_bo); 385 fprintf(stderr, "region: %d x %d\n", reg_width, reg_height); 386 } 387 388 /* Flush is needed to make sure that source buffer has correct data */ 389 radeonFlush(ctx, 0); 390 391 rcommonEnsureCmdBufSpace(&r100->radeon, 59, __func__); 392 393 if (!validate_buffers(r100, src_bo, dst_bo)) 394 return GL_FALSE; 395 396 /* 8 */ 397 emit_vtx_state(r100); 398 /* 18 */ 399 emit_tx_setup(r100, src_mesaformat, src_bo, src_offset, src_width, src_height, src_pitch); 400 /* 18 */ 401 emit_cb_setup(r100, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height); 402 /* 15 */ 403 emit_draw_packet(r100, src_width, src_height, 404 src_x_offset, src_y_offset, 405 dst_x_offset, dst_y_offset, 406 reg_width, reg_height, 407 flip_y); 408 409 radeonFlush(ctx, 0); 410 411 /* We submitted those packets outside our state atom mechanism. Thus 412 * make sure they are all resubmitted the next time. */ 413 r100->hw.ctx.dirty = GL_TRUE; 414 r100->hw.msk.dirty = GL_TRUE; 415 r100->hw.set.dirty = GL_TRUE; 416 r100->hw.tex[0].dirty = GL_TRUE; 417 r100->hw.txr[0].dirty = GL_TRUE; 418 419 return GL_TRUE; 420} 421