| /src/lib/libform/ |
| form.h | 135 #define REQ_DEL_WORD (KEY_MAX + 0x125) /* delete the word at the cursor */
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| form.h | 135 #define REQ_DEL_WORD (KEY_MAX + 0x125) /* delete the word at the cursor */
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| /src/sys/arch/powerpc/include/ibm4xx/ |
| dcr4xx.h | 126 #define DCR_DMA0_SLP 0x125 /* DMA Sleep Mode Register */
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| dcr4xx.h | 126 #define DCR_DMA0_SLP 0x125 /* DMA Sleep Mode Register */
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| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| fiji_ppsmc.h | 214 #define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
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| smu7_ppsmc.h | 211 #define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
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| tonga_ppsmc.h | 238 #define PPSMC_MSG_NBDPM_Config ((uint16_t) 0x125)
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| fiji_ppsmc.h | 214 #define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
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| smu7_ppsmc.h | 211 #define PPSMC_MSG_VddNB_Request ((uint16_t) 0x125)
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| tonga_ppsmc.h | 238 #define PPSMC_MSG_NBDPM_Config ((uint16_t) 0x125)
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| /src/sys/external/gpl2/dts/dist/include/dt-bindings/input/ |
| linux-event-codes.h | 372 #define BTN_PINKIE 0x125
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| linux-event-codes.h | 372 #define BTN_PINKIE 0x125
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/ |
| bif_5_0_d.h | 438 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125
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| bif_5_0_d.h | 438 #define mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1 0x125
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| /src/sys/arch/powerpc/powerpc/ |
| db_disasm.c | 580 { 0x125, "dma0_slp" },
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| db_disasm.c | 580 { 0x125, "dma0_slp" },
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| /src/sys/dev/qbus/ |
| qfont.c | 99 ,0x125 ,0x126 ,0x127 ,0x128 ,0x129 ,0x12a ,0x12b ,0x12c /* 152 */
134 ,0x125 ,0x126 ,0x127 ,0x128 ,0x129 ,0x12a ,0x12b ,0x12c /* 152 */
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| qfont.c | 99 ,0x125 ,0x126 ,0x127 ,0x128 ,0x129 ,0x12a ,0x12b ,0x12c /* 152 */
134 ,0x125 ,0x126 ,0x127 ,0x128 ,0x129 ,0x12a ,0x12b ,0x12c /* 152 */
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/ |
| gmc_7_1_d.h | 1194 #define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
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| gmc_8_1_d.h | 1298 #define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
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| gmc_7_1_d.h | 1194 #define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
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| gmc_8_1_d.h | 1298 #define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125
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| /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/ |
| gfx_8_0_enum.h | 421 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
1621 SC_PA2_SC_DATA_FIFO_WE = 0x125,
3582 #define SQ_DPP_ROW_RR5 0x125
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| gfx_8_1_enum.h | 421 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
1639 SC_PA2_SC_DATA_FIFO_WE = 0x125,
3600 #define SQ_DPP_ROW_RR5 0x125
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| gfx_8_0_enum.h | 421 CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125,
1621 SC_PA2_SC_DATA_FIFO_WE = 0x125,
3582 #define SQ_DPP_ROW_RR5 0x125
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