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  /src/sys/arch/hpcmips/tx/
tx39timerreg.h 37 #define TX39_TIMERALARMHI_REG 0x148
tx39timerreg.h 37 #define TX39_TIMERALARMHI_REG 0x148
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 161 #define CM_BURSTCTL 0x148
bcm2835_cm.h 161 #define CM_BURSTCTL 0x148
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 124 #define PCI_ABITOR_STATUS 0x148
ixp12x0_pcireg.h 124 #define PCI_ABITOR_STATUS 0x148
  /src/sys/arch/arm/nvidia/
tegra124_xusbpadreg.h 114 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG 0x148
tegra124_xusbpadreg.h 114 #define XUSB_PADCTL_IOPHY_MISC_PAD_S0_CTL1_REG 0x148
  /src/sys/dev/pci/
if_nfereg.h 68 #define NFE_TX_RING_ADDR_HI 0x148
if_nfereg.h 68 #define NFE_TX_RING_ADDR_HI 0x148
cs4281reg.h 104 #define CS4281_DBA3 0x148 /* DMA Engine 3 Base Address Register */
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
omap4.h 124 #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
omap5.h 86 #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
omap4.h 124 #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148)
omap5.h 86 #define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
dra7.h 154 #define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
328 #define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
dra7.h 154 #define DRA7_UART2_CLKCTRL _DRA7_L4PER_CLKCTRL_INDEX(0x148)
328 #define DRA7_L4PER_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
  /src/lib/libcurses/
keyname.c 142 if (key < 0x148) {
151 if (key == 0x148) {
keyname.c 142 if (key < 0x148) {
151 if (key == 0x148) {
  /src/tests/lib/libcurses/tests/
std_defines 55 assign KEY_DL 0x148
std_defines 55 assign KEY_DL 0x148
  /src/sys/arch/amiga/amiga/
cc_registers.h 190 #define R_SPR1_POS 0x148
  /src/sys/arch/arm/footbridge/
dc21285reg.h 228 #define XBUS_CYCLE_ARBITER 0x148
  /src/sys/arch/arm/s3c2xx0/
s3c2800reg.h 314 #define PCICTL_PCIBATPA1 0x148 /* address translation PCI to AHB BAR1 */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
ppsmc.h 138 #define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)

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