| /src/sys/dev/ic/ |
| igpioreg.h | 175 { "INTC1056", 0, 0, 94, 0x200, 0x220 },
176 { "INTC1056", 1, 95, 150, 0x200, 0x220 },
177 { "INTC1056", 2, 151, 199, 0x200, 0x220 },
178 { "INTC1056", 3, 200, 269, 0x200, 0x220 },
179 { "INTC1056", 4, 270, 303, 0x200, 0x220 },
188 { "INTC1085", 0, 0, 94, 0x200, 0x220 },
189 { "INTC1085", 1, 95, 150, 0x200, 0x220 },
190 { "INTC1085", 2, 151, 199, 0x200, 0x220 },
191 { "INTC1085", 3, 200, 269, 0x200, 0x220 },
192 { "INTC1085", 4, 270, 303, 0x200, 0x220 },
[all...] |
| /src/sys/dev/gpib/ |
| ctreg.h | 61 #define CT7946ID 0x220
|
| rdreg.h | 62 #define RD7946AID 0x220 /* also 7945A */
|
| /src/sys/dev/isa/ |
| madreg.h | 96 #define MAD_REG1 0x220
|
| ioat66.c | 67 int ioatbases[NSLAVES]={0x220,0x228,0x240,0x248,0x260,0x268};
|
| if_fmv_isa.c | 79 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x300, 0x340
|
| essreg.h | 166 #define ESS_BASE_VALID(base) ((base) == 0x220 || (base) == 0x230 || (base) == 0x240 || (base) == 0x250)
|
| /src/games/bcd/ |
| bcd.c | 98 0x404, 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208,
102 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
114 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
118 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, 0x204,
|
| /src/sys/arch/hpcmips/dev/ |
| plumicureg.h | 116 #define PLUM_INT_PCCLKSL_REG 0x220
|
| /src/sys/arch/x86/pci/ |
| lpssreg.h | 59 #define LPSS_TX_IRQ 0x220
|
| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| dm814.h | 36 #define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
|
| lpc18xx-ccu.h | 25 #define CLK_APB1_CAN1 0x220
|
| am4.h | 17 #define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
52 #define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
123 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
125 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
162 #define AM4_L3S_GPMC_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x220)
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_tconreg.h | 72 #define SUNXI_TCON_LVDS_ANA0 0x220
|
| /src/sys/arch/hp300/dev/ |
| ctreg.h | 101 #define CT7946ID 0x220
|
| /src/sys/arch/arm/cortex/ |
| pl310_reg.h | 102 #define L2C_INT_CLR 0x220
|
| /src/sys/arch/sh3/include/ |
| exception.h | 136 #define SH4_INTEVT_IRQ1 0x220
|
| pcicreg.h | 108 #define SH4_PCIPDR (SH4_PCIC+0x220) /* 32bit */
|
| /src/sys/arch/mac68k/include/ |
| iopreg.h | 92 #define IOP_ADDR_SEND_MSG 0x220
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| trinityd.h | 169 #define SMC_INT_REQ 0x220
|
| /src/sys/arch/arm/marvell/ |
| mv78xx0reg.h | 176 #define MV78XX0_ICI_FIQIMLR 0x220 /* FIQ Interrupt Mask Low */
|
| dovereg.h | 154 #define DOVE_DB_PCIEIMR 0x220 /* PCIe0/PCIe1 intr Mask reg */
|
| /src/sys/arch/arm/ti/ |
| omap2_gpmcreg.h | 166 #define GPMC_ECC9_RESULT 0x220
|
| /src/sys/arch/sparc64/dev/ |
| ffbreg.h | 159 #define FFB_FBC_VCLIPMIN 0x220 /* Viewclip XY Min Bounds */
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/ |
| stingray-pinctrl.dtsi | 316 0x220 MODE_NAND /* uart0_dcd */
|
