1 //===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This describes the calling conventions for the AMD Radeon GPUs. 10 // 11 //===----------------------------------------------------------------------===// 12 13 // Inversion of CCIfInReg 14 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {} 15 class CCIfExtend<CCAction A> 16 : CCIf<"ArgFlags.isSExt() || ArgFlags.isZExt()", A>; 17 18 // Calling convention for SI 19 def CC_SI_Gfx : CallingConv<[ 20 // 0-3 are reserved for the stack buffer descriptor 21 // 30-31 are reserved for the return address 22 // 32 is reserved for the stack pointer 23 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[ 24 SGPR4, SGPR5, SGPR6, SGPR7, 25 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, 26 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, 27 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, 28 ]>>>, 29 30 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[ 31 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 32 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 33 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 34 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31 35 ]>>>, 36 37 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>> 38 ]>; 39 40 def RetCC_SI_Gfx : CallingConv<[ 41 CCIfType<[i1], CCPromoteToType<i32>>, 42 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>, 43 44 // 0-3 are reserved for the stack buffer descriptor 45 // 32 is reserved for the stack pointer 46 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[ 47 SGPR4, SGPR5, SGPR6, SGPR7, 48 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, 49 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, 50 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, 51 SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39, 52 SGPR40, SGPR41, SGPR42, SGPR43 53 ]>>>, 54 55 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[ 56 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 57 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 58 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 59 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, 60 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, 61 VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, 62 VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, 63 VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, 64 VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, 65 VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, 66 VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, 67 VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, 68 VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, 69 VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, 70 VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, 71 VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, 72 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 73 ]>>>, 74 ]>; 75 76 def CC_SI_SHADER : CallingConv<[ 77 78 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[ 79 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, 80 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, 81 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, 82 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, 83 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39, 84 SGPR40, SGPR41, SGPR42, SGPR43 85 ]>>>, 86 87 // 32*4 + 4 is the minimum for a fetch shader consumer with 32 inputs. 88 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[ 89 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 90 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 91 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 92 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, 93 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, 94 VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, 95 VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, 96 VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, 97 VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, 98 VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, 99 VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, 100 VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, 101 VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, 102 VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, 103 VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, 104 VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, 105 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 106 ]>>> 107 ]>; 108 109 def RetCC_SI_Shader : CallingConv<[ 110 CCIfType<[i32, i16] , CCAssignToReg<[ 111 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, 112 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, 113 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21, SGPR22, SGPR23, 114 SGPR24, SGPR25, SGPR26, SGPR27, SGPR28, SGPR29, SGPR30, SGPR31, 115 SGPR32, SGPR33, SGPR34, SGPR35, SGPR36, SGPR37, SGPR38, SGPR39, 116 SGPR40, SGPR41, SGPR42, SGPR43 117 ]>>, 118 119 // 32*4 + 4 is the minimum for a fetch shader with 32 outputs. 120 CCIfType<[f32, f16, v2f16] , CCAssignToReg<[ 121 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 122 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 123 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 124 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31, 125 VGPR32, VGPR33, VGPR34, VGPR35, VGPR36, VGPR37, VGPR38, VGPR39, 126 VGPR40, VGPR41, VGPR42, VGPR43, VGPR44, VGPR45, VGPR46, VGPR47, 127 VGPR48, VGPR49, VGPR50, VGPR51, VGPR52, VGPR53, VGPR54, VGPR55, 128 VGPR56, VGPR57, VGPR58, VGPR59, VGPR60, VGPR61, VGPR62, VGPR63, 129 VGPR64, VGPR65, VGPR66, VGPR67, VGPR68, VGPR69, VGPR70, VGPR71, 130 VGPR72, VGPR73, VGPR74, VGPR75, VGPR76, VGPR77, VGPR78, VGPR79, 131 VGPR80, VGPR81, VGPR82, VGPR83, VGPR84, VGPR85, VGPR86, VGPR87, 132 VGPR88, VGPR89, VGPR90, VGPR91, VGPR92, VGPR93, VGPR94, VGPR95, 133 VGPR96, VGPR97, VGPR98, VGPR99, VGPR100, VGPR101, VGPR102, VGPR103, 134 VGPR104, VGPR105, VGPR106, VGPR107, VGPR108, VGPR109, VGPR110, VGPR111, 135 VGPR112, VGPR113, VGPR114, VGPR115, VGPR116, VGPR117, VGPR118, VGPR119, 136 VGPR120, VGPR121, VGPR122, VGPR123, VGPR124, VGPR125, VGPR126, VGPR127, 137 VGPR128, VGPR129, VGPR130, VGPR131, VGPR132, VGPR133, VGPR134, VGPR135 138 ]>> 139 ]>; 140 141 def CSR_AMDGPU_VGPRs_24_255 : CalleeSavedRegs< 142 (sequence "VGPR%u", 24, 255) 143 >; 144 145 def CSR_AMDGPU_VGPRs_32_255 : CalleeSavedRegs< 146 (sequence "VGPR%u", 32, 255) 147 >; 148 149 def CSR_AMDGPU_VGPRs : CalleeSavedRegs< 150 // The CSRs & scratch-registers are interleaved at a split boundary of 8. 151 (add (sequence "VGPR%u", 40, 47), 152 (sequence "VGPR%u", 56, 63), 153 (sequence "VGPR%u", 72, 79), 154 (sequence "VGPR%u", 88, 95), 155 (sequence "VGPR%u", 104, 111), 156 (sequence "VGPR%u", 120, 127), 157 (sequence "VGPR%u", 136, 143), 158 (sequence "VGPR%u", 152, 159), 159 (sequence "VGPR%u", 168, 175), 160 (sequence "VGPR%u", 184, 191), 161 (sequence "VGPR%u", 200, 207), 162 (sequence "VGPR%u", 216, 223), 163 (sequence "VGPR%u", 232, 239), 164 (sequence "VGPR%u", 248, 255)) 165 >; 166 167 def CSR_AMDGPU_AGPRs_32_255 : CalleeSavedRegs< 168 (sequence "AGPR%u", 32, 255) 169 >; 170 171 def CSR_AMDGPU_SGPRs_32_105 : CalleeSavedRegs< 172 (sequence "SGPR%u", 32, 105) 173 >; 174 175 // Just to get the regmask, not for calling convention purposes. 176 def CSR_AMDGPU_AllVGPRs : CalleeSavedRegs< 177 (sequence "VGPR%u", 0, 255) 178 >; 179 180 def CSR_AMDGPU_AllAGPRs : CalleeSavedRegs< 181 (sequence "AGPR%u", 0, 255) 182 >; 183 def CSR_AMDGPU_AllVectorRegs : CalleeSavedRegs< 184 (add CSR_AMDGPU_AllVGPRs, CSR_AMDGPU_AllAGPRs) 185 >; 186 187 // Just to get the regmask, not for calling convention purposes. 188 def CSR_AMDGPU_AllAllocatableSRegs : CalleeSavedRegs< 189 (add (sequence "SGPR%u", 0, 105), VCC_LO, VCC_HI) 190 >; 191 192 def CSR_AMDGPU_HighRegs : CalleeSavedRegs< 193 (add CSR_AMDGPU_VGPRs, CSR_AMDGPU_SGPRs_32_105) 194 >; 195 196 def CSR_AMDGPU_HighRegs_With_AGPRs : CalleeSavedRegs< 197 (add CSR_AMDGPU_HighRegs, CSR_AMDGPU_AGPRs_32_255) 198 >; 199 200 def CSR_AMDGPU_NoRegs : CalleeSavedRegs<(add)>; 201 202 // Calling convention for leaf functions 203 def CC_AMDGPU_Func : CallingConv<[ 204 CCIfByVal<CCPassByVal<4, 4>>, 205 CCIfType<[i1], CCPromoteToType<i32>>, 206 CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>, 207 CCIfType<[i32, f32, i16, f16, v2i16, v2f16, i1], CCAssignToReg<[ 208 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 209 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 210 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 211 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>, 212 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>> 213 ]>; 214 215 // Calling convention for leaf functions 216 def RetCC_AMDGPU_Func : CallingConv<[ 217 CCIfType<[i1], CCPromoteToType<i32>>, 218 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>, 219 CCIfType<[i32, f32, i16, f16, v2i16, v2f16], CCAssignToReg<[ 220 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 221 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 222 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 223 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31]>>, 224 ]>; 225 226 def CC_AMDGPU : CallingConv<[ 227 CCIf<"static_cast<const GCNSubtarget&>" 228 "(State.getMachineFunction().getSubtarget()).getGeneration() >= " 229 "AMDGPUSubtarget::SOUTHERN_ISLANDS", 230 CCDelegateTo<CC_SI_SHADER>>, 231 CCIf<"static_cast<const GCNSubtarget&>" 232 "(State.getMachineFunction().getSubtarget()).getGeneration() >= " 233 "AMDGPUSubtarget::SOUTHERN_ISLANDS && State.getCallingConv() == CallingConv::C", 234 CCDelegateTo<CC_AMDGPU_Func>> 235 ]>; 236
Indexes created Sat Feb 28 05:31:39 UTC 2026