1 @section Relocations 2 BFD maintains relocations in much the same way it maintains 3 symbols: they are left alone until required, then read in 4 en-masse and translated into an internal form. A common 5 routine @code{bfd_perform_relocation} acts upon the 6 canonical form to do the fixup. 7 8 Relocations are maintained on a per section basis, 9 while symbols are maintained on a per BFD basis. 10 11 All that a back end has to do to fit the BFD interface is to create 12 a @code{struct reloc_cache_entry} for each relocation 13 in a particular section, and fill in the right bits of the structures. 14 15 @menu 16 * typedef arelent:: 17 * howto manager:: 18 @end menu 19 20 21 @node typedef arelent, howto manager, Relocations, Relocations 22 @subsection typedef arelent 23 This is the structure of a relocation entry: 24 25 26 @example 27 struct reloc_cache_entry 28 @{ 29 /* A pointer into the canonical table of pointers. */ 30 struct bfd_symbol **sym_ptr_ptr; 31 32 /* offset in section. */ 33 bfd_size_type address; 34 35 /* addend for relocation value. */ 36 bfd_vma addend; 37 38 /* Pointer to how to perform the required relocation. */ 39 reloc_howto_type *howto; 40 41 @}; 42 43 @end example 44 Here is a description of each of the fields within an @code{arelent}: 45 46 @itemize @bullet 47 48 @item 49 @code{sym_ptr_ptr} 50 @end itemize 51 The symbol table pointer points to a pointer to the symbol 52 associated with the relocation request. It is the pointer 53 into the table returned by the back end's 54 @code{canonicalize_symtab} action. @xref{Symbols}. The symbol is 55 referenced through a pointer to a pointer so that tools like 56 the linker can fix up all the symbols of the same name by 57 modifying only one pointer. The relocation routine looks in 58 the symbol and uses the base of the section the symbol is 59 attached to and the value of the symbol as the initial 60 relocation offset. If the symbol pointer is zero, then the 61 section provided is looked up. 62 63 @itemize @bullet 64 65 @item 66 @code{address} 67 @end itemize 68 The @code{address} field gives the offset in bytes from the base of 69 the section data which owns the relocation record to the first 70 byte of relocatable information. The actual data relocated 71 will be relative to this point; for example, a relocation 72 type which modifies the bottom two bytes of a four byte word 73 would not touch the first byte pointed to in a big endian 74 world. 75 76 @itemize @bullet 77 78 @item 79 @code{addend} 80 @end itemize 81 The @code{addend} is a value provided by the back end to be added (!) 82 to the relocation offset. Its interpretation is dependent upon 83 the howto. For example, on the 68k the code: 84 85 @example 86 char foo[]; 87 main() 88 @{ 89 return foo[0x12345678]; 90 @} 91 @end example 92 93 Could be compiled into: 94 95 @example 96 linkw fp,#-4 97 moveb @@#12345678,d0 98 extbl d0 99 unlk fp 100 rts 101 @end example 102 103 This could create a reloc pointing to @code{foo}, but leave the 104 offset in the data, something like: 105 106 @example 107 RELOCATION RECORDS FOR [.text]: 108 offset type value 109 00000006 32 _foo 110 111 00000000 4e56 fffc ; linkw fp,#-4 112 00000004 1039 1234 5678 ; moveb @@#12345678,d0 113 0000000a 49c0 ; extbl d0 114 0000000c 4e5e ; unlk fp 115 0000000e 4e75 ; rts 116 @end example 117 118 Using coff and an 88k, some instructions don't have enough 119 space in them to represent the full address range, and 120 pointers have to be loaded in two parts. So you'd get something like: 121 122 @example 123 or.u r13,r0,hi16(_foo+0x12345678) 124 ld.b r2,r13,lo16(_foo+0x12345678) 125 jmp r1 126 @end example 127 128 This should create two relocs, both pointing to @code{_foo}, and with 129 0x12340000 in their addend field. The data would consist of: 130 131 @example 132 RELOCATION RECORDS FOR [.text]: 133 offset type value 134 00000002 HVRT16 _foo+0x12340000 135 00000006 LVRT16 _foo+0x12340000 136 137 00000000 5da05678 ; or.u r13,r0,0x5678 138 00000004 1c4d5678 ; ld.b r2,r13,0x5678 139 00000008 f400c001 ; jmp r1 140 @end example 141 142 The relocation routine digs out the value from the data, adds 143 it to the addend to get the original offset, and then adds the 144 value of @code{_foo}. Note that all 32 bits have to be kept around 145 somewhere, to cope with carry from bit 15 to bit 16. 146 147 One further example is the sparc and the a.out format. The 148 sparc has a similar problem to the 88k, in that some 149 instructions don't have room for an entire offset, but on the 150 sparc the parts are created in odd sized lumps. The designers of 151 the a.out format chose to not use the data within the section 152 for storing part of the offset; all the offset is kept within 153 the reloc. Anything in the data should be ignored. 154 155 @example 156 save %sp,-112,%sp 157 sethi %hi(_foo+0x12345678),%g2 158 ldsb [%g2+%lo(_foo+0x12345678)],%i0 159 ret 160 restore 161 @end example 162 163 Both relocs contain a pointer to @code{foo}, and the offsets 164 contain junk. 165 166 @example 167 RELOCATION RECORDS FOR [.text]: 168 offset type value 169 00000004 HI22 _foo+0x12345678 170 00000008 LO10 _foo+0x12345678 171 172 00000000 9de3bf90 ; save %sp,-112,%sp 173 00000004 05000000 ; sethi %hi(_foo+0),%g2 174 00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0 175 0000000c 81c7e008 ; ret 176 00000010 81e80000 ; restore 177 @end example 178 179 @itemize @bullet 180 181 @item 182 @code{howto} 183 @end itemize 184 The @code{howto} field can be imagined as a 185 relocation instruction. It is a pointer to a structure which 186 contains information on what to do with all of the other 187 information in the reloc record and data section. A back end 188 would normally have a relocation instruction set and turn 189 relocations into pointers to the correct structure on input - 190 but it would be possible to create each howto field on demand. 191 192 @subsubsection @code{enum complain_overflow} 193 Indicates what sort of overflow checking should be done when 194 performing a relocation. 195 196 197 @example 198 enum complain_overflow 199 @{ 200 /* Do not complain on overflow. */ 201 complain_overflow_dont, 202 203 /* Complain if the value overflows when considered as a signed 204 number one bit larger than the field. ie. A bitfield of N bits 205 is allowed to represent -2**n to 2**n-1. */ 206 complain_overflow_bitfield, 207 208 /* Complain if the value overflows when considered as a signed 209 number. */ 210 complain_overflow_signed, 211 212 /* Complain if the value overflows when considered as an 213 unsigned number. */ 214 complain_overflow_unsigned 215 @}; 216 217 @end example 218 @subsubsection @code{reloc_howto_type} 219 The @code{reloc_howto_type} is a structure which contains all the 220 information that libbfd needs to know to tie up a back end's data. 221 222 223 @example 224 struct reloc_howto_struct 225 @{ 226 /* The type field has mainly a documentary use - the back end can 227 do what it wants with it, though normally the back end's idea of 228 an external reloc number is stored in this field. */ 229 unsigned int type; 230 231 /* The size of the item to be relocated in bytes. */ 232 unsigned int size:4; 233 234 /* The number of bits in the field to be relocated. This is used 235 when doing overflow checking. */ 236 unsigned int bitsize:7; 237 238 /* The value the final relocation is shifted right by. This drops 239 unwanted data from the relocation. */ 240 unsigned int rightshift:6; 241 242 /* The bit position of the reloc value in the destination. 243 The relocated value is left shifted by this amount. */ 244 unsigned int bitpos:6; 245 246 /* What type of overflow error should be checked for when 247 relocating. */ 248 ENUM_BITFIELD (complain_overflow) complain_on_overflow:2; 249 250 /* The relocation value should be negated before applying. */ 251 unsigned int negate:1; 252 253 /* The relocation is relative to the item being relocated. */ 254 unsigned int pc_relative:1; 255 256 /* Some formats record a relocation addend in the section contents 257 rather than with the relocation. For ELF formats this is the 258 distinction between USE_REL and USE_RELA (though the code checks 259 for USE_REL == 1/0). The value of this field is TRUE if the 260 addend is recorded with the section contents; when performing a 261 partial link (ld -r) the section contents (the data) will be 262 modified. The value of this field is FALSE if addends are 263 recorded with the relocation (in arelent.addend); when performing 264 a partial link the relocation will be modified. 265 All relocations for all ELF USE_RELA targets should set this field 266 to FALSE (values of TRUE should be looked on with suspicion). 267 However, the converse is not true: not all relocations of all ELF 268 USE_REL targets set this field to TRUE. Why this is so is peculiar 269 to each particular target. For relocs that aren't used in partial 270 links (e.g. GOT stuff) it doesn't matter what this is set to. */ 271 unsigned int partial_inplace:1; 272 273 /* When some formats create PC relative instructions, they leave 274 the value of the pc of the place being relocated in the offset 275 slot of the instruction, so that a PC relative relocation can 276 be made just by adding in an ordinary offset (e.g., sun3 a.out). 277 Some formats leave the displacement part of an instruction 278 empty (e.g., ELF); this flag signals the fact. */ 279 unsigned int pcrel_offset:1; 280 281 /* Whether bfd_install_relocation should just install the addend, 282 or should follow the practice of some older object formats and 283 install a value including the symbol. */ 284 unsigned int install_addend:1; 285 286 /* src_mask selects the part of the instruction (or data) to be used 287 in the relocation sum. If the target relocations don't have an 288 addend in the reloc, eg. ELF USE_REL, src_mask will normally equal 289 dst_mask to extract the addend from the section contents. If 290 relocations do have an addend in the reloc, eg. ELF USE_RELA, this 291 field should normally be zero. Non-zero values for ELF USE_RELA 292 targets should be viewed with suspicion as normally the value in 293 the dst_mask part of the section contents should be ignored. */ 294 bfd_vma src_mask; 295 296 /* dst_mask selects which parts of the instruction (or data) are 297 replaced with a relocated value. */ 298 bfd_vma dst_mask; 299 300 /* If this field is non null, then the supplied function is 301 called rather than the normal function. This allows really 302 strange relocation methods to be accommodated. */ 303 bfd_reloc_status_type (*special_function) 304 (bfd *, arelent *, struct bfd_symbol *, void *, asection *, 305 bfd *, char **); 306 307 /* The textual name of the relocation type. */ 308 const char *name; 309 @}; 310 311 @end example 312 @findex The HOWTO Macro 313 @subsubsection @code{The HOWTO Macro} 314 The HOWTO macro fills in a reloc_howto_type (a typedef for 315 const struct reloc_howto_struct). 316 @example 317 #define HOWTO_INSTALL_ADDEND 0 318 #define HOWTO_RSIZE(sz) ((sz) < 0 ? -(sz) : (sz)) 319 #define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \ 320 inplace, src_mask, dst_mask, pcrel_off) \ 321 @{ (unsigned) type, HOWTO_RSIZE (size), bits, right, left, ovf, \ 322 size < 0, pcrel, inplace, pcrel_off, HOWTO_INSTALL_ADDEND, \ 323 src_mask, dst_mask, func, name @} 324 @end example 325 326 This is used to fill in an empty howto entry in an array. 327 @example 328 #define EMPTY_HOWTO(C) \ 329 HOWTO ((C), 0, 1, 0, false, 0, complain_overflow_dont, NULL, \ 330 NULL, false, 0, 0, false) 331 332 static inline unsigned int 333 bfd_get_reloc_size (reloc_howto_type *howto) 334 @{ 335 return howto->size; 336 @} 337 338 @end example 339 340 @findex arelent_chain 341 @subsubsection @code{arelent_chain} 342 How relocs are tied together in an @code{asection}: 343 @example 344 typedef struct relent_chain 345 @{ 346 arelent relent; 347 struct relent_chain *next; 348 @} 349 arelent_chain; 350 351 @end example 352 353 @findex bfd_check_overflow 354 @subsubsection @code{bfd_check_overflow} 355 @deftypefn {Function} bfd_reloc_status_type bfd_check_overflow (enum complain_overflow how, unsigned int bitsize, unsigned int rightshift, unsigned int addrsize, bfd_vma relocation); 356 Perform overflow checking on @var{relocation} which has 357 @var{bitsize} significant bits and will be shifted right by 358 @var{rightshift} bits, on a machine with addresses containing 359 @var{addrsize} significant bits. The result is either of 360 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}. 361 362 @end deftypefn 363 @findex bfd_reloc_offset_in_range 364 @subsubsection @code{bfd_reloc_offset_in_range} 365 @deftypefn {Function} bool bfd_reloc_offset_in_range (reloc_howto_type *howto, bfd *abfd, asection *section, bfd_size_type offset); 366 Returns TRUE if the reloc described by @var{HOWTO} can be 367 applied at @var{OFFSET} octets in @var{SECTION}. 368 369 @end deftypefn 370 @findex bfd_perform_relocation 371 @subsubsection @code{bfd_perform_relocation} 372 @deftypefn {Function} bfd_reloc_status_type bfd_perform_relocation (bfd *abfd, arelent *reloc_entry, void *data, asection *input_section, bfd *output_bfd, char **error_message); 373 If @var{output_bfd} is supplied to this function, the 374 generated image will be relocatable; the relocations are 375 copied to the output file after they have been changed to 376 reflect the new state of the world. There are two ways of 377 reflecting the results of partial linkage in an output file: 378 by modifying the output data in place, and by modifying the 379 relocation record. Some native formats (e.g., basic a.out and 380 basic coff) have no way of specifying an addend in the 381 relocation type, so the addend has to go in the output data. 382 This is no big deal since in these formats the output data 383 slot will always be big enough for the addend. Complex reloc 384 types with addends were invented to solve just this problem. 385 The @var{error_message} argument is set to an error message if 386 this return @code{bfd_reloc_dangerous}. 387 388 @end deftypefn 389 @findex bfd_install_relocation 390 @subsubsection @code{bfd_install_relocation} 391 @deftypefn {Function} bfd_reloc_status_type bfd_install_relocation (bfd *abfd, arelent *reloc_entry, void *data, bfd_vma data_start, asection *input_section, char **error_message); 392 This looks remarkably like @code{bfd_perform_relocation}, except it 393 does not expect that the section contents have been filled in. 394 I.e., it's suitable for use when creating, rather than applying 395 a relocation. 396 397 For now, this function should be considered reserved for the 398 assembler. 399 400 @end deftypefn 401 402 @node howto manager, , typedef arelent, Relocations 403 @subsection The howto manager 404 When an application wants to create a relocation, but doesn't 405 know what the target machine might call it, it can find out by 406 using this bit of code. 407 408 @findex bfd_reloc_code_real_type 409 @subsubsection @code{bfd_reloc_code_real_type} 410 The insides of a reloc code. The idea is that, eventually, there 411 will be one enumerator for every type of relocation we ever do. 412 Pass one of these values to @code{bfd_reloc_type_lookup}, and it'll 413 return a howto pointer. 414 415 This does mean that the application must determine the correct 416 enumerator value; you can't get a howto pointer from a random set 417 of attributes. 418 419 Here are the possible values for @code{enum bfd_reloc_code_real}: 420 421 @deffn {} BFD_RELOC_64 422 @deffnx {} BFD_RELOC_32 423 @deffnx {} BFD_RELOC_26 424 @deffnx {} BFD_RELOC_24 425 @deffnx {} BFD_RELOC_16 426 @deffnx {} BFD_RELOC_14 427 @deffnx {} BFD_RELOC_8 428 Basic absolute relocations of N bits. 429 @end deffn 430 @deffn {} BFD_RELOC_64_PCREL 431 @deffnx {} BFD_RELOC_32_PCREL 432 @deffnx {} BFD_RELOC_24_PCREL 433 @deffnx {} BFD_RELOC_16_PCREL 434 @deffnx {} BFD_RELOC_12_PCREL 435 @deffnx {} BFD_RELOC_8_PCREL 436 PC-relative relocations. Sometimes these are relative to the 437 address of the relocation itself; sometimes they are relative to the 438 start of the section containing the relocation. It depends on the 439 specific target. 440 @end deffn 441 @deffn {} BFD_RELOC_32_SECREL 442 @deffnx {} BFD_RELOC_16_SECIDX 443 Section relative relocations. Some targets need this for DWARF2. 444 @end deffn 445 @deffn {} BFD_RELOC_32_GOT_PCREL 446 @deffnx {} BFD_RELOC_16_GOT_PCREL 447 @deffnx {} BFD_RELOC_8_GOT_PCREL 448 @deffnx {} BFD_RELOC_32_GOTOFF 449 @deffnx {} BFD_RELOC_16_GOTOFF 450 @deffnx {} BFD_RELOC_LO16_GOTOFF 451 @deffnx {} BFD_RELOC_HI16_GOTOFF 452 @deffnx {} BFD_RELOC_HI16_S_GOTOFF 453 @deffnx {} BFD_RELOC_8_GOTOFF 454 @deffnx {} BFD_RELOC_64_PLT_PCREL 455 @deffnx {} BFD_RELOC_32_PLT_PCREL 456 @deffnx {} BFD_RELOC_24_PLT_PCREL 457 @deffnx {} BFD_RELOC_16_PLT_PCREL 458 @deffnx {} BFD_RELOC_8_PLT_PCREL 459 @deffnx {} BFD_RELOC_64_PLTOFF 460 @deffnx {} BFD_RELOC_32_PLTOFF 461 @deffnx {} BFD_RELOC_16_PLTOFF 462 @deffnx {} BFD_RELOC_LO16_PLTOFF 463 @deffnx {} BFD_RELOC_HI16_PLTOFF 464 @deffnx {} BFD_RELOC_HI16_S_PLTOFF 465 @deffnx {} BFD_RELOC_8_PLTOFF 466 For ELF. 467 @end deffn 468 @deffn {} BFD_RELOC_SIZE32 469 @deffnx {} BFD_RELOC_SIZE64 470 Size relocations. 471 @end deffn 472 @deffn {} BFD_RELOC_68K_GLOB_DAT 473 @deffnx {} BFD_RELOC_68K_JMP_SLOT 474 @deffnx {} BFD_RELOC_68K_RELATIVE 475 @deffnx {} BFD_RELOC_68K_TLS_GD32 476 @deffnx {} BFD_RELOC_68K_TLS_GD16 477 @deffnx {} BFD_RELOC_68K_TLS_GD8 478 @deffnx {} BFD_RELOC_68K_TLS_LDM32 479 @deffnx {} BFD_RELOC_68K_TLS_LDM16 480 @deffnx {} BFD_RELOC_68K_TLS_LDM8 481 @deffnx {} BFD_RELOC_68K_TLS_LDO32 482 @deffnx {} BFD_RELOC_68K_TLS_LDO16 483 @deffnx {} BFD_RELOC_68K_TLS_LDO8 484 @deffnx {} BFD_RELOC_68K_TLS_IE32 485 @deffnx {} BFD_RELOC_68K_TLS_IE16 486 @deffnx {} BFD_RELOC_68K_TLS_IE8 487 @deffnx {} BFD_RELOC_68K_TLS_LE32 488 @deffnx {} BFD_RELOC_68K_TLS_LE16 489 @deffnx {} BFD_RELOC_68K_TLS_LE8 490 Relocations used by 68K ELF. 491 @end deffn 492 @deffn {} BFD_RELOC_VAX_GLOB_DAT 493 @deffnx {} BFD_RELOC_VAX_GLOB_REF 494 @deffnx {} BFD_RELOC_VAX_JMP_SLOT 495 @deffnx {} BFD_RELOC_VAX_RELATIVE 496 Relocations used by VAX ELF. 497 @end deffn 498 @deffn {} BFD_RELOC_32_BASEREL 499 @deffnx {} BFD_RELOC_16_BASEREL 500 @deffnx {} BFD_RELOC_LO16_BASEREL 501 @deffnx {} BFD_RELOC_HI16_BASEREL 502 @deffnx {} BFD_RELOC_HI16_S_BASEREL 503 @deffnx {} BFD_RELOC_8_BASEREL 504 @deffnx {} BFD_RELOC_RVA 505 Linkage-table relative. 506 @end deffn 507 @deffn {} BFD_RELOC_8_FFnn 508 Absolute 8-bit relocation, but used to form an address like 0xFFnn. 509 @end deffn 510 @deffn {} BFD_RELOC_32_PCREL_S2 511 @deffnx {} BFD_RELOC_16_PCREL_S2 512 @deffnx {} BFD_RELOC_23_PCREL_S2 513 These PC-relative relocations are stored as word displacements -- 514 i.e., byte displacements shifted right two bits. The 30-bit word 515 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the 516 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The 517 signed 16-bit displacement is used on the MIPS, and the 23-bit 518 displacement is used on the Alpha. 519 @end deffn 520 @deffn {} BFD_RELOC_HI22 521 @deffnx {} BFD_RELOC_LO10 522 High 22 bits and low 10 bits of 32-bit value, placed into lower bits 523 of the target word. These are used on the SPARC. 524 @end deffn 525 @deffn {} BFD_RELOC_GPREL16 526 @deffnx {} BFD_RELOC_GPREL32 527 For systems that allocate a Global Pointer register, these are 528 displacements off that register. These relocation types are 529 handled specially, because the value the register will have is 530 decided relatively late. 531 @end deffn 532 @deffn {} BFD_RELOC_NONE 533 @deffnx {} BFD_RELOC_SPARC_WDISP22 534 @deffnx {} BFD_RELOC_SPARC22 535 @deffnx {} BFD_RELOC_SPARC13 536 @deffnx {} BFD_RELOC_SPARC_GOT10 537 @deffnx {} BFD_RELOC_SPARC_GOT13 538 @deffnx {} BFD_RELOC_SPARC_GOT22 539 @deffnx {} BFD_RELOC_SPARC_PC10 540 @deffnx {} BFD_RELOC_SPARC_PC22 541 @deffnx {} BFD_RELOC_SPARC_WPLT30 542 @deffnx {} BFD_RELOC_SPARC_COPY 543 @deffnx {} BFD_RELOC_SPARC_GLOB_DAT 544 @deffnx {} BFD_RELOC_SPARC_JMP_SLOT 545 @deffnx {} BFD_RELOC_SPARC_RELATIVE 546 @deffnx {} BFD_RELOC_SPARC_UA16 547 @deffnx {} BFD_RELOC_SPARC_UA32 548 @deffnx {} BFD_RELOC_SPARC_UA64 549 @deffnx {} BFD_RELOC_SPARC_GOTDATA_HIX22 550 @deffnx {} BFD_RELOC_SPARC_GOTDATA_LOX10 551 @deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_HIX22 552 @deffnx {} BFD_RELOC_SPARC_GOTDATA_OP_LOX10 553 @deffnx {} BFD_RELOC_SPARC_GOTDATA_OP 554 @deffnx {} BFD_RELOC_SPARC_JMP_IREL 555 @deffnx {} BFD_RELOC_SPARC_IRELATIVE 556 SPARC ELF relocations. There is probably some overlap with other 557 relocation types already defined. 558 @end deffn 559 @deffn {} BFD_RELOC_SPARC_BASE13 560 @deffnx {} BFD_RELOC_SPARC_BASE22 561 I think these are specific to SPARC a.out (e.g., Sun 4). 562 @end deffn 563 @deffn {} BFD_RELOC_SPARC_64 564 @deffnx {} BFD_RELOC_SPARC_10 565 @deffnx {} BFD_RELOC_SPARC_11 566 @deffnx {} BFD_RELOC_SPARC_OLO10 567 @deffnx {} BFD_RELOC_SPARC_HH22 568 @deffnx {} BFD_RELOC_SPARC_HM10 569 @deffnx {} BFD_RELOC_SPARC_LM22 570 @deffnx {} BFD_RELOC_SPARC_PC_HH22 571 @deffnx {} BFD_RELOC_SPARC_PC_HM10 572 @deffnx {} BFD_RELOC_SPARC_PC_LM22 573 @deffnx {} BFD_RELOC_SPARC_WDISP16 574 @deffnx {} BFD_RELOC_SPARC_WDISP19 575 @deffnx {} BFD_RELOC_SPARC_7 576 @deffnx {} BFD_RELOC_SPARC_6 577 @deffnx {} BFD_RELOC_SPARC_5 578 @deffnx {} BFD_RELOC_SPARC_DISP64 579 @deffnx {} BFD_RELOC_SPARC_PLT32 580 @deffnx {} BFD_RELOC_SPARC_PLT64 581 @deffnx {} BFD_RELOC_SPARC_HIX22 582 @deffnx {} BFD_RELOC_SPARC_LOX10 583 @deffnx {} BFD_RELOC_SPARC_H44 584 @deffnx {} BFD_RELOC_SPARC_M44 585 @deffnx {} BFD_RELOC_SPARC_L44 586 @deffnx {} BFD_RELOC_SPARC_REGISTER 587 @deffnx {} BFD_RELOC_SPARC_H34 588 @deffnx {} BFD_RELOC_SPARC_SIZE32 589 @deffnx {} BFD_RELOC_SPARC_SIZE64 590 @deffnx {} BFD_RELOC_SPARC_WDISP10 591 SPARC64 relocations. 592 @end deffn 593 @deffn {} BFD_RELOC_SPARC_REV32 594 SPARC little endian relocation. 595 @end deffn 596 @deffn {} BFD_RELOC_SPARC_TLS_GD_HI22 597 @deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10 598 @deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD 599 @deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL 600 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22 601 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_LO10 602 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_ADD 603 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_CALL 604 @deffnx {} BFD_RELOC_SPARC_TLS_LDO_HIX22 605 @deffnx {} BFD_RELOC_SPARC_TLS_LDO_LOX10 606 @deffnx {} BFD_RELOC_SPARC_TLS_LDO_ADD 607 @deffnx {} BFD_RELOC_SPARC_TLS_IE_HI22 608 @deffnx {} BFD_RELOC_SPARC_TLS_IE_LO10 609 @deffnx {} BFD_RELOC_SPARC_TLS_IE_LD 610 @deffnx {} BFD_RELOC_SPARC_TLS_IE_LDX 611 @deffnx {} BFD_RELOC_SPARC_TLS_IE_ADD 612 @deffnx {} BFD_RELOC_SPARC_TLS_LE_HIX22 613 @deffnx {} BFD_RELOC_SPARC_TLS_LE_LOX10 614 @deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD32 615 @deffnx {} BFD_RELOC_SPARC_TLS_DTPMOD64 616 @deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF32 617 @deffnx {} BFD_RELOC_SPARC_TLS_DTPOFF64 618 @deffnx {} BFD_RELOC_SPARC_TLS_TPOFF32 619 @deffnx {} BFD_RELOC_SPARC_TLS_TPOFF64 620 SPARC TLS relocations. 621 @end deffn 622 @deffn {} BFD_RELOC_SPU_IMM7 623 @deffnx {} BFD_RELOC_SPU_IMM8 624 @deffnx {} BFD_RELOC_SPU_IMM10 625 @deffnx {} BFD_RELOC_SPU_IMM10W 626 @deffnx {} BFD_RELOC_SPU_IMM16 627 @deffnx {} BFD_RELOC_SPU_IMM16W 628 @deffnx {} BFD_RELOC_SPU_IMM18 629 @deffnx {} BFD_RELOC_SPU_PCREL9a 630 @deffnx {} BFD_RELOC_SPU_PCREL9b 631 @deffnx {} BFD_RELOC_SPU_PCREL16 632 @deffnx {} BFD_RELOC_SPU_LO16 633 @deffnx {} BFD_RELOC_SPU_HI16 634 @deffnx {} BFD_RELOC_SPU_PPU32 635 @deffnx {} BFD_RELOC_SPU_PPU64 636 @deffnx {} BFD_RELOC_SPU_ADD_PIC 637 SPU Relocations. 638 @end deffn 639 @deffn {} BFD_RELOC_ALPHA_GPDISP_HI16 640 Alpha ECOFF and ELF relocations. Some of these treat the symbol or 641 "addend" in some special way. 642 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when 643 writing; when reading, it will be the absolute section symbol. The 644 addend is the displacement in bytes of the "lda" instruction from 645 the "ldah" instruction (which is at the address of this reloc). 646 @end deffn 647 @deffn {} BFD_RELOC_ALPHA_GPDISP_LO16 648 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as 649 with GPDISP_HI16 relocs. The addend is ignored when writing the 650 relocations out, and is filled in with the file's GP value on 651 reading, for convenience. 652 @end deffn 653 @deffn {} BFD_RELOC_ALPHA_GPDISP 654 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16 655 relocation except that there is no accompanying GPDISP_LO16 656 relocation. 657 @end deffn 658 @deffn {} BFD_RELOC_ALPHA_LITERAL 659 @deffnx {} BFD_RELOC_ALPHA_ELF_LITERAL 660 @deffnx {} BFD_RELOC_ALPHA_LITUSE 661 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference; 662 the assembler turns it into a LDQ instruction to load the address of 663 the symbol, and then fills in a register in the real instruction. 664 665 The LITERAL reloc, at the LDQ instruction, refers to the .lita 666 section symbol. The addend is ignored when writing, but is filled 667 in with the file's GP value on reading, for convenience, as with the 668 GPDISP_LO16 reloc. 669 670 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16. 671 It should refer to the symbol to be referenced, as with 16_GOTOFF, 672 but it generates output not based on the position within the .got 673 section, but relative to the GP value chosen for the file during the 674 final link stage. 675 676 The LITUSE reloc, on the instruction using the loaded address, gives 677 information to the linker that it might be able to use to optimize 678 away some literal section references. The symbol is ignored (read 679 as the absolute section symbol), and the "addend" indicates the type 680 of instruction using the register: 681 1 - "memory" fmt insn 682 2 - byte-manipulation (byte offset reg) 683 3 - jsr (target of branch) 684 @end deffn 685 @deffn {} BFD_RELOC_ALPHA_HINT 686 The HINT relocation indicates a value that should be filled into the 687 "hint" field of a jmp/jsr/ret instruction, for possible branch- 688 prediction logic which may be provided on some processors. 689 @end deffn 690 @deffn {} BFD_RELOC_ALPHA_LINKAGE 691 The LINKAGE relocation outputs a linkage pair in the object file, 692 which is filled by the linker. 693 @end deffn 694 @deffn {} BFD_RELOC_ALPHA_CODEADDR 695 The CODEADDR relocation outputs a STO_CA in the object file, 696 which is filled by the linker. 697 @end deffn 698 @deffn {} BFD_RELOC_ALPHA_GPREL_HI16 699 @deffnx {} BFD_RELOC_ALPHA_GPREL_LO16 700 The GPREL_HI/LO relocations together form a 32-bit offset from the 701 GP register. 702 @end deffn 703 @deffn {} BFD_RELOC_ALPHA_BRSGP 704 Like BFD_RELOC_23_PCREL_S2, except that the source and target must 705 share a common GP, and the target address is adjusted for 706 STO_ALPHA_STD_GPLOAD. 707 @end deffn 708 @deffn {} BFD_RELOC_ALPHA_NOP 709 The NOP relocation outputs a NOP if the longword displacement 710 between two procedure entry points is < 2^21. 711 @end deffn 712 @deffn {} BFD_RELOC_ALPHA_BSR 713 The BSR relocation outputs a BSR if the longword displacement 714 between two procedure entry points is < 2^21. 715 @end deffn 716 @deffn {} BFD_RELOC_ALPHA_LDA 717 The LDA relocation outputs a LDA if the longword displacement 718 between two procedure entry points is < 2^16. 719 @end deffn 720 @deffn {} BFD_RELOC_ALPHA_BOH 721 The BOH relocation outputs a BSR if the longword displacement 722 between two procedure entry points is < 2^21, or else a hint. 723 @end deffn 724 @deffn {} BFD_RELOC_ALPHA_TLSGD 725 @deffnx {} BFD_RELOC_ALPHA_TLSLDM 726 @deffnx {} BFD_RELOC_ALPHA_DTPMOD64 727 @deffnx {} BFD_RELOC_ALPHA_GOTDTPREL16 728 @deffnx {} BFD_RELOC_ALPHA_DTPREL64 729 @deffnx {} BFD_RELOC_ALPHA_DTPREL_HI16 730 @deffnx {} BFD_RELOC_ALPHA_DTPREL_LO16 731 @deffnx {} BFD_RELOC_ALPHA_DTPREL16 732 @deffnx {} BFD_RELOC_ALPHA_GOTTPREL16 733 @deffnx {} BFD_RELOC_ALPHA_TPREL64 734 @deffnx {} BFD_RELOC_ALPHA_TPREL_HI16 735 @deffnx {} BFD_RELOC_ALPHA_TPREL_LO16 736 @deffnx {} BFD_RELOC_ALPHA_TPREL16 737 Alpha thread-local storage relocations. 738 @end deffn 739 @deffn {} BFD_RELOC_MIPS_JMP 740 @deffnx {} BFD_RELOC_MICROMIPS_JMP 741 The MIPS jump instruction. 742 @end deffn 743 @deffn {} BFD_RELOC_MIPS16_JMP 744 The MIPS16 jump instruction. 745 @end deffn 746 @deffn {} BFD_RELOC_MIPS16_GPREL 747 MIPS16 GP relative reloc. 748 @end deffn 749 @deffn {} BFD_RELOC_HI16 750 High 16 bits of 32-bit value; simple reloc. 751 @end deffn 752 @deffn {} BFD_RELOC_HI16_S 753 High 16 bits of 32-bit value but the low 16 bits will be sign 754 extended and added to form the final result. If the low 16 755 bits form a negative number, we need to add one to the high value 756 to compensate for the borrow when the low bits are added. 757 @end deffn 758 @deffn {} BFD_RELOC_LO16 759 Low 16 bits. 760 @end deffn 761 @deffn {} BFD_RELOC_HI16_PCREL 762 High 16 bits of 32-bit pc-relative value. 763 @end deffn 764 @deffn {} BFD_RELOC_HI16_S_PCREL 765 High 16 bits of 32-bit pc-relative value, adjusted. 766 @end deffn 767 @deffn {} BFD_RELOC_LO16_PCREL 768 Low 16 bits of pc-relative value. 769 @end deffn 770 @deffn {} BFD_RELOC_MIPS16_GOT16 771 @deffnx {} BFD_RELOC_MIPS16_CALL16 772 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of 773 16-bit immediate fields. 774 @end deffn 775 @deffn {} BFD_RELOC_MIPS16_HI16 776 MIPS16 high 16 bits of 32-bit value. 777 @end deffn 778 @deffn {} BFD_RELOC_MIPS16_HI16_S 779 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign 780 extended and added to form the final result. If the low 16 781 bits form a negative number, we need to add one to the high value 782 to compensate for the borrow when the low bits are added. 783 @end deffn 784 @deffn {} BFD_RELOC_MIPS16_LO16 785 MIPS16 low 16 bits. 786 @end deffn 787 @deffn {} BFD_RELOC_MIPS16_TLS_GD 788 @deffnx {} BFD_RELOC_MIPS16_TLS_LDM 789 @deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16 790 @deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16 791 @deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL 792 @deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16 793 @deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16 794 MIPS16 TLS relocations. 795 @end deffn 796 @deffn {} BFD_RELOC_MIPS_LITERAL 797 @deffnx {} BFD_RELOC_MICROMIPS_LITERAL 798 Relocation against a MIPS literal section. 799 @end deffn 800 @deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1 801 @deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1 802 @deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1 803 microMIPS PC-relative relocations. 804 @end deffn 805 @deffn {} BFD_RELOC_MIPS16_16_PCREL_S1 806 MIPS16 PC-relative relocation. 807 @end deffn 808 @deffn {} BFD_RELOC_MIPS_21_PCREL_S2 809 @deffnx {} BFD_RELOC_MIPS_26_PCREL_S2 810 @deffnx {} BFD_RELOC_MIPS_18_PCREL_S3 811 @deffnx {} BFD_RELOC_MIPS_19_PCREL_S2 812 MIPS PC-relative relocations. 813 @end deffn 814 @deffn {} BFD_RELOC_MICROMIPS_GPREL16 815 @deffnx {} BFD_RELOC_MICROMIPS_HI16 816 @deffnx {} BFD_RELOC_MICROMIPS_HI16_S 817 @deffnx {} BFD_RELOC_MICROMIPS_LO16 818 microMIPS versions of generic BFD relocs. 819 @end deffn 820 @deffn {} BFD_RELOC_MIPS_GOT16 821 @deffnx {} BFD_RELOC_MICROMIPS_GOT16 822 @deffnx {} BFD_RELOC_MIPS_CALL16 823 @deffnx {} BFD_RELOC_MICROMIPS_CALL16 824 @deffnx {} BFD_RELOC_MIPS_GOT_HI16 825 @deffnx {} BFD_RELOC_MICROMIPS_GOT_HI16 826 @deffnx {} BFD_RELOC_MIPS_GOT_LO16 827 @deffnx {} BFD_RELOC_MICROMIPS_GOT_LO16 828 @deffnx {} BFD_RELOC_MIPS_CALL_HI16 829 @deffnx {} BFD_RELOC_MICROMIPS_CALL_HI16 830 @deffnx {} BFD_RELOC_MIPS_CALL_LO16 831 @deffnx {} BFD_RELOC_MICROMIPS_CALL_LO16 832 @deffnx {} BFD_RELOC_MIPS_SUB 833 @deffnx {} BFD_RELOC_MICROMIPS_SUB 834 @deffnx {} BFD_RELOC_MIPS_GOT_PAGE 835 @deffnx {} BFD_RELOC_MICROMIPS_GOT_PAGE 836 @deffnx {} BFD_RELOC_MIPS_GOT_OFST 837 @deffnx {} BFD_RELOC_MICROMIPS_GOT_OFST 838 @deffnx {} BFD_RELOC_MIPS_GOT_DISP 839 @deffnx {} BFD_RELOC_MICROMIPS_GOT_DISP 840 @deffnx {} BFD_RELOC_MIPS_SHIFT5 841 @deffnx {} BFD_RELOC_MIPS_SHIFT6 842 @deffnx {} BFD_RELOC_MIPS_INSERT_A 843 @deffnx {} BFD_RELOC_MIPS_INSERT_B 844 @deffnx {} BFD_RELOC_MIPS_DELETE 845 @deffnx {} BFD_RELOC_MIPS_HIGHEST 846 @deffnx {} BFD_RELOC_MICROMIPS_HIGHEST 847 @deffnx {} BFD_RELOC_MIPS_HIGHER 848 @deffnx {} BFD_RELOC_MICROMIPS_HIGHER 849 @deffnx {} BFD_RELOC_MIPS_SCN_DISP 850 @deffnx {} BFD_RELOC_MICROMIPS_SCN_DISP 851 @deffnx {} BFD_RELOC_MIPS_16 852 @deffnx {} BFD_RELOC_MIPS_RELGOT 853 @deffnx {} BFD_RELOC_MIPS_JALR 854 @deffnx {} BFD_RELOC_MICROMIPS_JALR 855 @deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD32 856 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL32 857 @deffnx {} BFD_RELOC_MIPS_TLS_DTPMOD64 858 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL64 859 @deffnx {} BFD_RELOC_MIPS_TLS_GD 860 @deffnx {} BFD_RELOC_MICROMIPS_TLS_GD 861 @deffnx {} BFD_RELOC_MIPS_TLS_LDM 862 @deffnx {} BFD_RELOC_MICROMIPS_TLS_LDM 863 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_HI16 864 @deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16 865 @deffnx {} BFD_RELOC_MIPS_TLS_DTPREL_LO16 866 @deffnx {} BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16 867 @deffnx {} BFD_RELOC_MIPS_TLS_GOTTPREL 868 @deffnx {} BFD_RELOC_MICROMIPS_TLS_GOTTPREL 869 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL32 870 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL64 871 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL_HI16 872 @deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_HI16 873 @deffnx {} BFD_RELOC_MIPS_TLS_TPREL_LO16 874 @deffnx {} BFD_RELOC_MICROMIPS_TLS_TPREL_LO16 875 @deffnx {} BFD_RELOC_MIPS_EH 876 MIPS ELF relocations. 877 @end deffn 878 @deffn {} BFD_RELOC_MIPS_COPY 879 @deffnx {} BFD_RELOC_MIPS_JUMP_SLOT 880 MIPS ELF relocations (VxWorks and PLT extensions). 881 @end deffn 882 @deffn {} BFD_RELOC_MOXIE_10_PCREL 883 Moxie ELF relocations. 884 @end deffn 885 @deffn {} BFD_RELOC_FT32_10 886 @deffnx {} BFD_RELOC_FT32_20 887 @deffnx {} BFD_RELOC_FT32_17 888 @deffnx {} BFD_RELOC_FT32_18 889 @deffnx {} BFD_RELOC_FT32_RELAX 890 @deffnx {} BFD_RELOC_FT32_SC0 891 @deffnx {} BFD_RELOC_FT32_SC1 892 @deffnx {} BFD_RELOC_FT32_15 893 @deffnx {} BFD_RELOC_FT32_DIFF32 894 FT32 ELF relocations. 895 @end deffn 896 @deffn {} BFD_RELOC_FRV_LABEL16 897 @deffnx {} BFD_RELOC_FRV_LABEL24 898 @deffnx {} BFD_RELOC_FRV_LO16 899 @deffnx {} BFD_RELOC_FRV_HI16 900 @deffnx {} BFD_RELOC_FRV_GPREL12 901 @deffnx {} BFD_RELOC_FRV_GPRELU12 902 @deffnx {} BFD_RELOC_FRV_GPREL32 903 @deffnx {} BFD_RELOC_FRV_GPRELHI 904 @deffnx {} BFD_RELOC_FRV_GPRELLO 905 @deffnx {} BFD_RELOC_FRV_GOT12 906 @deffnx {} BFD_RELOC_FRV_GOTHI 907 @deffnx {} BFD_RELOC_FRV_GOTLO 908 @deffnx {} BFD_RELOC_FRV_FUNCDESC 909 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOT12 910 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTHI 911 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTLO 912 @deffnx {} BFD_RELOC_FRV_FUNCDESC_VALUE 913 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFF12 914 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFHI 915 @deffnx {} BFD_RELOC_FRV_FUNCDESC_GOTOFFLO 916 @deffnx {} BFD_RELOC_FRV_GOTOFF12 917 @deffnx {} BFD_RELOC_FRV_GOTOFFHI 918 @deffnx {} BFD_RELOC_FRV_GOTOFFLO 919 @deffnx {} BFD_RELOC_FRV_GETTLSOFF 920 @deffnx {} BFD_RELOC_FRV_TLSDESC_VALUE 921 @deffnx {} BFD_RELOC_FRV_GOTTLSDESC12 922 @deffnx {} BFD_RELOC_FRV_GOTTLSDESCHI 923 @deffnx {} BFD_RELOC_FRV_GOTTLSDESCLO 924 @deffnx {} BFD_RELOC_FRV_TLSMOFF12 925 @deffnx {} BFD_RELOC_FRV_TLSMOFFHI 926 @deffnx {} BFD_RELOC_FRV_TLSMOFFLO 927 @deffnx {} BFD_RELOC_FRV_GOTTLSOFF12 928 @deffnx {} BFD_RELOC_FRV_GOTTLSOFFHI 929 @deffnx {} BFD_RELOC_FRV_GOTTLSOFFLO 930 @deffnx {} BFD_RELOC_FRV_TLSOFF 931 @deffnx {} BFD_RELOC_FRV_TLSDESC_RELAX 932 @deffnx {} BFD_RELOC_FRV_GETTLSOFF_RELAX 933 @deffnx {} BFD_RELOC_FRV_TLSOFF_RELAX 934 @deffnx {} BFD_RELOC_FRV_TLSMOFF 935 Fujitsu Frv Relocations. 936 @end deffn 937 @deffn {} BFD_RELOC_MN10300_GOTOFF24 938 This is a 24bit GOT-relative reloc for the mn10300. 939 @end deffn 940 @deffn {} BFD_RELOC_MN10300_GOT32 941 This is a 32bit GOT-relative reloc for the mn10300, offset by two 942 bytes in the instruction. 943 @end deffn 944 @deffn {} BFD_RELOC_MN10300_GOT24 945 This is a 24bit GOT-relative reloc for the mn10300, offset by two 946 bytes in the instruction. 947 @end deffn 948 @deffn {} BFD_RELOC_MN10300_GOT16 949 This is a 16bit GOT-relative reloc for the mn10300, offset by two 950 bytes in the instruction. 951 @end deffn 952 @deffn {} BFD_RELOC_MN10300_COPY 953 Copy symbol at runtime. 954 @end deffn 955 @deffn {} BFD_RELOC_MN10300_GLOB_DAT 956 Create GOT entry. 957 @end deffn 958 @deffn {} BFD_RELOC_MN10300_JMP_SLOT 959 Create PLT entry. 960 @end deffn 961 @deffn {} BFD_RELOC_MN10300_RELATIVE 962 Adjust by program base. 963 @end deffn 964 @deffn {} BFD_RELOC_MN10300_SYM_DIFF 965 Together with another reloc targeted at the same location, allows 966 for a value that is the difference of two symbols in the same 967 section. 968 @end deffn 969 @deffn {} BFD_RELOC_MN10300_ALIGN 970 The addend of this reloc is an alignment power that must be honoured 971 at the offset's location, regardless of linker relaxation. 972 @end deffn 973 @deffn {} BFD_RELOC_MN10300_TLS_GD 974 @deffnx {} BFD_RELOC_MN10300_TLS_LD 975 @deffnx {} BFD_RELOC_MN10300_TLS_LDO 976 @deffnx {} BFD_RELOC_MN10300_TLS_GOTIE 977 @deffnx {} BFD_RELOC_MN10300_TLS_IE 978 @deffnx {} BFD_RELOC_MN10300_TLS_LE 979 @deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD 980 @deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF 981 @deffnx {} BFD_RELOC_MN10300_TLS_TPOFF 982 Various TLS-related relocations. 983 @end deffn 984 @deffn {} BFD_RELOC_MN10300_32_PCREL 985 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in 986 the instruction. 987 @end deffn 988 @deffn {} BFD_RELOC_MN10300_16_PCREL 989 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in 990 the instruction. 991 @end deffn 992 @deffn {} BFD_RELOC_386_GOT32 993 @deffnx {} BFD_RELOC_386_PLT32 994 @deffnx {} BFD_RELOC_386_COPY 995 @deffnx {} BFD_RELOC_386_GLOB_DAT 996 @deffnx {} BFD_RELOC_386_JUMP_SLOT 997 @deffnx {} BFD_RELOC_386_RELATIVE 998 @deffnx {} BFD_RELOC_386_GOTOFF 999 @deffnx {} BFD_RELOC_386_GOTPC 1000 @deffnx {} BFD_RELOC_386_TLS_TPOFF 1001 @deffnx {} BFD_RELOC_386_TLS_IE 1002 @deffnx {} BFD_RELOC_386_TLS_GOTIE 1003 @deffnx {} BFD_RELOC_386_TLS_LE 1004 @deffnx {} BFD_RELOC_386_TLS_GD 1005 @deffnx {} BFD_RELOC_386_TLS_LDM 1006 @deffnx {} BFD_RELOC_386_TLS_LDO_32 1007 @deffnx {} BFD_RELOC_386_TLS_IE_32 1008 @deffnx {} BFD_RELOC_386_TLS_LE_32 1009 @deffnx {} BFD_RELOC_386_TLS_DTPMOD32 1010 @deffnx {} BFD_RELOC_386_TLS_DTPOFF32 1011 @deffnx {} BFD_RELOC_386_TLS_TPOFF32 1012 @deffnx {} BFD_RELOC_386_TLS_GOTDESC 1013 @deffnx {} BFD_RELOC_386_TLS_DESC_CALL 1014 @deffnx {} BFD_RELOC_386_TLS_DESC 1015 @deffnx {} BFD_RELOC_386_IRELATIVE 1016 @deffnx {} BFD_RELOC_386_GOT32X 1017 i386/elf relocations. 1018 @end deffn 1019 @deffn {} BFD_RELOC_X86_64_GOT32 1020 @deffnx {} BFD_RELOC_X86_64_PLT32 1021 @deffnx {} BFD_RELOC_X86_64_COPY 1022 @deffnx {} BFD_RELOC_X86_64_GLOB_DAT 1023 @deffnx {} BFD_RELOC_X86_64_JUMP_SLOT 1024 @deffnx {} BFD_RELOC_X86_64_RELATIVE 1025 @deffnx {} BFD_RELOC_X86_64_GOTPCREL 1026 @deffnx {} BFD_RELOC_X86_64_32S 1027 @deffnx {} BFD_RELOC_X86_64_DTPMOD64 1028 @deffnx {} BFD_RELOC_X86_64_DTPOFF64 1029 @deffnx {} BFD_RELOC_X86_64_TPOFF64 1030 @deffnx {} BFD_RELOC_X86_64_TLSGD 1031 @deffnx {} BFD_RELOC_X86_64_TLSLD 1032 @deffnx {} BFD_RELOC_X86_64_DTPOFF32 1033 @deffnx {} BFD_RELOC_X86_64_GOTTPOFF 1034 @deffnx {} BFD_RELOC_X86_64_TPOFF32 1035 @deffnx {} BFD_RELOC_X86_64_GOTOFF64 1036 @deffnx {} BFD_RELOC_X86_64_GOTPC32 1037 @deffnx {} BFD_RELOC_X86_64_GOT64 1038 @deffnx {} BFD_RELOC_X86_64_GOTPCREL64 1039 @deffnx {} BFD_RELOC_X86_64_GOTPC64 1040 @deffnx {} BFD_RELOC_X86_64_GOTPLT64 1041 @deffnx {} BFD_RELOC_X86_64_PLTOFF64 1042 @deffnx {} BFD_RELOC_X86_64_GOTPC32_TLSDESC 1043 @deffnx {} BFD_RELOC_X86_64_TLSDESC_CALL 1044 @deffnx {} BFD_RELOC_X86_64_TLSDESC 1045 @deffnx {} BFD_RELOC_X86_64_IRELATIVE 1046 @deffnx {} BFD_RELOC_X86_64_PC32_BND 1047 @deffnx {} BFD_RELOC_X86_64_PLT32_BND 1048 @deffnx {} BFD_RELOC_X86_64_GOTPCRELX 1049 @deffnx {} BFD_RELOC_X86_64_REX_GOTPCRELX 1050 @deffnx {} BFD_RELOC_X86_64_CODE_4_GOTPCRELX 1051 @deffnx {} BFD_RELOC_X86_64_CODE_4_GOTTPOFF 1052 @deffnx {} BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC 1053 @deffnx {} BFD_RELOC_X86_64_CODE_5_GOTPCRELX 1054 @deffnx {} BFD_RELOC_X86_64_CODE_5_GOTTPOFF 1055 @deffnx {} BFD_RELOC_X86_64_CODE_5_GOTPC32_TLSDESC 1056 @deffnx {} BFD_RELOC_X86_64_CODE_6_GOTPCRELX 1057 @deffnx {} BFD_RELOC_X86_64_CODE_6_GOTTPOFF 1058 @deffnx {} BFD_RELOC_X86_64_CODE_6_GOTPC32_TLSDESC 1059 x86-64/elf relocations. 1060 @end deffn 1061 @deffn {} BFD_RELOC_NS32K_IMM_8 1062 @deffnx {} BFD_RELOC_NS32K_IMM_16 1063 @deffnx {} BFD_RELOC_NS32K_IMM_32 1064 @deffnx {} BFD_RELOC_NS32K_IMM_8_PCREL 1065 @deffnx {} BFD_RELOC_NS32K_IMM_16_PCREL 1066 @deffnx {} BFD_RELOC_NS32K_IMM_32_PCREL 1067 @deffnx {} BFD_RELOC_NS32K_DISP_8 1068 @deffnx {} BFD_RELOC_NS32K_DISP_16 1069 @deffnx {} BFD_RELOC_NS32K_DISP_32 1070 @deffnx {} BFD_RELOC_NS32K_DISP_8_PCREL 1071 @deffnx {} BFD_RELOC_NS32K_DISP_16_PCREL 1072 @deffnx {} BFD_RELOC_NS32K_DISP_32_PCREL 1073 ns32k relocations. 1074 @end deffn 1075 @deffn {} BFD_RELOC_PDP11_DISP_8_PCREL 1076 @deffnx {} BFD_RELOC_PDP11_DISP_6_PCREL 1077 PDP11 relocations. 1078 @end deffn 1079 @deffn {} BFD_RELOC_PJ_CODE_HI16 1080 @deffnx {} BFD_RELOC_PJ_CODE_LO16 1081 @deffnx {} BFD_RELOC_PJ_CODE_DIR16 1082 @deffnx {} BFD_RELOC_PJ_CODE_DIR32 1083 @deffnx {} BFD_RELOC_PJ_CODE_REL16 1084 @deffnx {} BFD_RELOC_PJ_CODE_REL32 1085 Picojava relocs. Not all of these appear in object files. 1086 @end deffn 1087 @deffn {} BFD_RELOC_PPC_B26 1088 @deffnx {} BFD_RELOC_PPC_BA26 1089 @deffnx {} BFD_RELOC_PPC_TOC16 1090 @deffnx {} BFD_RELOC_PPC_TOC16_LO 1091 @deffnx {} BFD_RELOC_PPC_TOC16_HI 1092 @deffnx {} BFD_RELOC_PPC_B16 1093 @deffnx {} BFD_RELOC_PPC_B16_BRTAKEN 1094 @deffnx {} BFD_RELOC_PPC_B16_BRNTAKEN 1095 @deffnx {} BFD_RELOC_PPC_BA16 1096 @deffnx {} BFD_RELOC_PPC_BA16_BRTAKEN 1097 @deffnx {} BFD_RELOC_PPC_BA16_BRNTAKEN 1098 @deffnx {} BFD_RELOC_PPC_COPY 1099 @deffnx {} BFD_RELOC_PPC_GLOB_DAT 1100 @deffnx {} BFD_RELOC_PPC_JMP_SLOT 1101 @deffnx {} BFD_RELOC_PPC_RELATIVE 1102 @deffnx {} BFD_RELOC_PPC_LOCAL24PC 1103 @deffnx {} BFD_RELOC_PPC_EMB_NADDR32 1104 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16 1105 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_LO 1106 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HI 1107 @deffnx {} BFD_RELOC_PPC_EMB_NADDR16_HA 1108 @deffnx {} BFD_RELOC_PPC_EMB_SDAI16 1109 @deffnx {} BFD_RELOC_PPC_EMB_SDA2I16 1110 @deffnx {} BFD_RELOC_PPC_EMB_SDA2REL 1111 @deffnx {} BFD_RELOC_PPC_EMB_SDA21 1112 @deffnx {} BFD_RELOC_PPC_EMB_MRKREF 1113 @deffnx {} BFD_RELOC_PPC_EMB_RELSEC16 1114 @deffnx {} BFD_RELOC_PPC_EMB_RELST_LO 1115 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HI 1116 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HA 1117 @deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD 1118 @deffnx {} BFD_RELOC_PPC_EMB_RELSDA 1119 @deffnx {} BFD_RELOC_PPC_VLE_REL8 1120 @deffnx {} BFD_RELOC_PPC_VLE_REL15 1121 @deffnx {} BFD_RELOC_PPC_VLE_REL24 1122 @deffnx {} BFD_RELOC_PPC_VLE_LO16A 1123 @deffnx {} BFD_RELOC_PPC_VLE_LO16D 1124 @deffnx {} BFD_RELOC_PPC_VLE_HI16A 1125 @deffnx {} BFD_RELOC_PPC_VLE_HI16D 1126 @deffnx {} BFD_RELOC_PPC_VLE_HA16A 1127 @deffnx {} BFD_RELOC_PPC_VLE_HA16D 1128 @deffnx {} BFD_RELOC_PPC_VLE_SDA21 1129 @deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO 1130 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A 1131 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D 1132 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A 1133 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D 1134 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A 1135 @deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D 1136 @deffnx {} BFD_RELOC_PPC_16DX_HA 1137 @deffnx {} BFD_RELOC_PPC_REL16DX_HA 1138 @deffnx {} BFD_RELOC_PPC_NEG 1139 @deffnx {} BFD_RELOC_PPC64_HIGHER 1140 @deffnx {} BFD_RELOC_PPC64_HIGHER_S 1141 @deffnx {} BFD_RELOC_PPC64_HIGHEST 1142 @deffnx {} BFD_RELOC_PPC64_HIGHEST_S 1143 @deffnx {} BFD_RELOC_PPC64_TOC16_LO 1144 @deffnx {} BFD_RELOC_PPC64_TOC16_HI 1145 @deffnx {} BFD_RELOC_PPC64_TOC16_HA 1146 @deffnx {} BFD_RELOC_PPC64_TOC 1147 @deffnx {} BFD_RELOC_PPC64_PLTGOT16 1148 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO 1149 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_HI 1150 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_HA 1151 @deffnx {} BFD_RELOC_PPC64_ADDR16_DS 1152 @deffnx {} BFD_RELOC_PPC64_ADDR16_LO_DS 1153 @deffnx {} BFD_RELOC_PPC64_GOT16_DS 1154 @deffnx {} BFD_RELOC_PPC64_GOT16_LO_DS 1155 @deffnx {} BFD_RELOC_PPC64_PLT16_LO_DS 1156 @deffnx {} BFD_RELOC_PPC64_SECTOFF_DS 1157 @deffnx {} BFD_RELOC_PPC64_SECTOFF_LO_DS 1158 @deffnx {} BFD_RELOC_PPC64_TOC16_DS 1159 @deffnx {} BFD_RELOC_PPC64_TOC16_LO_DS 1160 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_DS 1161 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO_DS 1162 @deffnx {} BFD_RELOC_PPC64_ADDR16_HIGH 1163 @deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHA 1164 @deffnx {} BFD_RELOC_PPC64_REL16_HIGH 1165 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHA 1166 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHER 1167 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA 1168 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST 1169 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA 1170 @deffnx {} BFD_RELOC_PPC64_ADDR64_LOCAL 1171 @deffnx {} BFD_RELOC_PPC64_ENTRY 1172 @deffnx {} BFD_RELOC_PPC64_REL24_NOTOC 1173 @deffnx {} BFD_RELOC_PPC64_REL24_P9NOTOC 1174 @deffnx {} BFD_RELOC_PPC64_D34 1175 @deffnx {} BFD_RELOC_PPC64_D34_LO 1176 @deffnx {} BFD_RELOC_PPC64_D34_HI30 1177 @deffnx {} BFD_RELOC_PPC64_D34_HA30 1178 @deffnx {} BFD_RELOC_PPC64_PCREL34 1179 @deffnx {} BFD_RELOC_PPC64_GOT_PCREL34 1180 @deffnx {} BFD_RELOC_PPC64_PLT_PCREL34 1181 @deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHER34 1182 @deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHERA34 1183 @deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHEST34 1184 @deffnx {} BFD_RELOC_PPC64_ADDR16_HIGHESTA34 1185 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHER34 1186 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHERA34 1187 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHEST34 1188 @deffnx {} BFD_RELOC_PPC64_REL16_HIGHESTA34 1189 @deffnx {} BFD_RELOC_PPC64_D28 1190 @deffnx {} BFD_RELOC_PPC64_PCREL28 1191 Power(rs6000) and PowerPC relocations. 1192 @end deffn 1193 @deffn {} BFD_RELOC_PPC_TLS 1194 @deffnx {} BFD_RELOC_PPC_TLSGD 1195 @deffnx {} BFD_RELOC_PPC_TLSLD 1196 @deffnx {} BFD_RELOC_PPC_TLSLE 1197 @deffnx {} BFD_RELOC_PPC_TLSIE 1198 @deffnx {} BFD_RELOC_PPC_TLSM 1199 @deffnx {} BFD_RELOC_PPC_TLSML 1200 @deffnx {} BFD_RELOC_PPC_DTPMOD 1201 @deffnx {} BFD_RELOC_PPC_TPREL16 1202 @deffnx {} BFD_RELOC_PPC_TPREL16_LO 1203 @deffnx {} BFD_RELOC_PPC_TPREL16_HI 1204 @deffnx {} BFD_RELOC_PPC_TPREL16_HA 1205 @deffnx {} BFD_RELOC_PPC_TPREL 1206 @deffnx {} BFD_RELOC_PPC_DTPREL16 1207 @deffnx {} BFD_RELOC_PPC_DTPREL16_LO 1208 @deffnx {} BFD_RELOC_PPC_DTPREL16_HI 1209 @deffnx {} BFD_RELOC_PPC_DTPREL16_HA 1210 @deffnx {} BFD_RELOC_PPC_DTPREL 1211 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16 1212 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_LO 1213 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HI 1214 @deffnx {} BFD_RELOC_PPC_GOT_TLSGD16_HA 1215 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16 1216 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_LO 1217 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HI 1218 @deffnx {} BFD_RELOC_PPC_GOT_TLSLD16_HA 1219 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16 1220 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16_LO 1221 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HI 1222 @deffnx {} BFD_RELOC_PPC_GOT_TPREL16_HA 1223 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16 1224 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_LO 1225 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HI 1226 @deffnx {} BFD_RELOC_PPC_GOT_DTPREL16_HA 1227 @deffnx {} BFD_RELOC_PPC64_TLSGD 1228 @deffnx {} BFD_RELOC_PPC64_TLSLD 1229 @deffnx {} BFD_RELOC_PPC64_TLSLE 1230 @deffnx {} BFD_RELOC_PPC64_TLSIE 1231 @deffnx {} BFD_RELOC_PPC64_TLSM 1232 @deffnx {} BFD_RELOC_PPC64_TLSML 1233 @deffnx {} BFD_RELOC_PPC64_TPREL16_DS 1234 @deffnx {} BFD_RELOC_PPC64_TPREL16_LO_DS 1235 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGH 1236 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHA 1237 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHER 1238 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHERA 1239 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHEST 1240 @deffnx {} BFD_RELOC_PPC64_TPREL16_HIGHESTA 1241 @deffnx {} BFD_RELOC_PPC64_DTPREL16_DS 1242 @deffnx {} BFD_RELOC_PPC64_DTPREL16_LO_DS 1243 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGH 1244 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHA 1245 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHER 1246 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHERA 1247 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHEST 1248 @deffnx {} BFD_RELOC_PPC64_DTPREL16_HIGHESTA 1249 @deffnx {} BFD_RELOC_PPC64_TPREL34 1250 @deffnx {} BFD_RELOC_PPC64_DTPREL34 1251 @deffnx {} BFD_RELOC_PPC64_GOT_TLSGD_PCREL34 1252 @deffnx {} BFD_RELOC_PPC64_GOT_TLSLD_PCREL34 1253 @deffnx {} BFD_RELOC_PPC64_GOT_TPREL_PCREL34 1254 @deffnx {} BFD_RELOC_PPC64_GOT_DTPREL_PCREL34 1255 @deffnx {} BFD_RELOC_PPC64_TLS_PCREL 1256 PowerPC and PowerPC64 thread-local storage relocations. 1257 @end deffn 1258 @deffn {} BFD_RELOC_I370_D12 1259 IBM 370/390 relocations. 1260 @end deffn 1261 @deffn {} BFD_RELOC_CTOR 1262 The type of reloc used to build a constructor table - at the moment 1263 probably a 32 bit wide absolute relocation, but the target can choose. 1264 It generally does map to one of the other relocation types. 1265 @end deffn 1266 @deffn {} BFD_RELOC_ARM_PCREL_BRANCH 1267 ARM 26 bit pc-relative branch. The lowest two bits must be zero and 1268 are not stored in the instruction. 1269 @end deffn 1270 @deffn {} BFD_RELOC_ARM_PCREL_BLX 1271 ARM 26 bit pc-relative branch. The lowest bit must be zero and is 1272 not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1273 field in the instruction. 1274 @end deffn 1275 @deffn {} BFD_RELOC_THUMB_PCREL_BLX 1276 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is 1277 not stored in the instruction. The 2nd lowest bit comes from a 1 bit 1278 field in the instruction. 1279 @end deffn 1280 @deffn {} BFD_RELOC_ARM_PCREL_CALL 1281 ARM 26-bit pc-relative branch for an unconditional BL or BLX 1282 instruction. 1283 @end deffn 1284 @deffn {} BFD_RELOC_ARM_PCREL_JUMP 1285 ARM 26-bit pc-relative branch for B or conditional BL instruction. 1286 @end deffn 1287 @deffn {} BFD_RELOC_THUMB_PCREL_BRANCH5 1288 ARM 5-bit pc-relative branch for Branch Future instructions. 1289 @end deffn 1290 @deffn {} BFD_RELOC_THUMB_PCREL_BFCSEL 1291 ARM 6-bit pc-relative branch for BFCSEL instruction. 1292 @end deffn 1293 @deffn {} BFD_RELOC_ARM_THUMB_BF17 1294 ARM 17-bit pc-relative branch for Branch Future instructions. 1295 @end deffn 1296 @deffn {} BFD_RELOC_ARM_THUMB_BF13 1297 ARM 13-bit pc-relative branch for BFCSEL instruction. 1298 @end deffn 1299 @deffn {} BFD_RELOC_ARM_THUMB_BF19 1300 ARM 19-bit pc-relative branch for Branch Future Link instruction. 1301 @end deffn 1302 @deffn {} BFD_RELOC_ARM_THUMB_LOOP12 1303 ARM 12-bit pc-relative branch for Low Overhead Loop instructions. 1304 @end deffn 1305 @deffn {} BFD_RELOC_THUMB_PCREL_BRANCH7 1306 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH9 1307 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH12 1308 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH20 1309 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH23 1310 @deffnx {} BFD_RELOC_THUMB_PCREL_BRANCH25 1311 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. 1312 The lowest bit must be zero and is not stored in the instruction. 1313 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an 1314 "nn" one smaller in all cases. Note further that BRANCH23 1315 corresponds to R_ARM_THM_CALL. 1316 @end deffn 1317 @deffn {} BFD_RELOC_ARM_OFFSET_IMM 1318 12-bit immediate offset, used in ARM-format ldr and str instructions. 1319 @end deffn 1320 @deffn {} BFD_RELOC_ARM_THUMB_OFFSET 1321 5-bit immediate offset, used in Thumb-format ldr and str instructions. 1322 @end deffn 1323 @deffn {} BFD_RELOC_ARM_TARGET1 1324 Pc-relative or absolute relocation depending on target. Used for 1325 entries in .init_array sections. 1326 @end deffn 1327 @deffn {} BFD_RELOC_ARM_ROSEGREL32 1328 Read-only segment base relative address. 1329 @end deffn 1330 @deffn {} BFD_RELOC_ARM_SBREL32 1331 Data segment base relative address. 1332 @end deffn 1333 @deffn {} BFD_RELOC_ARM_TARGET2 1334 This reloc is used for references to RTTI data from exception 1335 handling tables. The actual definition depends on the target. It 1336 may be a pc-relative or some form of GOT-indirect relocation. 1337 @end deffn 1338 @deffn {} BFD_RELOC_ARM_PREL31 1339 31-bit PC relative address. 1340 @end deffn 1341 @deffn {} BFD_RELOC_ARM_MOVW 1342 @deffnx {} BFD_RELOC_ARM_MOVT 1343 @deffnx {} BFD_RELOC_ARM_MOVW_PCREL 1344 @deffnx {} BFD_RELOC_ARM_MOVT_PCREL 1345 @deffnx {} BFD_RELOC_ARM_THUMB_MOVW 1346 @deffnx {} BFD_RELOC_ARM_THUMB_MOVT 1347 @deffnx {} BFD_RELOC_ARM_THUMB_MOVW_PCREL 1348 @deffnx {} BFD_RELOC_ARM_THUMB_MOVT_PCREL 1349 Low and High halfword relocations for MOVW and MOVT instructions. 1350 @end deffn 1351 @deffn {} BFD_RELOC_ARM_GOTFUNCDESC 1352 @deffnx {} BFD_RELOC_ARM_GOTOFFFUNCDESC 1353 @deffnx {} BFD_RELOC_ARM_FUNCDESC 1354 @deffnx {} BFD_RELOC_ARM_FUNCDESC_VALUE 1355 @deffnx {} BFD_RELOC_ARM_TLS_GD32_FDPIC 1356 @deffnx {} BFD_RELOC_ARM_TLS_LDM32_FDPIC 1357 @deffnx {} BFD_RELOC_ARM_TLS_IE32_FDPIC 1358 ARM FDPIC specific relocations. 1359 @end deffn 1360 @deffn {} BFD_RELOC_ARM_JUMP_SLOT 1361 @deffnx {} BFD_RELOC_ARM_GLOB_DAT 1362 @deffnx {} BFD_RELOC_ARM_GOT32 1363 @deffnx {} BFD_RELOC_ARM_PLT32 1364 @deffnx {} BFD_RELOC_ARM_RELATIVE 1365 @deffnx {} BFD_RELOC_ARM_GOTOFF 1366 @deffnx {} BFD_RELOC_ARM_GOTPC 1367 @deffnx {} BFD_RELOC_ARM_GOT_PREL 1368 Relocations for setting up GOTs and PLTs for shared libraries. 1369 @end deffn 1370 @deffn {} BFD_RELOC_ARM_TLS_GD32 1371 @deffnx {} BFD_RELOC_ARM_TLS_LDO32 1372 @deffnx {} BFD_RELOC_ARM_TLS_LDM32 1373 @deffnx {} BFD_RELOC_ARM_TLS_DTPOFF32 1374 @deffnx {} BFD_RELOC_ARM_TLS_DTPMOD32 1375 @deffnx {} BFD_RELOC_ARM_TLS_TPOFF32 1376 @deffnx {} BFD_RELOC_ARM_TLS_IE32 1377 @deffnx {} BFD_RELOC_ARM_TLS_LE32 1378 @deffnx {} BFD_RELOC_ARM_TLS_GOTDESC 1379 @deffnx {} BFD_RELOC_ARM_TLS_CALL 1380 @deffnx {} BFD_RELOC_ARM_THM_TLS_CALL 1381 @deffnx {} BFD_RELOC_ARM_TLS_DESCSEQ 1382 @deffnx {} BFD_RELOC_ARM_THM_TLS_DESCSEQ 1383 @deffnx {} BFD_RELOC_ARM_TLS_DESC 1384 ARM thread-local storage relocations. 1385 @end deffn 1386 @deffn {} BFD_RELOC_ARM_ALU_PC_G0_NC 1387 @deffnx {} BFD_RELOC_ARM_ALU_PC_G0 1388 @deffnx {} BFD_RELOC_ARM_ALU_PC_G1_NC 1389 @deffnx {} BFD_RELOC_ARM_ALU_PC_G1 1390 @deffnx {} BFD_RELOC_ARM_ALU_PC_G2 1391 @deffnx {} BFD_RELOC_ARM_LDR_PC_G0 1392 @deffnx {} BFD_RELOC_ARM_LDR_PC_G1 1393 @deffnx {} BFD_RELOC_ARM_LDR_PC_G2 1394 @deffnx {} BFD_RELOC_ARM_LDRS_PC_G0 1395 @deffnx {} BFD_RELOC_ARM_LDRS_PC_G1 1396 @deffnx {} BFD_RELOC_ARM_LDRS_PC_G2 1397 @deffnx {} BFD_RELOC_ARM_LDC_PC_G0 1398 @deffnx {} BFD_RELOC_ARM_LDC_PC_G1 1399 @deffnx {} BFD_RELOC_ARM_LDC_PC_G2 1400 @deffnx {} BFD_RELOC_ARM_ALU_SB_G0_NC 1401 @deffnx {} BFD_RELOC_ARM_ALU_SB_G0 1402 @deffnx {} BFD_RELOC_ARM_ALU_SB_G1_NC 1403 @deffnx {} BFD_RELOC_ARM_ALU_SB_G1 1404 @deffnx {} BFD_RELOC_ARM_ALU_SB_G2 1405 @deffnx {} BFD_RELOC_ARM_LDR_SB_G0 1406 @deffnx {} BFD_RELOC_ARM_LDR_SB_G1 1407 @deffnx {} BFD_RELOC_ARM_LDR_SB_G2 1408 @deffnx {} BFD_RELOC_ARM_LDRS_SB_G0 1409 @deffnx {} BFD_RELOC_ARM_LDRS_SB_G1 1410 @deffnx {} BFD_RELOC_ARM_LDRS_SB_G2 1411 @deffnx {} BFD_RELOC_ARM_LDC_SB_G0 1412 @deffnx {} BFD_RELOC_ARM_LDC_SB_G1 1413 @deffnx {} BFD_RELOC_ARM_LDC_SB_G2 1414 ARM group relocations. 1415 @end deffn 1416 @deffn {} BFD_RELOC_ARM_V4BX 1417 Annotation of BX instructions. 1418 @end deffn 1419 @deffn {} BFD_RELOC_ARM_IRELATIVE 1420 ARM support for STT_GNU_IFUNC. 1421 @end deffn 1422 @deffn {} BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC 1423 @deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC 1424 @deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC 1425 @deffnx {} BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC 1426 Thumb1 relocations to support execute-only code. 1427 @end deffn 1428 @deffn {} BFD_RELOC_ARM_IMMEDIATE 1429 @deffnx {} BFD_RELOC_ARM_ADRL_IMMEDIATE 1430 @deffnx {} BFD_RELOC_ARM_T32_IMMEDIATE 1431 @deffnx {} BFD_RELOC_ARM_T32_ADD_IMM 1432 @deffnx {} BFD_RELOC_ARM_T32_IMM12 1433 @deffnx {} BFD_RELOC_ARM_T32_ADD_PC12 1434 @deffnx {} BFD_RELOC_ARM_SHIFT_IMM 1435 @deffnx {} BFD_RELOC_ARM_SMC 1436 @deffnx {} BFD_RELOC_ARM_HVC 1437 @deffnx {} BFD_RELOC_ARM_SWI 1438 @deffnx {} BFD_RELOC_ARM_MULTI 1439 @deffnx {} BFD_RELOC_ARM_CP_OFF_IMM 1440 @deffnx {} BFD_RELOC_ARM_CP_OFF_IMM_S2 1441 @deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM 1442 @deffnx {} BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 1443 @deffnx {} BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM 1444 @deffnx {} BFD_RELOC_ARM_ADR_IMM 1445 @deffnx {} BFD_RELOC_ARM_LDR_IMM 1446 @deffnx {} BFD_RELOC_ARM_LITERAL 1447 @deffnx {} BFD_RELOC_ARM_IN_POOL 1448 @deffnx {} BFD_RELOC_ARM_OFFSET_IMM8 1449 @deffnx {} BFD_RELOC_ARM_T32_OFFSET_U8 1450 @deffnx {} BFD_RELOC_ARM_T32_OFFSET_IMM 1451 @deffnx {} BFD_RELOC_ARM_HWLITERAL 1452 @deffnx {} BFD_RELOC_ARM_THUMB_ADD 1453 @deffnx {} BFD_RELOC_ARM_THUMB_IMM 1454 @deffnx {} BFD_RELOC_ARM_THUMB_SHIFT 1455 These relocs are only used within the ARM assembler. They are not 1456 (at present) written to any object files. 1457 @end deffn 1458 @deffn {} BFD_RELOC_SH_PCDISP8BY2 1459 @deffnx {} BFD_RELOC_SH_PCDISP12BY2 1460 @deffnx {} BFD_RELOC_SH_IMM3 1461 @deffnx {} BFD_RELOC_SH_IMM3U 1462 @deffnx {} BFD_RELOC_SH_DISP12 1463 @deffnx {} BFD_RELOC_SH_DISP12BY2 1464 @deffnx {} BFD_RELOC_SH_DISP12BY4 1465 @deffnx {} BFD_RELOC_SH_DISP12BY8 1466 @deffnx {} BFD_RELOC_SH_DISP20 1467 @deffnx {} BFD_RELOC_SH_DISP20BY8 1468 @deffnx {} BFD_RELOC_SH_IMM4 1469 @deffnx {} BFD_RELOC_SH_IMM4BY2 1470 @deffnx {} BFD_RELOC_SH_IMM4BY4 1471 @deffnx {} BFD_RELOC_SH_IMM8 1472 @deffnx {} BFD_RELOC_SH_IMM8BY2 1473 @deffnx {} BFD_RELOC_SH_IMM8BY4 1474 @deffnx {} BFD_RELOC_SH_PCRELIMM8BY2 1475 @deffnx {} BFD_RELOC_SH_PCRELIMM8BY4 1476 @deffnx {} BFD_RELOC_SH_SWITCH16 1477 @deffnx {} BFD_RELOC_SH_SWITCH32 1478 @deffnx {} BFD_RELOC_SH_USES 1479 @deffnx {} BFD_RELOC_SH_COUNT 1480 @deffnx {} BFD_RELOC_SH_ALIGN 1481 @deffnx {} BFD_RELOC_SH_CODE 1482 @deffnx {} BFD_RELOC_SH_DATA 1483 @deffnx {} BFD_RELOC_SH_LABEL 1484 @deffnx {} BFD_RELOC_SH_LOOP_START 1485 @deffnx {} BFD_RELOC_SH_LOOP_END 1486 @deffnx {} BFD_RELOC_SH_COPY 1487 @deffnx {} BFD_RELOC_SH_GLOB_DAT 1488 @deffnx {} BFD_RELOC_SH_JMP_SLOT 1489 @deffnx {} BFD_RELOC_SH_RELATIVE 1490 @deffnx {} BFD_RELOC_SH_GOTPC 1491 @deffnx {} BFD_RELOC_SH_GOT_LOW16 1492 @deffnx {} BFD_RELOC_SH_GOT_MEDLOW16 1493 @deffnx {} BFD_RELOC_SH_GOT_MEDHI16 1494 @deffnx {} BFD_RELOC_SH_GOT_HI16 1495 @deffnx {} BFD_RELOC_SH_GOTPLT_LOW16 1496 @deffnx {} BFD_RELOC_SH_GOTPLT_MEDLOW16 1497 @deffnx {} BFD_RELOC_SH_GOTPLT_MEDHI16 1498 @deffnx {} BFD_RELOC_SH_GOTPLT_HI16 1499 @deffnx {} BFD_RELOC_SH_PLT_LOW16 1500 @deffnx {} BFD_RELOC_SH_PLT_MEDLOW16 1501 @deffnx {} BFD_RELOC_SH_PLT_MEDHI16 1502 @deffnx {} BFD_RELOC_SH_PLT_HI16 1503 @deffnx {} BFD_RELOC_SH_GOTOFF_LOW16 1504 @deffnx {} BFD_RELOC_SH_GOTOFF_MEDLOW16 1505 @deffnx {} BFD_RELOC_SH_GOTOFF_MEDHI16 1506 @deffnx {} BFD_RELOC_SH_GOTOFF_HI16 1507 @deffnx {} BFD_RELOC_SH_GOTPC_LOW16 1508 @deffnx {} BFD_RELOC_SH_GOTPC_MEDLOW16 1509 @deffnx {} BFD_RELOC_SH_GOTPC_MEDHI16 1510 @deffnx {} BFD_RELOC_SH_GOTPC_HI16 1511 @deffnx {} BFD_RELOC_SH_COPY64 1512 @deffnx {} BFD_RELOC_SH_GLOB_DAT64 1513 @deffnx {} BFD_RELOC_SH_JMP_SLOT64 1514 @deffnx {} BFD_RELOC_SH_RELATIVE64 1515 @deffnx {} BFD_RELOC_SH_GOT10BY4 1516 @deffnx {} BFD_RELOC_SH_GOT10BY8 1517 @deffnx {} BFD_RELOC_SH_GOTPLT10BY4 1518 @deffnx {} BFD_RELOC_SH_GOTPLT10BY8 1519 @deffnx {} BFD_RELOC_SH_GOTPLT32 1520 @deffnx {} BFD_RELOC_SH_SHMEDIA_CODE 1521 @deffnx {} BFD_RELOC_SH_IMMU5 1522 @deffnx {} BFD_RELOC_SH_IMMS6 1523 @deffnx {} BFD_RELOC_SH_IMMS6BY32 1524 @deffnx {} BFD_RELOC_SH_IMMU6 1525 @deffnx {} BFD_RELOC_SH_IMMS10 1526 @deffnx {} BFD_RELOC_SH_IMMS10BY2 1527 @deffnx {} BFD_RELOC_SH_IMMS10BY4 1528 @deffnx {} BFD_RELOC_SH_IMMS10BY8 1529 @deffnx {} BFD_RELOC_SH_IMMS16 1530 @deffnx {} BFD_RELOC_SH_IMMU16 1531 @deffnx {} BFD_RELOC_SH_IMM_LOW16 1532 @deffnx {} BFD_RELOC_SH_IMM_LOW16_PCREL 1533 @deffnx {} BFD_RELOC_SH_IMM_MEDLOW16 1534 @deffnx {} BFD_RELOC_SH_IMM_MEDLOW16_PCREL 1535 @deffnx {} BFD_RELOC_SH_IMM_MEDHI16 1536 @deffnx {} BFD_RELOC_SH_IMM_MEDHI16_PCREL 1537 @deffnx {} BFD_RELOC_SH_IMM_HI16 1538 @deffnx {} BFD_RELOC_SH_IMM_HI16_PCREL 1539 @deffnx {} BFD_RELOC_SH_PT_16 1540 @deffnx {} BFD_RELOC_SH_TLS_GD_32 1541 @deffnx {} BFD_RELOC_SH_TLS_LD_32 1542 @deffnx {} BFD_RELOC_SH_TLS_LDO_32 1543 @deffnx {} BFD_RELOC_SH_TLS_IE_32 1544 @deffnx {} BFD_RELOC_SH_TLS_LE_32 1545 @deffnx {} BFD_RELOC_SH_TLS_DTPMOD32 1546 @deffnx {} BFD_RELOC_SH_TLS_DTPOFF32 1547 @deffnx {} BFD_RELOC_SH_TLS_TPOFF32 1548 @deffnx {} BFD_RELOC_SH_GOT20 1549 @deffnx {} BFD_RELOC_SH_GOTOFF20 1550 @deffnx {} BFD_RELOC_SH_GOTFUNCDESC 1551 @deffnx {} BFD_RELOC_SH_GOTFUNCDESC20 1552 @deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC 1553 @deffnx {} BFD_RELOC_SH_GOTOFFFUNCDESC20 1554 @deffnx {} BFD_RELOC_SH_FUNCDESC 1555 Renesas / SuperH SH relocs. Not all of these appear in object files. 1556 @end deffn 1557 @deffn {} BFD_RELOC_ARC_NONE 1558 @deffnx {} BFD_RELOC_ARC_8 1559 @deffnx {} BFD_RELOC_ARC_16 1560 @deffnx {} BFD_RELOC_ARC_24 1561 @deffnx {} BFD_RELOC_ARC_32 1562 @deffnx {} BFD_RELOC_ARC_N8 1563 @deffnx {} BFD_RELOC_ARC_N16 1564 @deffnx {} BFD_RELOC_ARC_N24 1565 @deffnx {} BFD_RELOC_ARC_N32 1566 @deffnx {} BFD_RELOC_ARC_SDA 1567 @deffnx {} BFD_RELOC_ARC_SECTOFF 1568 @deffnx {} BFD_RELOC_ARC_S21H_PCREL 1569 @deffnx {} BFD_RELOC_ARC_S21W_PCREL 1570 @deffnx {} BFD_RELOC_ARC_S25H_PCREL 1571 @deffnx {} BFD_RELOC_ARC_S25W_PCREL 1572 @deffnx {} BFD_RELOC_ARC_SDA32 1573 @deffnx {} BFD_RELOC_ARC_SDA_LDST 1574 @deffnx {} BFD_RELOC_ARC_SDA_LDST1 1575 @deffnx {} BFD_RELOC_ARC_SDA_LDST2 1576 @deffnx {} BFD_RELOC_ARC_SDA16_LD 1577 @deffnx {} BFD_RELOC_ARC_SDA16_LD1 1578 @deffnx {} BFD_RELOC_ARC_SDA16_LD2 1579 @deffnx {} BFD_RELOC_ARC_S13_PCREL 1580 @deffnx {} BFD_RELOC_ARC_W 1581 @deffnx {} BFD_RELOC_ARC_32_ME 1582 @deffnx {} BFD_RELOC_ARC_32_ME_S 1583 @deffnx {} BFD_RELOC_ARC_N32_ME 1584 @deffnx {} BFD_RELOC_ARC_SECTOFF_ME 1585 @deffnx {} BFD_RELOC_ARC_SDA32_ME 1586 @deffnx {} BFD_RELOC_ARC_W_ME 1587 @deffnx {} BFD_RELOC_AC_SECTOFF_U8 1588 @deffnx {} BFD_RELOC_AC_SECTOFF_U8_1 1589 @deffnx {} BFD_RELOC_AC_SECTOFF_U8_2 1590 @deffnx {} BFD_RELOC_AC_SECTOFF_S9 1591 @deffnx {} BFD_RELOC_AC_SECTOFF_S9_1 1592 @deffnx {} BFD_RELOC_AC_SECTOFF_S9_2 1593 @deffnx {} BFD_RELOC_ARC_SECTOFF_ME_1 1594 @deffnx {} BFD_RELOC_ARC_SECTOFF_ME_2 1595 @deffnx {} BFD_RELOC_ARC_SECTOFF_1 1596 @deffnx {} BFD_RELOC_ARC_SECTOFF_2 1597 @deffnx {} BFD_RELOC_ARC_SDA_12 1598 @deffnx {} BFD_RELOC_ARC_SDA16_ST2 1599 @deffnx {} BFD_RELOC_ARC_32_PCREL 1600 @deffnx {} BFD_RELOC_ARC_PC32 1601 @deffnx {} BFD_RELOC_ARC_GOT32 1602 @deffnx {} BFD_RELOC_ARC_GOTPC32 1603 @deffnx {} BFD_RELOC_ARC_PLT32 1604 @deffnx {} BFD_RELOC_ARC_COPY 1605 @deffnx {} BFD_RELOC_ARC_GLOB_DAT 1606 @deffnx {} BFD_RELOC_ARC_JMP_SLOT 1607 @deffnx {} BFD_RELOC_ARC_RELATIVE 1608 @deffnx {} BFD_RELOC_ARC_GOTOFF 1609 @deffnx {} BFD_RELOC_ARC_GOTPC 1610 @deffnx {} BFD_RELOC_ARC_S21W_PCREL_PLT 1611 @deffnx {} BFD_RELOC_ARC_S25H_PCREL_PLT 1612 @deffnx {} BFD_RELOC_ARC_TLS_DTPMOD 1613 @deffnx {} BFD_RELOC_ARC_TLS_TPOFF 1614 @deffnx {} BFD_RELOC_ARC_TLS_GD_GOT 1615 @deffnx {} BFD_RELOC_ARC_TLS_GD_LD 1616 @deffnx {} BFD_RELOC_ARC_TLS_GD_CALL 1617 @deffnx {} BFD_RELOC_ARC_TLS_IE_GOT 1618 @deffnx {} BFD_RELOC_ARC_TLS_DTPOFF 1619 @deffnx {} BFD_RELOC_ARC_TLS_DTPOFF_S9 1620 @deffnx {} BFD_RELOC_ARC_TLS_LE_S9 1621 @deffnx {} BFD_RELOC_ARC_TLS_LE_32 1622 @deffnx {} BFD_RELOC_ARC_S25W_PCREL_PLT 1623 @deffnx {} BFD_RELOC_ARC_S21H_PCREL_PLT 1624 @deffnx {} BFD_RELOC_ARC_NPS_CMEM16 1625 @deffnx {} BFD_RELOC_ARC_JLI_SECTOFF 1626 ARC relocs. 1627 @end deffn 1628 @deffn {} BFD_RELOC_BFIN_16_IMM 1629 ADI Blackfin 16 bit immediate absolute reloc. 1630 @end deffn 1631 @deffn {} BFD_RELOC_BFIN_16_HIGH 1632 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. 1633 @end deffn 1634 @deffn {} BFD_RELOC_BFIN_4_PCREL 1635 ADI Blackfin 'a' part of LSETUP. 1636 @end deffn 1637 @deffn {} BFD_RELOC_BFIN_5_PCREL 1638 ADI Blackfin. 1639 @end deffn 1640 @deffn {} BFD_RELOC_BFIN_16_LOW 1641 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. 1642 @end deffn 1643 @deffn {} BFD_RELOC_BFIN_10_PCREL 1644 ADI Blackfin. 1645 @end deffn 1646 @deffn {} BFD_RELOC_BFIN_11_PCREL 1647 ADI Blackfin 'b' part of LSETUP. 1648 @end deffn 1649 @deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP 1650 ADI Blackfin. 1651 @end deffn 1652 @deffn {} BFD_RELOC_BFIN_12_PCREL_JUMP_S 1653 ADI Blackfin Short jump, pcrel. 1654 @end deffn 1655 @deffn {} BFD_RELOC_BFIN_24_PCREL_CALL_X 1656 ADI Blackfin Call.x not implemented. 1657 @end deffn 1658 @deffn {} BFD_RELOC_BFIN_24_PCREL_JUMP_L 1659 ADI Blackfin Long Jump pcrel. 1660 @end deffn 1661 @deffn {} BFD_RELOC_BFIN_GOT17M4 1662 @deffnx {} BFD_RELOC_BFIN_GOTHI 1663 @deffnx {} BFD_RELOC_BFIN_GOTLO 1664 @deffnx {} BFD_RELOC_BFIN_FUNCDESC 1665 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOT17M4 1666 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTHI 1667 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTLO 1668 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_VALUE 1669 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 1670 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI 1671 @deffnx {} BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO 1672 @deffnx {} BFD_RELOC_BFIN_GOTOFF17M4 1673 @deffnx {} BFD_RELOC_BFIN_GOTOFFHI 1674 @deffnx {} BFD_RELOC_BFIN_GOTOFFLO 1675 ADI Blackfin FD-PIC relocations. 1676 @end deffn 1677 @deffn {} BFD_RELOC_BFIN_GOT 1678 ADI Blackfin GOT relocation. 1679 @end deffn 1680 @deffn {} BFD_RELOC_BFIN_PLTPC 1681 ADI Blackfin PLTPC relocation. 1682 @end deffn 1683 @deffn {} BFD_ARELOC_BFIN_PUSH 1684 ADI Blackfin arithmetic relocation. 1685 @end deffn 1686 @deffn {} BFD_ARELOC_BFIN_CONST 1687 ADI Blackfin arithmetic relocation. 1688 @end deffn 1689 @deffn {} BFD_ARELOC_BFIN_ADD 1690 ADI Blackfin arithmetic relocation. 1691 @end deffn 1692 @deffn {} BFD_ARELOC_BFIN_SUB 1693 ADI Blackfin arithmetic relocation. 1694 @end deffn 1695 @deffn {} BFD_ARELOC_BFIN_MULT 1696 ADI Blackfin arithmetic relocation. 1697 @end deffn 1698 @deffn {} BFD_ARELOC_BFIN_DIV 1699 ADI Blackfin arithmetic relocation. 1700 @end deffn 1701 @deffn {} BFD_ARELOC_BFIN_MOD 1702 ADI Blackfin arithmetic relocation. 1703 @end deffn 1704 @deffn {} BFD_ARELOC_BFIN_LSHIFT 1705 ADI Blackfin arithmetic relocation. 1706 @end deffn 1707 @deffn {} BFD_ARELOC_BFIN_RSHIFT 1708 ADI Blackfin arithmetic relocation. 1709 @end deffn 1710 @deffn {} BFD_ARELOC_BFIN_AND 1711 ADI Blackfin arithmetic relocation. 1712 @end deffn 1713 @deffn {} BFD_ARELOC_BFIN_OR 1714 ADI Blackfin arithmetic relocation. 1715 @end deffn 1716 @deffn {} BFD_ARELOC_BFIN_XOR 1717 ADI Blackfin arithmetic relocation. 1718 @end deffn 1719 @deffn {} BFD_ARELOC_BFIN_LAND 1720 ADI Blackfin arithmetic relocation. 1721 @end deffn 1722 @deffn {} BFD_ARELOC_BFIN_LOR 1723 ADI Blackfin arithmetic relocation. 1724 @end deffn 1725 @deffn {} BFD_ARELOC_BFIN_LEN 1726 ADI Blackfin arithmetic relocation. 1727 @end deffn 1728 @deffn {} BFD_ARELOC_BFIN_NEG 1729 ADI Blackfin arithmetic relocation. 1730 @end deffn 1731 @deffn {} BFD_ARELOC_BFIN_COMP 1732 ADI Blackfin arithmetic relocation. 1733 @end deffn 1734 @deffn {} BFD_ARELOC_BFIN_PAGE 1735 ADI Blackfin arithmetic relocation. 1736 @end deffn 1737 @deffn {} BFD_ARELOC_BFIN_HWPAGE 1738 ADI Blackfin arithmetic relocation. 1739 @end deffn 1740 @deffn {} BFD_ARELOC_BFIN_ADDR 1741 ADI Blackfin arithmetic relocation. 1742 @end deffn 1743 @deffn {} BFD_RELOC_D10V_10_PCREL_R 1744 Mitsubishi D10V relocs. 1745 This is a 10-bit reloc with the right 2 bits assumed to be 0. 1746 @end deffn 1747 @deffn {} BFD_RELOC_D10V_10_PCREL_L 1748 Mitsubishi D10V relocs. 1749 This is a 10-bit reloc with the right 2 bits assumed to be 0. This 1750 is the same as the previous reloc except it is in the left 1751 container, i.e., shifted left 15 bits. 1752 @end deffn 1753 @deffn {} BFD_RELOC_D10V_18 1754 This is an 18-bit reloc with the right 2 bits assumed to be 0. 1755 @end deffn 1756 @deffn {} BFD_RELOC_D10V_18_PCREL 1757 This is an 18-bit reloc with the right 2 bits assumed to be 0. 1758 @end deffn 1759 @deffn {} BFD_RELOC_D30V_6 1760 Mitsubishi D30V relocs. 1761 This is a 6-bit absolute reloc. 1762 @end deffn 1763 @deffn {} BFD_RELOC_D30V_9_PCREL 1764 This is a 6-bit pc-relative reloc with the right 3 bits assumed to 1765 be 0. 1766 @end deffn 1767 @deffn {} BFD_RELOC_D30V_9_PCREL_R 1768 This is a 6-bit pc-relative reloc with the right 3 bits assumed to 1769 be 0. Same as the previous reloc but on the right side of the 1770 container. 1771 @end deffn 1772 @deffn {} BFD_RELOC_D30V_15 1773 This is a 12-bit absolute reloc with the right 3 bitsassumed to 1774 be 0. 1775 @end deffn 1776 @deffn {} BFD_RELOC_D30V_15_PCREL 1777 This is a 12-bit pc-relative reloc with the right 3 bits assumed to 1778 be 0. 1779 @end deffn 1780 @deffn {} BFD_RELOC_D30V_15_PCREL_R 1781 This is a 12-bit pc-relative reloc with the right 3 bits assumed to 1782 be 0. Same as the previous reloc but on the right side of the 1783 container. 1784 @end deffn 1785 @deffn {} BFD_RELOC_D30V_21 1786 This is an 18-bit absolute reloc with the right 3 bits assumed to 1787 be 0. 1788 @end deffn 1789 @deffn {} BFD_RELOC_D30V_21_PCREL 1790 This is an 18-bit pc-relative reloc with the right 3 bits assumed to 1791 be 0. 1792 @end deffn 1793 @deffn {} BFD_RELOC_D30V_21_PCREL_R 1794 This is an 18-bit pc-relative reloc with the right 3 bits assumed to 1795 be 0. Same as the previous reloc but on the right side of the 1796 container. 1797 @end deffn 1798 @deffn {} BFD_RELOC_D30V_32 1799 This is a 32-bit absolute reloc. 1800 @end deffn 1801 @deffn {} BFD_RELOC_D30V_32_PCREL 1802 This is a 32-bit pc-relative reloc. 1803 @end deffn 1804 @deffn {} BFD_RELOC_DLX_HI16_S 1805 @deffnx {} BFD_RELOC_DLX_LO16 1806 @deffnx {} BFD_RELOC_DLX_JMP26 1807 DLX relocs. 1808 @end deffn 1809 @deffn {} BFD_RELOC_M32C_HI8 1810 @deffnx {} BFD_RELOC_M32C_RL_JUMP 1811 @deffnx {} BFD_RELOC_M32C_RL_1ADDR 1812 @deffnx {} BFD_RELOC_M32C_RL_2ADDR 1813 Renesas M16C/M32C Relocations. 1814 @end deffn 1815 @deffn {} BFD_RELOC_M32R_24 1816 Renesas M32R (formerly Mitsubishi M32R) relocs. 1817 This is a 24 bit absolute address. 1818 @end deffn 1819 @deffn {} BFD_RELOC_M32R_10_PCREL 1820 This is a 10-bit pc-relative reloc with the right 2 bits assumed to 1821 be 0. 1822 @end deffn 1823 @deffn {} BFD_RELOC_M32R_18_PCREL 1824 This is an 18-bit reloc with the right 2 bits assumed to be 0. 1825 @end deffn 1826 @deffn {} BFD_RELOC_M32R_26_PCREL 1827 This is a 26-bit reloc with the right 2 bits assumed to be 0. 1828 @end deffn 1829 @deffn {} BFD_RELOC_M32R_HI16_ULO 1830 This is a 16-bit reloc containing the high 16 bits of an address 1831 used when the lower 16 bits are treated as unsigned. 1832 @end deffn 1833 @deffn {} BFD_RELOC_M32R_HI16_SLO 1834 This is a 16-bit reloc containing the high 16 bits of an address 1835 used when the lower 16 bits are treated as signed. 1836 @end deffn 1837 @deffn {} BFD_RELOC_M32R_LO16 1838 This is a 16-bit reloc containing the lower 16 bits of an address. 1839 @end deffn 1840 @deffn {} BFD_RELOC_M32R_SDA16 1841 This is a 16-bit reloc containing the small data area offset for use 1842 in add3, load, and store instructions. 1843 @end deffn 1844 @deffn {} BFD_RELOC_M32R_GOT24 1845 @deffnx {} BFD_RELOC_M32R_26_PLTREL 1846 @deffnx {} BFD_RELOC_M32R_COPY 1847 @deffnx {} BFD_RELOC_M32R_GLOB_DAT 1848 @deffnx {} BFD_RELOC_M32R_JMP_SLOT 1849 @deffnx {} BFD_RELOC_M32R_RELATIVE 1850 @deffnx {} BFD_RELOC_M32R_GOTOFF 1851 @deffnx {} BFD_RELOC_M32R_GOTOFF_HI_ULO 1852 @deffnx {} BFD_RELOC_M32R_GOTOFF_HI_SLO 1853 @deffnx {} BFD_RELOC_M32R_GOTOFF_LO 1854 @deffnx {} BFD_RELOC_M32R_GOTPC24 1855 @deffnx {} BFD_RELOC_M32R_GOT16_HI_ULO 1856 @deffnx {} BFD_RELOC_M32R_GOT16_HI_SLO 1857 @deffnx {} BFD_RELOC_M32R_GOT16_LO 1858 @deffnx {} BFD_RELOC_M32R_GOTPC_HI_ULO 1859 @deffnx {} BFD_RELOC_M32R_GOTPC_HI_SLO 1860 @deffnx {} BFD_RELOC_M32R_GOTPC_LO 1861 For PIC. 1862 @end deffn 1863 @deffn {} BFD_RELOC_NDS32_20 1864 NDS32 relocs. 1865 This is a 20 bit absolute address. 1866 @end deffn 1867 @deffn {} BFD_RELOC_NDS32_9_PCREL 1868 This is a 9-bit pc-relative reloc with the right 1 bit assumed to 1869 be 0. 1870 @end deffn 1871 @deffn {} BFD_RELOC_NDS32_WORD_9_PCREL 1872 This is a 9-bit pc-relative reloc with the right 1 bit assumed to 1873 be 0. 1874 @end deffn 1875 @deffn {} BFD_RELOC_NDS32_15_PCREL 1876 This is an 15-bit reloc with the right 1 bit assumed to be 0. 1877 @end deffn 1878 @deffn {} BFD_RELOC_NDS32_17_PCREL 1879 This is an 17-bit reloc with the right 1 bit assumed to be 0. 1880 @end deffn 1881 @deffn {} BFD_RELOC_NDS32_25_PCREL 1882 This is a 25-bit reloc with the right 1 bit assumed to be 0. 1883 @end deffn 1884 @deffn {} BFD_RELOC_NDS32_HI20 1885 This is a 20-bit reloc containing the high 20 bits of an address 1886 used with the lower 12 bits. 1887 @end deffn 1888 @deffn {} BFD_RELOC_NDS32_LO12S3 1889 This is a 12-bit reloc containing the lower 12 bits of an address 1890 then shift right by 3. This is used with ldi,sdi. 1891 @end deffn 1892 @deffn {} BFD_RELOC_NDS32_LO12S2 1893 This is a 12-bit reloc containing the lower 12 bits of an address 1894 then shift left by 2. This is used with lwi,swi. 1895 @end deffn 1896 @deffn {} BFD_RELOC_NDS32_LO12S1 1897 This is a 12-bit reloc containing the lower 12 bits of an address 1898 then shift left by 1. This is used with lhi,shi. 1899 @end deffn 1900 @deffn {} BFD_RELOC_NDS32_LO12S0 1901 This is a 12-bit reloc containing the lower 12 bits of an address 1902 then shift left by 0. This is used with lbisbi. 1903 @end deffn 1904 @deffn {} BFD_RELOC_NDS32_LO12S0_ORI 1905 This is a 12-bit reloc containing the lower 12 bits of an address 1906 then shift left by 0. This is only used with branch relaxations. 1907 @end deffn 1908 @deffn {} BFD_RELOC_NDS32_SDA15S3 1909 This is a 15-bit reloc containing the small data area 18-bit signed 1910 offset and shift left by 3 for use in ldi, sdi. 1911 @end deffn 1912 @deffn {} BFD_RELOC_NDS32_SDA15S2 1913 This is a 15-bit reloc containing the small data area 17-bit signed 1914 offset and shift left by 2 for use in lwi, swi. 1915 @end deffn 1916 @deffn {} BFD_RELOC_NDS32_SDA15S1 1917 This is a 15-bit reloc containing the small data area 16-bit signed 1918 offset and shift left by 1 for use in lhi, shi. 1919 @end deffn 1920 @deffn {} BFD_RELOC_NDS32_SDA15S0 1921 This is a 15-bit reloc containing the small data area 15-bit signed 1922 offset and shift left by 0 for use in lbi, sbi. 1923 @end deffn 1924 @deffn {} BFD_RELOC_NDS32_SDA16S3 1925 This is a 16-bit reloc containing the small data area 16-bit signed 1926 offset and shift left by 3. 1927 @end deffn 1928 @deffn {} BFD_RELOC_NDS32_SDA17S2 1929 This is a 17-bit reloc containing the small data area 17-bit signed 1930 offset and shift left by 2 for use in lwi.gp, swi.gp. 1931 @end deffn 1932 @deffn {} BFD_RELOC_NDS32_SDA18S1 1933 This is a 18-bit reloc containing the small data area 18-bit signed 1934 offset and shift left by 1 for use in lhi.gp, shi.gp. 1935 @end deffn 1936 @deffn {} BFD_RELOC_NDS32_SDA19S0 1937 This is a 19-bit reloc containing the small data area 19-bit signed 1938 offset and shift left by 0 for use in lbi.gp, sbi.gp. 1939 @end deffn 1940 @deffn {} BFD_RELOC_NDS32_GOT20 1941 @deffnx {} BFD_RELOC_NDS32_9_PLTREL 1942 @deffnx {} BFD_RELOC_NDS32_25_PLTREL 1943 @deffnx {} BFD_RELOC_NDS32_COPY 1944 @deffnx {} BFD_RELOC_NDS32_GLOB_DAT 1945 @deffnx {} BFD_RELOC_NDS32_JMP_SLOT 1946 @deffnx {} BFD_RELOC_NDS32_RELATIVE 1947 @deffnx {} BFD_RELOC_NDS32_GOTOFF 1948 @deffnx {} BFD_RELOC_NDS32_GOTOFF_HI20 1949 @deffnx {} BFD_RELOC_NDS32_GOTOFF_LO12 1950 @deffnx {} BFD_RELOC_NDS32_GOTPC20 1951 @deffnx {} BFD_RELOC_NDS32_GOT_HI20 1952 @deffnx {} BFD_RELOC_NDS32_GOT_LO12 1953 @deffnx {} BFD_RELOC_NDS32_GOTPC_HI20 1954 @deffnx {} BFD_RELOC_NDS32_GOTPC_LO12 1955 For PIC. 1956 @end deffn 1957 @deffn {} BFD_RELOC_NDS32_INSN16 1958 @deffnx {} BFD_RELOC_NDS32_LABEL 1959 @deffnx {} BFD_RELOC_NDS32_LONGCALL1 1960 @deffnx {} BFD_RELOC_NDS32_LONGCALL2 1961 @deffnx {} BFD_RELOC_NDS32_LONGCALL3 1962 @deffnx {} BFD_RELOC_NDS32_LONGJUMP1 1963 @deffnx {} BFD_RELOC_NDS32_LONGJUMP2 1964 @deffnx {} BFD_RELOC_NDS32_LONGJUMP3 1965 @deffnx {} BFD_RELOC_NDS32_LOADSTORE 1966 @deffnx {} BFD_RELOC_NDS32_9_FIXED 1967 @deffnx {} BFD_RELOC_NDS32_15_FIXED 1968 @deffnx {} BFD_RELOC_NDS32_17_FIXED 1969 @deffnx {} BFD_RELOC_NDS32_25_FIXED 1970 @deffnx {} BFD_RELOC_NDS32_LONGCALL4 1971 @deffnx {} BFD_RELOC_NDS32_LONGCALL5 1972 @deffnx {} BFD_RELOC_NDS32_LONGCALL6 1973 @deffnx {} BFD_RELOC_NDS32_LONGJUMP4 1974 @deffnx {} BFD_RELOC_NDS32_LONGJUMP5 1975 @deffnx {} BFD_RELOC_NDS32_LONGJUMP6 1976 @deffnx {} BFD_RELOC_NDS32_LONGJUMP7 1977 For relax. 1978 @end deffn 1979 @deffn {} BFD_RELOC_NDS32_PLTREL_HI20 1980 @deffnx {} BFD_RELOC_NDS32_PLTREL_LO12 1981 @deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_HI20 1982 @deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO12 1983 For PIC. 1984 @end deffn 1985 @deffn {} BFD_RELOC_NDS32_SDA12S2_DP 1986 @deffnx {} BFD_RELOC_NDS32_SDA12S2_SP 1987 @deffnx {} BFD_RELOC_NDS32_LO12S2_DP 1988 @deffnx {} BFD_RELOC_NDS32_LO12S2_SP 1989 For floating point. 1990 @end deffn 1991 @deffn {} BFD_RELOC_NDS32_DWARF2_OP1 1992 @deffnx {} BFD_RELOC_NDS32_DWARF2_OP2 1993 @deffnx {} BFD_RELOC_NDS32_DWARF2_LEB 1994 For dwarf2 debug_line. 1995 @end deffn 1996 @deffn {} BFD_RELOC_NDS32_UPDATE_TA 1997 For eliminating 16-bit instructions. 1998 @end deffn 1999 @deffn {} BFD_RELOC_NDS32_PLT_GOTREL_LO20 2000 @deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO15 2001 @deffnx {} BFD_RELOC_NDS32_PLT_GOTREL_LO19 2002 @deffnx {} BFD_RELOC_NDS32_GOT_LO15 2003 @deffnx {} BFD_RELOC_NDS32_GOT_LO19 2004 @deffnx {} BFD_RELOC_NDS32_GOTOFF_LO15 2005 @deffnx {} BFD_RELOC_NDS32_GOTOFF_LO19 2006 @deffnx {} BFD_RELOC_NDS32_GOT15S2 2007 @deffnx {} BFD_RELOC_NDS32_GOT17S2 2008 For PIC object relaxation. 2009 @end deffn 2010 @deffn {} BFD_RELOC_NDS32_5 2011 NDS32 relocs. 2012 This is a 5 bit absolute address. 2013 @end deffn 2014 @deffn {} BFD_RELOC_NDS32_10_UPCREL 2015 This is a 10-bit unsigned pc-relative reloc with the right 1 bit 2016 assumed to be 0. 2017 @end deffn 2018 @deffn {} BFD_RELOC_NDS32_SDA_FP7U2_RELA 2019 If fp were omitted, fp can used as another gp. 2020 @end deffn 2021 @deffn {} BFD_RELOC_NDS32_RELAX_ENTRY 2022 @deffnx {} BFD_RELOC_NDS32_GOT_SUFF 2023 @deffnx {} BFD_RELOC_NDS32_GOTOFF_SUFF 2024 @deffnx {} BFD_RELOC_NDS32_PLT_GOT_SUFF 2025 @deffnx {} BFD_RELOC_NDS32_MULCALL_SUFF 2026 @deffnx {} BFD_RELOC_NDS32_PTR 2027 @deffnx {} BFD_RELOC_NDS32_PTR_COUNT 2028 @deffnx {} BFD_RELOC_NDS32_PTR_RESOLVED 2029 @deffnx {} BFD_RELOC_NDS32_PLTBLOCK 2030 @deffnx {} BFD_RELOC_NDS32_RELAX_REGION_BEGIN 2031 @deffnx {} BFD_RELOC_NDS32_RELAX_REGION_END 2032 @deffnx {} BFD_RELOC_NDS32_MINUEND 2033 @deffnx {} BFD_RELOC_NDS32_SUBTRAHEND 2034 @deffnx {} BFD_RELOC_NDS32_DIFF8 2035 @deffnx {} BFD_RELOC_NDS32_DIFF16 2036 @deffnx {} BFD_RELOC_NDS32_DIFF32 2037 @deffnx {} BFD_RELOC_NDS32_DIFF_ULEB128 2038 @deffnx {} BFD_RELOC_NDS32_EMPTY 2039 Relaxation relative relocation types. 2040 @end deffn 2041 @deffn {} BFD_RELOC_NDS32_25_ABS 2042 This is a 25 bit absolute address. 2043 @end deffn 2044 @deffn {} BFD_RELOC_NDS32_DATA 2045 @deffnx {} BFD_RELOC_NDS32_TRAN 2046 @deffnx {} BFD_RELOC_NDS32_17IFC_PCREL 2047 @deffnx {} BFD_RELOC_NDS32_10IFCU_PCREL 2048 For ex9 and ifc using. 2049 @end deffn 2050 @deffn {} BFD_RELOC_NDS32_TPOFF 2051 @deffnx {} BFD_RELOC_NDS32_GOTTPOFF 2052 @deffnx {} BFD_RELOC_NDS32_TLS_LE_HI20 2053 @deffnx {} BFD_RELOC_NDS32_TLS_LE_LO12 2054 @deffnx {} BFD_RELOC_NDS32_TLS_LE_20 2055 @deffnx {} BFD_RELOC_NDS32_TLS_LE_15S0 2056 @deffnx {} BFD_RELOC_NDS32_TLS_LE_15S1 2057 @deffnx {} BFD_RELOC_NDS32_TLS_LE_15S2 2058 @deffnx {} BFD_RELOC_NDS32_TLS_LE_ADD 2059 @deffnx {} BFD_RELOC_NDS32_TLS_LE_LS 2060 @deffnx {} BFD_RELOC_NDS32_TLS_IE_HI20 2061 @deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12 2062 @deffnx {} BFD_RELOC_NDS32_TLS_IE_LO12S2 2063 @deffnx {} BFD_RELOC_NDS32_TLS_IEGP_HI20 2064 @deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12 2065 @deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LO12S2 2066 @deffnx {} BFD_RELOC_NDS32_TLS_IEGP_LW 2067 @deffnx {} BFD_RELOC_NDS32_TLS_DESC 2068 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_HI20 2069 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_LO12 2070 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_20 2071 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_SDA17S2 2072 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_ADD 2073 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_FUNC 2074 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_CALL 2075 @deffnx {} BFD_RELOC_NDS32_TLS_DESC_MEM 2076 @deffnx {} BFD_RELOC_NDS32_REMOVE 2077 @deffnx {} BFD_RELOC_NDS32_GROUP 2078 For TLS. 2079 @end deffn 2080 @deffn {} BFD_RELOC_NDS32_LSI 2081 For floating load store relaxation. 2082 @end deffn 2083 @deffn {} BFD_RELOC_V850_9_PCREL 2084 This is a 9-bit reloc. 2085 @end deffn 2086 @deffn {} BFD_RELOC_V850_22_PCREL 2087 This is a 22-bit reloc. 2088 @end deffn 2089 @deffn {} BFD_RELOC_V850_SDA_16_16_OFFSET 2090 This is a 16 bit offset from the short data area pointer. 2091 @end deffn 2092 @deffn {} BFD_RELOC_V850_SDA_15_16_OFFSET 2093 This is a 16 bit offset (of which only 15 bits are used) from the 2094 short data area pointer. 2095 @end deffn 2096 @deffn {} BFD_RELOC_V850_ZDA_16_16_OFFSET 2097 This is a 16 bit offset from the zero data area pointer. 2098 @end deffn 2099 @deffn {} BFD_RELOC_V850_ZDA_15_16_OFFSET 2100 This is a 16 bit offset (of which only 15 bits are used) from the 2101 zero data area pointer. 2102 @end deffn 2103 @deffn {} BFD_RELOC_V850_TDA_6_8_OFFSET 2104 This is an 8 bit offset (of which only 6 bits are used) from the 2105 tiny data area pointer. 2106 @end deffn 2107 @deffn {} BFD_RELOC_V850_TDA_7_8_OFFSET 2108 This is an 8bit offset (of which only 7 bits are used) from the tiny 2109 data area pointer. 2110 @end deffn 2111 @deffn {} BFD_RELOC_V850_TDA_7_7_OFFSET 2112 This is a 7 bit offset from the tiny data area pointer. 2113 @end deffn 2114 @deffn {} BFD_RELOC_V850_TDA_16_16_OFFSET 2115 This is a 16 bit offset from the tiny data area pointer. 2116 @end deffn 2117 @deffn {} BFD_RELOC_V850_TDA_4_5_OFFSET 2118 This is a 5 bit offset (of which only 4 bits are used) from the tiny 2119 data area pointer. 2120 @end deffn 2121 @deffn {} BFD_RELOC_V850_TDA_4_4_OFFSET 2122 This is a 4 bit offset from the tiny data area pointer. 2123 @end deffn 2124 @deffn {} BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET 2125 This is a 16 bit offset from the short data area pointer, with the 2126 bits placed non-contiguously in the instruction. 2127 @end deffn 2128 @deffn {} BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET 2129 This is a 16 bit offset from the zero data area pointer, with the 2130 bits placed non-contiguously in the instruction. 2131 @end deffn 2132 @deffn {} BFD_RELOC_V850_CALLT_6_7_OFFSET 2133 This is a 6 bit offset from the call table base pointer. 2134 @end deffn 2135 @deffn {} BFD_RELOC_V850_CALLT_16_16_OFFSET 2136 This is a 16 bit offset from the call table base pointer. 2137 @end deffn 2138 @deffn {} BFD_RELOC_V850_LONGCALL 2139 Used for relaxing indirect function calls. 2140 @end deffn 2141 @deffn {} BFD_RELOC_V850_LONGJUMP 2142 Used for relaxing indirect jumps. 2143 @end deffn 2144 @deffn {} BFD_RELOC_V850_ALIGN 2145 Used to maintain alignment whilst relaxing. 2146 @end deffn 2147 @deffn {} BFD_RELOC_V850_LO16_SPLIT_OFFSET 2148 This is a variation of BFD_RELOC_LO16 that can be used in v850e 2149 ld.bu instructions. 2150 @end deffn 2151 @deffn {} BFD_RELOC_V850_16_PCREL 2152 This is a 16-bit reloc. 2153 @end deffn 2154 @deffn {} BFD_RELOC_V850_17_PCREL 2155 This is a 17-bit reloc. 2156 @end deffn 2157 @deffn {} BFD_RELOC_V850_23 2158 This is a 23-bit reloc. 2159 @end deffn 2160 @deffn {} BFD_RELOC_V850_32_PCREL 2161 This is a 32-bit reloc. 2162 @end deffn 2163 @deffn {} BFD_RELOC_V850_32_ABS 2164 This is a 32-bit reloc. 2165 @end deffn 2166 @deffn {} BFD_RELOC_V850_16_SPLIT_OFFSET 2167 This is a 16-bit reloc. 2168 @end deffn 2169 @deffn {} BFD_RELOC_V850_16_S1 2170 This is a 16-bit reloc. 2171 @end deffn 2172 @deffn {} BFD_RELOC_V850_LO16_S1 2173 Low 16 bits. 16 bit shifted by 1. 2174 @end deffn 2175 @deffn {} BFD_RELOC_V850_CALLT_15_16_OFFSET 2176 This is a 16 bit offset from the call table base pointer. 2177 @end deffn 2178 @deffn {} BFD_RELOC_V850_32_GOTPCREL 2179 @deffnx {} BFD_RELOC_V850_16_GOT 2180 @deffnx {} BFD_RELOC_V850_32_GOT 2181 @deffnx {} BFD_RELOC_V850_22_PLT_PCREL 2182 @deffnx {} BFD_RELOC_V850_32_PLT_PCREL 2183 @deffnx {} BFD_RELOC_V850_COPY 2184 @deffnx {} BFD_RELOC_V850_GLOB_DAT 2185 @deffnx {} BFD_RELOC_V850_JMP_SLOT 2186 @deffnx {} BFD_RELOC_V850_RELATIVE 2187 @deffnx {} BFD_RELOC_V850_16_GOTOFF 2188 @deffnx {} BFD_RELOC_V850_32_GOTOFF 2189 DSO relocations. 2190 @end deffn 2191 @deffn {} BFD_RELOC_V850_CODE 2192 Start code. 2193 @end deffn 2194 @deffn {} BFD_RELOC_V850_DATA 2195 Start data in text. 2196 @end deffn 2197 @deffn {} BFD_RELOC_TIC30_LDP 2198 This is a 8bit DP reloc for the tms320c30, where the most 2199 significant 8 bits of a 24 bit word are placed into the least 2200 significant 8 bits of the opcode. 2201 @end deffn 2202 @deffn {} BFD_RELOC_TIC54X_PARTLS7 2203 This is a 7bit reloc for the tms320c54x, where the least 2204 significant 7 bits of a 16 bit word are placed into the least 2205 significant 7 bits of the opcode. 2206 @end deffn 2207 @deffn {} BFD_RELOC_TIC54X_PARTMS9 2208 This is a 9bit DP reloc for the tms320c54x, where the most 2209 significant 9 bits of a 16 bit word are placed into the least 2210 significant 9 bits of the opcode. 2211 @end deffn 2212 @deffn {} BFD_RELOC_TIC54X_23 2213 This is an extended address 23-bit reloc for the tms320c54x. 2214 @end deffn 2215 @deffn {} BFD_RELOC_TIC54X_16_OF_23 2216 This is a 16-bit reloc for the tms320c54x, where the least 2217 significant 16 bits of a 23-bit extended address are placed into 2218 the opcode. 2219 @end deffn 2220 @deffn {} BFD_RELOC_TIC54X_MS7_OF_23 2221 This is a reloc for the tms320c54x, where the most 2222 significant 7 bits of a 23-bit extended address are placed into 2223 the opcode. 2224 @end deffn 2225 @deffn {} BFD_RELOC_C6000_PCR_S21 2226 @deffnx {} BFD_RELOC_C6000_PCR_S12 2227 @deffnx {} BFD_RELOC_C6000_PCR_S10 2228 @deffnx {} BFD_RELOC_C6000_PCR_S7 2229 @deffnx {} BFD_RELOC_C6000_ABS_S16 2230 @deffnx {} BFD_RELOC_C6000_ABS_L16 2231 @deffnx {} BFD_RELOC_C6000_ABS_H16 2232 @deffnx {} BFD_RELOC_C6000_SBR_U15_B 2233 @deffnx {} BFD_RELOC_C6000_SBR_U15_H 2234 @deffnx {} BFD_RELOC_C6000_SBR_U15_W 2235 @deffnx {} BFD_RELOC_C6000_SBR_S16 2236 @deffnx {} BFD_RELOC_C6000_SBR_L16_B 2237 @deffnx {} BFD_RELOC_C6000_SBR_L16_H 2238 @deffnx {} BFD_RELOC_C6000_SBR_L16_W 2239 @deffnx {} BFD_RELOC_C6000_SBR_H16_B 2240 @deffnx {} BFD_RELOC_C6000_SBR_H16_H 2241 @deffnx {} BFD_RELOC_C6000_SBR_H16_W 2242 @deffnx {} BFD_RELOC_C6000_SBR_GOT_U15_W 2243 @deffnx {} BFD_RELOC_C6000_SBR_GOT_L16_W 2244 @deffnx {} BFD_RELOC_C6000_SBR_GOT_H16_W 2245 @deffnx {} BFD_RELOC_C6000_DSBT_INDEX 2246 @deffnx {} BFD_RELOC_C6000_PREL31 2247 @deffnx {} BFD_RELOC_C6000_COPY 2248 @deffnx {} BFD_RELOC_C6000_JUMP_SLOT 2249 @deffnx {} BFD_RELOC_C6000_EHTYPE 2250 @deffnx {} BFD_RELOC_C6000_PCR_H16 2251 @deffnx {} BFD_RELOC_C6000_PCR_L16 2252 @deffnx {} BFD_RELOC_C6000_ALIGN 2253 @deffnx {} BFD_RELOC_C6000_FPHEAD 2254 @deffnx {} BFD_RELOC_C6000_NOCMP 2255 TMS320C6000 relocations. 2256 @end deffn 2257 @deffn {} BFD_RELOC_FR30_48 2258 This is a 48 bit reloc for the FR30 that stores 32 bits. 2259 @end deffn 2260 @deffn {} BFD_RELOC_FR30_20 2261 This is a 32 bit reloc for the FR30 that stores 20 bits split up 2262 into two sections. 2263 @end deffn 2264 @deffn {} BFD_RELOC_FR30_6_IN_4 2265 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset 2266 in 4 bits. 2267 @end deffn 2268 @deffn {} BFD_RELOC_FR30_8_IN_8 2269 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset 2270 into 8 bits. 2271 @end deffn 2272 @deffn {} BFD_RELOC_FR30_9_IN_8 2273 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset 2274 into 8 bits. 2275 @end deffn 2276 @deffn {} BFD_RELOC_FR30_10_IN_8 2277 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset 2278 into 8 bits. 2279 @end deffn 2280 @deffn {} BFD_RELOC_FR30_9_PCREL 2281 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative 2282 short offset into 8 bits. 2283 @end deffn 2284 @deffn {} BFD_RELOC_FR30_12_PCREL 2285 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative 2286 short offset into 11 bits. 2287 @end deffn 2288 @deffn {} BFD_RELOC_MCORE_PCREL_IMM8BY4 2289 @deffnx {} BFD_RELOC_MCORE_PCREL_IMM11BY2 2290 @deffnx {} BFD_RELOC_MCORE_PCREL_IMM4BY2 2291 @deffnx {} BFD_RELOC_MCORE_PCREL_32 2292 @deffnx {} BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 2293 @deffnx {} BFD_RELOC_MCORE_RVA 2294 Motorola Mcore relocations. 2295 @end deffn 2296 @deffn {} BFD_RELOC_MEP_8 2297 @deffnx {} BFD_RELOC_MEP_16 2298 @deffnx {} BFD_RELOC_MEP_32 2299 @deffnx {} BFD_RELOC_MEP_PCREL8A2 2300 @deffnx {} BFD_RELOC_MEP_PCREL12A2 2301 @deffnx {} BFD_RELOC_MEP_PCREL17A2 2302 @deffnx {} BFD_RELOC_MEP_PCREL24A2 2303 @deffnx {} BFD_RELOC_MEP_PCABS24A2 2304 @deffnx {} BFD_RELOC_MEP_LOW16 2305 @deffnx {} BFD_RELOC_MEP_HI16U 2306 @deffnx {} BFD_RELOC_MEP_HI16S 2307 @deffnx {} BFD_RELOC_MEP_GPREL 2308 @deffnx {} BFD_RELOC_MEP_TPREL 2309 @deffnx {} BFD_RELOC_MEP_TPREL7 2310 @deffnx {} BFD_RELOC_MEP_TPREL7A2 2311 @deffnx {} BFD_RELOC_MEP_TPREL7A4 2312 @deffnx {} BFD_RELOC_MEP_UIMM24 2313 @deffnx {} BFD_RELOC_MEP_ADDR24A4 2314 @deffnx {} BFD_RELOC_MEP_GNU_VTINHERIT 2315 @deffnx {} BFD_RELOC_MEP_GNU_VTENTRY 2316 Toshiba Media Processor Relocations. 2317 @end deffn 2318 @deffn {} BFD_RELOC_METAG_HIADDR16 2319 @deffnx {} BFD_RELOC_METAG_LOADDR16 2320 @deffnx {} BFD_RELOC_METAG_RELBRANCH 2321 @deffnx {} BFD_RELOC_METAG_GETSETOFF 2322 @deffnx {} BFD_RELOC_METAG_HIOG 2323 @deffnx {} BFD_RELOC_METAG_LOOG 2324 @deffnx {} BFD_RELOC_METAG_REL8 2325 @deffnx {} BFD_RELOC_METAG_REL16 2326 @deffnx {} BFD_RELOC_METAG_HI16_GOTOFF 2327 @deffnx {} BFD_RELOC_METAG_LO16_GOTOFF 2328 @deffnx {} BFD_RELOC_METAG_GETSET_GOTOFF 2329 @deffnx {} BFD_RELOC_METAG_GETSET_GOT 2330 @deffnx {} BFD_RELOC_METAG_HI16_GOTPC 2331 @deffnx {} BFD_RELOC_METAG_LO16_GOTPC 2332 @deffnx {} BFD_RELOC_METAG_HI16_PLT 2333 @deffnx {} BFD_RELOC_METAG_LO16_PLT 2334 @deffnx {} BFD_RELOC_METAG_RELBRANCH_PLT 2335 @deffnx {} BFD_RELOC_METAG_GOTOFF 2336 @deffnx {} BFD_RELOC_METAG_PLT 2337 @deffnx {} BFD_RELOC_METAG_COPY 2338 @deffnx {} BFD_RELOC_METAG_JMP_SLOT 2339 @deffnx {} BFD_RELOC_METAG_RELATIVE 2340 @deffnx {} BFD_RELOC_METAG_GLOB_DAT 2341 @deffnx {} BFD_RELOC_METAG_TLS_GD 2342 @deffnx {} BFD_RELOC_METAG_TLS_LDM 2343 @deffnx {} BFD_RELOC_METAG_TLS_LDO_HI16 2344 @deffnx {} BFD_RELOC_METAG_TLS_LDO_LO16 2345 @deffnx {} BFD_RELOC_METAG_TLS_LDO 2346 @deffnx {} BFD_RELOC_METAG_TLS_IE 2347 @deffnx {} BFD_RELOC_METAG_TLS_IENONPIC 2348 @deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_HI16 2349 @deffnx {} BFD_RELOC_METAG_TLS_IENONPIC_LO16 2350 @deffnx {} BFD_RELOC_METAG_TLS_TPOFF 2351 @deffnx {} BFD_RELOC_METAG_TLS_DTPMOD 2352 @deffnx {} BFD_RELOC_METAG_TLS_DTPOFF 2353 @deffnx {} BFD_RELOC_METAG_TLS_LE 2354 @deffnx {} BFD_RELOC_METAG_TLS_LE_HI16 2355 @deffnx {} BFD_RELOC_METAG_TLS_LE_LO16 2356 Imagination Technologies Meta relocations. 2357 @end deffn 2358 @deffn {} BFD_RELOC_MMIX_GETA 2359 @deffnx {} BFD_RELOC_MMIX_GETA_1 2360 @deffnx {} BFD_RELOC_MMIX_GETA_2 2361 @deffnx {} BFD_RELOC_MMIX_GETA_3 2362 These are relocations for the GETA instruction. 2363 @end deffn 2364 @deffn {} BFD_RELOC_MMIX_CBRANCH 2365 @deffnx {} BFD_RELOC_MMIX_CBRANCH_J 2366 @deffnx {} BFD_RELOC_MMIX_CBRANCH_1 2367 @deffnx {} BFD_RELOC_MMIX_CBRANCH_2 2368 @deffnx {} BFD_RELOC_MMIX_CBRANCH_3 2369 These are relocations for a conditional branch instruction. 2370 @end deffn 2371 @deffn {} BFD_RELOC_MMIX_PUSHJ 2372 @deffnx {} BFD_RELOC_MMIX_PUSHJ_1 2373 @deffnx {} BFD_RELOC_MMIX_PUSHJ_2 2374 @deffnx {} BFD_RELOC_MMIX_PUSHJ_3 2375 @deffnx {} BFD_RELOC_MMIX_PUSHJ_STUBBABLE 2376 These are relocations for the PUSHJ instruction. 2377 @end deffn 2378 @deffn {} BFD_RELOC_MMIX_JMP 2379 @deffnx {} BFD_RELOC_MMIX_JMP_1 2380 @deffnx {} BFD_RELOC_MMIX_JMP_2 2381 @deffnx {} BFD_RELOC_MMIX_JMP_3 2382 These are relocations for the JMP instruction. 2383 @end deffn 2384 @deffn {} BFD_RELOC_MMIX_ADDR19 2385 This is a relocation for a relative address as in a GETA instruction 2386 or a branch. 2387 @end deffn 2388 @deffn {} BFD_RELOC_MMIX_ADDR27 2389 This is a relocation for a relative address as in a JMP instruction. 2390 @end deffn 2391 @deffn {} BFD_RELOC_MMIX_REG_OR_BYTE 2392 This is a relocation for an instruction field that may be a general 2393 register or a value 0..255. 2394 @end deffn 2395 @deffn {} BFD_RELOC_MMIX_REG 2396 This is a relocation for an instruction field that may be a general 2397 register. 2398 @end deffn 2399 @deffn {} BFD_RELOC_MMIX_BASE_PLUS_OFFSET 2400 This is a relocation for two instruction fields holding a register 2401 and an offset, the equivalent of the relocation. 2402 @end deffn 2403 @deffn {} BFD_RELOC_MMIX_LOCAL 2404 This relocation is an assertion that the expression is not allocated 2405 as a global register. It does not modify contents. 2406 @end deffn 2407 @deffn {} BFD_RELOC_AVR_7_PCREL 2408 This is a 16 bit reloc for the AVR that stores 8 bit pc relative 2409 short offset into 7 bits. 2410 @end deffn 2411 @deffn {} BFD_RELOC_AVR_13_PCREL 2412 This is a 16 bit reloc for the AVR that stores 13 bit pc relative 2413 short offset into 12 bits. 2414 @end deffn 2415 @deffn {} BFD_RELOC_AVR_16_PM 2416 This is a 16 bit reloc for the AVR that stores 17 bit value (usually 2417 program memory address) into 16 bits. 2418 @end deffn 2419 @deffn {} BFD_RELOC_AVR_LO8_LDI 2420 This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2421 data memory address) into 8 bit immediate value of LDI insn. 2422 @end deffn 2423 @deffn {} BFD_RELOC_AVR_HI8_LDI 2424 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2425 of data memory address) into 8 bit immediate value of LDI insn. 2426 @end deffn 2427 @deffn {} BFD_RELOC_AVR_HH8_LDI 2428 This is a 16 bit reloc for the AVR that stores 8 bit value (most 2429 high 8 bit of program memory address) into 8 bit immediate value of 2430 LDI insn. 2431 @end deffn 2432 @deffn {} BFD_RELOC_AVR_MS8_LDI 2433 This is a 16 bit reloc for the AVR that stores 8 bit value (most 2434 high 8 bit of 32 bit value) into 8 bit immediate value of LDI insn. 2435 @end deffn 2436 @deffn {} BFD_RELOC_AVR_LO8_LDI_NEG 2437 This is a 16 bit reloc for the AVR that stores negated 8 bit value 2438 (usually data memory address) into 8 bit immediate value of SUBI insn. 2439 @end deffn 2440 @deffn {} BFD_RELOC_AVR_HI8_LDI_NEG 2441 This is a 16 bit reloc for the AVR that stores negated 8 bit value 2442 (high 8 bit of data memory address) into 8 bit immediate value of 2443 SUBI insn. 2444 @end deffn 2445 @deffn {} BFD_RELOC_AVR_HH8_LDI_NEG 2446 This is a 16 bit reloc for the AVR that stores negated 8 bit value 2447 (most high 8 bit of program memory address) into 8 bit immediate 2448 value of LDI or SUBI insn. 2449 @end deffn 2450 @deffn {} BFD_RELOC_AVR_MS8_LDI_NEG 2451 This is a 16 bit reloc for the AVR that stores negated 8 bit value 2452 (msb of 32 bit value) into 8 bit immediate value of LDI insn. 2453 @end deffn 2454 @deffn {} BFD_RELOC_AVR_LO8_LDI_PM 2455 This is a 16 bit reloc for the AVR that stores 8 bit value (usually 2456 command address) into 8 bit immediate value of LDI insn. 2457 @end deffn 2458 @deffn {} BFD_RELOC_AVR_LO8_LDI_GS 2459 This is a 16 bit reloc for the AVR that stores 8 bit value 2460 (command address) into 8 bit immediate value of LDI insn. If the 2461 address is beyond the 128k boundary, the linker inserts a jump stub 2462 for this reloc in the lower 128k. 2463 @end deffn 2464 @deffn {} BFD_RELOC_AVR_HI8_LDI_PM 2465 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2466 of command address) into 8 bit immediate value of LDI insn. 2467 @end deffn 2468 @deffn {} BFD_RELOC_AVR_HI8_LDI_GS 2469 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit 2470 of command address) into 8 bit immediate value of LDI insn. If the 2471 address is beyond the 128k boundary, the linker inserts a jump stub 2472 for this reloc below 128k. 2473 @end deffn 2474 @deffn {} BFD_RELOC_AVR_HH8_LDI_PM 2475 This is a 16 bit reloc for the AVR that stores 8 bit value (most 2476 high 8 bit of command address) into 8 bit immediate value of LDI 2477 insn. 2478 @end deffn 2479 @deffn {} BFD_RELOC_AVR_LO8_LDI_PM_NEG 2480 This is a 16 bit reloc for the AVR that stores negated 8 bit value 2481 (usually command address) into 8 bit immediate value of SUBI insn. 2482 @end deffn 2483 @deffn {} BFD_RELOC_AVR_HI8_LDI_PM_NEG 2484 This is a 16 bit reloc for the AVR that stores negated 8 bit value 2485 (high 8 bit of 16 bit command address) into 8 bit immediate value 2486 of SUBI insn. 2487 @end deffn 2488 @deffn {} BFD_RELOC_AVR_HH8_LDI_PM_NEG 2489 This is a 16 bit reloc for the AVR that stores negated 8 bit value 2490 (high 6 bit of 22 bit command address) into 8 bit immediate 2491 value of SUBI insn. 2492 @end deffn 2493 @deffn {} BFD_RELOC_AVR_CALL 2494 This is a 32 bit reloc for the AVR that stores 23 bit value 2495 into 22 bits. 2496 @end deffn 2497 @deffn {} BFD_RELOC_AVR_LDI 2498 This is a 16 bit reloc for the AVR that stores all needed bits 2499 for absolute addressing with ldi with overflow check to linktime. 2500 @end deffn 2501 @deffn {} BFD_RELOC_AVR_6 2502 This is a 6 bit reloc for the AVR that stores offset for ldd/std 2503 instructions. 2504 @end deffn 2505 @deffn {} BFD_RELOC_AVR_6_ADIW 2506 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw 2507 instructions. 2508 @end deffn 2509 @deffn {} BFD_RELOC_AVR_8_LO 2510 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol 2511 in .byte lo8(symbol). 2512 @end deffn 2513 @deffn {} BFD_RELOC_AVR_8_HI 2514 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol 2515 in .byte hi8(symbol). 2516 @end deffn 2517 @deffn {} BFD_RELOC_AVR_8_HLO 2518 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol 2519 in .byte hlo8(symbol). 2520 @end deffn 2521 @deffn {} BFD_RELOC_AVR_DIFF8 2522 @deffnx {} BFD_RELOC_AVR_DIFF16 2523 @deffnx {} BFD_RELOC_AVR_DIFF32 2524 AVR relocations to mark the difference of two local symbols. 2525 These are only needed to support linker relaxation and can be ignored 2526 when not relaxing. The field is set to the value of the difference 2527 assuming no relaxation. The relocation encodes the position of the 2528 second symbol so the linker can determine whether to adjust the field 2529 value. 2530 @end deffn 2531 @deffn {} BFD_RELOC_AVR_LDS_STS_16 2532 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit 2533 lds and sts instructions supported only tiny core. 2534 @end deffn 2535 @deffn {} BFD_RELOC_AVR_PORT6 2536 This is a 6 bit reloc for the AVR that stores an I/O register 2537 number for the IN and OUT instructions. 2538 @end deffn 2539 @deffn {} BFD_RELOC_AVR_PORT5 2540 This is a 5 bit reloc for the AVR that stores an I/O register 2541 number for the SBIC, SBIS, SBI and CBI instructions. 2542 @end deffn 2543 @deffn {} BFD_RELOC_RISCV_HI20 2544 @deffnx {} BFD_RELOC_RISCV_PCREL_HI20 2545 @deffnx {} BFD_RELOC_RISCV_PCREL_LO12_I 2546 @deffnx {} BFD_RELOC_RISCV_PCREL_LO12_S 2547 @deffnx {} BFD_RELOC_RISCV_LO12_I 2548 @deffnx {} BFD_RELOC_RISCV_LO12_S 2549 @deffnx {} BFD_RELOC_RISCV_GPREL12_I 2550 @deffnx {} BFD_RELOC_RISCV_GPREL12_S 2551 @deffnx {} BFD_RELOC_RISCV_TPREL_HI20 2552 @deffnx {} BFD_RELOC_RISCV_TPREL_LO12_I 2553 @deffnx {} BFD_RELOC_RISCV_TPREL_LO12_S 2554 @deffnx {} BFD_RELOC_RISCV_TPREL_ADD 2555 @deffnx {} BFD_RELOC_RISCV_CALL 2556 @deffnx {} BFD_RELOC_RISCV_CALL_PLT 2557 @deffnx {} BFD_RELOC_RISCV_ADD8 2558 @deffnx {} BFD_RELOC_RISCV_ADD16 2559 @deffnx {} BFD_RELOC_RISCV_ADD32 2560 @deffnx {} BFD_RELOC_RISCV_ADD64 2561 @deffnx {} BFD_RELOC_RISCV_SUB8 2562 @deffnx {} BFD_RELOC_RISCV_SUB16 2563 @deffnx {} BFD_RELOC_RISCV_SUB32 2564 @deffnx {} BFD_RELOC_RISCV_SUB64 2565 @deffnx {} BFD_RELOC_RISCV_GOT_HI20 2566 @deffnx {} BFD_RELOC_RISCV_TLS_GOT_HI20 2567 @deffnx {} BFD_RELOC_RISCV_TLS_GD_HI20 2568 @deffnx {} BFD_RELOC_RISCV_JMP 2569 @deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD32 2570 @deffnx {} BFD_RELOC_RISCV_TLS_DTPREL32 2571 @deffnx {} BFD_RELOC_RISCV_TLS_DTPMOD64 2572 @deffnx {} BFD_RELOC_RISCV_TLS_DTPREL64 2573 @deffnx {} BFD_RELOC_RISCV_TLS_TPREL32 2574 @deffnx {} BFD_RELOC_RISCV_TLS_TPREL64 2575 @deffnx {} BFD_RELOC_RISCV_TLSDESC_HI20 2576 @deffnx {} BFD_RELOC_RISCV_TLSDESC_LOAD_LO12 2577 @deffnx {} BFD_RELOC_RISCV_TLSDESC_ADD_LO12 2578 @deffnx {} BFD_RELOC_RISCV_TLSDESC_CALL 2579 @deffnx {} BFD_RELOC_RISCV_ALIGN 2580 @deffnx {} BFD_RELOC_RISCV_RVC_BRANCH 2581 @deffnx {} BFD_RELOC_RISCV_RVC_JUMP 2582 @deffnx {} BFD_RELOC_RISCV_RELAX 2583 @deffnx {} BFD_RELOC_RISCV_CFA 2584 @deffnx {} BFD_RELOC_RISCV_SUB6 2585 @deffnx {} BFD_RELOC_RISCV_SET6 2586 @deffnx {} BFD_RELOC_RISCV_SET8 2587 @deffnx {} BFD_RELOC_RISCV_SET16 2588 @deffnx {} BFD_RELOC_RISCV_SET32 2589 @deffnx {} BFD_RELOC_RISCV_32_PCREL 2590 @deffnx {} BFD_RELOC_RISCV_SET_ULEB128 2591 @deffnx {} BFD_RELOC_RISCV_SUB_ULEB128 2592 RISC-V relocations. 2593 @end deffn 2594 @deffn {} BFD_RELOC_RL78_NEG8 2595 @deffnx {} BFD_RELOC_RL78_NEG16 2596 @deffnx {} BFD_RELOC_RL78_NEG24 2597 @deffnx {} BFD_RELOC_RL78_NEG32 2598 @deffnx {} BFD_RELOC_RL78_16_OP 2599 @deffnx {} BFD_RELOC_RL78_24_OP 2600 @deffnx {} BFD_RELOC_RL78_32_OP 2601 @deffnx {} BFD_RELOC_RL78_8U 2602 @deffnx {} BFD_RELOC_RL78_16U 2603 @deffnx {} BFD_RELOC_RL78_24U 2604 @deffnx {} BFD_RELOC_RL78_DIR3U_PCREL 2605 @deffnx {} BFD_RELOC_RL78_DIFF 2606 @deffnx {} BFD_RELOC_RL78_GPRELB 2607 @deffnx {} BFD_RELOC_RL78_GPRELW 2608 @deffnx {} BFD_RELOC_RL78_GPRELL 2609 @deffnx {} BFD_RELOC_RL78_SYM 2610 @deffnx {} BFD_RELOC_RL78_OP_SUBTRACT 2611 @deffnx {} BFD_RELOC_RL78_OP_NEG 2612 @deffnx {} BFD_RELOC_RL78_OP_AND 2613 @deffnx {} BFD_RELOC_RL78_OP_SHRA 2614 @deffnx {} BFD_RELOC_RL78_ABS8 2615 @deffnx {} BFD_RELOC_RL78_ABS16 2616 @deffnx {} BFD_RELOC_RL78_ABS16_REV 2617 @deffnx {} BFD_RELOC_RL78_ABS32 2618 @deffnx {} BFD_RELOC_RL78_ABS32_REV 2619 @deffnx {} BFD_RELOC_RL78_ABS16U 2620 @deffnx {} BFD_RELOC_RL78_ABS16UW 2621 @deffnx {} BFD_RELOC_RL78_ABS16UL 2622 @deffnx {} BFD_RELOC_RL78_RELAX 2623 @deffnx {} BFD_RELOC_RL78_HI16 2624 @deffnx {} BFD_RELOC_RL78_HI8 2625 @deffnx {} BFD_RELOC_RL78_LO16 2626 @deffnx {} BFD_RELOC_RL78_CODE 2627 @deffnx {} BFD_RELOC_RL78_SADDR 2628 Renesas RL78 Relocations. 2629 @end deffn 2630 @deffn {} BFD_RELOC_RX_NEG8 2631 @deffnx {} BFD_RELOC_RX_NEG16 2632 @deffnx {} BFD_RELOC_RX_NEG24 2633 @deffnx {} BFD_RELOC_RX_NEG32 2634 @deffnx {} BFD_RELOC_RX_16_OP 2635 @deffnx {} BFD_RELOC_RX_24_OP 2636 @deffnx {} BFD_RELOC_RX_32_OP 2637 @deffnx {} BFD_RELOC_RX_8U 2638 @deffnx {} BFD_RELOC_RX_16U 2639 @deffnx {} BFD_RELOC_RX_24U 2640 @deffnx {} BFD_RELOC_RX_DIR3U_PCREL 2641 @deffnx {} BFD_RELOC_RX_DIFF 2642 @deffnx {} BFD_RELOC_RX_GPRELB 2643 @deffnx {} BFD_RELOC_RX_GPRELW 2644 @deffnx {} BFD_RELOC_RX_GPRELL 2645 @deffnx {} BFD_RELOC_RX_SYM 2646 @deffnx {} BFD_RELOC_RX_OP_SUBTRACT 2647 @deffnx {} BFD_RELOC_RX_OP_NEG 2648 @deffnx {} BFD_RELOC_RX_ABS8 2649 @deffnx {} BFD_RELOC_RX_ABS16 2650 @deffnx {} BFD_RELOC_RX_ABS16_REV 2651 @deffnx {} BFD_RELOC_RX_ABS32 2652 @deffnx {} BFD_RELOC_RX_ABS32_REV 2653 @deffnx {} BFD_RELOC_RX_ABS16U 2654 @deffnx {} BFD_RELOC_RX_ABS16UW 2655 @deffnx {} BFD_RELOC_RX_ABS16UL 2656 @deffnx {} BFD_RELOC_RX_RELAX 2657 Renesas RX Relocations. 2658 @end deffn 2659 @deffn {} BFD_RELOC_390_12 2660 Direct 12 bit. 2661 @end deffn 2662 @deffn {} BFD_RELOC_390_GOT12 2663 12 bit GOT offset. 2664 @end deffn 2665 @deffn {} BFD_RELOC_390_PLT32 2666 32 bit PC relative PLT address. 2667 @end deffn 2668 @deffn {} BFD_RELOC_390_COPY 2669 Copy symbol at runtime. 2670 @end deffn 2671 @deffn {} BFD_RELOC_390_GLOB_DAT 2672 Create GOT entry. 2673 @end deffn 2674 @deffn {} BFD_RELOC_390_JMP_SLOT 2675 Create PLT entry. 2676 @end deffn 2677 @deffn {} BFD_RELOC_390_RELATIVE 2678 Adjust by program base. 2679 @end deffn 2680 @deffn {} BFD_RELOC_390_GOTPC 2681 32 bit PC relative offset to GOT. 2682 @end deffn 2683 @deffn {} BFD_RELOC_390_GOT16 2684 16 bit GOT offset. 2685 @end deffn 2686 @deffn {} BFD_RELOC_390_PC12DBL 2687 PC relative 12 bit shifted by 1. 2688 @end deffn 2689 @deffn {} BFD_RELOC_390_PLT12DBL 2690 12 bit PC rel. PLT shifted by 1. 2691 @end deffn 2692 @deffn {} BFD_RELOC_390_PC16DBL 2693 PC relative 16 bit shifted by 1. 2694 @end deffn 2695 @deffn {} BFD_RELOC_390_PLT16DBL 2696 16 bit PC rel. PLT shifted by 1. 2697 @end deffn 2698 @deffn {} BFD_RELOC_390_PC24DBL 2699 PC relative 24 bit shifted by 1. 2700 @end deffn 2701 @deffn {} BFD_RELOC_390_PLT24DBL 2702 24 bit PC rel. PLT shifted by 1. 2703 @end deffn 2704 @deffn {} BFD_RELOC_390_PC32DBL 2705 PC relative 32 bit shifted by 1. 2706 @end deffn 2707 @deffn {} BFD_RELOC_390_PLT32DBL 2708 32 bit PC rel. PLT shifted by 1. 2709 @end deffn 2710 @deffn {} BFD_RELOC_390_GOTPCDBL 2711 32 bit PC rel. GOT shifted by 1. 2712 @end deffn 2713 @deffn {} BFD_RELOC_390_GOT64 2714 64 bit GOT offset. 2715 @end deffn 2716 @deffn {} BFD_RELOC_390_PLT64 2717 64 bit PC relative PLT address. 2718 @end deffn 2719 @deffn {} BFD_RELOC_390_GOTENT 2720 32 bit rel. offset to GOT entry. 2721 @end deffn 2722 @deffn {} BFD_RELOC_390_GOTOFF64 2723 64 bit offset to GOT. 2724 @end deffn 2725 @deffn {} BFD_RELOC_390_GOTPLT12 2726 12-bit offset to symbol-entry within GOT, with PLT handling. 2727 @end deffn 2728 @deffn {} BFD_RELOC_390_GOTPLT16 2729 16-bit offset to symbol-entry within GOT, with PLT handling. 2730 @end deffn 2731 @deffn {} BFD_RELOC_390_GOTPLT32 2732 32-bit offset to symbol-entry within GOT, with PLT handling. 2733 @end deffn 2734 @deffn {} BFD_RELOC_390_GOTPLT64 2735 64-bit offset to symbol-entry within GOT, with PLT handling. 2736 @end deffn 2737 @deffn {} BFD_RELOC_390_GOTPLTENT 2738 32-bit rel. offset to symbol-entry within GOT, with PLT handling. 2739 @end deffn 2740 @deffn {} BFD_RELOC_390_PLTOFF16 2741 16-bit rel. offset from the GOT to a PLT entry. 2742 @end deffn 2743 @deffn {} BFD_RELOC_390_PLTOFF32 2744 32-bit rel. offset from the GOT to a PLT entry. 2745 @end deffn 2746 @deffn {} BFD_RELOC_390_PLTOFF64 2747 64-bit rel. offset from the GOT to a PLT entry. 2748 @end deffn 2749 @deffn {} BFD_RELOC_390_TLS_LOAD 2750 @deffnx {} BFD_RELOC_390_TLS_GDCALL 2751 @deffnx {} BFD_RELOC_390_TLS_LDCALL 2752 @deffnx {} BFD_RELOC_390_TLS_GD32 2753 @deffnx {} BFD_RELOC_390_TLS_GD64 2754 @deffnx {} BFD_RELOC_390_TLS_GOTIE12 2755 @deffnx {} BFD_RELOC_390_TLS_GOTIE32 2756 @deffnx {} BFD_RELOC_390_TLS_GOTIE64 2757 @deffnx {} BFD_RELOC_390_TLS_LDM32 2758 @deffnx {} BFD_RELOC_390_TLS_LDM64 2759 @deffnx {} BFD_RELOC_390_TLS_IE32 2760 @deffnx {} BFD_RELOC_390_TLS_IE64 2761 @deffnx {} BFD_RELOC_390_TLS_IEENT 2762 @deffnx {} BFD_RELOC_390_TLS_LE32 2763 @deffnx {} BFD_RELOC_390_TLS_LE64 2764 @deffnx {} BFD_RELOC_390_TLS_LDO32 2765 @deffnx {} BFD_RELOC_390_TLS_LDO64 2766 @deffnx {} BFD_RELOC_390_TLS_DTPMOD 2767 @deffnx {} BFD_RELOC_390_TLS_DTPOFF 2768 @deffnx {} BFD_RELOC_390_TLS_TPOFF 2769 s390 tls relocations. 2770 @end deffn 2771 @deffn {} BFD_RELOC_390_20 2772 @deffnx {} BFD_RELOC_390_GOT20 2773 @deffnx {} BFD_RELOC_390_GOTPLT20 2774 @deffnx {} BFD_RELOC_390_TLS_GOTIE20 2775 Long displacement extension. 2776 @end deffn 2777 @deffn {} BFD_RELOC_390_IRELATIVE 2778 STT_GNU_IFUNC relocation. 2779 @end deffn 2780 @deffn {} BFD_RELOC_SCORE_GPREL15 2781 Score relocations. 2782 Low 16 bit for load/store. 2783 @end deffn 2784 @deffn {} BFD_RELOC_SCORE_DUMMY2 2785 @deffnx {} BFD_RELOC_SCORE_JMP 2786 This is a 24-bit reloc with the right 1 bit assumed to be 0. 2787 @end deffn 2788 @deffn {} BFD_RELOC_SCORE_BRANCH 2789 This is a 19-bit reloc with the right 1 bit assumed to be 0. 2790 @end deffn 2791 @deffn {} BFD_RELOC_SCORE_IMM30 2792 This is a 32-bit reloc for 48-bit instructions. 2793 @end deffn 2794 @deffn {} BFD_RELOC_SCORE_IMM32 2795 This is a 32-bit reloc for 48-bit instructions. 2796 @end deffn 2797 @deffn {} BFD_RELOC_SCORE16_JMP 2798 This is a 11-bit reloc with the right 1 bit assumed to be 0. 2799 @end deffn 2800 @deffn {} BFD_RELOC_SCORE16_BRANCH 2801 This is a 8-bit reloc with the right 1 bit assumed to be 0. 2802 @end deffn 2803 @deffn {} BFD_RELOC_SCORE_BCMP 2804 This is a 9-bit reloc with the right 1 bit assumed to be 0. 2805 @end deffn 2806 @deffn {} BFD_RELOC_SCORE_GOT15 2807 @deffnx {} BFD_RELOC_SCORE_GOT_LO16 2808 @deffnx {} BFD_RELOC_SCORE_CALL15 2809 @deffnx {} BFD_RELOC_SCORE_DUMMY_HI16 2810 Undocumented Score relocs. 2811 @end deffn 2812 @deffn {} BFD_RELOC_IP2K_FR9 2813 Scenix IP2K - 9-bit register number / data address. 2814 @end deffn 2815 @deffn {} BFD_RELOC_IP2K_BANK 2816 Scenix IP2K - 4-bit register/data bank number. 2817 @end deffn 2818 @deffn {} BFD_RELOC_IP2K_ADDR16CJP 2819 Scenix IP2K - low 13 bits of instruction word address. 2820 @end deffn 2821 @deffn {} BFD_RELOC_IP2K_PAGE3 2822 Scenix IP2K - high 3 bits of instruction word address. 2823 @end deffn 2824 @deffn {} BFD_RELOC_IP2K_LO8DATA 2825 @deffnx {} BFD_RELOC_IP2K_HI8DATA 2826 @deffnx {} BFD_RELOC_IP2K_EX8DATA 2827 Scenix IP2K - ext/low/high 8 bits of data address. 2828 @end deffn 2829 @deffn {} BFD_RELOC_IP2K_LO8INSN 2830 @deffnx {} BFD_RELOC_IP2K_HI8INSN 2831 Scenix IP2K - low/high 8 bits of instruction word address. 2832 @end deffn 2833 @deffn {} BFD_RELOC_IP2K_PC_SKIP 2834 Scenix IP2K - even/odd PC modifier to modify snb pcl.0. 2835 @end deffn 2836 @deffn {} BFD_RELOC_IP2K_TEXT 2837 Scenix IP2K - 16 bit word address in text section. 2838 @end deffn 2839 @deffn {} BFD_RELOC_IP2K_FR_OFFSET 2840 Scenix IP2K - 7-bit sp or dp offset. 2841 @end deffn 2842 @deffn {} BFD_RELOC_VPE4KMATH_DATA 2843 @deffnx {} BFD_RELOC_VPE4KMATH_INSN 2844 Scenix VPE4K coprocessor - data/insn-space addressing. 2845 @end deffn 2846 @deffn {} BFD_RELOC_VTABLE_INHERIT 2847 @deffnx {} BFD_RELOC_VTABLE_ENTRY 2848 These two relocations are used by the linker to determine which of 2849 the entries in a C++ virtual function table are actually used. When 2850 the --gc-sections option is given, the linker will zero out the 2851 entries that are not used, so that the code for those functions need 2852 not be included in the output. 2853 2854 VTABLE_INHERIT is a zero-space relocation used to describe to the 2855 linker the inheritance tree of a C++ virtual function table. The 2856 relocation's symbol should be the parent class' vtable, and the 2857 relocation should be located at the child vtable. 2858 2859 VTABLE_ENTRY is a zero-space relocation that describes the use of a 2860 virtual function table entry. The reloc's symbol should refer to 2861 the table of the class mentioned in the code. Off of that base, an 2862 offset describes the entry that is being used. For Rela hosts, this 2863 offset is stored in the reloc's addend. For Rel hosts, we are 2864 forced to put this offset in the reloc's section offset. 2865 @end deffn 2866 @deffn {} BFD_RELOC_IA64_IMM14 2867 @deffnx {} BFD_RELOC_IA64_IMM22 2868 @deffnx {} BFD_RELOC_IA64_IMM64 2869 @deffnx {} BFD_RELOC_IA64_DIR32MSB 2870 @deffnx {} BFD_RELOC_IA64_DIR32LSB 2871 @deffnx {} BFD_RELOC_IA64_DIR64MSB 2872 @deffnx {} BFD_RELOC_IA64_DIR64LSB 2873 @deffnx {} BFD_RELOC_IA64_GPREL22 2874 @deffnx {} BFD_RELOC_IA64_GPREL64I 2875 @deffnx {} BFD_RELOC_IA64_GPREL32MSB 2876 @deffnx {} BFD_RELOC_IA64_GPREL32LSB 2877 @deffnx {} BFD_RELOC_IA64_GPREL64MSB 2878 @deffnx {} BFD_RELOC_IA64_GPREL64LSB 2879 @deffnx {} BFD_RELOC_IA64_LTOFF22 2880 @deffnx {} BFD_RELOC_IA64_LTOFF64I 2881 @deffnx {} BFD_RELOC_IA64_PLTOFF22 2882 @deffnx {} BFD_RELOC_IA64_PLTOFF64I 2883 @deffnx {} BFD_RELOC_IA64_PLTOFF64MSB 2884 @deffnx {} BFD_RELOC_IA64_PLTOFF64LSB 2885 @deffnx {} BFD_RELOC_IA64_FPTR64I 2886 @deffnx {} BFD_RELOC_IA64_FPTR32MSB 2887 @deffnx {} BFD_RELOC_IA64_FPTR32LSB 2888 @deffnx {} BFD_RELOC_IA64_FPTR64MSB 2889 @deffnx {} BFD_RELOC_IA64_FPTR64LSB 2890 @deffnx {} BFD_RELOC_IA64_PCREL21B 2891 @deffnx {} BFD_RELOC_IA64_PCREL21BI 2892 @deffnx {} BFD_RELOC_IA64_PCREL21M 2893 @deffnx {} BFD_RELOC_IA64_PCREL21F 2894 @deffnx {} BFD_RELOC_IA64_PCREL22 2895 @deffnx {} BFD_RELOC_IA64_PCREL60B 2896 @deffnx {} BFD_RELOC_IA64_PCREL64I 2897 @deffnx {} BFD_RELOC_IA64_PCREL32MSB 2898 @deffnx {} BFD_RELOC_IA64_PCREL32LSB 2899 @deffnx {} BFD_RELOC_IA64_PCREL64MSB 2900 @deffnx {} BFD_RELOC_IA64_PCREL64LSB 2901 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR22 2902 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64I 2903 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32MSB 2904 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR32LSB 2905 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64MSB 2906 @deffnx {} BFD_RELOC_IA64_LTOFF_FPTR64LSB 2907 @deffnx {} BFD_RELOC_IA64_SEGREL32MSB 2908 @deffnx {} BFD_RELOC_IA64_SEGREL32LSB 2909 @deffnx {} BFD_RELOC_IA64_SEGREL64MSB 2910 @deffnx {} BFD_RELOC_IA64_SEGREL64LSB 2911 @deffnx {} BFD_RELOC_IA64_SECREL32MSB 2912 @deffnx {} BFD_RELOC_IA64_SECREL32LSB 2913 @deffnx {} BFD_RELOC_IA64_SECREL64MSB 2914 @deffnx {} BFD_RELOC_IA64_SECREL64LSB 2915 @deffnx {} BFD_RELOC_IA64_REL32MSB 2916 @deffnx {} BFD_RELOC_IA64_REL32LSB 2917 @deffnx {} BFD_RELOC_IA64_REL64MSB 2918 @deffnx {} BFD_RELOC_IA64_REL64LSB 2919 @deffnx {} BFD_RELOC_IA64_LTV32MSB 2920 @deffnx {} BFD_RELOC_IA64_LTV32LSB 2921 @deffnx {} BFD_RELOC_IA64_LTV64MSB 2922 @deffnx {} BFD_RELOC_IA64_LTV64LSB 2923 @deffnx {} BFD_RELOC_IA64_IPLTMSB 2924 @deffnx {} BFD_RELOC_IA64_IPLTLSB 2925 @deffnx {} BFD_RELOC_IA64_COPY 2926 @deffnx {} BFD_RELOC_IA64_LTOFF22X 2927 @deffnx {} BFD_RELOC_IA64_LDXMOV 2928 @deffnx {} BFD_RELOC_IA64_TPREL14 2929 @deffnx {} BFD_RELOC_IA64_TPREL22 2930 @deffnx {} BFD_RELOC_IA64_TPREL64I 2931 @deffnx {} BFD_RELOC_IA64_TPREL64MSB 2932 @deffnx {} BFD_RELOC_IA64_TPREL64LSB 2933 @deffnx {} BFD_RELOC_IA64_LTOFF_TPREL22 2934 @deffnx {} BFD_RELOC_IA64_DTPMOD64MSB 2935 @deffnx {} BFD_RELOC_IA64_DTPMOD64LSB 2936 @deffnx {} BFD_RELOC_IA64_LTOFF_DTPMOD22 2937 @deffnx {} BFD_RELOC_IA64_DTPREL14 2938 @deffnx {} BFD_RELOC_IA64_DTPREL22 2939 @deffnx {} BFD_RELOC_IA64_DTPREL64I 2940 @deffnx {} BFD_RELOC_IA64_DTPREL32MSB 2941 @deffnx {} BFD_RELOC_IA64_DTPREL32LSB 2942 @deffnx {} BFD_RELOC_IA64_DTPREL64MSB 2943 @deffnx {} BFD_RELOC_IA64_DTPREL64LSB 2944 @deffnx {} BFD_RELOC_IA64_LTOFF_DTPREL22 2945 Intel IA64 Relocations. 2946 @end deffn 2947 @deffn {} BFD_RELOC_M68HC11_HI8 2948 Motorola 68HC11 reloc. 2949 This is the 8 bit high part of an absolute address. 2950 @end deffn 2951 @deffn {} BFD_RELOC_M68HC11_LO8 2952 Motorola 68HC11 reloc. 2953 This is the 8 bit low part of an absolute address. 2954 @end deffn 2955 @deffn {} BFD_RELOC_M68HC11_3B 2956 Motorola 68HC11 reloc. 2957 This is the 3 bit of a value. 2958 @end deffn 2959 @deffn {} BFD_RELOC_M68HC11_RL_JUMP 2960 Motorola 68HC11 reloc. 2961 This reloc marks the beginning of a jump/call instruction. 2962 It is used for linker relaxation to correctly identify beginning 2963 of instruction and change some branches to use PC-relative 2964 addressing mode. 2965 @end deffn 2966 @deffn {} BFD_RELOC_M68HC11_RL_GROUP 2967 Motorola 68HC11 reloc. 2968 This reloc marks a group of several instructions that gcc generates 2969 and for which the linker relaxation pass can modify and/or remove 2970 some of them. 2971 @end deffn 2972 @deffn {} BFD_RELOC_M68HC11_LO16 2973 Motorola 68HC11 reloc. 2974 This is the 16-bit lower part of an address. It is used for 'call' 2975 instruction to specify the symbol address without any special 2976 transformation (due to memory bank window). 2977 @end deffn 2978 @deffn {} BFD_RELOC_M68HC11_PAGE 2979 Motorola 68HC11 reloc. 2980 This is a 8-bit reloc that specifies the page number of an address. 2981 It is used by 'call' instruction to specify the page number of 2982 the symbol. 2983 @end deffn 2984 @deffn {} BFD_RELOC_M68HC11_24 2985 Motorola 68HC11 reloc. 2986 This is a 24-bit reloc that represents the address with a 16-bit 2987 value and a 8-bit page number. The symbol address is transformed 2988 to follow the 16K memory bank of 68HC12 (seen as mapped in the 2989 window). 2990 @end deffn 2991 @deffn {} BFD_RELOC_M68HC12_5B 2992 Motorola 68HC12 reloc. 2993 This is the 5 bits of a value. 2994 @end deffn 2995 @deffn {} BFD_RELOC_XGATE_RL_JUMP 2996 Freescale XGATE reloc. 2997 This reloc marks the beginning of a bra/jal instruction. 2998 @end deffn 2999 @deffn {} BFD_RELOC_XGATE_RL_GROUP 3000 Freescale XGATE reloc. 3001 This reloc marks a group of several instructions that gcc generates 3002 and for which the linker relaxation pass can modify and/or remove 3003 some of them. 3004 @end deffn 3005 @deffn {} BFD_RELOC_XGATE_LO16 3006 Freescale XGATE reloc. 3007 This is the 16-bit lower part of an address. It is used for the 3008 '16-bit' instructions. 3009 @end deffn 3010 @deffn {} BFD_RELOC_XGATE_GPAGE 3011 Freescale XGATE reloc. 3012 @end deffn 3013 @deffn {} BFD_RELOC_XGATE_24 3014 Freescale XGATE reloc. 3015 @end deffn 3016 @deffn {} BFD_RELOC_XGATE_PCREL_9 3017 Freescale XGATE reloc. 3018 This is a 9-bit pc-relative reloc. 3019 @end deffn 3020 @deffn {} BFD_RELOC_XGATE_PCREL_10 3021 Freescale XGATE reloc. 3022 This is a 10-bit pc-relative reloc. 3023 @end deffn 3024 @deffn {} BFD_RELOC_XGATE_IMM8_LO 3025 Freescale XGATE reloc. 3026 This is the 16-bit lower part of an address. It is used for the 3027 '16-bit' instructions. 3028 @end deffn 3029 @deffn {} BFD_RELOC_XGATE_IMM8_HI 3030 Freescale XGATE reloc. 3031 This is the 16-bit higher part of an address. It is used for the 3032 '16-bit' instructions. 3033 @end deffn 3034 @deffn {} BFD_RELOC_XGATE_IMM3 3035 Freescale XGATE reloc. 3036 This is a 3-bit pc-relative reloc. 3037 @end deffn 3038 @deffn {} BFD_RELOC_XGATE_IMM4 3039 Freescale XGATE reloc. 3040 This is a 4-bit pc-relative reloc. 3041 @end deffn 3042 @deffn {} BFD_RELOC_XGATE_IMM5 3043 Freescale XGATE reloc. 3044 This is a 5-bit pc-relative reloc. 3045 @end deffn 3046 @deffn {} BFD_RELOC_M68HC12_9B 3047 Motorola 68HC12 reloc. 3048 This is the 9 bits of a value. 3049 @end deffn 3050 @deffn {} BFD_RELOC_M68HC12_16B 3051 Motorola 68HC12 reloc. 3052 This is the 16 bits of a value. 3053 @end deffn 3054 @deffn {} BFD_RELOC_M68HC12_9_PCREL 3055 Motorola 68HC12/XGATE reloc. 3056 This is a PCREL9 branch. 3057 @end deffn 3058 @deffn {} BFD_RELOC_M68HC12_10_PCREL 3059 Motorola 68HC12/XGATE reloc. 3060 This is a PCREL10 branch. 3061 @end deffn 3062 @deffn {} BFD_RELOC_M68HC12_LO8XG 3063 Motorola 68HC12/XGATE reloc. 3064 This is the 8 bit low part of an absolute address and immediately 3065 precedes a matching HI8XG part. 3066 @end deffn 3067 @deffn {} BFD_RELOC_M68HC12_HI8XG 3068 Motorola 68HC12/XGATE reloc. 3069 This is the 8 bit high part of an absolute address and immediately 3070 follows a matching LO8XG part. 3071 @end deffn 3072 @deffn {} BFD_RELOC_S12Z_15_PCREL 3073 Freescale S12Z reloc. 3074 This is a 15 bit relative address. If the most significant bits are 3075 all zero then it may be truncated to 8 bits. 3076 @end deffn 3077 @deffn {} BFD_RELOC_CR16_NUM8 3078 @deffnx {} BFD_RELOC_CR16_NUM16 3079 @deffnx {} BFD_RELOC_CR16_NUM32 3080 @deffnx {} BFD_RELOC_CR16_NUM32a 3081 @deffnx {} BFD_RELOC_CR16_REGREL0 3082 @deffnx {} BFD_RELOC_CR16_REGREL4 3083 @deffnx {} BFD_RELOC_CR16_REGREL4a 3084 @deffnx {} BFD_RELOC_CR16_REGREL14 3085 @deffnx {} BFD_RELOC_CR16_REGREL14a 3086 @deffnx {} BFD_RELOC_CR16_REGREL16 3087 @deffnx {} BFD_RELOC_CR16_REGREL20 3088 @deffnx {} BFD_RELOC_CR16_REGREL20a 3089 @deffnx {} BFD_RELOC_CR16_ABS20 3090 @deffnx {} BFD_RELOC_CR16_ABS24 3091 @deffnx {} BFD_RELOC_CR16_IMM4 3092 @deffnx {} BFD_RELOC_CR16_IMM8 3093 @deffnx {} BFD_RELOC_CR16_IMM16 3094 @deffnx {} BFD_RELOC_CR16_IMM20 3095 @deffnx {} BFD_RELOC_CR16_IMM24 3096 @deffnx {} BFD_RELOC_CR16_IMM32 3097 @deffnx {} BFD_RELOC_CR16_IMM32a 3098 @deffnx {} BFD_RELOC_CR16_DISP4 3099 @deffnx {} BFD_RELOC_CR16_DISP8 3100 @deffnx {} BFD_RELOC_CR16_DISP16 3101 @deffnx {} BFD_RELOC_CR16_DISP20 3102 @deffnx {} BFD_RELOC_CR16_DISP24 3103 @deffnx {} BFD_RELOC_CR16_DISP24a 3104 @deffnx {} BFD_RELOC_CR16_SWITCH8 3105 @deffnx {} BFD_RELOC_CR16_SWITCH16 3106 @deffnx {} BFD_RELOC_CR16_SWITCH32 3107 @deffnx {} BFD_RELOC_CR16_GOT_REGREL20 3108 @deffnx {} BFD_RELOC_CR16_GOTC_REGREL20 3109 @deffnx {} BFD_RELOC_CR16_GLOB_DAT 3110 NS CR16 Relocations. 3111 @end deffn 3112 @deffn {} BFD_RELOC_CRX_REL4 3113 @deffnx {} BFD_RELOC_CRX_REL8 3114 @deffnx {} BFD_RELOC_CRX_REL8_CMP 3115 @deffnx {} BFD_RELOC_CRX_REL16 3116 @deffnx {} BFD_RELOC_CRX_REL24 3117 @deffnx {} BFD_RELOC_CRX_REL32 3118 @deffnx {} BFD_RELOC_CRX_REGREL12 3119 @deffnx {} BFD_RELOC_CRX_REGREL22 3120 @deffnx {} BFD_RELOC_CRX_REGREL28 3121 @deffnx {} BFD_RELOC_CRX_REGREL32 3122 @deffnx {} BFD_RELOC_CRX_ABS16 3123 @deffnx {} BFD_RELOC_CRX_ABS32 3124 @deffnx {} BFD_RELOC_CRX_NUM8 3125 @deffnx {} BFD_RELOC_CRX_NUM16 3126 @deffnx {} BFD_RELOC_CRX_NUM32 3127 @deffnx {} BFD_RELOC_CRX_IMM16 3128 @deffnx {} BFD_RELOC_CRX_IMM32 3129 @deffnx {} BFD_RELOC_CRX_SWITCH8 3130 @deffnx {} BFD_RELOC_CRX_SWITCH16 3131 @deffnx {} BFD_RELOC_CRX_SWITCH32 3132 NS CRX Relocations. 3133 @end deffn 3134 @deffn {} BFD_RELOC_CRIS_BDISP8 3135 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_5 3136 @deffnx {} BFD_RELOC_CRIS_SIGNED_6 3137 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_6 3138 @deffnx {} BFD_RELOC_CRIS_SIGNED_8 3139 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_8 3140 @deffnx {} BFD_RELOC_CRIS_SIGNED_16 3141 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_16 3142 @deffnx {} BFD_RELOC_CRIS_LAPCQ_OFFSET 3143 @deffnx {} BFD_RELOC_CRIS_UNSIGNED_4 3144 These relocs are only used within the CRIS assembler. They are not 3145 (at present) written to any object files. 3146 @end deffn 3147 @deffn {} BFD_RELOC_CRIS_COPY 3148 @deffnx {} BFD_RELOC_CRIS_GLOB_DAT 3149 @deffnx {} BFD_RELOC_CRIS_JUMP_SLOT 3150 @deffnx {} BFD_RELOC_CRIS_RELATIVE 3151 Relocs used in ELF shared libraries for CRIS. 3152 @end deffn 3153 @deffn {} BFD_RELOC_CRIS_32_GOT 3154 32-bit offset to symbol-entry within GOT. 3155 @end deffn 3156 @deffn {} BFD_RELOC_CRIS_16_GOT 3157 16-bit offset to symbol-entry within GOT. 3158 @end deffn 3159 @deffn {} BFD_RELOC_CRIS_32_GOTPLT 3160 32-bit offset to symbol-entry within GOT, with PLT handling. 3161 @end deffn 3162 @deffn {} BFD_RELOC_CRIS_16_GOTPLT 3163 16-bit offset to symbol-entry within GOT, with PLT handling. 3164 @end deffn 3165 @deffn {} BFD_RELOC_CRIS_32_GOTREL 3166 32-bit offset to symbol, relative to GOT. 3167 @end deffn 3168 @deffn {} BFD_RELOC_CRIS_32_PLT_GOTREL 3169 32-bit offset to symbol with PLT entry, relative to GOT. 3170 @end deffn 3171 @deffn {} BFD_RELOC_CRIS_32_PLT_PCREL 3172 32-bit offset to symbol with PLT entry, relative to this 3173 relocation. 3174 @end deffn 3175 @deffn {} BFD_RELOC_CRIS_32_GOT_GD 3176 @deffnx {} BFD_RELOC_CRIS_16_GOT_GD 3177 @deffnx {} BFD_RELOC_CRIS_32_GD 3178 @deffnx {} BFD_RELOC_CRIS_DTP 3179 @deffnx {} BFD_RELOC_CRIS_32_DTPREL 3180 @deffnx {} BFD_RELOC_CRIS_16_DTPREL 3181 @deffnx {} BFD_RELOC_CRIS_32_GOT_TPREL 3182 @deffnx {} BFD_RELOC_CRIS_16_GOT_TPREL 3183 @deffnx {} BFD_RELOC_CRIS_32_TPREL 3184 @deffnx {} BFD_RELOC_CRIS_16_TPREL 3185 @deffnx {} BFD_RELOC_CRIS_DTPMOD 3186 @deffnx {} BFD_RELOC_CRIS_32_IE 3187 Relocs used in TLS code for CRIS. 3188 @end deffn 3189 @deffn {} BFD_RELOC_OR1K_REL_26 3190 @deffnx {} BFD_RELOC_OR1K_SLO16 3191 @deffnx {} BFD_RELOC_OR1K_PCREL_PG21 3192 @deffnx {} BFD_RELOC_OR1K_LO13 3193 @deffnx {} BFD_RELOC_OR1K_SLO13 3194 @deffnx {} BFD_RELOC_OR1K_GOTPC_HI16 3195 @deffnx {} BFD_RELOC_OR1K_GOTPC_LO16 3196 @deffnx {} BFD_RELOC_OR1K_GOT_AHI16 3197 @deffnx {} BFD_RELOC_OR1K_GOT16 3198 @deffnx {} BFD_RELOC_OR1K_GOT_PG21 3199 @deffnx {} BFD_RELOC_OR1K_GOT_LO13 3200 @deffnx {} BFD_RELOC_OR1K_PLT26 3201 @deffnx {} BFD_RELOC_OR1K_PLTA26 3202 @deffnx {} BFD_RELOC_OR1K_GOTOFF_SLO16 3203 @deffnx {} BFD_RELOC_OR1K_COPY 3204 @deffnx {} BFD_RELOC_OR1K_GLOB_DAT 3205 @deffnx {} BFD_RELOC_OR1K_JMP_SLOT 3206 @deffnx {} BFD_RELOC_OR1K_RELATIVE 3207 @deffnx {} BFD_RELOC_OR1K_TLS_GD_HI16 3208 @deffnx {} BFD_RELOC_OR1K_TLS_GD_LO16 3209 @deffnx {} BFD_RELOC_OR1K_TLS_GD_PG21 3210 @deffnx {} BFD_RELOC_OR1K_TLS_GD_LO13 3211 @deffnx {} BFD_RELOC_OR1K_TLS_LDM_HI16 3212 @deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO16 3213 @deffnx {} BFD_RELOC_OR1K_TLS_LDM_PG21 3214 @deffnx {} BFD_RELOC_OR1K_TLS_LDM_LO13 3215 @deffnx {} BFD_RELOC_OR1K_TLS_LDO_HI16 3216 @deffnx {} BFD_RELOC_OR1K_TLS_LDO_LO16 3217 @deffnx {} BFD_RELOC_OR1K_TLS_IE_HI16 3218 @deffnx {} BFD_RELOC_OR1K_TLS_IE_AHI16 3219 @deffnx {} BFD_RELOC_OR1K_TLS_IE_LO16 3220 @deffnx {} BFD_RELOC_OR1K_TLS_IE_PG21 3221 @deffnx {} BFD_RELOC_OR1K_TLS_IE_LO13 3222 @deffnx {} BFD_RELOC_OR1K_TLS_LE_HI16 3223 @deffnx {} BFD_RELOC_OR1K_TLS_LE_AHI16 3224 @deffnx {} BFD_RELOC_OR1K_TLS_LE_LO16 3225 @deffnx {} BFD_RELOC_OR1K_TLS_LE_SLO16 3226 @deffnx {} BFD_RELOC_OR1K_TLS_TPOFF 3227 @deffnx {} BFD_RELOC_OR1K_TLS_DTPOFF 3228 @deffnx {} BFD_RELOC_OR1K_TLS_DTPMOD 3229 OpenRISC 1000 Relocations. 3230 @end deffn 3231 @deffn {} BFD_RELOC_H8_DIR16A8 3232 @deffnx {} BFD_RELOC_H8_DIR16R8 3233 @deffnx {} BFD_RELOC_H8_DIR24A8 3234 @deffnx {} BFD_RELOC_H8_DIR24R8 3235 @deffnx {} BFD_RELOC_H8_DIR32A16 3236 @deffnx {} BFD_RELOC_H8_DISP32A16 3237 H8 elf Relocations. 3238 @end deffn 3239 @deffn {} BFD_RELOC_XSTORMY16_REL_12 3240 @deffnx {} BFD_RELOC_XSTORMY16_12 3241 @deffnx {} BFD_RELOC_XSTORMY16_24 3242 @deffnx {} BFD_RELOC_XSTORMY16_FPTR16 3243 Sony Xstormy16 Relocations. 3244 @end deffn 3245 @deffn {} BFD_RELOC_RELC 3246 Self-describing complex relocations. 3247 @end deffn 3248 @deffn {} BFD_RELOC_VAX_GLOB_DAT 3249 @deffnx {} BFD_RELOC_VAX_JMP_SLOT 3250 @deffnx {} BFD_RELOC_VAX_RELATIVE 3251 Relocations used by VAX ELF. 3252 @end deffn 3253 @deffn {} BFD_RELOC_MT_PC16 3254 Morpho MT - 16 bit immediate relocation. 3255 @end deffn 3256 @deffn {} BFD_RELOC_MT_HI16 3257 Morpho MT - Hi 16 bits of an address. 3258 @end deffn 3259 @deffn {} BFD_RELOC_MT_LO16 3260 Morpho MT - Low 16 bits of an address. 3261 @end deffn 3262 @deffn {} BFD_RELOC_MT_GNU_VTINHERIT 3263 Morpho MT - Used to tell the linker which vtable entries are used. 3264 @end deffn 3265 @deffn {} BFD_RELOC_MT_GNU_VTENTRY 3266 Morpho MT - Used to tell the linker which vtable entries are used. 3267 @end deffn 3268 @deffn {} BFD_RELOC_MT_PCINSN8 3269 Morpho MT - 8 bit immediate relocation. 3270 @end deffn 3271 @deffn {} BFD_RELOC_MSP430_10_PCREL 3272 @deffnx {} BFD_RELOC_MSP430_16_PCREL 3273 @deffnx {} BFD_RELOC_MSP430_16 3274 @deffnx {} BFD_RELOC_MSP430_16_PCREL_BYTE 3275 @deffnx {} BFD_RELOC_MSP430_16_BYTE 3276 @deffnx {} BFD_RELOC_MSP430_2X_PCREL 3277 @deffnx {} BFD_RELOC_MSP430_RL_PCREL 3278 @deffnx {} BFD_RELOC_MSP430_ABS8 3279 @deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_SRC 3280 @deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_DST 3281 @deffnx {} BFD_RELOC_MSP430X_PCR20_EXT_ODST 3282 @deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_SRC 3283 @deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_DST 3284 @deffnx {} BFD_RELOC_MSP430X_ABS20_EXT_ODST 3285 @deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_SRC 3286 @deffnx {} BFD_RELOC_MSP430X_ABS20_ADR_DST 3287 @deffnx {} BFD_RELOC_MSP430X_PCR16 3288 @deffnx {} BFD_RELOC_MSP430X_PCR20_CALL 3289 @deffnx {} BFD_RELOC_MSP430X_ABS16 3290 @deffnx {} BFD_RELOC_MSP430_ABS_HI16 3291 @deffnx {} BFD_RELOC_MSP430_PREL31 3292 @deffnx {} BFD_RELOC_MSP430_SYM_DIFF 3293 @deffnx {} BFD_RELOC_MSP430_SET_ULEB128 3294 @deffnx {} BFD_RELOC_MSP430_SUB_ULEB128 3295 msp430 specific relocation codes. 3296 @end deffn 3297 @deffn {} BFD_RELOC_PRU_U16 3298 PRU LDI 16-bit unsigned data-memory relocation. 3299 @end deffn 3300 @deffn {} BFD_RELOC_PRU_U16_PMEMIMM 3301 PRU LDI 16-bit unsigned instruction-memory relocation. 3302 @end deffn 3303 @deffn {} BFD_RELOC_PRU_LDI32 3304 PRU relocation for two consecutive LDI load instructions that load a 3305 32 bit value into a register. If the higher bits are all zero, then 3306 the second instruction may be relaxed. 3307 @end deffn 3308 @deffn {} BFD_RELOC_PRU_S10_PCREL 3309 PRU QBBx 10-bit signed PC-relative relocation. 3310 @end deffn 3311 @deffn {} BFD_RELOC_PRU_U8_PCREL 3312 PRU 8-bit unsigned relocation used for the LOOP instruction. 3313 @end deffn 3314 @deffn {} BFD_RELOC_PRU_32_PMEM 3315 @deffnx {} BFD_RELOC_PRU_16_PMEM 3316 PRU Program Memory relocations. Used to convert from byte 3317 addressing to 32-bit word addressing. 3318 @end deffn 3319 @deffn {} BFD_RELOC_PRU_GNU_DIFF8 3320 @deffnx {} BFD_RELOC_PRU_GNU_DIFF16 3321 @deffnx {} BFD_RELOC_PRU_GNU_DIFF32 3322 @deffnx {} BFD_RELOC_PRU_GNU_DIFF16_PMEM 3323 @deffnx {} BFD_RELOC_PRU_GNU_DIFF32_PMEM 3324 PRU relocations to mark the difference of two local symbols. 3325 These are only needed to support linker relaxation and can be 3326 ignored when not relaxing. The field is set to the value of the 3327 difference assuming no relaxation. The relocation encodes the 3328 position of the second symbol so the linker can determine whether to 3329 adjust the field value. The PMEM variants encode the word 3330 difference, instead of byte difference between symbols. 3331 @end deffn 3332 @deffn {} BFD_RELOC_IQ2000_OFFSET_16 3333 @deffnx {} BFD_RELOC_IQ2000_OFFSET_21 3334 @deffnx {} BFD_RELOC_IQ2000_UHI16 3335 IQ2000 Relocations. 3336 @end deffn 3337 @deffn {} BFD_RELOC_XTENSA_RTLD 3338 Special Xtensa relocation used only by PLT entries in ELF shared 3339 objects to indicate that the runtime linker should set the value 3340 to one of its own internal functions or data structures. 3341 @end deffn 3342 @deffn {} BFD_RELOC_XTENSA_GLOB_DAT 3343 @deffnx {} BFD_RELOC_XTENSA_JMP_SLOT 3344 @deffnx {} BFD_RELOC_XTENSA_RELATIVE 3345 Xtensa relocations for ELF shared objects. 3346 @end deffn 3347 @deffn {} BFD_RELOC_XTENSA_PLT 3348 Xtensa relocation used in ELF object files for symbols that may 3349 require PLT entries. Otherwise, this is just a generic 32-bit 3350 relocation. 3351 @end deffn 3352 @deffn {} BFD_RELOC_XTENSA_DIFF8 3353 @deffnx {} BFD_RELOC_XTENSA_DIFF16 3354 @deffnx {} BFD_RELOC_XTENSA_DIFF32 3355 Xtensa relocations for backward compatibility. These have been 3356 replaced by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF. 3357 Xtensa relocations to mark the difference of two local symbols. 3358 These are only needed to support linker relaxation and can be 3359 ignored when not relaxing. The field is set to the value of the 3360 difference assuming no relaxation. The relocation encodes the 3361 position of the first symbol so the linker can determine whether to 3362 adjust the field value. 3363 @end deffn 3364 @deffn {} BFD_RELOC_XTENSA_SLOT0_OP 3365 @deffnx {} BFD_RELOC_XTENSA_SLOT1_OP 3366 @deffnx {} BFD_RELOC_XTENSA_SLOT2_OP 3367 @deffnx {} BFD_RELOC_XTENSA_SLOT3_OP 3368 @deffnx {} BFD_RELOC_XTENSA_SLOT4_OP 3369 @deffnx {} BFD_RELOC_XTENSA_SLOT5_OP 3370 @deffnx {} BFD_RELOC_XTENSA_SLOT6_OP 3371 @deffnx {} BFD_RELOC_XTENSA_SLOT7_OP 3372 @deffnx {} BFD_RELOC_XTENSA_SLOT8_OP 3373 @deffnx {} BFD_RELOC_XTENSA_SLOT9_OP 3374 @deffnx {} BFD_RELOC_XTENSA_SLOT10_OP 3375 @deffnx {} BFD_RELOC_XTENSA_SLOT11_OP 3376 @deffnx {} BFD_RELOC_XTENSA_SLOT12_OP 3377 @deffnx {} BFD_RELOC_XTENSA_SLOT13_OP 3378 @deffnx {} BFD_RELOC_XTENSA_SLOT14_OP 3379 Generic Xtensa relocations for instruction operands. Only the slot 3380 number is encoded in the relocation. The relocation applies to the 3381 last PC-relative immediate operand, or if there are no PC-relative 3382 immediates, to the last immediate operand. 3383 @end deffn 3384 @deffn {} BFD_RELOC_XTENSA_SLOT0_ALT 3385 @deffnx {} BFD_RELOC_XTENSA_SLOT1_ALT 3386 @deffnx {} BFD_RELOC_XTENSA_SLOT2_ALT 3387 @deffnx {} BFD_RELOC_XTENSA_SLOT3_ALT 3388 @deffnx {} BFD_RELOC_XTENSA_SLOT4_ALT 3389 @deffnx {} BFD_RELOC_XTENSA_SLOT5_ALT 3390 @deffnx {} BFD_RELOC_XTENSA_SLOT6_ALT 3391 @deffnx {} BFD_RELOC_XTENSA_SLOT7_ALT 3392 @deffnx {} BFD_RELOC_XTENSA_SLOT8_ALT 3393 @deffnx {} BFD_RELOC_XTENSA_SLOT9_ALT 3394 @deffnx {} BFD_RELOC_XTENSA_SLOT10_ALT 3395 @deffnx {} BFD_RELOC_XTENSA_SLOT11_ALT 3396 @deffnx {} BFD_RELOC_XTENSA_SLOT12_ALT 3397 @deffnx {} BFD_RELOC_XTENSA_SLOT13_ALT 3398 @deffnx {} BFD_RELOC_XTENSA_SLOT14_ALT 3399 Alternate Xtensa relocations. Only the slot is encoded in the 3400 relocation. The meaning of these relocations is opcode-specific. 3401 @end deffn 3402 @deffn {} BFD_RELOC_XTENSA_OP0 3403 @deffnx {} BFD_RELOC_XTENSA_OP1 3404 @deffnx {} BFD_RELOC_XTENSA_OP2 3405 Xtensa relocations for backward compatibility. These have all been 3406 replaced by BFD_RELOC_XTENSA_SLOT0_OP. 3407 @end deffn 3408 @deffn {} BFD_RELOC_XTENSA_ASM_EXPAND 3409 Xtensa relocation to mark that the assembler expanded the 3410 instructions from an original target. The expansion size is 3411 encoded in the reloc size. 3412 @end deffn 3413 @deffn {} BFD_RELOC_XTENSA_ASM_SIMPLIFY 3414 Xtensa relocation to mark that the linker should simplify 3415 assembler-expanded instructions. This is commonly used 3416 internally by the linker after analysis of a 3417 BFD_RELOC_XTENSA_ASM_EXPAND. 3418 @end deffn 3419 @deffn {} BFD_RELOC_XTENSA_TLSDESC_FN 3420 @deffnx {} BFD_RELOC_XTENSA_TLSDESC_ARG 3421 @deffnx {} BFD_RELOC_XTENSA_TLS_DTPOFF 3422 @deffnx {} BFD_RELOC_XTENSA_TLS_TPOFF 3423 @deffnx {} BFD_RELOC_XTENSA_TLS_FUNC 3424 @deffnx {} BFD_RELOC_XTENSA_TLS_ARG 3425 @deffnx {} BFD_RELOC_XTENSA_TLS_CALL 3426 Xtensa TLS relocations. 3427 @end deffn 3428 @deffn {} BFD_RELOC_XTENSA_PDIFF8 3429 @deffnx {} BFD_RELOC_XTENSA_PDIFF16 3430 @deffnx {} BFD_RELOC_XTENSA_PDIFF32 3431 @deffnx {} BFD_RELOC_XTENSA_NDIFF8 3432 @deffnx {} BFD_RELOC_XTENSA_NDIFF16 3433 @deffnx {} BFD_RELOC_XTENSA_NDIFF32 3434 Xtensa relocations to mark the difference of two local symbols. 3435 These are only needed to support linker relaxation and can be 3436 ignored when not relaxing. The field is set to the value of the 3437 difference assuming no relaxation. The relocation encodes the 3438 position of the subtracted symbol so the linker can determine 3439 whether to adjust the field value. PDIFF relocations are used for 3440 positive differences, NDIFF relocations are used for negative 3441 differences. The difference value is treated as unsigned with these 3442 relocation types, giving full 8/16 value ranges. 3443 @end deffn 3444 @deffn {} BFD_RELOC_Z80_DISP8 3445 8 bit signed offset in (ix+d) or (iy+d). 3446 @end deffn 3447 @deffn {} BFD_RELOC_Z80_BYTE0 3448 First 8 bits of multibyte (32, 24 or 16 bit) value. 3449 @end deffn 3450 @deffn {} BFD_RELOC_Z80_BYTE1 3451 Second 8 bits of multibyte (32, 24 or 16 bit) value. 3452 @end deffn 3453 @deffn {} BFD_RELOC_Z80_BYTE2 3454 Third 8 bits of multibyte (32 or 24 bit) value. 3455 @end deffn 3456 @deffn {} BFD_RELOC_Z80_BYTE3 3457 Fourth 8 bits of multibyte (32 bit) value. 3458 @end deffn 3459 @deffn {} BFD_RELOC_Z80_WORD0 3460 Lowest 16 bits of multibyte (32 or 24 bit) value. 3461 @end deffn 3462 @deffn {} BFD_RELOC_Z80_WORD1 3463 Highest 16 bits of multibyte (32 or 24 bit) value. 3464 @end deffn 3465 @deffn {} BFD_RELOC_Z80_16_BE 3466 Like BFD_RELOC_16 but big-endian. 3467 @end deffn 3468 @deffn {} BFD_RELOC_Z8K_DISP7 3469 DJNZ offset. 3470 @end deffn 3471 @deffn {} BFD_RELOC_Z8K_CALLR 3472 CALR offset. 3473 @end deffn 3474 @deffn {} BFD_RELOC_Z8K_IMM4L 3475 4 bit value. 3476 @end deffn 3477 @deffn {} BFD_RELOC_LM32_CALL 3478 @deffnx {} BFD_RELOC_LM32_BRANCH 3479 @deffnx {} BFD_RELOC_LM32_16_GOT 3480 @deffnx {} BFD_RELOC_LM32_GOTOFF_HI16 3481 @deffnx {} BFD_RELOC_LM32_GOTOFF_LO16 3482 @deffnx {} BFD_RELOC_LM32_COPY 3483 @deffnx {} BFD_RELOC_LM32_GLOB_DAT 3484 @deffnx {} BFD_RELOC_LM32_JMP_SLOT 3485 @deffnx {} BFD_RELOC_LM32_RELATIVE 3486 Lattice Mico32 relocations. 3487 @end deffn 3488 @deffn {} BFD_RELOC_MACH_O_SECTDIFF 3489 Difference between two section addreses. Must be followed by a 3490 BFD_RELOC_MACH_O_PAIR. 3491 @end deffn 3492 @deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF 3493 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol. 3494 @end deffn 3495 @deffn {} BFD_RELOC_MACH_O_PAIR 3496 Pair of relocation. Contains the first symbol. 3497 @end deffn 3498 @deffn {} BFD_RELOC_MACH_O_SUBTRACTOR32 3499 Symbol will be substracted. Must be followed by a BFD_RELOC_32. 3500 @end deffn 3501 @deffn {} BFD_RELOC_MACH_O_SUBTRACTOR64 3502 Symbol will be substracted. Must be followed by a BFD_RELOC_64. 3503 @end deffn 3504 @deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32 3505 @deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8 3506 PCREL relocations. They are marked as branch to create PLT entry if 3507 required. 3508 @end deffn 3509 @deffn {} BFD_RELOC_MACH_O_X86_64_GOT 3510 Used when referencing a GOT entry. 3511 @end deffn 3512 @deffn {} BFD_RELOC_MACH_O_X86_64_GOT_LOAD 3513 Used when loading a GOT entry with movq. It is specially marked so 3514 that the linker could optimize the movq to a leaq if possible. 3515 @end deffn 3516 @deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_1 3517 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend. 3518 @end deffn 3519 @deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_2 3520 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend. 3521 @end deffn 3522 @deffn {} BFD_RELOC_MACH_O_X86_64_PCREL32_4 3523 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend. 3524 @end deffn 3525 @deffn {} BFD_RELOC_MACH_O_X86_64_TLV 3526 Used when referencing a TLV entry. 3527 @end deffn 3528 @deffn {} BFD_RELOC_MACH_O_ARM64_ADDEND 3529 Addend for PAGE or PAGEOFF. 3530 @end deffn 3531 @deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21 3532 Relative offset to page of GOT slot. 3533 @end deffn 3534 @deffn {} BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12 3535 Relative offset within page of GOT slot. 3536 @end deffn 3537 @deffn {} BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT 3538 Address of a GOT entry. 3539 @end deffn 3540 @deffn {} BFD_RELOC_MICROBLAZE_32_LO 3541 This is a 32 bit reloc for the microblaze that stores the low 16 3542 bits of a value. 3543 @end deffn 3544 @deffn {} BFD_RELOC_MICROBLAZE_32_LO_PCREL 3545 This is a 32 bit pc-relative reloc for the microblaze that stores 3546 the low 16 bits of a value. 3547 @end deffn 3548 @deffn {} BFD_RELOC_MICROBLAZE_32_ROSDA 3549 This is a 32 bit reloc for the microblaze that stores a value 3550 relative to the read-only small data area anchor. 3551 @end deffn 3552 @deffn {} BFD_RELOC_MICROBLAZE_32_RWSDA 3553 This is a 32 bit reloc for the microblaze that stores a value 3554 relative to the read-write small data area anchor. 3555 @end deffn 3556 @deffn {} BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM 3557 This is a 32 bit reloc for the microblaze to handle expressions of 3558 the form "Symbol Op Symbol". 3559 @end deffn 3560 @deffn {} BFD_RELOC_MICROBLAZE_32_NONE 3561 This is a 32 bit reloc that stores the 32 bit pc relative value in 3562 two words (with an imm instruction). No relocation is done here - 3563 only used for relaxing. 3564 @end deffn 3565 @deffn {} BFD_RELOC_MICROBLAZE_64_NONE 3566 This is a 64 bit reloc that stores the 32 bit pc relative value in 3567 two words (with an imm instruction). No relocation is done here - 3568 only used for relaxing. 3569 @end deffn 3570 @deffn {} BFD_RELOC_MICROBLAZE_64_GOTPC 3571 This is a 64 bit reloc that stores the 32 bit pc relative value in 3572 two words (with an imm instruction). The relocation is PC-relative 3573 GOT offset. 3574 @end deffn 3575 @deffn {} BFD_RELOC_MICROBLAZE_64_GOT 3576 This is a 64 bit reloc that stores the 32 bit pc relative value in 3577 two words (with an imm instruction). The relocation is GOT offset. 3578 @end deffn 3579 @deffn {} BFD_RELOC_MICROBLAZE_64_PLT 3580 This is a 64 bit reloc that stores the 32 bit pc relative value in 3581 two words (with an imm instruction). The relocation is PC-relative 3582 offset into PLT. 3583 @end deffn 3584 @deffn {} BFD_RELOC_MICROBLAZE_64_GOTOFF 3585 This is a 64 bit reloc that stores the 32 bit GOT relative value in 3586 two words (with an imm instruction). The relocation is relative 3587 offset from _GLOBAL_OFFSET_TABLE_. 3588 @end deffn 3589 @deffn {} BFD_RELOC_MICROBLAZE_32_GOTOFF 3590 This is a 32 bit reloc that stores the 32 bit GOT relative value in 3591 a word. The relocation is relative offset from 3592 _GLOBAL_OFFSET_TABLE_. 3593 @end deffn 3594 @deffn {} BFD_RELOC_MICROBLAZE_COPY 3595 This is used to tell the dynamic linker to copy the value out of 3596 the dynamic object into the runtime process image. 3597 @end deffn 3598 @deffn {} BFD_RELOC_MICROBLAZE_64_TLS 3599 Unused Reloc. 3600 @end deffn 3601 @deffn {} BFD_RELOC_MICROBLAZE_64_TLSGD 3602 This is a 64 bit reloc that stores the 32 bit GOT relative value 3603 of the GOT TLS GD info entry in two words (with an imm instruction). 3604 The relocation is GOT offset. 3605 @end deffn 3606 @deffn {} BFD_RELOC_MICROBLAZE_64_TLSLD 3607 This is a 64 bit reloc that stores the 32 bit GOT relative value 3608 of the GOT TLS LD info entry in two words (with an imm instruction). 3609 The relocation is GOT offset. 3610 @end deffn 3611 @deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPMOD 3612 This is a 32 bit reloc that stores the Module ID to GOT(n). 3613 @end deffn 3614 @deffn {} BFD_RELOC_MICROBLAZE_32_TLSDTPREL 3615 This is a 32 bit reloc that stores TLS offset to GOT(n+1). 3616 @end deffn 3617 @deffn {} BFD_RELOC_MICROBLAZE_64_TLSDTPREL 3618 This is a 32 bit reloc for storing TLS offset to two words (uses imm 3619 instruction). 3620 @end deffn 3621 @deffn {} BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL 3622 This is a 64 bit reloc that stores 32-bit thread pointer relative 3623 offset to two words (uses imm instruction). 3624 @end deffn 3625 @deffn {} BFD_RELOC_MICROBLAZE_64_TLSTPREL 3626 This is a 64 bit reloc that stores 32-bit thread pointer relative 3627 offset to two words (uses imm instruction). 3628 @end deffn 3629 @deffn {} BFD_RELOC_MICROBLAZE_64_TEXTPCREL 3630 This is a 64 bit reloc that stores the 32 bit pc relative value in 3631 two words (with an imm instruction). The relocation is PC-relative 3632 offset from start of TEXT. 3633 @end deffn 3634 @deffn {} BFD_RELOC_MICROBLAZE_64_TEXTREL 3635 This is a 64 bit reloc that stores the 32 bit offset value in two 3636 words (with an imm instruction). The relocation is relative offset 3637 from start of TEXT. 3638 @end deffn 3639 @deffn {} BFD_RELOC_KVX_RELOC_START 3640 KVX pseudo relocation code to mark the start of the KVX relocation 3641 enumerators. N.B. the order of the enumerators is important as 3642 several tables in the KVX bfd backend are indexed by these 3643 enumerators; make sure they are all synced. 3644 @end deffn 3645 @deffn {} BFD_RELOC_KVX_NONE 3646 KVX null relocation code. 3647 @end deffn 3648 @deffn {} BFD_RELOC_KVX_16 3649 @deffnx {} BFD_RELOC_KVX_32 3650 @deffnx {} BFD_RELOC_KVX_64 3651 @deffnx {} BFD_RELOC_KVX_S16_PCREL 3652 @deffnx {} BFD_RELOC_KVX_PCREL17 3653 @deffnx {} BFD_RELOC_KVX_PCREL27 3654 @deffnx {} BFD_RELOC_KVX_32_PCREL 3655 @deffnx {} BFD_RELOC_KVX_S37_PCREL_LO10 3656 @deffnx {} BFD_RELOC_KVX_S37_PCREL_UP27 3657 @deffnx {} BFD_RELOC_KVX_S43_PCREL_LO10 3658 @deffnx {} BFD_RELOC_KVX_S43_PCREL_UP27 3659 @deffnx {} BFD_RELOC_KVX_S43_PCREL_EX6 3660 @deffnx {} BFD_RELOC_KVX_S64_PCREL_LO10 3661 @deffnx {} BFD_RELOC_KVX_S64_PCREL_UP27 3662 @deffnx {} BFD_RELOC_KVX_S64_PCREL_EX27 3663 @deffnx {} BFD_RELOC_KVX_64_PCREL 3664 @deffnx {} BFD_RELOC_KVX_S16 3665 @deffnx {} BFD_RELOC_KVX_S32_LO5 3666 @deffnx {} BFD_RELOC_KVX_S32_UP27 3667 @deffnx {} BFD_RELOC_KVX_S37_LO10 3668 @deffnx {} BFD_RELOC_KVX_S37_UP27 3669 @deffnx {} BFD_RELOC_KVX_S37_GOTOFF_LO10 3670 @deffnx {} BFD_RELOC_KVX_S37_GOTOFF_UP27 3671 @deffnx {} BFD_RELOC_KVX_S43_GOTOFF_LO10 3672 @deffnx {} BFD_RELOC_KVX_S43_GOTOFF_UP27 3673 @deffnx {} BFD_RELOC_KVX_S43_GOTOFF_EX6 3674 @deffnx {} BFD_RELOC_KVX_32_GOTOFF 3675 @deffnx {} BFD_RELOC_KVX_64_GOTOFF 3676 @deffnx {} BFD_RELOC_KVX_32_GOT 3677 @deffnx {} BFD_RELOC_KVX_S37_GOT_LO10 3678 @deffnx {} BFD_RELOC_KVX_S37_GOT_UP27 3679 @deffnx {} BFD_RELOC_KVX_S43_GOT_LO10 3680 @deffnx {} BFD_RELOC_KVX_S43_GOT_UP27 3681 @deffnx {} BFD_RELOC_KVX_S43_GOT_EX6 3682 @deffnx {} BFD_RELOC_KVX_64_GOT 3683 @deffnx {} BFD_RELOC_KVX_GLOB_DAT 3684 @deffnx {} BFD_RELOC_KVX_COPY 3685 @deffnx {} BFD_RELOC_KVX_JMP_SLOT 3686 @deffnx {} BFD_RELOC_KVX_RELATIVE 3687 @deffnx {} BFD_RELOC_KVX_S43_LO10 3688 @deffnx {} BFD_RELOC_KVX_S43_UP27 3689 @deffnx {} BFD_RELOC_KVX_S43_EX6 3690 @deffnx {} BFD_RELOC_KVX_S64_LO10 3691 @deffnx {} BFD_RELOC_KVX_S64_UP27 3692 @deffnx {} BFD_RELOC_KVX_S64_EX27 3693 @deffnx {} BFD_RELOC_KVX_S37_GOTADDR_LO10 3694 @deffnx {} BFD_RELOC_KVX_S37_GOTADDR_UP27 3695 @deffnx {} BFD_RELOC_KVX_S43_GOTADDR_LO10 3696 @deffnx {} BFD_RELOC_KVX_S43_GOTADDR_UP27 3697 @deffnx {} BFD_RELOC_KVX_S43_GOTADDR_EX6 3698 @deffnx {} BFD_RELOC_KVX_S64_GOTADDR_LO10 3699 @deffnx {} BFD_RELOC_KVX_S64_GOTADDR_UP27 3700 @deffnx {} BFD_RELOC_KVX_S64_GOTADDR_EX27 3701 @deffnx {} BFD_RELOC_KVX_64_DTPMOD 3702 @deffnx {} BFD_RELOC_KVX_64_DTPOFF 3703 @deffnx {} BFD_RELOC_KVX_S37_TLS_DTPOFF_LO10 3704 @deffnx {} BFD_RELOC_KVX_S37_TLS_DTPOFF_UP27 3705 @deffnx {} BFD_RELOC_KVX_S43_TLS_DTPOFF_LO10 3706 @deffnx {} BFD_RELOC_KVX_S43_TLS_DTPOFF_UP27 3707 @deffnx {} BFD_RELOC_KVX_S43_TLS_DTPOFF_EX6 3708 @deffnx {} BFD_RELOC_KVX_S37_TLS_GD_LO10 3709 @deffnx {} BFD_RELOC_KVX_S37_TLS_GD_UP27 3710 @deffnx {} BFD_RELOC_KVX_S43_TLS_GD_LO10 3711 @deffnx {} BFD_RELOC_KVX_S43_TLS_GD_UP27 3712 @deffnx {} BFD_RELOC_KVX_S43_TLS_GD_EX6 3713 @deffnx {} BFD_RELOC_KVX_S37_TLS_LD_LO10 3714 @deffnx {} BFD_RELOC_KVX_S37_TLS_LD_UP27 3715 @deffnx {} BFD_RELOC_KVX_S43_TLS_LD_LO10 3716 @deffnx {} BFD_RELOC_KVX_S43_TLS_LD_UP27 3717 @deffnx {} BFD_RELOC_KVX_S43_TLS_LD_EX6 3718 @deffnx {} BFD_RELOC_KVX_64_TPOFF 3719 @deffnx {} BFD_RELOC_KVX_S37_TLS_IE_LO10 3720 @deffnx {} BFD_RELOC_KVX_S37_TLS_IE_UP27 3721 @deffnx {} BFD_RELOC_KVX_S43_TLS_IE_LO10 3722 @deffnx {} BFD_RELOC_KVX_S43_TLS_IE_UP27 3723 @deffnx {} BFD_RELOC_KVX_S43_TLS_IE_EX6 3724 @deffnx {} BFD_RELOC_KVX_S37_TLS_LE_LO10 3725 @deffnx {} BFD_RELOC_KVX_S37_TLS_LE_UP27 3726 @deffnx {} BFD_RELOC_KVX_S43_TLS_LE_LO10 3727 @deffnx {} BFD_RELOC_KVX_S43_TLS_LE_UP27 3728 @deffnx {} BFD_RELOC_KVX_S43_TLS_LE_EX6 3729 @deffnx {} BFD_RELOC_KVX_8 3730 KVX Relocations. 3731 @end deffn 3732 @deffn {} BFD_RELOC_KVX_RELOC_END 3733 KVX pseudo relocation code to mark the end of the KVX relocation 3734 enumerators that have direct mapping to ELF reloc codes. There are 3735 a few more enumerators after this one; those are mainly used by the 3736 KVX assembler for the internal fixup or to select one of the above 3737 enumerators. 3738 @end deffn 3739 @deffn {} BFD_RELOC_AARCH64_RELOC_START 3740 AArch64 pseudo relocation code to mark the start of the AArch64 3741 relocation enumerators. N.B. the order of the enumerators is 3742 important as several tables in the AArch64 bfd backend are indexed 3743 by these enumerators; make sure they are all synced. 3744 @end deffn 3745 @deffn {} BFD_RELOC_AARCH64_NULL 3746 Deprecated AArch64 null relocation code. 3747 @end deffn 3748 @deffn {} BFD_RELOC_AARCH64_NONE 3749 AArch64 null relocation code. 3750 @end deffn 3751 @deffn {} BFD_RELOC_AARCH64_64 3752 @deffnx {} BFD_RELOC_AARCH64_32 3753 @deffnx {} BFD_RELOC_AARCH64_16 3754 Basic absolute relocations of N bits. These are equivalent to 3755 BFD_RELOC_N and they were added to assist the indexing of the howto 3756 table. 3757 @end deffn 3758 @deffn {} BFD_RELOC_AARCH64_64_PCREL 3759 @deffnx {} BFD_RELOC_AARCH64_32_PCREL 3760 @deffnx {} BFD_RELOC_AARCH64_16_PCREL 3761 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL 3762 and they were added to assist the indexing of the howto table. 3763 @end deffn 3764 @deffn {} BFD_RELOC_AARCH64_MOVW_G0 3765 AArch64 MOV[NZK] instruction with most significant bits 0 to 15 of 3766 an unsigned address/value. 3767 @end deffn 3768 @deffn {} BFD_RELOC_AARCH64_MOVW_G0_NC 3769 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of 3770 an address/value. No overflow checking. 3771 @end deffn 3772 @deffn {} BFD_RELOC_AARCH64_MOVW_G1 3773 AArch64 MOV[NZK] instruction with most significant bits 16 to 31 of 3774 an unsigned address/value. 3775 @end deffn 3776 @deffn {} BFD_RELOC_AARCH64_MOVW_G1_NC 3777 AArch64 MOV[NZK] instruction with less significant bits 16 to 31 of 3778 an address/value. No overflow checking. 3779 @end deffn 3780 @deffn {} BFD_RELOC_AARCH64_MOVW_G2 3781 AArch64 MOV[NZK] instruction with most significant bits 32 to 47 of 3782 an unsigned address/value. 3783 @end deffn 3784 @deffn {} BFD_RELOC_AARCH64_MOVW_G2_NC 3785 AArch64 MOV[NZK] instruction with less significant bits 32 to 47 of 3786 an address/value. No overflow checking. 3787 @end deffn 3788 @deffn {} BFD_RELOC_AARCH64_MOVW_G3 3789 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64 of a 3790 signed or unsigned address/value. 3791 @end deffn 3792 @deffn {} BFD_RELOC_AARCH64_MOVW_G0_S 3793 AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a 3794 signed value. Changes instruction to MOVZ or MOVN depending on the 3795 value's sign. 3796 @end deffn 3797 @deffn {} BFD_RELOC_AARCH64_MOVW_G1_S 3798 AArch64 MOV[NZ] instruction with most significant bits 16 to 31 of a 3799 signed value. Changes instruction to MOVZ or MOVN depending on the 3800 value's sign. 3801 @end deffn 3802 @deffn {} BFD_RELOC_AARCH64_MOVW_G2_S 3803 AArch64 MOV[NZ] instruction with most significant bits 32 to 47 of a 3804 signed value. Changes instruction to MOVZ or MOVN depending on the 3805 value's sign. 3806 @end deffn 3807 @deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0 3808 AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a 3809 signed value. Changes instruction to MOVZ or MOVN depending on the 3810 value's sign. 3811 @end deffn 3812 @deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G0_NC 3813 AArch64 MOV[NZ] instruction with most significant bits 0 to 15 of a 3814 signed value. Changes instruction to MOVZ or MOVN depending on the 3815 value's sign. 3816 @end deffn 3817 @deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1 3818 AArch64 MOVK instruction with most significant bits 16 to 31 of a 3819 signed value. 3820 @end deffn 3821 @deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G1_NC 3822 AArch64 MOVK instruction with most significant bits 16 to 31 of a 3823 signed value. 3824 @end deffn 3825 @deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2 3826 AArch64 MOVK instruction with most significant bits 32 to 47 of a 3827 signed value. 3828 @end deffn 3829 @deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G2_NC 3830 AArch64 MOVK instruction with most significant bits 32 to 47 of a 3831 signed value. 3832 @end deffn 3833 @deffn {} BFD_RELOC_AARCH64_MOVW_PREL_G3 3834 AArch64 MOVK instruction with most significant bits 47 to 63 of a 3835 signed value. 3836 @end deffn 3837 @deffn {} BFD_RELOC_AARCH64_LD_LO19_PCREL 3838 AArch64 Load Literal instruction, holding a 19 bit pc-relative word 3839 offset. The lowest two bits must be zero and are not stored in the 3840 instruction, giving a 21 bit signed byte offset. 3841 @end deffn 3842 @deffn {} BFD_RELOC_AARCH64_ADR_LO21_PCREL 3843 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte 3844 offset. 3845 @end deffn 3846 @deffn {} BFD_RELOC_AARCH64_ADR_HI21_PCREL 3847 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3848 offset, giving a 4KB aligned page base address. 3849 @end deffn 3850 @deffn {} BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL 3851 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page 3852 offset, giving a 4KB aligned page base address, but with no overflow 3853 checking. 3854 @end deffn 3855 @deffn {} BFD_RELOC_AARCH64_ADD_LO12 3856 AArch64 ADD immediate instruction, holding bits 0 to 11 of the 3857 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3858 @end deffn 3859 @deffn {} BFD_RELOC_AARCH64_LDST8_LO12 3860 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the 3861 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3862 @end deffn 3863 @deffn {} BFD_RELOC_AARCH64_TSTBR14 3864 AArch64 14 bit pc-relative test bit and branch. 3865 The lowest two bits must be zero and are not stored in the 3866 instruction, giving a 16 bit signed byte offset. 3867 @end deffn 3868 @deffn {} BFD_RELOC_AARCH64_BRANCH19 3869 AArch64 19 bit pc-relative conditional branch and compare & branch. 3870 The lowest two bits must be zero and are not stored in the 3871 instruction, giving a 21 bit signed byte offset. 3872 @end deffn 3873 @deffn {} BFD_RELOC_AARCH64_JUMP26 3874 AArch64 26 bit pc-relative unconditional branch. 3875 The lowest two bits must be zero and are not stored in the 3876 instruction, giving a 28 bit signed byte offset. 3877 @end deffn 3878 @deffn {} BFD_RELOC_AARCH64_CALL26 3879 AArch64 26 bit pc-relative unconditional branch and link. 3880 The lowest two bits must be zero and are not stored in the 3881 instruction, giving a 28 bit signed byte offset. 3882 @end deffn 3883 @deffn {} BFD_RELOC_AARCH64_LDST16_LO12 3884 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the 3885 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3886 @end deffn 3887 @deffn {} BFD_RELOC_AARCH64_LDST32_LO12 3888 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the 3889 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3890 @end deffn 3891 @deffn {} BFD_RELOC_AARCH64_LDST64_LO12 3892 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the 3893 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3894 @end deffn 3895 @deffn {} BFD_RELOC_AARCH64_LDST128_LO12 3896 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the 3897 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 3898 @end deffn 3899 @deffn {} BFD_RELOC_AARCH64_GOT_LD_PREL19 3900 AArch64 Load Literal instruction, holding a 19 bit PC relative word 3901 offset of the global offset table entry for a symbol. The lowest 3902 two bits must be zero and are not stored in the instruction, giving 3903 a 21 bit signed byte offset. This relocation type requires signed 3904 overflow checking. 3905 @end deffn 3906 @deffn {} BFD_RELOC_AARCH64_ADR_GOT_PAGE 3907 Get to the page base of the global offset table entry for a symbol 3908 as part of an ADRP instruction using a 21 bit PC relative value. 3909 Used in conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC. 3910 @end deffn 3911 @deffn {} BFD_RELOC_AARCH64_LD64_GOT_LO12_NC 3912 Unsigned 12 bit byte offset for 64 bit load/store from the page of 3913 the GOT entry for this symbol. Used in conjunction with 3914 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only. 3915 @end deffn 3916 @deffn {} BFD_RELOC_AARCH64_LD32_GOT_LO12_NC 3917 Unsigned 12 bit byte offset for 32 bit load/store from the page of 3918 the GOT entry for this symbol. Used in conjunction with 3919 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only. 3920 @end deffn 3921 @deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC 3922 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry 3923 for this symbol. Valid in LP64 ABI only. 3924 @end deffn 3925 @deffn {} BFD_RELOC_AARCH64_MOVW_GOTOFF_G1 3926 Unsigned 16 bit byte higher offset for 64 bit load/store from the 3927 GOT entry for this symbol. Valid in LP64 ABI only. 3928 @end deffn 3929 @deffn {} BFD_RELOC_AARCH64_LD64_GOTOFF_LO15 3930 Unsigned 15 bit byte offset for 64 bit load/store from the page of 3931 the GOT entry for this symbol. Valid in LP64 ABI only. 3932 @end deffn 3933 @deffn {} BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14 3934 Scaled 14 bit byte offset to the page base of the global offset 3935 table. 3936 @end deffn 3937 @deffn {} BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15 3938 Scaled 15 bit byte offset to the page base of the global offset 3939 table. 3940 @end deffn 3941 @deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21 3942 Get to the page base of the global offset table entry for a symbols 3943 tls_index structure as part of an adrp instruction using a 21 bit PC 3944 relative value. Used in conjunction with 3945 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC. 3946 @end deffn 3947 @deffn {} BFD_RELOC_AARCH64_TLSGD_ADR_PREL21 3948 AArch64 TLS General Dynamic. 3949 @end deffn 3950 @deffn {} BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC 3951 Unsigned 12 bit byte offset to global offset table entry for a 3952 symbol's tls_index structure. Used in conjunction with 3953 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21. 3954 @end deffn 3955 @deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC 3956 AArch64 TLS General Dynamic relocation. 3957 @end deffn 3958 @deffn {} BFD_RELOC_AARCH64_TLSGD_MOVW_G1 3959 AArch64 TLS General Dynamic relocation. 3960 @end deffn 3961 @deffn {} BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 3962 AArch64 TLS INITIAL EXEC relocation. 3963 @end deffn 3964 @deffn {} BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC 3965 AArch64 TLS INITIAL EXEC relocation. 3966 @end deffn 3967 @deffn {} BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC 3968 AArch64 TLS INITIAL EXEC relocation. 3969 @end deffn 3970 @deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19 3971 AArch64 TLS INITIAL EXEC relocation. 3972 @end deffn 3973 @deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC 3974 AArch64 TLS INITIAL EXEC relocation. 3975 @end deffn 3976 @deffn {} BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1 3977 AArch64 TLS INITIAL EXEC relocation. 3978 @end deffn 3979 @deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12 3980 bit[23:12] of byte offset to module TLS base address. 3981 @end deffn 3982 @deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12 3983 Unsigned 12 bit byte offset to module TLS base address. 3984 @end deffn 3985 @deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC 3986 No overflow check version of 3987 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12. 3988 @end deffn 3989 @deffn {} BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC 3990 Unsigned 12 bit byte offset to global offset table entry for a 3991 symbol's tls_index structure. Used in conjunction with 3992 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21. 3993 @end deffn 3994 @deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21 3995 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP 3996 instruction. 3997 @end deffn 3998 @deffn {} BFD_RELOC_AARCH64_TLSLD_ADR_PREL21 3999 GOT entry address for AArch64 TLS Local Dynamic, used with ADR 4000 instruction. 4001 @end deffn 4002 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12 4003 bit[11:1] of byte offset to module TLS base address, encoded in ldst 4004 instructions. 4005 @end deffn 4006 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC 4007 Similar to BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no 4008 overflow check. 4009 @end deffn 4010 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12 4011 bit[11:2] of byte offset to module TLS base address, encoded in ldst 4012 instructions. 4013 @end deffn 4014 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC 4015 Similar to BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no 4016 overflow check. 4017 @end deffn 4018 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12 4019 bit[11:3] of byte offset to module TLS base address, encoded in ldst 4020 instructions. 4021 @end deffn 4022 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC 4023 Similar to BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no 4024 overflow check. 4025 @end deffn 4026 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12 4027 bit[11:0] of byte offset to module TLS base address, encoded in ldst 4028 instructions. 4029 @end deffn 4030 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC 4031 Similar to BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no 4032 overflow check. 4033 @end deffn 4034 @deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0 4035 bit[15:0] of byte offset to module TLS base address. 4036 @end deffn 4037 @deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC 4038 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0. 4039 @end deffn 4040 @deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1 4041 bit[31:16] of byte offset to module TLS base address. 4042 @end deffn 4043 @deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC 4044 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1. 4045 @end deffn 4046 @deffn {} BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2 4047 bit[47:32] of byte offset to module TLS base address. 4048 @end deffn 4049 @deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2 4050 AArch64 TLS LOCAL EXEC relocation. 4051 @end deffn 4052 @deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 4053 AArch64 TLS LOCAL EXEC relocation. 4054 @end deffn 4055 @deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC 4056 AArch64 TLS LOCAL EXEC relocation. 4057 @end deffn 4058 @deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 4059 AArch64 TLS LOCAL EXEC relocation. 4060 @end deffn 4061 @deffn {} BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC 4062 AArch64 TLS LOCAL EXEC relocation. 4063 @end deffn 4064 @deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 4065 AArch64 TLS LOCAL EXEC relocation. 4066 @end deffn 4067 @deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 4068 AArch64 TLS LOCAL EXEC relocation. 4069 @end deffn 4070 @deffn {} BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC 4071 AArch64 TLS LOCAL EXEC relocation. 4072 @end deffn 4073 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12 4074 bit[11:1] of byte offset to module TLS base address, encoded in ldst 4075 instructions. 4076 @end deffn 4077 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC 4078 Similar to BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no 4079 overflow check. 4080 @end deffn 4081 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12 4082 bit[11:2] of byte offset to module TLS base address, encoded in ldst 4083 instructions. 4084 @end deffn 4085 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC 4086 Similar to BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no 4087 overflow check. 4088 @end deffn 4089 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12 4090 bit[11:3] of byte offset to module TLS base address, encoded in ldst 4091 instructions. 4092 @end deffn 4093 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC 4094 Similar to BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no 4095 overflow check. 4096 @end deffn 4097 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12 4098 bit[11:0] of byte offset to module TLS base address, encoded in ldst 4099 instructions. 4100 @end deffn 4101 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC 4102 Similar to BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow 4103 check. 4104 @end deffn 4105 @deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_PREL19 4106 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21 4107 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 4108 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_LD64_LO12 4109 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC 4110 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADD_LO12 4111 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_OFF_G1 4112 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC 4113 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_LDR 4114 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_ADD 4115 @deffnx {} BFD_RELOC_AARCH64_TLSDESC_CALL 4116 AArch64 TLS DESC relocations. 4117 @end deffn 4118 @deffn {} BFD_RELOC_AARCH64_COPY 4119 @deffnx {} BFD_RELOC_AARCH64_GLOB_DAT 4120 @deffnx {} BFD_RELOC_AARCH64_JUMP_SLOT 4121 @deffnx {} BFD_RELOC_AARCH64_RELATIVE 4122 AArch64 DSO relocations. 4123 @end deffn 4124 @deffn {} BFD_RELOC_AARCH64_TLS_DTPMOD 4125 @deffnx {} BFD_RELOC_AARCH64_TLS_DTPREL 4126 @deffnx {} BFD_RELOC_AARCH64_TLS_TPREL 4127 @deffnx {} BFD_RELOC_AARCH64_TLSDESC 4128 AArch64 TLS relocations. 4129 @end deffn 4130 @deffn {} BFD_RELOC_AARCH64_IRELATIVE 4131 AArch64 support for STT_GNU_IFUNC. 4132 @end deffn 4133 @deffn {} BFD_RELOC_AARCH64_RELOC_END 4134 AArch64 pseudo relocation code to mark the end of the AArch64 4135 relocation enumerators that have direct mapping to ELF reloc codes. 4136 There are a few more enumerators after this one; those are mainly 4137 used by the AArch64 assembler for the internal fixup or to select 4138 one of the above enumerators. 4139 @end deffn 4140 @deffn {} BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP 4141 AArch64 pseudo relocation code to be used internally by the AArch64 4142 assembler and not (currently) written to any object files. 4143 @end deffn 4144 @deffn {} BFD_RELOC_AARCH64_LDST_LO12 4145 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the 4146 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL. 4147 @end deffn 4148 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12 4149 AArch64 pseudo relocation code for TLS local dynamic mode. It's to 4150 be used internally by the AArch64 assembler and not (currently) 4151 written to any object files. 4152 @end deffn 4153 @deffn {} BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC 4154 Similar to BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow 4155 check. 4156 @end deffn 4157 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12 4158 AArch64 pseudo relocation code for TLS local exec mode. It's to be 4159 used internally by the AArch64 assembler and not (currently) written 4160 to any object files. 4161 @end deffn 4162 @deffn {} BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC 4163 Similar to BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow 4164 check. 4165 @end deffn 4166 @deffn {} BFD_RELOC_AARCH64_LD_GOT_LO12_NC 4167 AArch64 pseudo relocation code to be used internally by the AArch64 4168 assembler and not (currently) written to any object files. 4169 @end deffn 4170 @deffn {} BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC 4171 AArch64 pseudo relocation code to be used internally by the AArch64 4172 assembler and not (currently) written to any object files. 4173 @end deffn 4174 @deffn {} BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC 4175 AArch64 pseudo relocation code to be used internally by the AArch64 4176 assembler and not (currently) written to any object files. 4177 @end deffn 4178 @deffn {} BFD_RELOC_AARCH64_BRANCH9 4179 AArch64 9 bit pc-relative conditional branch and compare & branch. 4180 The lowest two bits must be zero and are not stored in the 4181 instruction, giving an 11 bit signed byte offset. 4182 @end deffn 4183 @deffn {} BFD_RELOC_TILEPRO_COPY 4184 @deffnx {} BFD_RELOC_TILEPRO_GLOB_DAT 4185 @deffnx {} BFD_RELOC_TILEPRO_JMP_SLOT 4186 @deffnx {} BFD_RELOC_TILEPRO_RELATIVE 4187 @deffnx {} BFD_RELOC_TILEPRO_BROFF_X1 4188 @deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1 4189 @deffnx {} BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT 4190 @deffnx {} BFD_RELOC_TILEPRO_IMM8_X0 4191 @deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0 4192 @deffnx {} BFD_RELOC_TILEPRO_IMM8_X1 4193 @deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1 4194 @deffnx {} BFD_RELOC_TILEPRO_DEST_IMM8_X1 4195 @deffnx {} BFD_RELOC_TILEPRO_MT_IMM15_X1 4196 @deffnx {} BFD_RELOC_TILEPRO_MF_IMM15_X1 4197 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0 4198 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1 4199 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO 4200 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO 4201 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI 4202 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI 4203 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA 4204 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA 4205 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_PCREL 4206 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_PCREL 4207 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL 4208 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL 4209 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL 4210 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL 4211 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL 4212 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL 4213 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT 4214 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT 4215 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO 4216 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO 4217 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI 4218 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI 4219 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA 4220 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA 4221 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0 4222 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X0 4223 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1 4224 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X1 4225 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0 4226 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1 4227 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0 4228 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1 4229 @deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL 4230 @deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD 4231 @deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD 4232 @deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD 4233 @deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD 4234 @deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD 4235 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD 4236 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD 4237 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO 4238 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO 4239 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI 4240 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI 4241 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA 4242 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA 4243 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE 4244 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE 4245 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO 4246 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO 4247 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI 4248 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI 4249 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA 4250 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA 4251 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32 4252 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32 4253 @deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32 4254 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE 4255 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE 4256 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO 4257 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO 4258 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI 4259 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI 4260 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA 4261 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA 4262 Tilera TILEPro Relocations. 4263 @end deffn 4264 @deffn {} BFD_RELOC_TILEGX_HW0 4265 @deffnx {} BFD_RELOC_TILEGX_HW1 4266 @deffnx {} BFD_RELOC_TILEGX_HW2 4267 @deffnx {} BFD_RELOC_TILEGX_HW3 4268 @deffnx {} BFD_RELOC_TILEGX_HW0_LAST 4269 @deffnx {} BFD_RELOC_TILEGX_HW1_LAST 4270 @deffnx {} BFD_RELOC_TILEGX_HW2_LAST 4271 @deffnx {} BFD_RELOC_TILEGX_COPY 4272 @deffnx {} BFD_RELOC_TILEGX_GLOB_DAT 4273 @deffnx {} BFD_RELOC_TILEGX_JMP_SLOT 4274 @deffnx {} BFD_RELOC_TILEGX_RELATIVE 4275 @deffnx {} BFD_RELOC_TILEGX_BROFF_X1 4276 @deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1 4277 @deffnx {} BFD_RELOC_TILEGX_JUMPOFF_X1_PLT 4278 @deffnx {} BFD_RELOC_TILEGX_IMM8_X0 4279 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y0 4280 @deffnx {} BFD_RELOC_TILEGX_IMM8_X1 4281 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y1 4282 @deffnx {} BFD_RELOC_TILEGX_DEST_IMM8_X1 4283 @deffnx {} BFD_RELOC_TILEGX_MT_IMM14_X1 4284 @deffnx {} BFD_RELOC_TILEGX_MF_IMM14_X1 4285 @deffnx {} BFD_RELOC_TILEGX_MMSTART_X0 4286 @deffnx {} BFD_RELOC_TILEGX_MMEND_X0 4287 @deffnx {} BFD_RELOC_TILEGX_SHAMT_X0 4288 @deffnx {} BFD_RELOC_TILEGX_SHAMT_X1 4289 @deffnx {} BFD_RELOC_TILEGX_SHAMT_Y0 4290 @deffnx {} BFD_RELOC_TILEGX_SHAMT_Y1 4291 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0 4292 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0 4293 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1 4294 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1 4295 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2 4296 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2 4297 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3 4298 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3 4299 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST 4300 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST 4301 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST 4302 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST 4303 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST 4304 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST 4305 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL 4306 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL 4307 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL 4308 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL 4309 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL 4310 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL 4311 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL 4312 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL 4313 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL 4314 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL 4315 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL 4316 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL 4317 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL 4318 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL 4319 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT 4320 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT 4321 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL 4322 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL 4323 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL 4324 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL 4325 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL 4326 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL 4327 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT 4328 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT 4329 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT 4330 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT 4331 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL 4332 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL 4333 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD 4334 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD 4335 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE 4336 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE 4337 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE 4338 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE 4339 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE 4340 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE 4341 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD 4342 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD 4343 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD 4344 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD 4345 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE 4346 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE 4347 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL 4348 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL 4349 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL 4350 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL 4351 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL 4352 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL 4353 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE 4354 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE 4355 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE 4356 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE 4357 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64 4358 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64 4359 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64 4360 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32 4361 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32 4362 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32 4363 @deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL 4364 @deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD 4365 @deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD 4366 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD 4367 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD 4368 @deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD 4369 @deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD 4370 @deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD 4371 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD 4372 @deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD 4373 Tilera TILE-Gx Relocations. 4374 @end deffn 4375 @deffn {} BFD_RELOC_BPF_64 4376 @deffnx {} BFD_RELOC_BPF_DISP32 4377 @deffnx {} BFD_RELOC_BPF_DISPCALL32 4378 @deffnx {} BFD_RELOC_BPF_DISP16 4379 Linux eBPF relocations. 4380 @end deffn 4381 @deffn {} BFD_RELOC_EPIPHANY_SIMM8 4382 Adapteva EPIPHANY - 8 bit signed pc-relative displacement. 4383 @end deffn 4384 @deffn {} BFD_RELOC_EPIPHANY_SIMM24 4385 Adapteva EPIPHANY - 24 bit signed pc-relative displacement. 4386 @end deffn 4387 @deffn {} BFD_RELOC_EPIPHANY_HIGH 4388 Adapteva EPIPHANY - 16 most-significant bits of absolute address. 4389 @end deffn 4390 @deffn {} BFD_RELOC_EPIPHANY_LOW 4391 Adapteva EPIPHANY - 16 least-significant bits of absolute address. 4392 @end deffn 4393 @deffn {} BFD_RELOC_EPIPHANY_SIMM11 4394 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate. 4395 @end deffn 4396 @deffn {} BFD_RELOC_EPIPHANY_IMM11 4397 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st 4398 displacement). 4399 @end deffn 4400 @deffn {} BFD_RELOC_EPIPHANY_IMM8 4401 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction. 4402 @end deffn 4403 @deffn {} BFD_RELOC_VISIUM_HI16 4404 @deffnx {} BFD_RELOC_VISIUM_LO16 4405 @deffnx {} BFD_RELOC_VISIUM_IM16 4406 @deffnx {} BFD_RELOC_VISIUM_REL16 4407 @deffnx {} BFD_RELOC_VISIUM_HI16_PCREL 4408 @deffnx {} BFD_RELOC_VISIUM_LO16_PCREL 4409 @deffnx {} BFD_RELOC_VISIUM_IM16_PCREL 4410 Visium Relocations. 4411 @end deffn 4412 @deffn {} BFD_RELOC_WASM32_LEB128 4413 @deffnx {} BFD_RELOC_WASM32_LEB128_GOT 4414 @deffnx {} BFD_RELOC_WASM32_LEB128_GOT_CODE 4415 @deffnx {} BFD_RELOC_WASM32_LEB128_PLT 4416 @deffnx {} BFD_RELOC_WASM32_PLT_INDEX 4417 @deffnx {} BFD_RELOC_WASM32_ABS32_CODE 4418 @deffnx {} BFD_RELOC_WASM32_COPY 4419 @deffnx {} BFD_RELOC_WASM32_CODE_POINTER 4420 @deffnx {} BFD_RELOC_WASM32_INDEX 4421 @deffnx {} BFD_RELOC_WASM32_PLT_SIG 4422 WebAssembly relocations. 4423 @end deffn 4424 @deffn {} BFD_RELOC_CKCORE_NONE 4425 @deffnx {} BFD_RELOC_CKCORE_ADDR32 4426 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM8BY4 4427 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM11BY2 4428 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM4BY2 4429 @deffnx {} BFD_RELOC_CKCORE_PCREL32 4430 @deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2 4431 @deffnx {} BFD_RELOC_CKCORE_GNU_VTINHERIT 4432 @deffnx {} BFD_RELOC_CKCORE_GNU_VTENTRY 4433 @deffnx {} BFD_RELOC_CKCORE_RELATIVE 4434 @deffnx {} BFD_RELOC_CKCORE_COPY 4435 @deffnx {} BFD_RELOC_CKCORE_GLOB_DAT 4436 @deffnx {} BFD_RELOC_CKCORE_JUMP_SLOT 4437 @deffnx {} BFD_RELOC_CKCORE_GOTOFF 4438 @deffnx {} BFD_RELOC_CKCORE_GOTPC 4439 @deffnx {} BFD_RELOC_CKCORE_GOT32 4440 @deffnx {} BFD_RELOC_CKCORE_PLT32 4441 @deffnx {} BFD_RELOC_CKCORE_ADDRGOT 4442 @deffnx {} BFD_RELOC_CKCORE_ADDRPLT 4443 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM26BY2 4444 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY2 4445 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM16BY4 4446 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY2 4447 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM10BY4 4448 @deffnx {} BFD_RELOC_CKCORE_ADDR_HI16 4449 @deffnx {} BFD_RELOC_CKCORE_ADDR_LO16 4450 @deffnx {} BFD_RELOC_CKCORE_GOTPC_HI16 4451 @deffnx {} BFD_RELOC_CKCORE_GOTPC_LO16 4452 @deffnx {} BFD_RELOC_CKCORE_GOTOFF_HI16 4453 @deffnx {} BFD_RELOC_CKCORE_GOTOFF_LO16 4454 @deffnx {} BFD_RELOC_CKCORE_GOT12 4455 @deffnx {} BFD_RELOC_CKCORE_GOT_HI16 4456 @deffnx {} BFD_RELOC_CKCORE_GOT_LO16 4457 @deffnx {} BFD_RELOC_CKCORE_PLT12 4458 @deffnx {} BFD_RELOC_CKCORE_PLT_HI16 4459 @deffnx {} BFD_RELOC_CKCORE_PLT_LO16 4460 @deffnx {} BFD_RELOC_CKCORE_ADDRGOT_HI16 4461 @deffnx {} BFD_RELOC_CKCORE_ADDRGOT_LO16 4462 @deffnx {} BFD_RELOC_CKCORE_ADDRPLT_HI16 4463 @deffnx {} BFD_RELOC_CKCORE_ADDRPLT_LO16 4464 @deffnx {} BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2 4465 @deffnx {} BFD_RELOC_CKCORE_TOFFSET_LO16 4466 @deffnx {} BFD_RELOC_CKCORE_DOFFSET_LO16 4467 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM18BY2 4468 @deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18 4469 @deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 4470 @deffnx {} BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 4471 @deffnx {} BFD_RELOC_CKCORE_GOTOFF_IMM18 4472 @deffnx {} BFD_RELOC_CKCORE_GOT_IMM18BY4 4473 @deffnx {} BFD_RELOC_CKCORE_PLT_IMM18BY4 4474 @deffnx {} BFD_RELOC_CKCORE_PCREL_IMM7BY4 4475 @deffnx {} BFD_RELOC_CKCORE_TLS_LE32 4476 @deffnx {} BFD_RELOC_CKCORE_TLS_IE32 4477 @deffnx {} BFD_RELOC_CKCORE_TLS_GD32 4478 @deffnx {} BFD_RELOC_CKCORE_TLS_LDM32 4479 @deffnx {} BFD_RELOC_CKCORE_TLS_LDO32 4480 @deffnx {} BFD_RELOC_CKCORE_TLS_DTPMOD32 4481 @deffnx {} BFD_RELOC_CKCORE_TLS_DTPOFF32 4482 @deffnx {} BFD_RELOC_CKCORE_TLS_TPOFF32 4483 @deffnx {} BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 4484 @deffnx {} BFD_RELOC_CKCORE_NOJSRI 4485 @deffnx {} BFD_RELOC_CKCORE_CALLGRAPH 4486 @deffnx {} BFD_RELOC_CKCORE_IRELATIVE 4487 @deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4 4488 @deffnx {} BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4 4489 C-SKY relocations. 4490 @end deffn 4491 @deffn {} BFD_RELOC_S12Z_OPR 4492 S12Z relocations. 4493 @end deffn 4494 @deffn {} BFD_RELOC_LARCH_TLS_DTPMOD32 4495 @deffnx {} BFD_RELOC_LARCH_TLS_DTPREL32 4496 @deffnx {} BFD_RELOC_LARCH_TLS_DTPMOD64 4497 @deffnx {} BFD_RELOC_LARCH_TLS_DTPREL64 4498 @deffnx {} BFD_RELOC_LARCH_TLS_TPREL32 4499 @deffnx {} BFD_RELOC_LARCH_TLS_TPREL64 4500 @deffnx {} BFD_RELOC_LARCH_TLS_DESC32 4501 @deffnx {} BFD_RELOC_LARCH_TLS_DESC64 4502 @deffnx {} BFD_RELOC_LARCH_MARK_LA 4503 @deffnx {} BFD_RELOC_LARCH_MARK_PCREL 4504 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_PCREL 4505 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE 4506 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_DUP 4507 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_GPREL 4508 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_TPREL 4509 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_GOT 4510 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_TLS_GD 4511 @deffnx {} BFD_RELOC_LARCH_SOP_PUSH_PLT_PCREL 4512 @deffnx {} BFD_RELOC_LARCH_SOP_ASSERT 4513 @deffnx {} BFD_RELOC_LARCH_SOP_NOT 4514 @deffnx {} BFD_RELOC_LARCH_SOP_SUB 4515 @deffnx {} BFD_RELOC_LARCH_SOP_SL 4516 @deffnx {} BFD_RELOC_LARCH_SOP_SR 4517 @deffnx {} BFD_RELOC_LARCH_SOP_ADD 4518 @deffnx {} BFD_RELOC_LARCH_SOP_AND 4519 @deffnx {} BFD_RELOC_LARCH_SOP_IF_ELSE 4520 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_5 4521 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_U_10_12 4522 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_12 4523 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_16 4524 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_10_16_S2 4525 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_5_20 4526 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2 4527 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_S_0_10_10_16_S2 4528 @deffnx {} BFD_RELOC_LARCH_SOP_POP_32_U 4529 @deffnx {} BFD_RELOC_LARCH_ADD8 4530 @deffnx {} BFD_RELOC_LARCH_ADD16 4531 @deffnx {} BFD_RELOC_LARCH_ADD24 4532 @deffnx {} BFD_RELOC_LARCH_ADD32 4533 @deffnx {} BFD_RELOC_LARCH_ADD64 4534 @deffnx {} BFD_RELOC_LARCH_SUB8 4535 @deffnx {} BFD_RELOC_LARCH_SUB16 4536 @deffnx {} BFD_RELOC_LARCH_SUB24 4537 @deffnx {} BFD_RELOC_LARCH_SUB32 4538 @deffnx {} BFD_RELOC_LARCH_SUB64 4539 @deffnx {} BFD_RELOC_LARCH_B16 4540 @deffnx {} BFD_RELOC_LARCH_B21 4541 @deffnx {} BFD_RELOC_LARCH_B26 4542 @deffnx {} BFD_RELOC_LARCH_ABS_HI20 4543 @deffnx {} BFD_RELOC_LARCH_ABS_LO12 4544 @deffnx {} BFD_RELOC_LARCH_ABS64_LO20 4545 @deffnx {} BFD_RELOC_LARCH_ABS64_HI12 4546 @deffnx {} BFD_RELOC_LARCH_PCALA_HI20 4547 @deffnx {} BFD_RELOC_LARCH_PCALA_LO12 4548 @deffnx {} BFD_RELOC_LARCH_PCALA64_LO20 4549 @deffnx {} BFD_RELOC_LARCH_PCALA64_HI12 4550 @deffnx {} BFD_RELOC_LARCH_GOT_PC_HI20 4551 @deffnx {} BFD_RELOC_LARCH_GOT_PC_LO12 4552 @deffnx {} BFD_RELOC_LARCH_GOT64_PC_LO20 4553 @deffnx {} BFD_RELOC_LARCH_GOT64_PC_HI12 4554 @deffnx {} BFD_RELOC_LARCH_GOT_HI20 4555 @deffnx {} BFD_RELOC_LARCH_GOT_LO12 4556 @deffnx {} BFD_RELOC_LARCH_GOT64_LO20 4557 @deffnx {} BFD_RELOC_LARCH_GOT64_HI12 4558 @deffnx {} BFD_RELOC_LARCH_TLS_LE_HI20 4559 @deffnx {} BFD_RELOC_LARCH_TLS_LE_LO12 4560 @deffnx {} BFD_RELOC_LARCH_TLS_LE64_LO20 4561 @deffnx {} BFD_RELOC_LARCH_TLS_LE64_HI12 4562 @deffnx {} BFD_RELOC_LARCH_TLS_IE_PC_HI20 4563 @deffnx {} BFD_RELOC_LARCH_TLS_IE_PC_LO12 4564 @deffnx {} BFD_RELOC_LARCH_TLS_IE64_PC_LO20 4565 @deffnx {} BFD_RELOC_LARCH_TLS_IE64_PC_HI12 4566 @deffnx {} BFD_RELOC_LARCH_TLS_IE_HI20 4567 @deffnx {} BFD_RELOC_LARCH_TLS_IE_LO12 4568 @deffnx {} BFD_RELOC_LARCH_TLS_IE64_LO20 4569 @deffnx {} BFD_RELOC_LARCH_TLS_IE64_HI12 4570 @deffnx {} BFD_RELOC_LARCH_TLS_LD_PC_HI20 4571 @deffnx {} BFD_RELOC_LARCH_TLS_LD_HI20 4572 @deffnx {} BFD_RELOC_LARCH_TLS_GD_PC_HI20 4573 @deffnx {} BFD_RELOC_LARCH_TLS_GD_HI20 4574 @deffnx {} BFD_RELOC_LARCH_32_PCREL 4575 @deffnx {} BFD_RELOC_LARCH_RELAX 4576 @deffnx {} BFD_RELOC_LARCH_DELETE 4577 @deffnx {} BFD_RELOC_LARCH_ALIGN 4578 @deffnx {} BFD_RELOC_LARCH_PCREL20_S2 4579 @deffnx {} BFD_RELOC_LARCH_CFA 4580 @deffnx {} BFD_RELOC_LARCH_ADD6 4581 @deffnx {} BFD_RELOC_LARCH_SUB6 4582 @deffnx {} BFD_RELOC_LARCH_ADD_ULEB128 4583 @deffnx {} BFD_RELOC_LARCH_SUB_ULEB128 4584 @deffnx {} BFD_RELOC_LARCH_64_PCREL 4585 @deffnx {} BFD_RELOC_LARCH_CALL36 4586 @deffnx {} BFD_RELOC_LARCH_TLS_DESC_PC_HI20 4587 @deffnx {} BFD_RELOC_LARCH_TLS_DESC_PC_LO12 4588 @deffnx {} BFD_RELOC_LARCH_TLS_DESC64_PC_LO20 4589 @deffnx {} BFD_RELOC_LARCH_TLS_DESC64_PC_HI12 4590 @deffnx {} BFD_RELOC_LARCH_TLS_DESC_HI20 4591 @deffnx {} BFD_RELOC_LARCH_TLS_DESC_LO12 4592 @deffnx {} BFD_RELOC_LARCH_TLS_DESC64_LO20 4593 @deffnx {} BFD_RELOC_LARCH_TLS_DESC64_HI12 4594 @deffnx {} BFD_RELOC_LARCH_TLS_DESC_LD 4595 @deffnx {} BFD_RELOC_LARCH_TLS_DESC_CALL 4596 @deffnx {} BFD_RELOC_LARCH_TLS_LE_HI20_R 4597 @deffnx {} BFD_RELOC_LARCH_TLS_LE_ADD_R 4598 @deffnx {} BFD_RELOC_LARCH_TLS_LE_LO12_R 4599 @deffnx {} BFD_RELOC_LARCH_TLS_LD_PCREL20_S2 4600 @deffnx {} BFD_RELOC_LARCH_TLS_GD_PCREL20_S2 4601 @deffnx {} BFD_RELOC_LARCH_TLS_DESC_PCREL20_S2 4602 LARCH relocations. 4603 @end deffn 4604 4605 @example 4606 typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; 4607 4608 @end example 4609 @findex bfd_reloc_type_lookup 4610 @subsubsection @code{bfd_reloc_type_lookup} 4611 @deftypefn {Function} reloc_howto_type *bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); reloc_howto_type *bfd_reloc_name_lookup (bfd *abfd, const char *reloc_name); 4612 Return a pointer to a howto structure which, when 4613 invoked, will perform the relocation @var{code} on data from the 4614 architecture noted. 4615 4616 @end deftypefn 4617 @findex bfd_default_reloc_type_lookup 4618 @subsubsection @code{bfd_default_reloc_type_lookup} 4619 @deftypefn {Function} reloc_howto_type *bfd_default_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code); 4620 Provides a default relocation lookup routine for any architecture. 4621 4622 @end deftypefn 4623 @findex bfd_get_reloc_code_name 4624 @subsubsection @code{bfd_get_reloc_code_name} 4625 @deftypefn {Function} const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code); 4626 Provides a printable name for the supplied relocation code. 4627 Useful mainly for printing error messages. 4628 4629 @end deftypefn 4630 @findex bfd_generic_relax_section 4631 @subsubsection @code{bfd_generic_relax_section} 4632 @deftypefn {Function} bool bfd_generic_relax_section (bfd *abfd, asection *section, struct bfd_link_info *, bool *); 4633 Provides default handling for relaxing for back ends which 4634 don't do relaxing. 4635 4636 @end deftypefn 4637 @findex bfd_generic_gc_sections 4638 @subsubsection @code{bfd_generic_gc_sections} 4639 @deftypefn {Function} bool bfd_generic_gc_sections (bfd *, struct bfd_link_info *); 4640 Provides default handling for relaxing for back ends which 4641 don't do section gc -- i.e., does nothing. 4642 4643 @end deftypefn 4644 @findex bfd_generic_lookup_section_flags 4645 @subsubsection @code{bfd_generic_lookup_section_flags} 4646 @deftypefn {Function} bool bfd_generic_lookup_section_flags (struct bfd_link_info *, struct flag_info *, asection *); 4647 Provides default handling for section flags lookup 4648 -- i.e., does nothing. 4649 Returns FALSE if the section should be omitted, otherwise TRUE. 4650 4651 @end deftypefn 4652 @findex bfd_generic_merge_sections 4653 @subsubsection @code{bfd_generic_merge_sections} 4654 @deftypefn {Function} bool bfd_generic_merge_sections (bfd *, struct bfd_link_info *); 4655 Provides default handling for SEC_MERGE section merging for back ends 4656 which don't have SEC_MERGE support -- i.e., does nothing. 4657 4658 @end deftypefn 4659 @findex bfd_generic_get_relocated_section_contents 4660 @subsubsection @code{bfd_generic_get_relocated_section_contents} 4661 @deftypefn {Function} bfd_byte *bfd_generic_get_relocated_section_contents (bfd *abfd, struct bfd_link_info *link_info, struct bfd_link_order *link_order, bfd_byte *data, bool relocatable, asymbol **symbols); 4662 Provides default handling of relocation effort for back ends 4663 which can't be bothered to do it efficiently. 4664 4665 @end deftypefn 4666 @findex _bfd_generic_set_reloc 4667 @subsubsection @code{_bfd_generic_set_reloc} 4668 @deftypefn {Function} void _bfd_generic_set_reloc (bfd *abfd, sec_ptr section, arelent **relptr, unsigned int count); 4669 Installs a new set of internal relocations in SECTION. 4670 4671 @end deftypefn 4672 @findex _bfd_unrecognized_reloc 4673 @subsubsection @code{_bfd_unrecognized_reloc} 4674 @deftypefn {Function} bool _bfd_unrecognized_reloc (bfd * abfd, sec_ptr section, unsigned int r_type); 4675 Reports an unrecognized reloc. 4676 Written as a function in order to reduce code duplication. 4677 Returns FALSE so that it can be called from a return statement. 4678 4679 @end deftypefn 4680
Indexes created Mon May 04 00:23:20 UTC 2026