1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* Instruction building/extraction support for m32r. -*- C -*- 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 5 - the resultant file is machine generated, cgen-ibld.in isn't 6 7 Copyright (C) 1996-2025 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "m32r-desc.h" 35 #include "m32r-opc.h" 36 #include "cgen/basic-modes.h" 37 #include "opintl.h" 38 #include "safe-ctype.h" 39 40 #undef min 41 #define min(a,b) ((a) < (b) ? (a) : (b)) 42 #undef max 43 #define max(a,b) ((a) > (b) ? (a) : (b)) 44 45 /* Used by the ifield rtx function. */ 46 #define FLD(f) (fields->f) 47 48 static const char * insert_normal 49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 51 static const char * insert_insn_normal 52 (CGEN_CPU_DESC, const CGEN_INSN *, 53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 54 static int extract_normal 55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 56 unsigned int, unsigned int, unsigned int, unsigned int, 57 unsigned int, unsigned int, bfd_vma, long *); 58 static int extract_insn_normal 59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 61 #if CGEN_INT_INSN_P 62 static void put_insn_int_value 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 64 #endif 65 #if ! CGEN_INT_INSN_P 66 static CGEN_INLINE void insert_1 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 68 static CGEN_INLINE int fill_cache 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 70 static CGEN_INLINE long extract_1 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 72 #endif 73 74 /* Operand insertion. */ 76 77 #if ! CGEN_INT_INSN_P 78 79 /* Subroutine of insert_normal. */ 80 81 static CGEN_INLINE void 82 insert_1 (CGEN_CPU_DESC cd, 83 unsigned long value, 84 int start, 85 int length, 86 int word_length, 87 unsigned char *bufp) 88 { 89 unsigned long x, mask; 90 int shift; 91 92 x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); 93 94 /* Written this way to avoid undefined behaviour. */ 95 mask = (1UL << (length - 1) << 1) - 1; 96 if (CGEN_INSN_LSB0_P) 97 shift = (start + 1) - length; 98 else 99 shift = (word_length - (start + length)); 100 x = (x & ~(mask << shift)) | ((value & mask) << shift); 101 102 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); 103 } 104 105 #endif /* ! CGEN_INT_INSN_P */ 106 107 /* Default insertion routine. 108 109 ATTRS is a mask of the boolean attributes. 110 WORD_OFFSET is the offset in bits from the start of the insn of the value. 111 WORD_LENGTH is the length of the word in bits in which the value resides. 112 START is the starting bit number in the word, architecture origin. 113 LENGTH is the length of VALUE in bits. 114 TOTAL_LENGTH is the total length of the insn in bits. 115 116 The result is an error message or NULL if success. */ 117 118 /* ??? This duplicates functionality with bfd's howto table and 119 bfd_install_relocation. */ 120 /* ??? This doesn't handle bfd_vma's. Create another function when 121 necessary. */ 122 123 static const char * 124 insert_normal (CGEN_CPU_DESC cd, 125 long value, 126 unsigned int attrs, 127 unsigned int word_offset, 128 unsigned int start, 129 unsigned int length, 130 unsigned int word_length, 131 unsigned int total_length, 132 CGEN_INSN_BYTES_PTR buffer) 133 { 134 static char errbuf[100]; 135 unsigned long mask; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 /* Written this way to avoid undefined behaviour. */ 142 mask = (1UL << (length - 1) << 1) - 1; 143 144 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 145 abort (); 146 147 /* For architectures with insns smaller than the base-insn-bitsize, 148 word_length may be too big. */ 149 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 150 { 151 if (word_offset == 0 152 && word_length > total_length) 153 word_length = total_length; 154 } 155 156 /* Ensure VALUE will fit. */ 157 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 158 { 159 long minval = - (1UL << (length - 1)); 160 unsigned long maxval = mask; 161 162 if ((value > 0 && (unsigned long) value > maxval) 163 || value < minval) 164 { 165 /* xgettext:c-format */ 166 sprintf (errbuf, 167 _("operand out of range (%ld not between %ld and %lu)"), 168 value, minval, maxval); 169 return errbuf; 170 } 171 } 172 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 173 { 174 unsigned long maxval = mask; 175 unsigned long val = (unsigned long) value; 176 177 /* For hosts with a word size > 32 check to see if value has been sign 178 extended beyond 32 bits. If so then ignore these higher sign bits 179 as the user is attempting to store a 32-bit signed value into an 180 unsigned 32-bit field which is allowed. */ 181 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 182 val &= 0xFFFFFFFF; 183 184 if (val > maxval) 185 { 186 /* xgettext:c-format */ 187 sprintf (errbuf, 188 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 189 val, maxval); 190 return errbuf; 191 } 192 } 193 else 194 { 195 if (! cgen_signed_overflow_ok_p (cd)) 196 { 197 long minval = - (1UL << (length - 1)); 198 long maxval = (1UL << (length - 1)) - 1; 199 200 if (value < minval || value > maxval) 201 { 202 sprintf 203 /* xgettext:c-format */ 204 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 205 value, minval, maxval); 206 return errbuf; 207 } 208 } 209 } 210 211 #if CGEN_INT_INSN_P 212 213 { 214 int shift_within_word, shift_to_word, shift; 215 216 /* How to shift the value to BIT0 of the word. */ 217 shift_to_word = total_length - (word_offset + word_length); 218 219 /* How to shift the value to the field within the word. */ 220 if (CGEN_INSN_LSB0_P) 221 shift_within_word = start + 1 - length; 222 else 223 shift_within_word = word_length - start - length; 224 225 /* The total SHIFT, then mask in the value. */ 226 shift = shift_to_word + shift_within_word; 227 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 228 } 229 230 #else /* ! CGEN_INT_INSN_P */ 231 232 { 233 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 234 235 insert_1 (cd, value, start, length, word_length, bufp); 236 } 237 238 #endif /* ! CGEN_INT_INSN_P */ 239 240 return NULL; 241 } 242 243 /* Default insn builder (insert handler). 244 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 245 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 246 recorded in host byte order, otherwise BUFFER is an array of bytes 247 and the value is recorded in target byte order). 248 The result is an error message or NULL if success. */ 249 250 static const char * 251 insert_insn_normal (CGEN_CPU_DESC cd, 252 const CGEN_INSN * insn, 253 CGEN_FIELDS * fields, 254 CGEN_INSN_BYTES_PTR buffer, 255 bfd_vma pc) 256 { 257 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 258 unsigned long value; 259 const CGEN_SYNTAX_CHAR_TYPE * syn; 260 261 CGEN_INIT_INSERT (cd); 262 value = CGEN_INSN_BASE_VALUE (insn); 263 264 /* If we're recording insns as numbers (rather than a string of bytes), 265 target byte order handling is deferred until later. */ 266 267 #if CGEN_INT_INSN_P 268 269 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 270 CGEN_FIELDS_BITSIZE (fields), value); 271 272 #else 273 274 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 275 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 276 value, cd->insn_endian); 277 278 #endif /* ! CGEN_INT_INSN_P */ 279 280 /* ??? It would be better to scan the format's fields. 281 Still need to be able to insert a value based on the operand though; 282 e.g. storing a branch displacement that got resolved later. 283 Needs more thought first. */ 284 285 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 286 { 287 const char *errmsg; 288 289 if (CGEN_SYNTAX_CHAR_P (* syn)) 290 continue; 291 292 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 293 fields, buffer, pc); 294 if (errmsg) 295 return errmsg; 296 } 297 298 return NULL; 299 } 300 301 #if CGEN_INT_INSN_P 302 /* Cover function to store an insn value into an integral insn. Must go here 303 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 304 305 static void 306 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 307 CGEN_INSN_BYTES_PTR buf, 308 int length, 309 int insn_length, 310 CGEN_INSN_INT value) 311 { 312 /* For architectures with insns smaller than the base-insn-bitsize, 313 length may be too big. */ 314 if (length > insn_length) 315 *buf = value; 316 else 317 { 318 int shift = insn_length - length; 319 /* Written this way to avoid undefined behaviour. */ 320 CGEN_INSN_INT mask = length == 0 ? 0 : (1UL << (length - 1) << 1) - 1; 321 322 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 323 } 324 } 325 #endif 326 327 /* Operand extraction. */ 329 330 #if ! CGEN_INT_INSN_P 331 332 /* Subroutine of extract_normal. 333 Ensure sufficient bytes are cached in EX_INFO. 334 OFFSET is the offset in bytes from the start of the insn of the value. 335 BYTES is the length of the needed value. 336 Returns 1 for success, 0 for failure. */ 337 338 static CGEN_INLINE int 339 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 340 CGEN_EXTRACT_INFO *ex_info, 341 int offset, 342 int bytes, 343 bfd_vma pc) 344 { 345 /* It's doubtful that the middle part has already been fetched so 346 we don't optimize that case. kiss. */ 347 unsigned int mask; 348 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 349 350 /* First do a quick check. */ 351 mask = (1 << bytes) - 1; 352 if (((ex_info->valid >> offset) & mask) == mask) 353 return 1; 354 355 /* Search for the first byte we need to read. */ 356 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 357 if (! (mask & ex_info->valid)) 358 break; 359 360 if (bytes) 361 { 362 int status; 363 364 pc += offset; 365 status = (*info->read_memory_func) 366 (pc, ex_info->insn_bytes + offset, bytes, info); 367 368 if (status != 0) 369 { 370 (*info->memory_error_func) (status, pc, info); 371 return 0; 372 } 373 374 ex_info->valid |= ((1 << bytes) - 1) << offset; 375 } 376 377 return 1; 378 } 379 380 /* Subroutine of extract_normal. */ 381 382 static CGEN_INLINE long 383 extract_1 (CGEN_CPU_DESC cd, 384 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 385 int start, 386 int length, 387 int word_length, 388 unsigned char *bufp, 389 bfd_vma pc ATTRIBUTE_UNUSED) 390 { 391 unsigned long x; 392 int shift; 393 394 x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); 395 396 if (CGEN_INSN_LSB0_P) 397 shift = (start + 1) - length; 398 else 399 shift = (word_length - (start + length)); 400 return x >> shift; 401 } 402 403 #endif /* ! CGEN_INT_INSN_P */ 404 405 /* Default extraction routine. 406 407 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 408 or sometimes less for cases like the m32r where the base insn size is 32 409 but some insns are 16 bits. 410 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 411 but for generality we take a bitmask of all of them. 412 WORD_OFFSET is the offset in bits from the start of the insn of the value. 413 WORD_LENGTH is the length of the word in bits in which the value resides. 414 START is the starting bit number in the word, architecture origin. 415 LENGTH is the length of VALUE in bits. 416 TOTAL_LENGTH is the total length of the insn in bits. 417 418 Returns 1 for success, 0 for failure. */ 419 420 /* ??? The return code isn't properly used. wip. */ 421 422 /* ??? This doesn't handle bfd_vma's. Create another function when 423 necessary. */ 424 425 static int 426 extract_normal (CGEN_CPU_DESC cd, 427 #if ! CGEN_INT_INSN_P 428 CGEN_EXTRACT_INFO *ex_info, 429 #else 430 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 431 #endif 432 CGEN_INSN_INT insn_value, 433 unsigned int attrs, 434 unsigned int word_offset, 435 unsigned int start, 436 unsigned int length, 437 unsigned int word_length, 438 unsigned int total_length, 439 #if ! CGEN_INT_INSN_P 440 bfd_vma pc, 441 #else 442 bfd_vma pc ATTRIBUTE_UNUSED, 443 #endif 444 long *valuep) 445 { 446 long value, mask; 447 448 /* If LENGTH is zero, this operand doesn't contribute to the value 449 so give it a standard value of zero. */ 450 if (length == 0) 451 { 452 *valuep = 0; 453 return 1; 454 } 455 456 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 457 abort (); 458 459 /* For architectures with insns smaller than the insn-base-bitsize, 460 word_length may be too big. */ 461 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 462 { 463 if (word_offset + word_length > total_length) 464 word_length = total_length - word_offset; 465 } 466 467 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 468 469 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 470 { 471 if (CGEN_INSN_LSB0_P) 472 value = insn_value >> ((word_offset + start + 1) - length); 473 else 474 value = insn_value >> (total_length - ( word_offset + start + length)); 475 } 476 477 #if ! CGEN_INT_INSN_P 478 479 else 480 { 481 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 482 483 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 484 abort (); 485 486 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 487 { 488 *valuep = 0; 489 return 0; 490 } 491 492 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 493 } 494 495 #endif /* ! CGEN_INT_INSN_P */ 496 497 /* Written this way to avoid undefined behaviour. */ 498 mask = (1UL << (length - 1) << 1) - 1; 499 500 value &= mask; 501 /* sign extend? */ 502 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 503 && (value & (1UL << (length - 1)))) 504 value |= ~mask; 505 506 *valuep = value; 507 508 return 1; 509 } 510 511 /* Default insn extractor. 512 513 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 514 The extracted fields are stored in FIELDS. 515 EX_INFO is used to handle reading variable length insns. 516 Return the length of the insn in bits, or 0 if no match, 517 or -1 if an error occurs fetching data (memory_error_func will have 518 been called). */ 519 520 static int 521 extract_insn_normal (CGEN_CPU_DESC cd, 522 const CGEN_INSN *insn, 523 CGEN_EXTRACT_INFO *ex_info, 524 CGEN_INSN_INT insn_value, 525 CGEN_FIELDS *fields, 526 bfd_vma pc) 527 { 528 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 529 const CGEN_SYNTAX_CHAR_TYPE *syn; 530 531 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 532 533 CGEN_INIT_EXTRACT (cd); 534 535 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 536 { 537 int length; 538 539 if (CGEN_SYNTAX_CHAR_P (*syn)) 540 continue; 541 542 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 543 ex_info, insn_value, fields, pc); 544 if (length <= 0) 545 return length; 546 } 547 548 /* We recognized and successfully extracted this insn. */ 549 return CGEN_INSN_BITSIZE (insn); 550 } 551 552 /* Machine generated code added here. */ 554 555 const char * m32r_cgen_insert_operand 556 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 557 558 /* Main entry point for operand insertion. 559 560 This function is basically just a big switch statement. Earlier versions 561 used tables to look up the function to use, but 562 - if the table contains both assembler and disassembler functions then 563 the disassembler contains much of the assembler and vice-versa, 564 - there's a lot of inlining possibilities as things grow, 565 - using a switch statement avoids the function call overhead. 566 567 This function could be moved into `parse_insn_normal', but keeping it 568 separate makes clear the interface between `parse_insn_normal' and each of 569 the handlers. It's also needed by GAS to insert operands that couldn't be 570 resolved during parsing. */ 571 572 const char * 573 m32r_cgen_insert_operand (CGEN_CPU_DESC cd, 574 int opindex, 575 CGEN_FIELDS * fields, 576 CGEN_INSN_BYTES_PTR buffer, 577 bfd_vma pc ATTRIBUTE_UNUSED) 578 { 579 const char * errmsg = NULL; 580 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 581 582 switch (opindex) 583 { 584 case M32R_OPERAND_ACC : 585 errmsg = insert_normal (cd, fields->f_acc, 0, 0, 8, 1, 32, total_length, buffer); 586 break; 587 case M32R_OPERAND_ACCD : 588 errmsg = insert_normal (cd, fields->f_accd, 0, 0, 4, 2, 32, total_length, buffer); 589 break; 590 case M32R_OPERAND_ACCS : 591 errmsg = insert_normal (cd, fields->f_accs, 0, 0, 12, 2, 32, total_length, buffer); 592 break; 593 case M32R_OPERAND_DCR : 594 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 595 break; 596 case M32R_OPERAND_DISP16 : 597 { 598 long value = fields->f_disp16; 599 value = ((SI) (((value) - (pc))) >> (2)); 600 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, buffer); 601 } 602 break; 603 case M32R_OPERAND_DISP24 : 604 { 605 long value = fields->f_disp24; 606 value = ((SI) (((value) - (pc))) >> (2)); 607 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, buffer); 608 } 609 break; 610 case M32R_OPERAND_DISP8 : 611 { 612 long value = fields->f_disp8; 613 value = ((SI) (((value) - (((pc) & (-4))))) >> (2)); 614 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, buffer); 615 } 616 break; 617 case M32R_OPERAND_DR : 618 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 619 break; 620 case M32R_OPERAND_HASH : 621 break; 622 case M32R_OPERAND_HI16 : 623 errmsg = insert_normal (cd, fields->f_hi16, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, buffer); 624 break; 625 case M32R_OPERAND_IMM1 : 626 { 627 long value = fields->f_imm1; 628 value = ((value) - (1)); 629 errmsg = insert_normal (cd, value, 0, 0, 15, 1, 32, total_length, buffer); 630 } 631 break; 632 case M32R_OPERAND_SCR : 633 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 634 break; 635 case M32R_OPERAND_SIMM16 : 636 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); 637 break; 638 case M32R_OPERAND_SIMM8 : 639 errmsg = insert_normal (cd, fields->f_simm8, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, buffer); 640 break; 641 case M32R_OPERAND_SLO16 : 642 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, buffer); 643 break; 644 case M32R_OPERAND_SR : 645 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 646 break; 647 case M32R_OPERAND_SRC1 : 648 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 4, 4, 32, total_length, buffer); 649 break; 650 case M32R_OPERAND_SRC2 : 651 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 12, 4, 32, total_length, buffer); 652 break; 653 case M32R_OPERAND_UIMM16 : 654 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); 655 break; 656 case M32R_OPERAND_UIMM24 : 657 errmsg = insert_normal (cd, fields->f_uimm24, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, buffer); 658 break; 659 case M32R_OPERAND_UIMM3 : 660 errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 5, 3, 32, total_length, buffer); 661 break; 662 case M32R_OPERAND_UIMM4 : 663 errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 12, 4, 32, total_length, buffer); 664 break; 665 case M32R_OPERAND_UIMM5 : 666 errmsg = insert_normal (cd, fields->f_uimm5, 0, 0, 11, 5, 32, total_length, buffer); 667 break; 668 case M32R_OPERAND_UIMM8 : 669 errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 8, 8, 32, total_length, buffer); 670 break; 671 case M32R_OPERAND_ULO16 : 672 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 16, 16, 32, total_length, buffer); 673 break; 674 675 default : 676 /* xgettext:c-format */ 677 opcodes_error_handler 678 (_("internal error: unrecognized field %d while building insn"), 679 opindex); 680 abort (); 681 } 682 683 return errmsg; 684 } 685 686 int m32r_cgen_extract_operand 687 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 688 689 /* Main entry point for operand extraction. 690 The result is <= 0 for error, >0 for success. 691 ??? Actual values aren't well defined right now. 692 693 This function is basically just a big switch statement. Earlier versions 694 used tables to look up the function to use, but 695 - if the table contains both assembler and disassembler functions then 696 the disassembler contains much of the assembler and vice-versa, 697 - there's a lot of inlining possibilities as things grow, 698 - using a switch statement avoids the function call overhead. 699 700 This function could be moved into `print_insn_normal', but keeping it 701 separate makes clear the interface between `print_insn_normal' and each of 702 the handlers. */ 703 704 int 705 m32r_cgen_extract_operand (CGEN_CPU_DESC cd, 706 int opindex, 707 CGEN_EXTRACT_INFO *ex_info, 708 CGEN_INSN_INT insn_value, 709 CGEN_FIELDS * fields, 710 bfd_vma pc) 711 { 712 /* Assume success (for those operands that are nops). */ 713 int length = 1; 714 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 715 716 switch (opindex) 717 { 718 case M32R_OPERAND_ACC : 719 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_acc); 720 break; 721 case M32R_OPERAND_ACCD : 722 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 2, 32, total_length, pc, & fields->f_accd); 723 break; 724 case M32R_OPERAND_ACCS : 725 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 2, 32, total_length, pc, & fields->f_accs); 726 break; 727 case M32R_OPERAND_DCR : 728 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 729 break; 730 case M32R_OPERAND_DISP16 : 731 { 732 long value; 733 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value); 734 value = ((((value) * (4))) + (pc)); 735 fields->f_disp16 = value; 736 } 737 break; 738 case M32R_OPERAND_DISP24 : 739 { 740 long value; 741 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value); 742 value = ((((value) * (4))) + (pc)); 743 fields->f_disp24 = value; 744 } 745 break; 746 case M32R_OPERAND_DISP8 : 747 { 748 long value; 749 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value); 750 value = ((((value) * (4))) + (((pc) & (-4)))); 751 fields->f_disp8 = value; 752 } 753 break; 754 case M32R_OPERAND_DR : 755 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 756 break; 757 case M32R_OPERAND_HASH : 758 break; 759 case M32R_OPERAND_HI16 : 760 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGN_OPT), 0, 16, 16, 32, total_length, pc, & fields->f_hi16); 761 break; 762 case M32R_OPERAND_IMM1 : 763 { 764 long value; 765 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 1, 32, total_length, pc, & value); 766 value = ((value) + (1)); 767 fields->f_imm1 = value; 768 } 769 break; 770 case M32R_OPERAND_SCR : 771 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 772 break; 773 case M32R_OPERAND_SIMM16 : 774 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16); 775 break; 776 case M32R_OPERAND_SIMM8 : 777 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 8, 8, 32, total_length, pc, & fields->f_simm8); 778 break; 779 case M32R_OPERAND_SLO16 : 780 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_simm16); 781 break; 782 case M32R_OPERAND_SR : 783 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 784 break; 785 case M32R_OPERAND_SRC1 : 786 length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 4, 32, total_length, pc, & fields->f_r1); 787 break; 788 case M32R_OPERAND_SRC2 : 789 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_r2); 790 break; 791 case M32R_OPERAND_UIMM16 : 792 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); 793 break; 794 case M32R_OPERAND_UIMM24 : 795 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24); 796 break; 797 case M32R_OPERAND_UIMM3 : 798 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 3, 32, total_length, pc, & fields->f_uimm3); 799 break; 800 case M32R_OPERAND_UIMM4 : 801 length = extract_normal (cd, ex_info, insn_value, 0, 0, 12, 4, 32, total_length, pc, & fields->f_uimm4); 802 break; 803 case M32R_OPERAND_UIMM5 : 804 length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 5, 32, total_length, pc, & fields->f_uimm5); 805 break; 806 case M32R_OPERAND_UIMM8 : 807 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 8, 32, total_length, pc, & fields->f_uimm8); 808 break; 809 case M32R_OPERAND_ULO16 : 810 length = extract_normal (cd, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_uimm16); 811 break; 812 813 default : 814 /* xgettext:c-format */ 815 opcodes_error_handler 816 (_("internal error: unrecognized field %d while decoding insn"), 817 opindex); 818 abort (); 819 } 820 821 return length; 822 } 823 824 cgen_insert_fn * const m32r_cgen_insert_handlers[] = 825 { 826 insert_insn_normal, 827 }; 828 829 cgen_extract_fn * const m32r_cgen_extract_handlers[] = 830 { 831 extract_insn_normal, 832 }; 833 834 int m32r_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 835 bfd_vma m32r_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 836 837 /* Getting values from cgen_fields is handled by a collection of functions. 838 They are distinguished by the type of the VALUE argument they return. 839 TODO: floating point, inlining support, remove cases where result type 840 not appropriate. */ 841 842 int 843 m32r_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 844 int opindex, 845 const CGEN_FIELDS * fields) 846 { 847 int value; 848 849 switch (opindex) 850 { 851 case M32R_OPERAND_ACC : 852 value = fields->f_acc; 853 break; 854 case M32R_OPERAND_ACCD : 855 value = fields->f_accd; 856 break; 857 case M32R_OPERAND_ACCS : 858 value = fields->f_accs; 859 break; 860 case M32R_OPERAND_DCR : 861 value = fields->f_r1; 862 break; 863 case M32R_OPERAND_DISP16 : 864 value = fields->f_disp16; 865 break; 866 case M32R_OPERAND_DISP24 : 867 value = fields->f_disp24; 868 break; 869 case M32R_OPERAND_DISP8 : 870 value = fields->f_disp8; 871 break; 872 case M32R_OPERAND_DR : 873 value = fields->f_r1; 874 break; 875 case M32R_OPERAND_HASH : 876 value = 0; 877 break; 878 case M32R_OPERAND_HI16 : 879 value = fields->f_hi16; 880 break; 881 case M32R_OPERAND_IMM1 : 882 value = fields->f_imm1; 883 break; 884 case M32R_OPERAND_SCR : 885 value = fields->f_r2; 886 break; 887 case M32R_OPERAND_SIMM16 : 888 value = fields->f_simm16; 889 break; 890 case M32R_OPERAND_SIMM8 : 891 value = fields->f_simm8; 892 break; 893 case M32R_OPERAND_SLO16 : 894 value = fields->f_simm16; 895 break; 896 case M32R_OPERAND_SR : 897 value = fields->f_r2; 898 break; 899 case M32R_OPERAND_SRC1 : 900 value = fields->f_r1; 901 break; 902 case M32R_OPERAND_SRC2 : 903 value = fields->f_r2; 904 break; 905 case M32R_OPERAND_UIMM16 : 906 value = fields->f_uimm16; 907 break; 908 case M32R_OPERAND_UIMM24 : 909 value = fields->f_uimm24; 910 break; 911 case M32R_OPERAND_UIMM3 : 912 value = fields->f_uimm3; 913 break; 914 case M32R_OPERAND_UIMM4 : 915 value = fields->f_uimm4; 916 break; 917 case M32R_OPERAND_UIMM5 : 918 value = fields->f_uimm5; 919 break; 920 case M32R_OPERAND_UIMM8 : 921 value = fields->f_uimm8; 922 break; 923 case M32R_OPERAND_ULO16 : 924 value = fields->f_uimm16; 925 break; 926 927 default : 928 /* xgettext:c-format */ 929 opcodes_error_handler 930 (_("internal error: unrecognized field %d while getting int operand"), 931 opindex); 932 abort (); 933 } 934 935 return value; 936 } 937 938 bfd_vma 939 m32r_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 940 int opindex, 941 const CGEN_FIELDS * fields) 942 { 943 bfd_vma value; 944 945 switch (opindex) 946 { 947 case M32R_OPERAND_ACC : 948 value = fields->f_acc; 949 break; 950 case M32R_OPERAND_ACCD : 951 value = fields->f_accd; 952 break; 953 case M32R_OPERAND_ACCS : 954 value = fields->f_accs; 955 break; 956 case M32R_OPERAND_DCR : 957 value = fields->f_r1; 958 break; 959 case M32R_OPERAND_DISP16 : 960 value = fields->f_disp16; 961 break; 962 case M32R_OPERAND_DISP24 : 963 value = fields->f_disp24; 964 break; 965 case M32R_OPERAND_DISP8 : 966 value = fields->f_disp8; 967 break; 968 case M32R_OPERAND_DR : 969 value = fields->f_r1; 970 break; 971 case M32R_OPERAND_HASH : 972 value = 0; 973 break; 974 case M32R_OPERAND_HI16 : 975 value = fields->f_hi16; 976 break; 977 case M32R_OPERAND_IMM1 : 978 value = fields->f_imm1; 979 break; 980 case M32R_OPERAND_SCR : 981 value = fields->f_r2; 982 break; 983 case M32R_OPERAND_SIMM16 : 984 value = fields->f_simm16; 985 break; 986 case M32R_OPERAND_SIMM8 : 987 value = fields->f_simm8; 988 break; 989 case M32R_OPERAND_SLO16 : 990 value = fields->f_simm16; 991 break; 992 case M32R_OPERAND_SR : 993 value = fields->f_r2; 994 break; 995 case M32R_OPERAND_SRC1 : 996 value = fields->f_r1; 997 break; 998 case M32R_OPERAND_SRC2 : 999 value = fields->f_r2; 1000 break; 1001 case M32R_OPERAND_UIMM16 : 1002 value = fields->f_uimm16; 1003 break; 1004 case M32R_OPERAND_UIMM24 : 1005 value = fields->f_uimm24; 1006 break; 1007 case M32R_OPERAND_UIMM3 : 1008 value = fields->f_uimm3; 1009 break; 1010 case M32R_OPERAND_UIMM4 : 1011 value = fields->f_uimm4; 1012 break; 1013 case M32R_OPERAND_UIMM5 : 1014 value = fields->f_uimm5; 1015 break; 1016 case M32R_OPERAND_UIMM8 : 1017 value = fields->f_uimm8; 1018 break; 1019 case M32R_OPERAND_ULO16 : 1020 value = fields->f_uimm16; 1021 break; 1022 1023 default : 1024 /* xgettext:c-format */ 1025 opcodes_error_handler 1026 (_("internal error: unrecognized field %d while getting vma operand"), 1027 opindex); 1028 abort (); 1029 } 1030 1031 return value; 1032 } 1033 1034 void m32r_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1035 void m32r_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1036 1037 /* Stuffing values in cgen_fields is handled by a collection of functions. 1038 They are distinguished by the type of the VALUE argument they accept. 1039 TODO: floating point, inlining support, remove cases where argument type 1040 not appropriate. */ 1041 1042 void 1043 m32r_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1044 int opindex, 1045 CGEN_FIELDS * fields, 1046 int value) 1047 { 1048 switch (opindex) 1049 { 1050 case M32R_OPERAND_ACC : 1051 fields->f_acc = value; 1052 break; 1053 case M32R_OPERAND_ACCD : 1054 fields->f_accd = value; 1055 break; 1056 case M32R_OPERAND_ACCS : 1057 fields->f_accs = value; 1058 break; 1059 case M32R_OPERAND_DCR : 1060 fields->f_r1 = value; 1061 break; 1062 case M32R_OPERAND_DISP16 : 1063 fields->f_disp16 = value; 1064 break; 1065 case M32R_OPERAND_DISP24 : 1066 fields->f_disp24 = value; 1067 break; 1068 case M32R_OPERAND_DISP8 : 1069 fields->f_disp8 = value; 1070 break; 1071 case M32R_OPERAND_DR : 1072 fields->f_r1 = value; 1073 break; 1074 case M32R_OPERAND_HASH : 1075 break; 1076 case M32R_OPERAND_HI16 : 1077 fields->f_hi16 = value; 1078 break; 1079 case M32R_OPERAND_IMM1 : 1080 fields->f_imm1 = value; 1081 break; 1082 case M32R_OPERAND_SCR : 1083 fields->f_r2 = value; 1084 break; 1085 case M32R_OPERAND_SIMM16 : 1086 fields->f_simm16 = value; 1087 break; 1088 case M32R_OPERAND_SIMM8 : 1089 fields->f_simm8 = value; 1090 break; 1091 case M32R_OPERAND_SLO16 : 1092 fields->f_simm16 = value; 1093 break; 1094 case M32R_OPERAND_SR : 1095 fields->f_r2 = value; 1096 break; 1097 case M32R_OPERAND_SRC1 : 1098 fields->f_r1 = value; 1099 break; 1100 case M32R_OPERAND_SRC2 : 1101 fields->f_r2 = value; 1102 break; 1103 case M32R_OPERAND_UIMM16 : 1104 fields->f_uimm16 = value; 1105 break; 1106 case M32R_OPERAND_UIMM24 : 1107 fields->f_uimm24 = value; 1108 break; 1109 case M32R_OPERAND_UIMM3 : 1110 fields->f_uimm3 = value; 1111 break; 1112 case M32R_OPERAND_UIMM4 : 1113 fields->f_uimm4 = value; 1114 break; 1115 case M32R_OPERAND_UIMM5 : 1116 fields->f_uimm5 = value; 1117 break; 1118 case M32R_OPERAND_UIMM8 : 1119 fields->f_uimm8 = value; 1120 break; 1121 case M32R_OPERAND_ULO16 : 1122 fields->f_uimm16 = value; 1123 break; 1124 1125 default : 1126 /* xgettext:c-format */ 1127 opcodes_error_handler 1128 (_("internal error: unrecognized field %d while setting int operand"), 1129 opindex); 1130 abort (); 1131 } 1132 } 1133 1134 void 1135 m32r_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1136 int opindex, 1137 CGEN_FIELDS * fields, 1138 bfd_vma value) 1139 { 1140 switch (opindex) 1141 { 1142 case M32R_OPERAND_ACC : 1143 fields->f_acc = value; 1144 break; 1145 case M32R_OPERAND_ACCD : 1146 fields->f_accd = value; 1147 break; 1148 case M32R_OPERAND_ACCS : 1149 fields->f_accs = value; 1150 break; 1151 case M32R_OPERAND_DCR : 1152 fields->f_r1 = value; 1153 break; 1154 case M32R_OPERAND_DISP16 : 1155 fields->f_disp16 = value; 1156 break; 1157 case M32R_OPERAND_DISP24 : 1158 fields->f_disp24 = value; 1159 break; 1160 case M32R_OPERAND_DISP8 : 1161 fields->f_disp8 = value; 1162 break; 1163 case M32R_OPERAND_DR : 1164 fields->f_r1 = value; 1165 break; 1166 case M32R_OPERAND_HASH : 1167 break; 1168 case M32R_OPERAND_HI16 : 1169 fields->f_hi16 = value; 1170 break; 1171 case M32R_OPERAND_IMM1 : 1172 fields->f_imm1 = value; 1173 break; 1174 case M32R_OPERAND_SCR : 1175 fields->f_r2 = value; 1176 break; 1177 case M32R_OPERAND_SIMM16 : 1178 fields->f_simm16 = value; 1179 break; 1180 case M32R_OPERAND_SIMM8 : 1181 fields->f_simm8 = value; 1182 break; 1183 case M32R_OPERAND_SLO16 : 1184 fields->f_simm16 = value; 1185 break; 1186 case M32R_OPERAND_SR : 1187 fields->f_r2 = value; 1188 break; 1189 case M32R_OPERAND_SRC1 : 1190 fields->f_r1 = value; 1191 break; 1192 case M32R_OPERAND_SRC2 : 1193 fields->f_r2 = value; 1194 break; 1195 case M32R_OPERAND_UIMM16 : 1196 fields->f_uimm16 = value; 1197 break; 1198 case M32R_OPERAND_UIMM24 : 1199 fields->f_uimm24 = value; 1200 break; 1201 case M32R_OPERAND_UIMM3 : 1202 fields->f_uimm3 = value; 1203 break; 1204 case M32R_OPERAND_UIMM4 : 1205 fields->f_uimm4 = value; 1206 break; 1207 case M32R_OPERAND_UIMM5 : 1208 fields->f_uimm5 = value; 1209 break; 1210 case M32R_OPERAND_UIMM8 : 1211 fields->f_uimm8 = value; 1212 break; 1213 case M32R_OPERAND_ULO16 : 1214 fields->f_uimm16 = value; 1215 break; 1216 1217 default : 1218 /* xgettext:c-format */ 1219 opcodes_error_handler 1220 (_("internal error: unrecognized field %d while setting vma operand"), 1221 opindex); 1222 abort (); 1223 } 1224 } 1225 1226 /* Function to call before using the instruction builder tables. */ 1227 1228 void 1229 m32r_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1230 { 1231 cd->insert_handlers = & m32r_cgen_insert_handlers[0]; 1232 cd->extract_handlers = & m32r_cgen_extract_handlers[0]; 1233 1234 cd->insert_operand = m32r_cgen_insert_operand; 1235 cd->extract_operand = m32r_cgen_extract_operand; 1236 1237 cd->get_int_operand = m32r_cgen_get_int_operand; 1238 cd->set_int_operand = m32r_cgen_set_int_operand; 1239 cd->get_vma_operand = m32r_cgen_get_vma_operand; 1240 cd->set_vma_operand = m32r_cgen_set_vma_operand; 1241 } 1242
Indexes created Sat Feb 28 05:31:39 UTC 2026