1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* Instruction building/extraction support for or1k. -*- C -*- 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator. 5 - the resultant file is machine generated, cgen-ibld.in isn't 6 7 Copyright (C) 1996-2025 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "or1k-desc.h" 35 #include "or1k-opc.h" 36 #include "cgen/basic-modes.h" 37 #include "opintl.h" 38 #include "safe-ctype.h" 39 40 #undef min 41 #define min(a,b) ((a) < (b) ? (a) : (b)) 42 #undef max 43 #define max(a,b) ((a) > (b) ? (a) : (b)) 44 45 /* Used by the ifield rtx function. */ 46 #define FLD(f) (fields->f) 47 48 static const char * insert_normal 49 (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, 50 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); 51 static const char * insert_insn_normal 52 (CGEN_CPU_DESC, const CGEN_INSN *, 53 CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 54 static int extract_normal 55 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 56 unsigned int, unsigned int, unsigned int, unsigned int, 57 unsigned int, unsigned int, bfd_vma, long *); 58 static int extract_insn_normal 59 (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, 60 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 61 #if CGEN_INT_INSN_P 62 static void put_insn_int_value 63 (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); 64 #endif 65 #if ! CGEN_INT_INSN_P 66 static CGEN_INLINE void insert_1 67 (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); 68 static CGEN_INLINE int fill_cache 69 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); 70 static CGEN_INLINE long extract_1 71 (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); 72 #endif 73 74 /* Operand insertion. */ 76 77 #if ! CGEN_INT_INSN_P 78 79 /* Subroutine of insert_normal. */ 80 81 static CGEN_INLINE void 82 insert_1 (CGEN_CPU_DESC cd, 83 unsigned long value, 84 int start, 85 int length, 86 int word_length, 87 unsigned char *bufp) 88 { 89 unsigned long x, mask; 90 int shift; 91 92 x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); 93 94 /* Written this way to avoid undefined behaviour. */ 95 mask = (1UL << (length - 1) << 1) - 1; 96 if (CGEN_INSN_LSB0_P) 97 shift = (start + 1) - length; 98 else 99 shift = (word_length - (start + length)); 100 x = (x & ~(mask << shift)) | ((value & mask) << shift); 101 102 cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); 103 } 104 105 #endif /* ! CGEN_INT_INSN_P */ 106 107 /* Default insertion routine. 108 109 ATTRS is a mask of the boolean attributes. 110 WORD_OFFSET is the offset in bits from the start of the insn of the value. 111 WORD_LENGTH is the length of the word in bits in which the value resides. 112 START is the starting bit number in the word, architecture origin. 113 LENGTH is the length of VALUE in bits. 114 TOTAL_LENGTH is the total length of the insn in bits. 115 116 The result is an error message or NULL if success. */ 117 118 /* ??? This duplicates functionality with bfd's howto table and 119 bfd_install_relocation. */ 120 /* ??? This doesn't handle bfd_vma's. Create another function when 121 necessary. */ 122 123 static const char * 124 insert_normal (CGEN_CPU_DESC cd, 125 long value, 126 unsigned int attrs, 127 unsigned int word_offset, 128 unsigned int start, 129 unsigned int length, 130 unsigned int word_length, 131 unsigned int total_length, 132 CGEN_INSN_BYTES_PTR buffer) 133 { 134 static char errbuf[100]; 135 unsigned long mask; 136 137 /* If LENGTH is zero, this operand doesn't contribute to the value. */ 138 if (length == 0) 139 return NULL; 140 141 /* Written this way to avoid undefined behaviour. */ 142 mask = (1UL << (length - 1) << 1) - 1; 143 144 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 145 abort (); 146 147 /* For architectures with insns smaller than the base-insn-bitsize, 148 word_length may be too big. */ 149 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 150 { 151 if (word_offset == 0 152 && word_length > total_length) 153 word_length = total_length; 154 } 155 156 /* Ensure VALUE will fit. */ 157 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) 158 { 159 long minval = - (1UL << (length - 1)); 160 unsigned long maxval = mask; 161 162 if ((value > 0 && (unsigned long) value > maxval) 163 || value < minval) 164 { 165 /* xgettext:c-format */ 166 sprintf (errbuf, 167 _("operand out of range (%ld not between %ld and %lu)"), 168 value, minval, maxval); 169 return errbuf; 170 } 171 } 172 else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) 173 { 174 unsigned long maxval = mask; 175 unsigned long val = (unsigned long) value; 176 177 /* For hosts with a word size > 32 check to see if value has been sign 178 extended beyond 32 bits. If so then ignore these higher sign bits 179 as the user is attempting to store a 32-bit signed value into an 180 unsigned 32-bit field which is allowed. */ 181 if (sizeof (unsigned long) > 4 && ((value >> 32) == -1)) 182 val &= 0xFFFFFFFF; 183 184 if (val > maxval) 185 { 186 /* xgettext:c-format */ 187 sprintf (errbuf, 188 _("operand out of range (0x%lx not between 0 and 0x%lx)"), 189 val, maxval); 190 return errbuf; 191 } 192 } 193 else 194 { 195 if (! cgen_signed_overflow_ok_p (cd)) 196 { 197 long minval = - (1UL << (length - 1)); 198 long maxval = (1UL << (length - 1)) - 1; 199 200 if (value < minval || value > maxval) 201 { 202 sprintf 203 /* xgettext:c-format */ 204 (errbuf, _("operand out of range (%ld not between %ld and %ld)"), 205 value, minval, maxval); 206 return errbuf; 207 } 208 } 209 } 210 211 #if CGEN_INT_INSN_P 212 213 { 214 int shift_within_word, shift_to_word, shift; 215 216 /* How to shift the value to BIT0 of the word. */ 217 shift_to_word = total_length - (word_offset + word_length); 218 219 /* How to shift the value to the field within the word. */ 220 if (CGEN_INSN_LSB0_P) 221 shift_within_word = start + 1 - length; 222 else 223 shift_within_word = word_length - start - length; 224 225 /* The total SHIFT, then mask in the value. */ 226 shift = shift_to_word + shift_within_word; 227 *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift); 228 } 229 230 #else /* ! CGEN_INT_INSN_P */ 231 232 { 233 unsigned char *bufp = (unsigned char *) buffer + word_offset / 8; 234 235 insert_1 (cd, value, start, length, word_length, bufp); 236 } 237 238 #endif /* ! CGEN_INT_INSN_P */ 239 240 return NULL; 241 } 242 243 /* Default insn builder (insert handler). 244 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning 245 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is 246 recorded in host byte order, otherwise BUFFER is an array of bytes 247 and the value is recorded in target byte order). 248 The result is an error message or NULL if success. */ 249 250 static const char * 251 insert_insn_normal (CGEN_CPU_DESC cd, 252 const CGEN_INSN * insn, 253 CGEN_FIELDS * fields, 254 CGEN_INSN_BYTES_PTR buffer, 255 bfd_vma pc) 256 { 257 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 258 unsigned long value; 259 const CGEN_SYNTAX_CHAR_TYPE * syn; 260 261 CGEN_INIT_INSERT (cd); 262 value = CGEN_INSN_BASE_VALUE (insn); 263 264 /* If we're recording insns as numbers (rather than a string of bytes), 265 target byte order handling is deferred until later. */ 266 267 #if CGEN_INT_INSN_P 268 269 put_insn_int_value (cd, buffer, cd->base_insn_bitsize, 270 CGEN_FIELDS_BITSIZE (fields), value); 271 272 #else 273 274 cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, 275 (unsigned) CGEN_FIELDS_BITSIZE (fields)), 276 value, cd->insn_endian); 277 278 #endif /* ! CGEN_INT_INSN_P */ 279 280 /* ??? It would be better to scan the format's fields. 281 Still need to be able to insert a value based on the operand though; 282 e.g. storing a branch displacement that got resolved later. 283 Needs more thought first. */ 284 285 for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn) 286 { 287 const char *errmsg; 288 289 if (CGEN_SYNTAX_CHAR_P (* syn)) 290 continue; 291 292 errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 293 fields, buffer, pc); 294 if (errmsg) 295 return errmsg; 296 } 297 298 return NULL; 299 } 300 301 #if CGEN_INT_INSN_P 302 /* Cover function to store an insn value into an integral insn. Must go here 303 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ 304 305 static void 306 put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 307 CGEN_INSN_BYTES_PTR buf, 308 int length, 309 int insn_length, 310 CGEN_INSN_INT value) 311 { 312 /* For architectures with insns smaller than the base-insn-bitsize, 313 length may be too big. */ 314 if (length > insn_length) 315 *buf = value; 316 else 317 { 318 int shift = insn_length - length; 319 /* Written this way to avoid undefined behaviour. */ 320 CGEN_INSN_INT mask = length == 0 ? 0 : (1UL << (length - 1) << 1) - 1; 321 322 *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); 323 } 324 } 325 #endif 326 327 /* Operand extraction. */ 329 330 #if ! CGEN_INT_INSN_P 331 332 /* Subroutine of extract_normal. 333 Ensure sufficient bytes are cached in EX_INFO. 334 OFFSET is the offset in bytes from the start of the insn of the value. 335 BYTES is the length of the needed value. 336 Returns 1 for success, 0 for failure. */ 337 338 static CGEN_INLINE int 339 fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 340 CGEN_EXTRACT_INFO *ex_info, 341 int offset, 342 int bytes, 343 bfd_vma pc) 344 { 345 /* It's doubtful that the middle part has already been fetched so 346 we don't optimize that case. kiss. */ 347 unsigned int mask; 348 disassemble_info *info = (disassemble_info *) ex_info->dis_info; 349 350 /* First do a quick check. */ 351 mask = (1 << bytes) - 1; 352 if (((ex_info->valid >> offset) & mask) == mask) 353 return 1; 354 355 /* Search for the first byte we need to read. */ 356 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1) 357 if (! (mask & ex_info->valid)) 358 break; 359 360 if (bytes) 361 { 362 int status; 363 364 pc += offset; 365 status = (*info->read_memory_func) 366 (pc, ex_info->insn_bytes + offset, bytes, info); 367 368 if (status != 0) 369 { 370 (*info->memory_error_func) (status, pc, info); 371 return 0; 372 } 373 374 ex_info->valid |= ((1 << bytes) - 1) << offset; 375 } 376 377 return 1; 378 } 379 380 /* Subroutine of extract_normal. */ 381 382 static CGEN_INLINE long 383 extract_1 (CGEN_CPU_DESC cd, 384 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 385 int start, 386 int length, 387 int word_length, 388 unsigned char *bufp, 389 bfd_vma pc ATTRIBUTE_UNUSED) 390 { 391 unsigned long x; 392 int shift; 393 394 x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); 395 396 if (CGEN_INSN_LSB0_P) 397 shift = (start + 1) - length; 398 else 399 shift = (word_length - (start + length)); 400 return x >> shift; 401 } 402 403 #endif /* ! CGEN_INT_INSN_P */ 404 405 /* Default extraction routine. 406 407 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order, 408 or sometimes less for cases like the m32r where the base insn size is 32 409 but some insns are 16 bits. 410 ATTRS is a mask of the boolean attributes. We only need `SIGNED', 411 but for generality we take a bitmask of all of them. 412 WORD_OFFSET is the offset in bits from the start of the insn of the value. 413 WORD_LENGTH is the length of the word in bits in which the value resides. 414 START is the starting bit number in the word, architecture origin. 415 LENGTH is the length of VALUE in bits. 416 TOTAL_LENGTH is the total length of the insn in bits. 417 418 Returns 1 for success, 0 for failure. */ 419 420 /* ??? The return code isn't properly used. wip. */ 421 422 /* ??? This doesn't handle bfd_vma's. Create another function when 423 necessary. */ 424 425 static int 426 extract_normal (CGEN_CPU_DESC cd, 427 #if ! CGEN_INT_INSN_P 428 CGEN_EXTRACT_INFO *ex_info, 429 #else 430 CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, 431 #endif 432 CGEN_INSN_INT insn_value, 433 unsigned int attrs, 434 unsigned int word_offset, 435 unsigned int start, 436 unsigned int length, 437 unsigned int word_length, 438 unsigned int total_length, 439 #if ! CGEN_INT_INSN_P 440 bfd_vma pc, 441 #else 442 bfd_vma pc ATTRIBUTE_UNUSED, 443 #endif 444 long *valuep) 445 { 446 long value, mask; 447 448 /* If LENGTH is zero, this operand doesn't contribute to the value 449 so give it a standard value of zero. */ 450 if (length == 0) 451 { 452 *valuep = 0; 453 return 1; 454 } 455 456 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 457 abort (); 458 459 /* For architectures with insns smaller than the insn-base-bitsize, 460 word_length may be too big. */ 461 if (cd->min_insn_bitsize < cd->base_insn_bitsize) 462 { 463 if (word_offset + word_length > total_length) 464 word_length = total_length - word_offset; 465 } 466 467 /* Does the value reside in INSN_VALUE, and at the right alignment? */ 468 469 if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) 470 { 471 if (CGEN_INSN_LSB0_P) 472 value = insn_value >> ((word_offset + start + 1) - length); 473 else 474 value = insn_value >> (total_length - ( word_offset + start + length)); 475 } 476 477 #if ! CGEN_INT_INSN_P 478 479 else 480 { 481 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8; 482 483 if (word_length > 8 * sizeof (CGEN_INSN_INT)) 484 abort (); 485 486 if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0) 487 { 488 *valuep = 0; 489 return 0; 490 } 491 492 value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc); 493 } 494 495 #endif /* ! CGEN_INT_INSN_P */ 496 497 /* Written this way to avoid undefined behaviour. */ 498 mask = (1UL << (length - 1) << 1) - 1; 499 500 value &= mask; 501 /* sign extend? */ 502 if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED) 503 && (value & (1UL << (length - 1)))) 504 value |= ~mask; 505 506 *valuep = value; 507 508 return 1; 509 } 510 511 /* Default insn extractor. 512 513 INSN_VALUE is the first base_insn_bitsize bits, translated to host order. 514 The extracted fields are stored in FIELDS. 515 EX_INFO is used to handle reading variable length insns. 516 Return the length of the insn in bits, or 0 if no match, 517 or -1 if an error occurs fetching data (memory_error_func will have 518 been called). */ 519 520 static int 521 extract_insn_normal (CGEN_CPU_DESC cd, 522 const CGEN_INSN *insn, 523 CGEN_EXTRACT_INFO *ex_info, 524 CGEN_INSN_INT insn_value, 525 CGEN_FIELDS *fields, 526 bfd_vma pc) 527 { 528 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 529 const CGEN_SYNTAX_CHAR_TYPE *syn; 530 531 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); 532 533 CGEN_INIT_EXTRACT (cd); 534 535 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 536 { 537 int length; 538 539 if (CGEN_SYNTAX_CHAR_P (*syn)) 540 continue; 541 542 length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn), 543 ex_info, insn_value, fields, pc); 544 if (length <= 0) 545 return length; 546 } 547 548 /* We recognized and successfully extracted this insn. */ 549 return CGEN_INSN_BITSIZE (insn); 550 } 551 552 /* Machine generated code added here. */ 554 555 const char * or1k_cgen_insert_operand 556 (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); 557 558 /* Main entry point for operand insertion. 559 560 This function is basically just a big switch statement. Earlier versions 561 used tables to look up the function to use, but 562 - if the table contains both assembler and disassembler functions then 563 the disassembler contains much of the assembler and vice-versa, 564 - there's a lot of inlining possibilities as things grow, 565 - using a switch statement avoids the function call overhead. 566 567 This function could be moved into `parse_insn_normal', but keeping it 568 separate makes clear the interface between `parse_insn_normal' and each of 569 the handlers. It's also needed by GAS to insert operands that couldn't be 570 resolved during parsing. */ 571 572 const char * 573 or1k_cgen_insert_operand (CGEN_CPU_DESC cd, 574 int opindex, 575 CGEN_FIELDS * fields, 576 CGEN_INSN_BYTES_PTR buffer, 577 bfd_vma pc ATTRIBUTE_UNUSED) 578 { 579 const char * errmsg = NULL; 580 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 581 582 switch (opindex) 583 { 584 case OR1K_OPERAND_DISP21 : 585 { 586 long value = fields->f_disp21; 587 value = ((((SI) (value) >> (13))) - (((SI) (pc) >> (13)))); 588 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, buffer); 589 } 590 break; 591 case OR1K_OPERAND_DISP26 : 592 { 593 long value = fields->f_disp26; 594 value = ((SI) (((value) - (pc))) >> (2)); 595 errmsg = insert_normal (cd, value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, buffer); 596 } 597 break; 598 case OR1K_OPERAND_RA : 599 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 600 break; 601 case OR1K_OPERAND_RAD32F : 602 { 603 { 604 FLD (f_r2) = ((FLD (f_rad32)) & (31)); 605 FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1)); 606 } 607 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 608 if (errmsg) 609 break; 610 errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer); 611 if (errmsg) 612 break; 613 } 614 break; 615 case OR1K_OPERAND_RADI : 616 { 617 { 618 FLD (f_r2) = ((FLD (f_rad32)) & (31)); 619 FLD (f_raoff_9_1) = ((((SI) (FLD (f_rad32)) >> (5))) & (1)); 620 } 621 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 622 if (errmsg) 623 break; 624 errmsg = insert_normal (cd, fields->f_raoff_9_1, 0, 0, 9, 1, 32, total_length, buffer); 625 if (errmsg) 626 break; 627 } 628 break; 629 case OR1K_OPERAND_RASF : 630 errmsg = insert_normal (cd, fields->f_r2, 0, 0, 20, 5, 32, total_length, buffer); 631 break; 632 case OR1K_OPERAND_RB : 633 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 634 break; 635 case OR1K_OPERAND_RBD32F : 636 { 637 { 638 FLD (f_r3) = ((FLD (f_rbd32)) & (31)); 639 FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1)); 640 } 641 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 642 if (errmsg) 643 break; 644 errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer); 645 if (errmsg) 646 break; 647 } 648 break; 649 case OR1K_OPERAND_RBDI : 650 { 651 { 652 FLD (f_r3) = ((FLD (f_rbd32)) & (31)); 653 FLD (f_rboff_8_1) = ((((SI) (FLD (f_rbd32)) >> (5))) & (1)); 654 } 655 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 656 if (errmsg) 657 break; 658 errmsg = insert_normal (cd, fields->f_rboff_8_1, 0, 0, 8, 1, 32, total_length, buffer); 659 if (errmsg) 660 break; 661 } 662 break; 663 case OR1K_OPERAND_RBSF : 664 errmsg = insert_normal (cd, fields->f_r3, 0, 0, 15, 5, 32, total_length, buffer); 665 break; 666 case OR1K_OPERAND_RD : 667 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 668 break; 669 case OR1K_OPERAND_RDD32F : 670 { 671 { 672 FLD (f_r1) = ((FLD (f_rdd32)) & (31)); 673 FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1)); 674 } 675 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 676 if (errmsg) 677 break; 678 errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer); 679 if (errmsg) 680 break; 681 } 682 break; 683 case OR1K_OPERAND_RDDI : 684 { 685 { 686 FLD (f_r1) = ((FLD (f_rdd32)) & (31)); 687 FLD (f_rdoff_10_1) = ((((SI) (FLD (f_rdd32)) >> (5))) & (1)); 688 } 689 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 690 if (errmsg) 691 break; 692 errmsg = insert_normal (cd, fields->f_rdoff_10_1, 0, 0, 10, 1, 32, total_length, buffer); 693 if (errmsg) 694 break; 695 } 696 break; 697 case OR1K_OPERAND_RDSF : 698 errmsg = insert_normal (cd, fields->f_r1, 0, 0, 25, 5, 32, total_length, buffer); 699 break; 700 case OR1K_OPERAND_SIMM16 : 701 errmsg = insert_normal (cd, fields->f_simm16, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, buffer); 702 break; 703 case OR1K_OPERAND_SIMM16_SPLIT : 704 { 705 { 706 FLD (f_imm16_25_5) = ((((INT) (FLD (f_simm16_split)) >> (11))) & (31)); 707 FLD (f_imm16_10_11) = ((FLD (f_simm16_split)) & (2047)); 708 } 709 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 710 if (errmsg) 711 break; 712 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 713 if (errmsg) 714 break; 715 } 716 break; 717 case OR1K_OPERAND_UIMM16 : 718 errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 15, 16, 32, total_length, buffer); 719 break; 720 case OR1K_OPERAND_UIMM16_SPLIT : 721 { 722 { 723 FLD (f_imm16_25_5) = ((((UINT) (FLD (f_uimm16_split)) >> (11))) & (31)); 724 FLD (f_imm16_10_11) = ((FLD (f_uimm16_split)) & (2047)); 725 } 726 errmsg = insert_normal (cd, fields->f_imm16_25_5, 0, 0, 25, 5, 32, total_length, buffer); 727 if (errmsg) 728 break; 729 errmsg = insert_normal (cd, fields->f_imm16_10_11, 0, 0, 10, 11, 32, total_length, buffer); 730 if (errmsg) 731 break; 732 } 733 break; 734 case OR1K_OPERAND_UIMM6 : 735 errmsg = insert_normal (cd, fields->f_uimm6, 0, 0, 5, 6, 32, total_length, buffer); 736 break; 737 738 default : 739 /* xgettext:c-format */ 740 opcodes_error_handler 741 (_("internal error: unrecognized field %d while building insn"), 742 opindex); 743 abort (); 744 } 745 746 return errmsg; 747 } 748 749 int or1k_cgen_extract_operand 750 (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); 751 752 /* Main entry point for operand extraction. 753 The result is <= 0 for error, >0 for success. 754 ??? Actual values aren't well defined right now. 755 756 This function is basically just a big switch statement. Earlier versions 757 used tables to look up the function to use, but 758 - if the table contains both assembler and disassembler functions then 759 the disassembler contains much of the assembler and vice-versa, 760 - there's a lot of inlining possibilities as things grow, 761 - using a switch statement avoids the function call overhead. 762 763 This function could be moved into `print_insn_normal', but keeping it 764 separate makes clear the interface between `print_insn_normal' and each of 765 the handlers. */ 766 767 int 768 or1k_cgen_extract_operand (CGEN_CPU_DESC cd, 769 int opindex, 770 CGEN_EXTRACT_INFO *ex_info, 771 CGEN_INSN_INT insn_value, 772 CGEN_FIELDS * fields, 773 bfd_vma pc) 774 { 775 /* Assume success (for those operands that are nops). */ 776 int length = 1; 777 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields); 778 779 switch (opindex) 780 { 781 case OR1K_OPERAND_DISP21 : 782 { 783 long value; 784 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_ABS_ADDR), 0, 20, 21, 32, total_length, pc, & value); 785 value = ((((value) + (((SI) (pc) >> (13))))) * (8192)); 786 fields->f_disp21 = value; 787 } 788 break; 789 case OR1K_OPERAND_DISP26 : 790 { 791 long value; 792 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 25, 26, 32, total_length, pc, & value); 793 value = ((((value) * (4))) + (pc)); 794 fields->f_disp26 = value; 795 } 796 break; 797 case OR1K_OPERAND_RA : 798 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 799 break; 800 case OR1K_OPERAND_RAD32F : 801 { 802 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 803 if (length <= 0) break; 804 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1); 805 if (length <= 0) break; 806 FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); 807 } 808 break; 809 case OR1K_OPERAND_RADI : 810 { 811 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 812 if (length <= 0) break; 813 length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_raoff_9_1); 814 if (length <= 0) break; 815 FLD (f_rad32) = ((FLD (f_r2)) | (((FLD (f_raoff_9_1)) << (5)))); 816 } 817 break; 818 case OR1K_OPERAND_RASF : 819 length = extract_normal (cd, ex_info, insn_value, 0, 0, 20, 5, 32, total_length, pc, & fields->f_r2); 820 break; 821 case OR1K_OPERAND_RB : 822 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 823 break; 824 case OR1K_OPERAND_RBD32F : 825 { 826 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 827 if (length <= 0) break; 828 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1); 829 if (length <= 0) break; 830 FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); 831 } 832 break; 833 case OR1K_OPERAND_RBDI : 834 { 835 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 836 if (length <= 0) break; 837 length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_rboff_8_1); 838 if (length <= 0) break; 839 FLD (f_rbd32) = ((FLD (f_r3)) | (((FLD (f_rboff_8_1)) << (5)))); 840 } 841 break; 842 case OR1K_OPERAND_RBSF : 843 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_r3); 844 break; 845 case OR1K_OPERAND_RD : 846 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 847 break; 848 case OR1K_OPERAND_RDD32F : 849 { 850 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 851 if (length <= 0) break; 852 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1); 853 if (length <= 0) break; 854 FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); 855 } 856 break; 857 case OR1K_OPERAND_RDDI : 858 { 859 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 860 if (length <= 0) break; 861 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 1, 32, total_length, pc, & fields->f_rdoff_10_1); 862 if (length <= 0) break; 863 FLD (f_rdd32) = ((FLD (f_r1)) | (((FLD (f_rdoff_10_1)) << (5)))); 864 } 865 break; 866 case OR1K_OPERAND_RDSF : 867 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_r1); 868 break; 869 case OR1K_OPERAND_SIMM16 : 870 length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_SIGN_OPT), 0, 15, 16, 32, total_length, pc, & fields->f_simm16); 871 break; 872 case OR1K_OPERAND_SIMM16_SPLIT : 873 { 874 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 875 if (length <= 0) break; 876 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 877 if (length <= 0) break; 878 FLD (f_simm16_split) = ((HI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 879 } 880 break; 881 case OR1K_OPERAND_UIMM16 : 882 length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 16, 32, total_length, pc, & fields->f_uimm16); 883 break; 884 case OR1K_OPERAND_UIMM16_SPLIT : 885 { 886 length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 5, 32, total_length, pc, & fields->f_imm16_25_5); 887 if (length <= 0) break; 888 length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 11, 32, total_length, pc, & fields->f_imm16_10_11); 889 if (length <= 0) break; 890 FLD (f_uimm16_split) = ((UHI) (UINT) (((((FLD (f_imm16_25_5)) << (11))) | (FLD (f_imm16_10_11))))); 891 } 892 break; 893 case OR1K_OPERAND_UIMM6 : 894 length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_uimm6); 895 break; 896 897 default : 898 /* xgettext:c-format */ 899 opcodes_error_handler 900 (_("internal error: unrecognized field %d while decoding insn"), 901 opindex); 902 abort (); 903 } 904 905 return length; 906 } 907 908 cgen_insert_fn * const or1k_cgen_insert_handlers[] = 909 { 910 insert_insn_normal, 911 }; 912 913 cgen_extract_fn * const or1k_cgen_extract_handlers[] = 914 { 915 extract_insn_normal, 916 }; 917 918 int or1k_cgen_get_int_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 919 bfd_vma or1k_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *); 920 921 /* Getting values from cgen_fields is handled by a collection of functions. 922 They are distinguished by the type of the VALUE argument they return. 923 TODO: floating point, inlining support, remove cases where result type 924 not appropriate. */ 925 926 int 927 or1k_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 928 int opindex, 929 const CGEN_FIELDS * fields) 930 { 931 int value; 932 933 switch (opindex) 934 { 935 case OR1K_OPERAND_DISP21 : 936 value = fields->f_disp21; 937 break; 938 case OR1K_OPERAND_DISP26 : 939 value = fields->f_disp26; 940 break; 941 case OR1K_OPERAND_RA : 942 value = fields->f_r2; 943 break; 944 case OR1K_OPERAND_RAD32F : 945 value = fields->f_rad32; 946 break; 947 case OR1K_OPERAND_RADI : 948 value = fields->f_rad32; 949 break; 950 case OR1K_OPERAND_RASF : 951 value = fields->f_r2; 952 break; 953 case OR1K_OPERAND_RB : 954 value = fields->f_r3; 955 break; 956 case OR1K_OPERAND_RBD32F : 957 value = fields->f_rbd32; 958 break; 959 case OR1K_OPERAND_RBDI : 960 value = fields->f_rbd32; 961 break; 962 case OR1K_OPERAND_RBSF : 963 value = fields->f_r3; 964 break; 965 case OR1K_OPERAND_RD : 966 value = fields->f_r1; 967 break; 968 case OR1K_OPERAND_RDD32F : 969 value = fields->f_rdd32; 970 break; 971 case OR1K_OPERAND_RDDI : 972 value = fields->f_rdd32; 973 break; 974 case OR1K_OPERAND_RDSF : 975 value = fields->f_r1; 976 break; 977 case OR1K_OPERAND_SIMM16 : 978 value = fields->f_simm16; 979 break; 980 case OR1K_OPERAND_SIMM16_SPLIT : 981 value = fields->f_simm16_split; 982 break; 983 case OR1K_OPERAND_UIMM16 : 984 value = fields->f_uimm16; 985 break; 986 case OR1K_OPERAND_UIMM16_SPLIT : 987 value = fields->f_uimm16_split; 988 break; 989 case OR1K_OPERAND_UIMM6 : 990 value = fields->f_uimm6; 991 break; 992 993 default : 994 /* xgettext:c-format */ 995 opcodes_error_handler 996 (_("internal error: unrecognized field %d while getting int operand"), 997 opindex); 998 abort (); 999 } 1000 1001 return value; 1002 } 1003 1004 bfd_vma 1005 or1k_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1006 int opindex, 1007 const CGEN_FIELDS * fields) 1008 { 1009 bfd_vma value; 1010 1011 switch (opindex) 1012 { 1013 case OR1K_OPERAND_DISP21 : 1014 value = fields->f_disp21; 1015 break; 1016 case OR1K_OPERAND_DISP26 : 1017 value = fields->f_disp26; 1018 break; 1019 case OR1K_OPERAND_RA : 1020 value = fields->f_r2; 1021 break; 1022 case OR1K_OPERAND_RAD32F : 1023 value = fields->f_rad32; 1024 break; 1025 case OR1K_OPERAND_RADI : 1026 value = fields->f_rad32; 1027 break; 1028 case OR1K_OPERAND_RASF : 1029 value = fields->f_r2; 1030 break; 1031 case OR1K_OPERAND_RB : 1032 value = fields->f_r3; 1033 break; 1034 case OR1K_OPERAND_RBD32F : 1035 value = fields->f_rbd32; 1036 break; 1037 case OR1K_OPERAND_RBDI : 1038 value = fields->f_rbd32; 1039 break; 1040 case OR1K_OPERAND_RBSF : 1041 value = fields->f_r3; 1042 break; 1043 case OR1K_OPERAND_RD : 1044 value = fields->f_r1; 1045 break; 1046 case OR1K_OPERAND_RDD32F : 1047 value = fields->f_rdd32; 1048 break; 1049 case OR1K_OPERAND_RDDI : 1050 value = fields->f_rdd32; 1051 break; 1052 case OR1K_OPERAND_RDSF : 1053 value = fields->f_r1; 1054 break; 1055 case OR1K_OPERAND_SIMM16 : 1056 value = fields->f_simm16; 1057 break; 1058 case OR1K_OPERAND_SIMM16_SPLIT : 1059 value = fields->f_simm16_split; 1060 break; 1061 case OR1K_OPERAND_UIMM16 : 1062 value = fields->f_uimm16; 1063 break; 1064 case OR1K_OPERAND_UIMM16_SPLIT : 1065 value = fields->f_uimm16_split; 1066 break; 1067 case OR1K_OPERAND_UIMM6 : 1068 value = fields->f_uimm6; 1069 break; 1070 1071 default : 1072 /* xgettext:c-format */ 1073 opcodes_error_handler 1074 (_("internal error: unrecognized field %d while getting vma operand"), 1075 opindex); 1076 abort (); 1077 } 1078 1079 return value; 1080 } 1081 1082 void or1k_cgen_set_int_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, int); 1083 void or1k_cgen_set_vma_operand (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma); 1084 1085 /* Stuffing values in cgen_fields is handled by a collection of functions. 1086 They are distinguished by the type of the VALUE argument they accept. 1087 TODO: floating point, inlining support, remove cases where argument type 1088 not appropriate. */ 1089 1090 void 1091 or1k_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1092 int opindex, 1093 CGEN_FIELDS * fields, 1094 int value) 1095 { 1096 switch (opindex) 1097 { 1098 case OR1K_OPERAND_DISP21 : 1099 fields->f_disp21 = value; 1100 break; 1101 case OR1K_OPERAND_DISP26 : 1102 fields->f_disp26 = value; 1103 break; 1104 case OR1K_OPERAND_RA : 1105 fields->f_r2 = value; 1106 break; 1107 case OR1K_OPERAND_RAD32F : 1108 fields->f_rad32 = value; 1109 break; 1110 case OR1K_OPERAND_RADI : 1111 fields->f_rad32 = value; 1112 break; 1113 case OR1K_OPERAND_RASF : 1114 fields->f_r2 = value; 1115 break; 1116 case OR1K_OPERAND_RB : 1117 fields->f_r3 = value; 1118 break; 1119 case OR1K_OPERAND_RBD32F : 1120 fields->f_rbd32 = value; 1121 break; 1122 case OR1K_OPERAND_RBDI : 1123 fields->f_rbd32 = value; 1124 break; 1125 case OR1K_OPERAND_RBSF : 1126 fields->f_r3 = value; 1127 break; 1128 case OR1K_OPERAND_RD : 1129 fields->f_r1 = value; 1130 break; 1131 case OR1K_OPERAND_RDD32F : 1132 fields->f_rdd32 = value; 1133 break; 1134 case OR1K_OPERAND_RDDI : 1135 fields->f_rdd32 = value; 1136 break; 1137 case OR1K_OPERAND_RDSF : 1138 fields->f_r1 = value; 1139 break; 1140 case OR1K_OPERAND_SIMM16 : 1141 fields->f_simm16 = value; 1142 break; 1143 case OR1K_OPERAND_SIMM16_SPLIT : 1144 fields->f_simm16_split = value; 1145 break; 1146 case OR1K_OPERAND_UIMM16 : 1147 fields->f_uimm16 = value; 1148 break; 1149 case OR1K_OPERAND_UIMM16_SPLIT : 1150 fields->f_uimm16_split = value; 1151 break; 1152 case OR1K_OPERAND_UIMM6 : 1153 fields->f_uimm6 = value; 1154 break; 1155 1156 default : 1157 /* xgettext:c-format */ 1158 opcodes_error_handler 1159 (_("internal error: unrecognized field %d while setting int operand"), 1160 opindex); 1161 abort (); 1162 } 1163 } 1164 1165 void 1166 or1k_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1167 int opindex, 1168 CGEN_FIELDS * fields, 1169 bfd_vma value) 1170 { 1171 switch (opindex) 1172 { 1173 case OR1K_OPERAND_DISP21 : 1174 fields->f_disp21 = value; 1175 break; 1176 case OR1K_OPERAND_DISP26 : 1177 fields->f_disp26 = value; 1178 break; 1179 case OR1K_OPERAND_RA : 1180 fields->f_r2 = value; 1181 break; 1182 case OR1K_OPERAND_RAD32F : 1183 fields->f_rad32 = value; 1184 break; 1185 case OR1K_OPERAND_RADI : 1186 fields->f_rad32 = value; 1187 break; 1188 case OR1K_OPERAND_RASF : 1189 fields->f_r2 = value; 1190 break; 1191 case OR1K_OPERAND_RB : 1192 fields->f_r3 = value; 1193 break; 1194 case OR1K_OPERAND_RBD32F : 1195 fields->f_rbd32 = value; 1196 break; 1197 case OR1K_OPERAND_RBDI : 1198 fields->f_rbd32 = value; 1199 break; 1200 case OR1K_OPERAND_RBSF : 1201 fields->f_r3 = value; 1202 break; 1203 case OR1K_OPERAND_RD : 1204 fields->f_r1 = value; 1205 break; 1206 case OR1K_OPERAND_RDD32F : 1207 fields->f_rdd32 = value; 1208 break; 1209 case OR1K_OPERAND_RDDI : 1210 fields->f_rdd32 = value; 1211 break; 1212 case OR1K_OPERAND_RDSF : 1213 fields->f_r1 = value; 1214 break; 1215 case OR1K_OPERAND_SIMM16 : 1216 fields->f_simm16 = value; 1217 break; 1218 case OR1K_OPERAND_SIMM16_SPLIT : 1219 fields->f_simm16_split = value; 1220 break; 1221 case OR1K_OPERAND_UIMM16 : 1222 fields->f_uimm16 = value; 1223 break; 1224 case OR1K_OPERAND_UIMM16_SPLIT : 1225 fields->f_uimm16_split = value; 1226 break; 1227 case OR1K_OPERAND_UIMM6 : 1228 fields->f_uimm6 = value; 1229 break; 1230 1231 default : 1232 /* xgettext:c-format */ 1233 opcodes_error_handler 1234 (_("internal error: unrecognized field %d while setting vma operand"), 1235 opindex); 1236 abort (); 1237 } 1238 } 1239 1240 /* Function to call before using the instruction builder tables. */ 1241 1242 void 1243 or1k_cgen_init_ibld_table (CGEN_CPU_DESC cd) 1244 { 1245 cd->insert_handlers = & or1k_cgen_insert_handlers[0]; 1246 cd->extract_handlers = & or1k_cgen_extract_handlers[0]; 1247 1248 cd->insert_operand = or1k_cgen_insert_operand; 1249 cd->extract_operand = or1k_cgen_extract_operand; 1250 1251 cd->get_int_operand = or1k_cgen_get_int_operand; 1252 cd->set_int_operand = or1k_cgen_set_int_operand; 1253 cd->get_vma_operand = or1k_cgen_get_vma_operand; 1254 cd->set_vma_operand = or1k_cgen_set_vma_operand; 1255 } 1256
Indexes created Sat Feb 28 05:31:39 UTC 2026