1 2016-12-31 Alan Modra <amodra (a] gmail.com> 2 3 * disassemble.c (disassembler): Add break accidentally removed 4 by PRU patch. 5 6 2016-12-31 Dimitar Dimitrov <dimitar (a] dinux.eu> 7 8 * Makefile.am: Add PRU source files. 9 * configure.ac: Add PRU target. 10 * disassemble.c (disassembler): Register PRU arch. 11 * pru-dis.c: New file. 12 * pru-opc.c: New file. 13 * Makefile.in: Regenerate. 14 * configure: Regenerate. 15 16 2016-12-29 Yao Qi <yao.qi (a] linaro.org> 17 18 * avr-dis.c: Include "bfd_stdint.h" 19 (avrdis_opcode): Change return type to int, add argument 20 insn. Set *INSN on success. 21 (print_insn_avr): Check return value of avrdis_opcode, and 22 return -1 on error. 23 24 2016-12-28 Alan Modra <amodra (a] gmail.com> 25 26 * configure.ac: Revert 2016-12-23. 27 * Makefile.am: Likewise. 28 (MIPS_DEFS): Define. 29 (mips-dis.lo): Add rule. 30 * Makefile.in: Regenerate. 31 * aclocal.m4: Regenerate. 32 * config.in: Regenerate. 33 * configure: Regenerate. 34 35 2016-12-23 Maciej W. Rozycki <macro (a] imgtec.com> 36 37 * mips16-opc.c (decode_mips16_operand): Add `0', `1', `2', `3', 38 `4' and `s' operand codes. 39 (mips16_opcodes): Add "asmacro" entry. 40 41 2016-12-23 Maciej W. Rozycki <macro (a] imgtec.com> 42 43 * mips-dis.c (print_mips16_insn_arg): Simplify processing of 44 extended operands. 45 * mips16-opc.c (decode_mips16_operand): Switch the extended 46 form of the `<' operand type to LSB position 22. 47 48 2016-12-23 Maciej W. Rozycki <macro (a] imgtec.com> 49 50 * mips16-opc.c (decode_mips16_operand): Replace `0' and `4' 51 operand codes with `.' and `F' respectively. 52 (mips16_opcodes): Likewise. 53 54 2016-12-23 Maciej W. Rozycki <macro (a] imgtec.com> 55 56 * mips-dis.c (print_insn_mips16): Disallow EXTEND prefix 57 matching for INSN2_SHORT_ONLY opcode table entries. 58 * mips16-opc.c (SH): New macro. 59 (mips16_opcodes): Set SH in `pinfo2' for non-extensible 60 instruction entries: "nop", "addu", "and", "break", "cmp", 61 "daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu", 62 "drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv", 63 "dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j", 64 "jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg", 65 "not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu", 66 "srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb", 67 "seh", "sew", "zeb", "zeh", "zew" and "extend". 68 69 2016-12-23 Maciej W. Rozycki <macro (a] imgtec.com> 70 71 * mips16-opc.c (decode_mips16_operand) <'6'>: Remove extended 72 encoding support. 73 74 2016-12-23 Maciej W. Rozycki <macro (a] imgtec.com> 75 76 * mips16-opc.c (mips16_opcodes): Set NODS in `pinfo' for 77 "extend". 78 79 2016-12-23 Maciej W. Rozycki <macro (a] imgtec.com> 80 81 * mips-dis.c (set_default_mips_dis_options): Use 82 HAVE_BFD_MIPS_ELF_GET_ABIFLAGS rather than BFD64 to guard the 83 call to `bfd_mips_elf_get_abiflags'. 84 * configure.ac: Check for `bfd_mips_elf_get_abiflags' in BFD. 85 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add `libbfd.la'. 86 * aclocal.m4: Regenerate. 87 * configure: Regenerate. 88 * config.in: Regenerate. 89 * Makefile.in: Regenerate. 90 91 2016-12-23 Tristan Gingold <gingold (a] adacore.com> 92 93 * configure: Regenerate. 94 95 2016-12-23 Tristan Gingold <gingold (a] adacore.com> 96 97 * po/opcodes.pot: Regenerate. 98 99 2016-12-21 Andrew Waterman <andrew (a] sifive.com> 100 101 * riscv-opc.c (riscv_opcodes): Reorder jal and call entries. 102 103 2016-12-20 Maciej W. Rozycki <macro (a] imgtec.com> 104 105 * mips-dis.c (mips_arch_choices): Use ISA_MIPS64 rather than 106 ISA_MIPS3 as the `isa' selection in the `bfd_mach_mips16' entry. 107 (print_insn_mips16): Check opcode entries for validity against 108 the ISA level and ASE set selected. 109 110 2016-12-20 Maciej W. Rozycki <macro (a] imgtec.com> 111 112 * mips-dis.c (print_mips16_insn_arg): Always handle `extend' and 113 `insn' together, with `extend' as the high-order 16 bits. 114 (match_kind): New enum. 115 (print_insn_mips16): Rework for 32-bit instruction matching. 116 Do not dump EXTEND prefixes here. 117 * mips16-opc.c (mips16_opcodes): Move "extend" entry to the end. 118 Recode `match' and `mask' fields as 32-bit in absolute "jal" and 119 "jalx" entries. 120 121 2016-12-20 Maciej W. Rozycki <macro (a] imgtec.com> 122 123 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather 124 than I1 for the "ddiv", "ddivu", "drem", "dremu" and "dsubu" 125 INSN_MACRO entries. 126 127 2016-12-20 Maciej W. Rozycki <macro (a] imgtec.com> 128 129 * mips16-opc.c (mips16_opcodes): Set membership to I3 rather 130 than I1 for the SP-relative "sd"/$ra entry (SDRASP minor 131 opcode). 132 133 2016-12-20 Andrew Waterman <andrew (a] sifive.com> 134 135 * riscv-opc.c (riscv_opcodes): Rename the "*.sc" instructions to 136 "*.aqrl". 137 138 2016-12-20 Andrew Waterman <andrew (a] sifive.com> 139 140 * riscv-opc.c (riscv_opcodes): Mark the rd* and csr* aliases as 141 INSN_ALIAS. 142 143 2016-12-20 Andrew Waterman <andrew (a] sifive.com> 144 145 * riscv-opc.c (riscv_opcodes): Change jr and jalr to "o(s)" 146 format. 147 148 2016-12-20 Andrew Waterman <andrew (a] sifive.com> 149 150 * riscv-dis.c (riscv_disassemble_insn): Default to the ELF's 151 XLEN when none is provided. 152 153 2016-12-20 Andrew Waterman <andrew (a] sifive.com> 154 155 * riscv-opc.c: Formatting fixes. 156 157 2016-12-20 Alan Modra <amodra (a] gmail.com> 158 159 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add riscv files. 160 * Makefile.in: Regenerate. 161 * po/POTFILES.in: Regenerate. 162 163 2016-12-19 Maciej W. Rozycki <macro (a] imgtec.com> 164 165 * mips-dis.c (set_default_mips_dis_options) [SYMTAB_AVAILABLE]: 166 Only examine ELF file structures here. 167 168 2016-12-19 Maciej W. Rozycki <macro (a] imgtec.com> 169 170 * mips-dis.c (set_default_mips_dis_options) [BFD64]: Only call 171 `bfd_mips_elf_get_abiflags' here. 172 173 2016-12-16 Nick Clifton <nickc (a] redhat.com> 174 175 * arm-dis.c (print_insn_thumb32): Fix compile time warning 176 computing value_in_comment. 177 178 2016-12-14 Maciej W. Rozycki <macro (a] imgtec.com> 179 180 * mips-dis.c (mips_convert_abiflags_ases): New function. 181 (set_default_mips_dis_options): Also infer ASE flags from ELF 182 file structures. 183 184 2016-12-14 Maciej W. Rozycki <macro (a] imgtec.com> 185 186 * mips-dis.c (set_default_mips_dis_options): Reorder ELF file 187 header flag interpretation code. 188 189 2016-12-14 Maciej W. Rozycki <macro (a] imgtec.com> 190 191 * mips16-opc.c (mips16_opcodes): Set RD_SP rather than RD_PC in 192 `pinfo2' with SP-relative "sd" entries. 193 194 2016-12-14 Maciej W. Rozycki <macro (a] imgtec.com> 195 196 * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e 197 compact jumps. 198 199 2016-12-13 Renlin Li <renlin.li (a] arm.com> 200 201 * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range 202 qualifier. 203 (operand_general_constraint_met_p): Remove case for CP_REG. 204 (aarch64_print_operand): Print CRn, CRm operand using imm field. 205 * aarch64-tbl.h (QL_SYS): Use CR qualifier. 206 (QL_SYSL): Likewise. 207 (aarch64_opcode_table): Change CRn, CRm operand class and type. 208 * aarch64-opc-2.c : Regenerate. 209 * aarch64-asm-2.c : Likewise. 210 * aarch64-dis-2.c : Likewise. 211 212 2016-12-12 Yao Qi <yao.qi (a] linaro.org> 213 214 * rx-dis.c: Include <setjmp.h> 215 (struct private): New. 216 (rx_get_byte): Check return value of read_memory_func, and 217 call memory_error_func and OPCODES_SIGLONGJMP on error. 218 (print_insn_rx): Call OPCODES_SIGSETJMP. 219 220 2016-12-12 Yao Qi <yao.qi (a] linaro.org> 221 222 * rl78-dis.c: Include <setjmp.h>. 223 (struct private): New. 224 (rl78_get_byte): Check return value of read_memory_func, and 225 call memory_error_func and OPCODES_SIGLONGJMP on error. 226 (print_insn_rl78_common): Call OPCODES_SIGJMP. 227 228 2016-12-09 Maciej W. Rozycki <macro (a] imgtec.com> 229 230 * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases. 231 232 2016-12-09 Maciej W. Rozycki <macro (a] imgtec.com> 233 234 * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather 235 than UINT. 236 237 2016-12-09 Maciej W. Rozycki <macro (a] imgtec.com> 238 239 * mips-dis.c (print_insn_mips16): Use a tab rather than a space 240 to separate `extend' and its uninterpreted argument output. 241 Separate hexadecimal halves of undecoded extended instructions 242 output. 243 244 2016-12-08 Maciej W. Rozycki <macro (a] imgtec.com> 245 246 * mips-dis.c (print_mips16_insn_arg): Remove extraneous 247 indentation space across. 248 249 2016-12-08 Maciej W. Rozycki <macro (a] imgtec.com> 250 251 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot 252 adjustment for PC-relative operations following MIPS16e compact 253 jumps or undefined RR/J(AL)R(C) encodings. 254 255 2016-12-08 Maciej W. Rozycki <macro (a] imgtec.com> 256 257 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local 258 variable to `reglane_index'. 259 260 2016-12-08 Luis Machado <lgustavo (a] codesourcery.com> 261 262 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section. 263 264 2016-12-07 Maciej W. Rozycki <macro (a] imgtec.com> 265 266 * mips-dis.c (print_mips16_insn_arg): Fix comment typo. 267 268 2016-12-07 Maciej W. Rozycki <macro (a] imgtec.com> 269 270 * mips16-opc.c (mips16_opcodes): Update comment naming structure 271 members. 272 273 2016-12-07 Maciej W. Rozycki <macro (a] imgtec.com> 274 275 * mips-dis.c (print_mips_disassembler_options): Reformat output. 276 277 2016-12-05 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 278 279 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd. 280 (print_insn_coprocessor): Add 'V' format for neon D or Q regs. 281 282 2016-12-05 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 283 284 * arm-dis.c (coprocessor_opcodes): Add vjcvt. 285 286 2016-12-01 Nick Clifton <nickc (a] redhat.com> 287 288 PR binutils/20893 289 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad 290 opcode designator. 291 292 2016-11-29 Claudiu Zissulescu <claziss (a] synopsys.com> 293 294 * arc-opc.c (insert_ra_chk): New function. 295 (insert_rb_chk): Likewise. 296 (insert_rad): Update text error message. 297 (insert_rcd): Likewise. 298 (insert_rhv2): Likewise. 299 (insert_r0): Likewise. 300 (insert_r1): Likewise. 301 (insert_r2): Likewise. 302 (insert_r3): Likewise. 303 (insert_sp): Likewise. 304 (insert_gp): Likewise. 305 (insert_pcl): Likewise. 306 (insert_blink): Likewise. 307 (insert_ilink1): Likewise. 308 (insert_ilink2): Likewise. 309 (insert_ras): Likewise. 310 (insert_rbs): Likewise. 311 (insert_rcs): Likewise. 312 (insert_simm3s): Likewise. 313 (insert_rrange): Likewise. 314 (insert_fpel): Likewise. 315 (insert_blinkel): Likewise. 316 (insert_pcel): Likewise. 317 (insert_nps_3bit_dst): Likewise. 318 (insert_nps_3bit_dst_short): Likewise. 319 (insert_nps_3bit_src2_short): Likewise. 320 (insert_nps_bitop_size_2b): Likewise. 321 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise. 322 (RA_CHK): Define. 323 (RB): Adjust. 324 (RB_CHK): Define. 325 (RC): Adjust. 326 * arc-dis.c (print_insn_arc): Add LOAD and STORE class. 327 * arc-tbl.h (div, divu): All instructions are DIVREM class. 328 Change first insn argument to check for LP_COUNT usage. 329 (rem): Likewise. 330 (ld, ldd): All instructions are LOAD class. Change first insn 331 argument to check for LP_COUNT usage. 332 (st, std): All instructions are STORE class. 333 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class. 334 Change first insn argument to check for LP_COUNT usage. 335 (mov): All instructions are MOVE class. Change first insn 336 argument to check for LP_COUNT usage. 337 338 2016-11-29 Claudiu Zissulescu <claziss (a] synopsys.com> 339 340 * arc-dis.c (is_compatible_p): Remove function. 341 (skip_this_opcode): Don't add any decoding class to decode list. 342 Remove warning. 343 (find_format_from_table): Go through all opcodes, and warn if we 344 use a guessed mnemonic. 345 346 2016-11-28 Ramiro Polla <ramiro (a] hex-rays.com> 347 Amit Pawar <amit.pawar (a] amd.com> 348 349 PR binutils/20637 350 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP 351 instructions. 352 353 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani (a] gmail.com> 354 355 * configure: Regenerate. 356 357 2016-11-22 Jose E. Marchesi <jose.marchesi (a] oracle.com> 358 359 * sparc-opc.c (HWS_V8): Definition moved from 360 gas/config/tc-sparc.c. 361 (HWS_V9): Likewise. 362 (HWS_VA): Likewise. 363 (HWS_VB): Likewise. 364 (HWS_VC): Likewise. 365 (HWS_VD): Likewise. 366 (HWS_VE): Likewise. 367 (HWS_VV): Likewise. 368 (HWS_VM): Likewise. 369 (HWS2_VM): Likewise. 370 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of 371 existing entries. 372 373 2016-11-22 Claudiu Zissulescu <claziss (a] synopsys.com> 374 375 * arc-tbl.h: Reorder conditional flags with delay flags for 'b' 376 instructions. 377 378 2016-11-18 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 379 380 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define. 381 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define. 382 (aarch64_opcode_table): Add fcmla and fcadd. 383 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}. 384 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare. 385 * aarch64-asm.c (aarch64_ins_imm_rotate): Define. 386 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare. 387 * aarch64-dis.c (aarch64_ext_imm_rotate): Define. 388 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}. 389 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}. 390 (operand_general_constraint_met_p): Rotate and index range check. 391 (aarch64_print_operand): Handle rotate operand. 392 * aarch64-asm-2.c: Regenerate. 393 * aarch64-dis-2.c: Likewise. 394 * aarch64-opc-2.c: Likewise. 395 396 2016-11-18 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 397 398 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr. 399 * aarch64-asm-2.c: Regenerate. 400 * aarch64-dis-2.c: Regenerate. 401 * aarch64-opc-2.c: Regenerate. 402 403 2016-11-18 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 404 405 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs. 406 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define. 407 * aarch64-asm-2.c: Regenerate. 408 * aarch64-dis-2.c: Regenerate. 409 * aarch64-opc-2.c: Regenerate. 410 411 2016-11-18 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 412 413 * aarch64-tbl.h (QL_X1NIL): New. 414 (arch64_opcode_table): Add ldraa, ldrab. 415 (AARCH64_OPERANDS): Add "ADDR_SIMM10". 416 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare. 417 * aarch64-asm.c (aarch64_ins_addr_simm10): Define. 418 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare. 419 * aarch64-dis.c (aarch64_ext_addr_simm10): Define. 420 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10. 421 * aarch64-opc.c (fields): Add data for FLD_S_simm10. 422 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10. 423 (aarch64_print_operand): Likewise. 424 * aarch64-asm-2.c: Regenerate. 425 * aarch64-dis-2.c: Regenerate. 426 * aarch64-opc-2.c: Regenerate. 427 428 2016-11-11 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 429 430 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz, 431 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab. 432 * aarch64-asm-2.c: Regenerate. 433 * aarch64-dis-2.c: Regenerate. 434 * aarch64-opc-2.c: Regenerate. 435 436 2016-11-11 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 437 438 * aarch64-tbl.h (arch64_opcode_table): Add pacga. 439 (AARCH64_OPERANDS): Add Rm_SP. 440 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP. 441 * aarch64-asm-2.c: Regenerate. 442 * aarch64-dis-2.c: Regenerate. 443 * aarch64-opc-2.c: Regenerate. 444 445 2016-11-11 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 446 447 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia, 448 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza, 449 autdzb, xpaci, xpacd. 450 * aarch64-asm-2.c: Regenerate. 451 * aarch64-dis-2.c: Regenerate. 452 * aarch64-opc-2.c: Regenerate. 453 454 2016-11-11 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 455 456 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1, 457 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1, 458 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1. 459 (aarch64_sys_reg_supported_p): Add feature test for new registers. 460 461 2016-11-11 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 462 463 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New. 464 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716, 465 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz, 466 autibsp. 467 * aarch64-asm-2.c: Regenerate. 468 * aarch64-dis-2.c: Regenerate. 469 470 2016-11-11 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 471 472 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32. 473 474 2016-11-09 H.J. Lu <hongjiu.lu (a] intel.com> 475 476 PR binutils/20799 477 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw. 478 * i386-dis.c (EdqwS): Removed. 479 (dqw_swap_mode): Likewise. 480 (intel_operand_size): Don't check dqw_swap_mode. 481 (OP_E_register): Likewise. 482 (OP_E_memory): Likewise. 483 (OP_G): Likewise. 484 (OP_EX): Likewise. 485 * i386-opc.tbl: Remove "S" from EVEX vpextrw. 486 * i386-tbl.h: Regerated. 487 488 2016-11-09 H.J. Lu <hongjiu.lu (a] intel.com> 489 490 * i386-opc.tbl: Merge AVX512F vmovq. 491 * i386-tbl.h: Regerated. 492 493 2016-11-08 H.J. Lu <hongjiu.lu (a] intel.com> 494 495 PR binutils/20701 496 * i386-dis.c (THREE_BYTE_0F7A): Removed. 497 (dis386_twobyte): Don't use THREE_BYTE_0F7A. 498 (three_byte_table): Remove THREE_BYTE_0F7A. 499 500 2016-11-07 H.J. Lu <hongjiu.lu (a] intel.com> 501 502 PR binutils/20775 503 * i386-dis.c (FGRPd9_2): Replace 0 with 1. 504 (FGRPd9_4): Replace 1 with 2. 505 (FGRPd9_5): Replace 2 with 3. 506 (FGRPd9_6): Replace 3 with 4. 507 (FGRPd9_7): Replace 4 with 5. 508 (FGRPda_5): Replace 5 with 6. 509 (FGRPdb_4): Replace 6 with 7. 510 (FGRPde_3): Replace 7 with 8. 511 (FGRPdf_4): Replace 8 with 9. 512 (fgrps): Add an entry for Bad_Opcode. 513 514 2016-11-04 Andrew Burgess <andrew.burgess (a] embecosm.com> 515 516 * arc-opc.c (arc_flag_operands): Add F_DI14. 517 (arc_flag_classes): Add C_DI14. 518 * arc-nps400-tbl.h: Add new exc instructions. 519 520 2016-11-03 Graham Markall <graham.markall (a] embecosm.com> 521 522 * arc-dis.c (arc_insn_length): Return length 8 for instructions with 523 major opcode 0xa. 524 * arc-nps-400-tbl.h: Add dcmac instruction. 525 * arc-opc.c (arc_operands): Added operands for dcmac instruction. 526 (insert_nps_rbdouble_64): Added. 527 (extract_nps_rbdouble_64): Added. 528 (insert_nps_proto_size): Added. 529 (extract_nps_proto_size): Added. 530 531 2016-11-03 Andrew Burgess <andrew.burgess (a] embecosm.com> 532 533 * arc-dis.c (struct arc_operand_iterator): Remove all fields 534 relating to long instruction processing, add new limm field. 535 (OPCODE): Rename to... 536 (OPCODE_32BIT_INSN): ...this. 537 (OPCODE_AC): Delete. 538 (skip_this_opcode): Handle different instruction lengths, update 539 macro name. 540 (special_flag_p): Update parameter type. 541 (find_format_from_table): Update for more instruction lengths. 542 (find_format_long_instructions): Delete. 543 (find_format): Update for more instruction lengths. 544 (arc_insn_length): Likewise. 545 (extract_operand_value): Update for more instruction lengths. 546 (operand_iterator_next): Remove code relating to long 547 instructions. 548 (arc_opcode_to_insn_type): New function. 549 (print_insn_arc):Update for more instructions lengths. 550 * arc-ext.c (extInstruction_t): Change argument type. 551 * arc-ext.h (extInstruction_t): Change argument type. 552 * arc-fxi.h: Change type unsigned to unsigned long long 553 extensively throughout. 554 * arc-nps400-tbl.h: Add long instructions taken from 555 arc_long_opcodes table in arc-opc.c. 556 * arc-opc.c: Update parameter types on insert/extract handlers. 557 (arc_long_opcodes): Delete. 558 (arc_num_long_opcodes): Delete. 559 (arc_opcode_len): Update for more instruction lengths. 560 561 2016-11-03 Graham Markall <graham.markall (a] embecosm.com> 562 563 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte. 564 565 2016-11-03 Graham Markall <graham.markall (a] embecosm.com> 566 567 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT 568 with arc_opcode_len. 569 (find_format_long_instructions): Likewise. 570 * arc-opc.c (arc_opcode_len): New function. 571 572 2016-11-03 Andrew Burgess <andrew.burgess (a] embecosm.com> 573 574 * arc-nps400-tbl.h: Fix some instruction masks. 575 576 2016-11-03 H.J. Lu <hongjiu.lu (a] intel.com> 577 578 * i386-dis.c (REG_82): Removed. 579 (X86_64_82_REG_0): Likewise. 580 (X86_64_82_REG_1): Likewise. 581 (X86_64_82_REG_2): Likewise. 582 (X86_64_82_REG_3): Likewise. 583 (X86_64_82_REG_4): Likewise. 584 (X86_64_82_REG_5): Likewise. 585 (X86_64_82_REG_6): Likewise. 586 (X86_64_82_REG_7): Likewise. 587 (X86_64_82): New. 588 (dis386): Use X86_64_82 instead of REG_82. 589 (reg_table): Remove REG_82. 590 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0, 591 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3, 592 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and 593 X86_64_82_REG_7. 594 595 2016-11-03 H.J. Lu <hongjiu.lu (a] intel.com> 596 597 PR binutils/20754 598 * i386-dis.c (REG_82): New. 599 (X86_64_82_REG_0): Likewise. 600 (X86_64_82_REG_1): Likewise. 601 (X86_64_82_REG_2): Likewise. 602 (X86_64_82_REG_3): Likewise. 603 (X86_64_82_REG_4): Likewise. 604 (X86_64_82_REG_5): Likewise. 605 (X86_64_82_REG_6): Likewise. 606 (X86_64_82_REG_7): Likewise. 607 (dis386): Use REG_82. 608 (reg_table): Add REG_82. 609 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1, 610 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4, 611 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7. 612 613 2016-11-03 H.J. Lu <hongjiu.lu (a] intel.com> 614 615 * i386-dis.c (REG_82): Renamed to ... 616 (REG_83): This. 617 (dis386): Updated. 618 (reg_table): Likewise. 619 620 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 621 622 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853. 623 * i386-dis-evex.h (evex_table): Updated. 624 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS, 625 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS. 626 (cpu_flags): Add CpuAVX512_4VNNIW. 627 * i386-opc.h (enum): (AVX512_4VNNIW): New. 628 (i386_cpu_flags): Add cpuavx512_4vnniw. 629 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions. 630 * i386-init.h: Regenerate. 631 * i386-tbl.h: Ditto. 632 633 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 634 635 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A, 636 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB. 637 * i386-dis-evex.h (evex_table): Updated. 638 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS, 639 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS. 640 (cpu_flags): Add CpuAVX512_4FMAPS. 641 (opcode_modifiers): Add ImplicitQuadGroup modifier. 642 * i386-opc.h (AVX512_4FMAP): New. 643 (i386_cpu_flags): Add cpuavx512_4fmaps. 644 (ImplicitQuadGroup): New. 645 (i386_opcode_modifier): Add implicitquadgroup. 646 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions. 647 * i386-init.h: Regenerate. 648 * i386-tbl.h: Ditto. 649 650 2016-11-01 Palmer Dabbelt <palmer (a] dabbelt.com> 651 Andrew Waterman <andrew (a] sifive.com> 652 653 Add support for RISC-V architecture. 654 * configure.ac: Add entry for bfd_riscv_arch. 655 * configure: Regenerate. 656 * disassemble.c (disassembler): Add support for riscv. 657 (disassembler_usage): Likewise. 658 * riscv-dis.c: New file. 659 * riscv-opc.c: New file. 660 661 2016-10-21 H.J. Lu <hongjiu.lu (a] intel.com> 662 663 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed. 664 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry. 665 (rm_table): Update the RM_0FAE_REG_7 entry. 666 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS. 667 (cpu_flags): Remove CpuPCOMMIT. 668 * i386-opc.h (CpuPCOMMIT): Removed. 669 (i386_cpu_flags): Remove cpupcommit. 670 * i386-opc.tbl: Remove pcommit. 671 * i386-init.h: Regenerated. 672 * i386-tbl.h: Likewise. 673 674 2016-10-20 H.J. Lu <hongjiu.lu (a] intel.com> 675 676 PR binutis/20705 677 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and 678 the highest bit in VEX.vvvv for the 3-byte VEX prefix in 679 32-bit mode. Don't check vex.register_specifier in 32-bit 680 mode. 681 (OP_VEX): Check for invalid mask registers. 682 683 2016-10-18 H.J. Lu <hongjiu.lu (a] intel.com> 684 685 PR binutis/20699 686 * i386-dis.c (OP_E_memory): Check addr32flag in stead of 687 sizeflag. 688 689 2016-10-18 H.J. Lu <hongjiu.lu (a] intel.com> 690 691 PR binutis/20704 692 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support. 693 694 2016-10-18 Maciej W. Rozycki <macro (a] imgtec.com> 695 696 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index' 697 local variable to `index_regno'. 698 699 2016-10-17 Cupertino Miranda <cmiranda (a] synopsys.com> 700 701 * arc-tbl.h: Removed any "inv.+" instructions from the table. 702 703 2016-10-14 Claudiu Zissulescu <claziss (a] synopsys.com> 704 705 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator 706 usage on ISA basis. 707 708 2016-10-11 Jiong Wang <jiong.wang (a] arm.com> 709 710 PR target/20666 711 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index. 712 713 2016-10-07 Jiong Wang <jiong.wang (a] arm.com> 714 715 PR target/20667 716 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's 717 available. 718 719 2016-10-07 Alan Modra <amodra (a] gmail.com> 720 721 * sh-opc.h (sh_merge_bfd_arch): Delete prototype. 722 723 2016-10-06 Alan Modra <amodra (a] gmail.com> 724 725 * aarch64-opc.c: Spell fall through comments consistently. 726 * i386-dis.c: Likewise. 727 * aarch64-dis.c: Add missing fall through comments. 728 * aarch64-opc.c: Likewise. 729 * arc-dis.c: Likewise. 730 * arm-dis.c: Likewise. 731 * i386-dis.c: Likewise. 732 * m68k-dis.c: Likewise. 733 * mep-asm.c: Likewise. 734 * ns32k-dis.c: Likewise. 735 * sh-dis.c: Likewise. 736 * tic4x-dis.c: Likewise. 737 * tic6x-dis.c: Likewise. 738 * vax-dis.c: Likewise. 739 740 2016-10-06 Alan Modra <amodra (a] gmail.com> 741 742 * arc-ext.c (create_map): Add missing break. 743 * msp430-decode.opc (encode_as): Likewise. 744 * msp430-decode.c: Regenerate. 745 746 2016-10-06 Alan Modra <amodra (a] gmail.com> 747 748 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic. 749 * crx-dis.c (print_insn_crx): Likewise. 750 751 2016-09-30 H.J. Lu <hongjiu.lu (a] intel.com> 752 753 PR binutils/20657 754 * i386-dis.c (putop): Don't assign alt twice. 755 756 2016-09-29 Jiong Wang <jiong.wang (a] arm.com> 757 758 PR target/20553 759 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field. 760 761 2016-09-29 Alan Modra <amodra (a] gmail.com> 762 763 * ppc-opc.c (L): Make compulsory. 764 (LOPT): New, optional form of L. 765 (HTM_R): Define as LOPT. 766 (L0, L1): Delete. 767 (L32OPT): New, optional for 32-bit L. 768 (L2OPT): New, 2-bit L for dcbf. 769 (SVC_LEC): Update. 770 (L2): Define. 771 (insert_l0, extract_l0, insert_l1, extract_l2): Delete. 772 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT. 773 <dcbf>: Use L2OPT. 774 <tlbiel, tlbie>: Use LOPT. 775 <wclr, wclrall>: Use L2. 776 777 2016-09-26 Vlad Zakharov <vzakhar (a] synopsys.com> 778 779 * Makefile.in: Regenerate. 780 * configure: Likewise. 781 782 2016-09-26 Claudiu Zissulescu <claziss (a] synopsys.com> 783 784 * arc-ext-tbl.h (EXTINSN2OPF): Define. 785 (EXTINSN2OP): Use EXTINSN2OPF. 786 (bspeekm, bspop, modapp): New extension instructions. 787 * arc-opc.c (F_DNZ_ND): Define. 788 (F_DNZ_D): Likewise. 789 (F_SIZEB1): Changed. 790 (C_DNZ_D): Define. 791 (C_HARD): Changed. 792 * arc-tbl.h (dbnz): New instruction. 793 (prealloc): Allow it for ARC EM. 794 (xbfu): Likewise. 795 796 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 797 798 * aarch64-opc.c (print_immediate_offset_address): Print spaces 799 after commas in addresses. 800 (aarch64_print_operand): Likewise. 801 802 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 803 804 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be" 805 rather than "should be" or "expected to be" in error messages. 806 807 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 808 809 * aarch64-dis.c (remove_dot_suffix): New function, split out from... 810 (print_mnemonic_name): ...here. 811 (print_comment): New function. 812 (print_aarch64_insn): Call it. 813 * aarch64-opc.c (aarch64_conds): Add SVE names. 814 (aarch64_print_operand): Print alternative condition names in 815 a comment. 816 817 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 818 819 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB) 820 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ) 821 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD) 822 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU) 823 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB) 824 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR) 825 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS) 826 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB) 827 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD) 828 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD) 829 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD) 830 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD) 831 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD) 832 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD) 833 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS) 834 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD) 835 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD) 836 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD) 837 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD) 838 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD) 839 (OP_SVE_XWU, OP_SVE_XXU): New macros. 840 (aarch64_feature_sve): New variable. 841 (SVE): New macro. 842 (_SVE_INSN): Likewise. 843 (aarch64_opcode_table): Add SVE instructions. 844 * aarch64-opc.h (extract_fields): Declare. 845 * aarch64-opc-2.c: Regenerate. 846 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops. 847 * aarch64-asm-2.c: Regenerate. 848 * aarch64-dis.c (extract_fields): Make global. 849 (do_misc_decoding): Handle the new SVE aarch64_ops. 850 * aarch64-dis-2.c: Regenerate. 851 852 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 853 854 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16) 855 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New 856 aarch64_field_kinds. 857 * aarch64-opc.c (fields): Add corresponding entries. 858 * aarch64-asm.c (aarch64_get_variant): New function. 859 (aarch64_encode_variant_using_iclass): Likewise. 860 (aarch64_opcode_encode): Call it. 861 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function. 862 (aarch64_opcode_decode): Call it. 863 864 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 865 866 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core 867 and FP register operands. 868 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm) 869 (FLD_SVE_Vn): New aarch64_field_kinds. 870 * aarch64-opc.c (fields): Add corresponding entries. 871 (aarch64_print_operand): Handle the new SVE core and FP register 872 operands. 873 * aarch64-opc-2.c: Regenerate. 874 * aarch64-asm-2.c: Likewise. 875 * aarch64-dis-2.c: Likewise. 876 877 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 878 879 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP 880 immediate operands. 881 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind. 882 * aarch64-opc.c (fields): Add corresponding entry. 883 (operand_general_constraint_met_p): Handle the new SVE FP immediate 884 operands. 885 (aarch64_print_operand): Likewise. 886 * aarch64-opc-2.c: Regenerate. 887 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two) 888 (ins_sve_float_zero_one): New inserters. 889 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function. 890 (aarch64_ins_sve_float_half_two): Likewise. 891 (aarch64_ins_sve_float_zero_one): Likewise. 892 * aarch64-asm-2.c: Regenerate. 893 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two) 894 (ext_sve_float_zero_one): New extractors. 895 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function. 896 (aarch64_ext_sve_float_half_two): Likewise. 897 (aarch64_ext_sve_float_zero_one): Likewise. 898 * aarch64-dis-2.c: Regenerate. 899 900 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 901 902 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE 903 integer immediate operands. 904 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5) 905 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9) 906 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds. 907 * aarch64-opc.c (fields): Add corresponding entries. 908 (operand_general_constraint_met_p): Handle the new SVE integer 909 immediate operands. 910 (aarch64_print_operand): Likewise. 911 (aarch64_sve_dupm_mov_immediate_p): New function. 912 * aarch64-opc-2.c: Regenerate. 913 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm) 914 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters. 915 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from... 916 (aarch64_ins_limm): ...here. 917 (aarch64_ins_inv_limm): New function. 918 (aarch64_ins_sve_aimm): Likewise. 919 (aarch64_ins_sve_asimm): Likewise. 920 (aarch64_ins_sve_limm_mov): Likewise. 921 (aarch64_ins_sve_shlimm): Likewise. 922 (aarch64_ins_sve_shrimm): Likewise. 923 * aarch64-asm-2.c: Regenerate. 924 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm) 925 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors. 926 * aarch64-dis.c (decode_limm): New function, split out from... 927 (aarch64_ext_limm): ...here. 928 (aarch64_ext_inv_limm): New function. 929 (decode_sve_aimm): Likewise. 930 (aarch64_ext_sve_aimm): Likewise. 931 (aarch64_ext_sve_asimm): Likewise. 932 (aarch64_ext_sve_limm_mov): Likewise. 933 (aarch64_top_bit): Likewise. 934 (aarch64_ext_sve_shlimm): Likewise. 935 (aarch64_ext_sve_shrimm): Likewise. 936 * aarch64-dis-2.c: Regenerate. 937 938 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 939 940 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL 941 operands. 942 * aarch64-opc.c (aarch64_operand_modifiers): Initialize 943 the AARCH64_MOD_MUL_VL entry. 944 (value_aligned_p): Cope with non-power-of-two alignments. 945 (operand_general_constraint_met_p): Handle the new MUL VL addresses. 946 (print_immediate_offset_address): Likewise. 947 (aarch64_print_operand): Likewise. 948 * aarch64-opc-2.c: Regenerate. 949 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl) 950 (ins_sve_addr_ri_s9xvl): New inserters. 951 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function. 952 (aarch64_ins_sve_addr_ri_s6xvl): Likewise. 953 (aarch64_ins_sve_addr_ri_s9xvl): Likewise. 954 * aarch64-asm-2.c: Regenerate. 955 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl) 956 (ext_sve_addr_ri_s9xvl): New extractors. 957 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function. 958 (aarch64_ext_sve_addr_ri_s4xvl): Likewise. 959 (aarch64_ext_sve_addr_ri_s6xvl): Likewise. 960 (aarch64_ext_sve_addr_ri_s9xvl): Likewise. 961 * aarch64-dis-2.c: Regenerate. 962 963 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 964 965 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE 966 address operands. 967 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14) 968 (FLD_SVE_xs_22): New aarch64_field_kinds. 969 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags. 970 (get_operand_specific_data): New function. 971 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz, 972 FLD_SVE_xs_14 and FLD_SVE_xs_22. 973 (operand_general_constraint_met_p): Handle the new SVE address 974 operands. 975 (sve_reg): New array. 976 (get_addr_sve_reg_name): New function. 977 (aarch64_print_operand): Handle the new SVE address operands. 978 * aarch64-opc-2.c: Regenerate. 979 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl) 980 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl) 981 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters. 982 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function. 983 (aarch64_ins_sve_addr_rr_lsl): Likewise. 984 (aarch64_ins_sve_addr_rz_xtw): Likewise. 985 (aarch64_ins_sve_addr_zi_u5): Likewise. 986 (aarch64_ins_sve_addr_zz): Likewise. 987 (aarch64_ins_sve_addr_zz_lsl): Likewise. 988 (aarch64_ins_sve_addr_zz_sxtw): Likewise. 989 (aarch64_ins_sve_addr_zz_uxtw): Likewise. 990 * aarch64-asm-2.c: Regenerate. 991 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl) 992 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl) 993 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors. 994 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function. 995 (aarch64_ext_sve_addr_ri_u6): Likewise. 996 (aarch64_ext_sve_addr_rr_lsl): Likewise. 997 (aarch64_ext_sve_addr_rz_xtw): Likewise. 998 (aarch64_ext_sve_addr_zi_u5): Likewise. 999 (aarch64_ext_sve_addr_zz): Likewise. 1000 (aarch64_ext_sve_addr_zz_lsl): Likewise. 1001 (aarch64_ext_sve_addr_zz_sxtw): Likewise. 1002 (aarch64_ext_sve_addr_zz_uxtw): Likewise. 1003 * aarch64-dis-2.c: Regenerate. 1004 1005 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1006 1007 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for 1008 AARCH64_OPND_SVE_PATTERN_SCALED. 1009 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind. 1010 * aarch64-opc.c (fields): Add a corresponding entry. 1011 (set_multiplier_out_of_range_error): New function. 1012 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL. 1013 (operand_general_constraint_met_p): Handle 1014 AARCH64_OPND_SVE_PATTERN_SCALED. 1015 (print_register_offset_address): Use PRIi64 to print the 1016 shift amount. 1017 (aarch64_print_operand): Likewise. Handle 1018 AARCH64_OPND_SVE_PATTERN_SCALED. 1019 * aarch64-opc-2.c: Regenerate. 1020 * aarch64-asm.h (ins_sve_scale): New inserter. 1021 * aarch64-asm.c (aarch64_ins_sve_scale): New function. 1022 * aarch64-asm-2.c: Regenerate. 1023 * aarch64-dis.h (ext_sve_scale): New inserter. 1024 * aarch64-dis.c (aarch64_ext_sve_scale): New function. 1025 * aarch64-dis-2.c: Regenerate. 1026 1027 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1028 1029 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for 1030 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP. 1031 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind. 1032 (FLD_SVE_prfop): Likewise. 1033 * aarch64-opc.c: Include libiberty.h. 1034 (aarch64_sve_pattern_array): New variable. 1035 (aarch64_sve_prfop_array): Likewise. 1036 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop. 1037 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and 1038 AARCH64_OPND_SVE_PRFOP. 1039 * aarch64-asm-2.c: Regenerate. 1040 * aarch64-dis-2.c: Likewise. 1041 * aarch64-opc-2.c: Likewise. 1042 1043 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1044 1045 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for 1046 AARCH64_OPND_QLF_P_[ZM]. 1047 (aarch64_print_operand): Print /z and /m where appropriate. 1048 1049 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1050 1051 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands. 1052 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5) 1053 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt) 1054 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16) 1055 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds. 1056 * aarch64-opc.c (fields): Add corresponding entries here. 1057 (operand_general_constraint_met_p): Check that SVE register lists 1058 have the correct length. Check the ranges of SVE index registers. 1059 Check for cases where p8-p15 are used in 3-bit predicate fields. 1060 (aarch64_print_operand): Handle the new SVE operands. 1061 * aarch64-opc-2.c: Regenerate. 1062 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters. 1063 * aarch64-asm.c (aarch64_ins_sve_index): New function. 1064 (aarch64_ins_sve_reglist): Likewise. 1065 * aarch64-asm-2.c: Regenerate. 1066 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors. 1067 * aarch64-dis.c (aarch64_ext_sve_index): New function. 1068 (aarch64_ext_sve_reglist): Likewise. 1069 * aarch64-dis-2.c: Regenerate. 1070 1071 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1072 1073 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN) 1074 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN) 1075 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field. 1076 * aarch64-opc.c (aarch64_match_operands_constraint): Check for 1077 tied operands. 1078 1079 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1080 1081 * aarch64-opc.c (get_offset_int_reg_name): New function. 1082 (print_immediate_offset_address): Likewise. 1083 (print_register_offset_address): Take the base and offset 1084 registers as parameters. 1085 (aarch64_print_operand): Update caller accordingly. Use 1086 print_immediate_offset_address. 1087 1088 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1089 1090 * aarch64-opc.c (BANK): New macro. 1091 (R32, R64): Take a register number as argument 1092 (int_reg): Use BANK. 1093 1094 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1095 1096 * aarch64-opc.c (print_register_list): Add a prefix parameter. 1097 (aarch64_print_operand): Update accordingly. 1098 1099 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1100 1101 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm 1102 for FPIMM. 1103 * aarch64-asm.h (ins_fpimm): New inserter. 1104 * aarch64-asm.c (aarch64_ins_fpimm): New function. 1105 * aarch64-asm-2.c: Regenerate. 1106 * aarch64-dis.h (ext_fpimm): New extractor. 1107 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test. 1108 (aarch64_ext_fpimm): New function. 1109 * aarch64-dis-2.c: Regenerate. 1110 1111 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1112 1113 * aarch64-asm.c: Include libiberty.h. 1114 (insert_fields): New function. 1115 (aarch64_ins_imm): Use it. 1116 * aarch64-dis.c (extract_fields): New function. 1117 (aarch64_ext_imm): Use it. 1118 1119 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1120 1121 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32 1122 with an esize parameter. 1123 (operand_general_constraint_met_p): Update accordingly. 1124 Fix misindented code. 1125 * aarch64-asm.c (aarch64_ins_limm): Update call to 1126 aarch64_logical_immediate_p. 1127 1128 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1129 1130 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT. 1131 1132 2016-09-21 Richard Sandiford <richard.sandiford (a] arm.com> 1133 1134 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit. 1135 1136 2016-09-15 Claudiu Zissulescu <claziss (a] synopsys.com> 1137 1138 * arc-dis.c (find_format): Walk the linked list pointed by einsn. 1139 1140 2016-09-14 Peter Bergner <bergner (a] vnet.ibm.com> 1141 1142 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic. 1143 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool, 1144 xor3>: Delete mnemonics. 1145 <cp_abort>: Rename mnemonic from ... 1146 <cpabort>: ...to this. 1147 <setb>: Change to a X form instruction. 1148 <sync>: Change to 1 operand form. 1149 <copy>: Delete mnemonic. 1150 <copy_first>: Rename mnemonic from ... 1151 <copy>: ...to this. 1152 <paste, paste.>: Delete mnemonics. 1153 <paste_last>: Rename mnemonic from ... 1154 <paste.>: ...to this. 1155 1156 2016-09-14 Anton Kolesov <Anton.Kolesov (a] synopsys.com> 1157 1158 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully. 1159 1160 2016-09-12 Andreas Krebbel <krebbel (a] linux.vnet.ibm.com> 1161 1162 * s390-mkopc.c (main): Support alternate arch strings. 1163 1164 2016-09-12 Patrick Steuer <steuer (a] linux.vnet.ibm.com> 1165 1166 * s390-opc.txt: Fix kmctr instruction type. 1167 1168 2016-09-07 H.J. Lu <hongjiu.lu (a] intel.com> 1169 1170 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS. 1171 * i386-init.h: Regenerated. 1172 1173 2016-08-30 Cupertino Miranda <cmiranda (a] synopsys.com> 1174 1175 * opcodes/arc-dis.c (print_insn_arc): Changed. 1176 1177 2016-08-26 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1178 1179 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi -> 1180 camellia_fl. 1181 1182 2016-08-26 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 1183 1184 * arm-dis.c (psr_name): Use hex as case labels. Add detection for 1185 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, 1186 FAULTMASK_NS, CONTROL_NS and SP_NS special registers. 1187 1188 2016-08-24 H.J. Lu <hongjiu.lu (a] intel.com> 1189 1190 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. 1191 (PREFIX_MOD_3_0FAE_REG_4): Likewise. 1192 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and 1193 PREFIX_MOD_3_0FAE_REG_4. 1194 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and 1195 PREFIX_MOD_3_0FAE_REG_4. 1196 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS. 1197 (cpu_flags): Add CpuPTWRITE. 1198 * i386-opc.h (CpuPTWRITE): New. 1199 (i386_cpu_flags): Add cpuptwrite. 1200 * i386-opc.tbl: Add ptwrite instruction. 1201 * i386-init.h: Regenerated. 1202 * i386-tbl.h: Likewise. 1203 1204 2016-08-24 Anton Kolesov <Anton.Kolesov (a] synopsys.com> 1205 1206 * arc-dis.h: Wrap around in extern "C". 1207 1208 2016-08-23 Richard Sandiford <richard.sandiford (a] arm.com> 1209 1210 * aarch64-tbl.h (V8_2_INSN): New macro. 1211 (aarch64_opcode_table): Use it. 1212 1213 2016-08-23 Richard Sandiford <richard.sandiford (a] arm.com> 1214 1215 * aarch64-tbl.h (aarch64_opcode_table): Make more use of 1216 CORE_INSN, __FP_INSN and SIMD_INSN. 1217 1218 2016-08-23 Richard Sandiford <richard.sandiford (a] arm.com> 1219 1220 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter. 1221 (aarch64_opcode_table): Update uses accordingly. 1222 1223 2016-07-25 Andrew Jenner <andrew (a] codesourcery.com> 1224 Kwok Cheung Yeung <kcy (a] codesourcery.com> 1225 1226 opcodes/ 1227 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and 1228 'e_cmplwi' to 'e_cmpli' instead. 1229 (OPVUPRT, OPVUPRT_MASK): Define. 1230 (powerpc_opcodes): Add E200Z4 insns. 1231 (vle_opcodes): Add context save/restore insns. 1232 1233 2016-07-27 Maciej W. Rozycki <macro (a] imgtec.com> 1234 1235 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b", 1236 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to 1237 "j". 1238 1239 2016-07-27 Graham Markall <graham.markall (a] embecosm.com> 1240 1241 * arc-nps400-tbl.h: Change block comments to GNU format. 1242 * arc-dis.c: Add new globals addrtypenames, 1243 addrtypenames_max, and addtypeunknown. 1244 (get_addrtype): New function. 1245 (print_insn_arc): Print colons and address types when 1246 required. 1247 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to 1248 define insert and extract functions for all address types. 1249 (arc_operands): Add operands for colon and all address 1250 types. 1251 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table. 1252 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands, 1253 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions. 1254 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table. 1255 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands, 1256 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions. 1257 1258 2016-07-21 H.J. Lu <hongjiu.lu (a] intel.com> 1259 1260 * configure: Regenerated. 1261 1262 2016-07-20 Claudiu Zissulescu <claziss (a] synopsys.com> 1263 1264 * arc-dis.c (skipclass): New structure. 1265 (decodelist): New variable. 1266 (is_compatible_p): New function. 1267 (new_element): Likewise. 1268 (skip_class_p): Likewise. 1269 (find_format_from_table): Use skip_class_p function. 1270 (find_format): Decode first the extension instructions. 1271 (print_insn_arc): Select either ARCEM or ARCHS based on elf 1272 e_flags. 1273 (parse_option): New function. 1274 (parse_disassembler_options): Likewise. 1275 (print_arc_disassembler_options): Likewise. 1276 (print_insn_arc): Use parse_disassembler_options function. Proper 1277 select ARCv2 cpu variant. 1278 * disassemble.c (disassembler_usage): Add ARC disassembler 1279 options. 1280 1281 2016-07-13 Maciej W. Rozycki <macro (a] imgtec.com> 1282 1283 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS 1284 annotation from the "nal" entry and reorder it beyond "bltzal". 1285 1286 2016-07-12 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1287 1288 * sparc-opc.c (ldtxa): New macro. 1289 (sparc_opcodes): Use the macro defined above to add entries for 1290 the LDTXA instructions. 1291 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA 1292 instruction. 1293 1294 2016-07-07 James Bowman <james.bowman (a] ftdichip.com> 1295 1296 * ft32-opc.c (ft32_opc_info): Correct mask for "callc" 1297 and "jmpc". 1298 1299 2016-07-01 Jan Beulich <jbeulich (a] suse.com> 1300 1301 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove. 1302 (movzb): Adjust to cover all permitted suffixes. 1303 (movzw): New. 1304 * i386-tbl.h: Re-generate. 1305 1306 2016-07-01 Jan Beulich <jbeulich (a] suse.com> 1307 1308 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant. 1309 (lgdt): Remove Tbyte from non-64-bit variant. 1310 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64, 1311 xsaves64, xsavec64): Remove Disp16. 1312 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd): 1313 Remove Disp32S from non-64-bit variants. Remove Disp16 from 1314 64-bit variants. 1315 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd, 1316 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi, 1317 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from 1318 64-bit variants. 1319 * i386-tbl.h: Re-generate. 1320 1321 2016-07-01 Jan Beulich <jbeulich (a] suse.com> 1322 1323 * i386-opc.tbl (xlat): Remove RepPrefixOk. 1324 * i386-tbl.h: Re-generate. 1325 1326 2016-06-30 Yao Qi <yao.qi (a] linaro.org> 1327 1328 * arm-dis.c (print_insn): Fix typo in comment. 1329 1330 2016-06-28 Richard Sandiford <richard.sandiford (a] arm.com> 1331 1332 * aarch64-opc.c (operand_general_constraint_met_p): Check the 1333 range of ldst_elemlist operands. 1334 (print_register_list): Use PRIi64 to print the index. 1335 (aarch64_print_operand): Likewise. 1336 1337 2016-06-25 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org> 1338 1339 * mcore-opc.h: Remove sentinal. 1340 * mcore-dis.c (print_insn_mcore): Adjust. 1341 1342 2016-06-23 Graham Markall <graham.markall (a] embecosm.com> 1343 1344 * arc-opc.c: Correct description of availability of NPS400 1345 features. 1346 1347 2016-06-22 Peter Bergner <bergner (a] vnet.ibm.com> 1348 1349 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines. 1350 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni, 1351 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool, 1352 xor3>: New mnemonics. 1353 <setb>: Change to a VX form instruction. 1354 (insert_sh6): Add support for rldixor. 1355 (extract_sh6): Likewise. 1356 1357 2016-06-22 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org> 1358 1359 * arc-ext.h: Wrap in extern C. 1360 1361 2016-06-21 Graham Markall <graham.markall (a] embecosm.com> 1362 1363 * arc-dis.c (arc_insn_length): Add comment on instruction length. 1364 Use same method for determining instruction length on ARC700 and 1365 NPS-400. 1366 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400. 1367 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions 1368 with the NPS400 subclass. 1369 * arc-opc.c: Likewise. 1370 1371 2016-06-17 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1372 1373 * sparc-opc.c (rdasr): New macro. 1374 (wrasr): Likewise. 1375 (rdpr): Likewise. 1376 (wrpr): Likewise. 1377 (rdhpr): Likewise. 1378 (wrhpr): Likewise. 1379 (sparc_opcodes): Use the macros above to fix and expand the 1380 definition of read/write instructions from/to 1381 asr/privileged/hyperprivileged instructions. 1382 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and 1383 %hva_mask_nz. Prefer softint_set and softint_clear over 1384 set_softint and clear_softint. 1385 (print_insn_sparc): Support %ver in Rd. 1386 1387 2016-06-17 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1388 1389 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode 1390 architecture according to the hardware capabilities they require. 1391 1392 2016-06-17 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1393 1394 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}. 1395 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and 1396 bfd_mach_sparc_v9{c,d,e,v,m}. 1397 * sparc-opc.c (MASK_V9C): Define. 1398 (MASK_V9D): Likewise. 1399 (MASK_V9E): Likewise. 1400 (MASK_V9V): Likewise. 1401 (MASK_V9M): Likewise. 1402 (v6): Add MASK_V9{C,D,E,V,M}. 1403 (v6notlet): Likewise. 1404 (v7): Likewise. 1405 (v8): Likewise. 1406 (v9): Likewise. 1407 (v9andleon): Likewise. 1408 (v9a): Likewise. 1409 (v9b): Likewise. 1410 (v9c): Define. 1411 (v9d): Likewise. 1412 (v9e): Likewise. 1413 (v9v): Likewise. 1414 (v9m): Likewise. 1415 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}. 1416 1417 2016-06-15 Nick Clifton <nickc (a] redhat.com> 1418 1419 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer 1420 constants to match expected behaviour. 1421 (nds32_parse_opcode): Likewise. Also for whitespace. 1422 1423 2016-06-15 Andrew Burgess <andrew.burgess (a] embecosm.com> 1424 1425 * arc-opc.c (extract_rhv1): Extract value from insn. 1426 1427 2016-06-14 Graham Markall <graham.markall (a] embecosm.com> 1428 1429 * arc-nps400-tbl.h: Add ldbit instruction. 1430 * arc-opc.c: Add flag classes required for ldbit. 1431 1432 2016-06-14 Graham Markall <graham.markall (a] embecosm.com> 1433 1434 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf 1435 * arc-opc.c: Add flag classes, insert/extract functions, and operands to 1436 support the above instructions. 1437 1438 2016-06-14 Graham Markall <graham.markall (a] embecosm.com> 1439 1440 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb, 1441 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms, 1442 csma, cbba, zncv, and hofs. 1443 * arc-opc.c: Add flag classes, insert/extract functions, and operands to 1444 support the above instructions. 1445 1446 2016-06-06 Graham Markall <graham.markall (a] embecosm.com> 1447 1448 * arc-nps400-tbl.h: Add andab and orab instructions. 1449 1450 2016-06-06 Graham Markall <graham.markall (a] embecosm.com> 1451 1452 * arc-nps400-tbl.h: Add addl-like instructions. 1453 1454 2016-06-06 Graham Markall <graham.markall (a] embecosm.com> 1455 1456 * arc-nps400-tbl.h: Add mxb and imxb instructions. 1457 1458 2016-06-06 Graham Markall <graham.markall (a] embecosm.com> 1459 1460 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey 1461 instructions. 1462 1463 2016-06-10 Andreas Krebbel <krebbel (a] linux.vnet.ibm.com> 1464 1465 * s390-dis.c (option_use_insn_len_bits_p): New file scope 1466 variable. 1467 (init_disasm): Handle new command line option "insnlength". 1468 (print_s390_disassembler_options): Mention new option in help 1469 output. 1470 (print_insn_s390): Use the encoded insn length when dumping 1471 unknown instructions. 1472 1473 2016-06-03 Pitchumani Sivanupandi <pitchumani.s (a] atmel.com> 1474 1475 * avr-dis.c (avr_operand): Add default data address space origin (0x800000) 1476 to the address and set as symbol address for LDS/ STS immediate operands. 1477 1478 2016-06-07 Alan Modra <amodra (a] gmail.com> 1479 1480 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default 1481 cpu for "vle" to e500. 1482 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE. 1483 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise. 1484 (PPCNONE): Delete, substitute throughout. 1485 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated" 1486 except for major opcode 4 and 31. 1487 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags. 1488 1489 2016-06-07 Matthew Wahab <matthew.wahab (a] arm.com> 1490 1491 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with 1492 ARM_EXT_RAS in relevant entries. 1493 1494 2016-06-03 Peter Bergner <bergner (a] vnet.ibm.com> 1495 1496 PR binutils/20196 1497 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable 1498 opcodes for E6500. 1499 1500 2016-06-03 H.J. Lu <hongjiu.lu (a] intel.com> 1501 1502 PR binutis/18386 1503 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode. 1504 (indir_v_mode): New. 1505 Add comments for '&'. 1506 (reg_table): Replace "{T|}" with "{&|}" on call and jmp. 1507 (putop): Handle '&'. 1508 (intel_operand_size): Handle indir_v_mode. 1509 (OP_E_register): Likewise. 1510 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add 1511 64-bit indirect call/jmp for AMD64. 1512 * i386-tbl.h: Regenerated 1513 1514 2016-06-02 Andrew Burgess <andrew.burgess (a] embecosm.com> 1515 1516 * arc-dis.c (struct arc_operand_iterator): New structure. 1517 (find_format_from_table): All the old content from find_format, 1518 with some minor adjustments, and parameter renaming. 1519 (find_format_long_instructions): New function. 1520 (find_format): Rewritten. 1521 (arc_insn_length): Add LSB parameter. 1522 (extract_operand_value): New function. 1523 (operand_iterator_next): New function. 1524 (print_insn_arc): Use new functions to find opcode, and iterator 1525 over operands. 1526 * arc-opc.c (insert_nps_3bit_dst_short): New function. 1527 (extract_nps_3bit_dst_short): New function. 1528 (insert_nps_3bit_src2_short): New function. 1529 (extract_nps_3bit_src2_short): New function. 1530 (insert_nps_bitop1_size): New function. 1531 (extract_nps_bitop1_size): New function. 1532 (insert_nps_bitop2_size): New function. 1533 (extract_nps_bitop2_size): New function. 1534 (insert_nps_bitop_mod4_msb): New function. 1535 (extract_nps_bitop_mod4_msb): New function. 1536 (insert_nps_bitop_mod4_lsb): New function. 1537 (extract_nps_bitop_mod4_lsb): New function. 1538 (insert_nps_bitop_dst_pos3_pos4): New function. 1539 (extract_nps_bitop_dst_pos3_pos4): New function. 1540 (insert_nps_bitop_ins_ext): New function. 1541 (extract_nps_bitop_ins_ext): New function. 1542 (arc_operands): Add new operands. 1543 (arc_long_opcodes): New global array. 1544 (arc_num_long_opcodes): New global. 1545 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes. 1546 1547 2016-06-01 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org> 1548 1549 * nds32-asm.h: Add extern "C". 1550 * sh-opc.h: Likewise. 1551 1552 2016-06-01 Graham Markall <graham.markall (a] embecosm.com> 1553 1554 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and 1555 0,b,limm to the rflt instruction. 1556 1557 2016-05-31 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org> 1558 1559 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned 1560 constant. 1561 1562 2016-05-29 H.J. Lu <hongjiu.lu (a] intel.com> 1563 1564 PR gas/20145 1565 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS, 1566 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS, 1567 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS, 1568 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS, 1569 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS. 1570 * i386-init.h: Regenerated. 1571 1572 2016-05-27 H.J. Lu <hongjiu.lu (a] intel.com> 1573 1574 PR gas/20145 1575 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove 1576 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from 1577 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS. 1578 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and 1579 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from 1580 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS, 1581 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS. 1582 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS, 1583 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS, 1584 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS, 1585 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX 1586 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable 1587 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and 1588 CpuRegMask for AVX512. 1589 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM 1590 and CpuRegMask. 1591 (set_bitfield_from_cpu_flag_init): New function. 1592 (set_bitfield): Remove const on f. Call 1593 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS. 1594 * i386-opc.h (CpuRegMMX): New. 1595 (CpuRegXMM): Likewise. 1596 (CpuRegYMM): Likewise. 1597 (CpuRegZMM): Likewise. 1598 (CpuRegMask): Likewise. 1599 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm 1600 and cpuregmask. 1601 * i386-init.h: Regenerated. 1602 * i386-tbl.h: Likewise. 1603 1604 2016-05-27 H.J. Lu <hongjiu.lu (a] intel.com> 1605 1606 PR gas/20154 1607 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64. 1608 (opcode_modifiers): Add AMD64 and Intel64. 1609 (main): Properly verify CpuMax. 1610 * i386-opc.h (CpuAMD64): Removed. 1611 (CpuIntel64): Likewise. 1612 (CpuMax): Set to CpuNo64. 1613 (i386_cpu_flags): Remove cpuamd64 and cpuintel64. 1614 (AMD64): New. 1615 (Intel64): Likewise. 1616 (i386_opcode_modifier): Add amd64 and intel64. 1617 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64 1618 on call and jmp. 1619 * i386-init.h: Regenerated. 1620 * i386-tbl.h: Likewise. 1621 1622 2016-05-27 H.J. Lu <hongjiu.lu (a] intel.com> 1623 1624 PR gas/20154 1625 * i386-gen.c (main): Fail if CpuMax is incorrect. 1626 * i386-opc.h (CpuMax): Set to CpuIntel64. 1627 * i386-tbl.h: Regenerated. 1628 1629 2016-05-27 Nick Clifton <nickc (a] redhat.com> 1630 1631 PR target/20150 1632 * msp430-dis.c (msp430dis_read_two_bytes): New function. 1633 (msp430dis_opcode_unsigned): New function. 1634 (msp430dis_opcode_signed): New function. 1635 (msp430_singleoperand): Use the new opcode reading functions. 1636 Only disassenmble bytes if they were successfully read. 1637 (msp430_doubleoperand): Likewise. 1638 (msp430_branchinstr): Likewise. 1639 (msp430x_callx_instr): Likewise. 1640 (print_insn_msp430): Check that it is safe to read bytes before 1641 attempting disassembly. Use the new opcode reading functions. 1642 1643 2016-05-26 Peter Bergner <bergner (a] vnet.ibm.com> 1644 1645 * ppc-opc.c (CY): New define. Document it. 1646 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics. 1647 1648 2016-05-25 H.J. Lu <hongjiu.lu (a] intel.com> 1649 1650 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS, 1651 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS 1652 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW, 1653 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to 1654 CPU_ANY_AVX_FLAGS. 1655 * i386-init.h: Regenerated. 1656 1657 2016-05-25 H.J. Lu <hongjiu.lu (a] intel.com> 1658 1659 PR gas/20141 1660 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS, 1661 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS. 1662 * i386-init.h: Regenerated. 1663 1664 2016-05-25 H.J. Lu <hongjiu.lu (a] intel.com> 1665 1666 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to 1667 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS. 1668 * i386-init.h: Regenerated. 1669 1670 2016-05-23 Claudiu Zissulescu <claziss (a] synopsys.com> 1671 1672 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type 1673 information. 1674 (print_insn_arc): Set insn_type information. 1675 * arc-opc.c (C_CC): Add F_CLASS_COND. 1676 * arc-tbl.h (bbit0, bbit1): Update subclass to COND. 1677 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. 1678 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. 1679 (breq, breq_s, brge, brhs, brlo, brlt): Likewise. 1680 (brne, brne_s, jeq_s, jne_s): Likewise. 1681 1682 2016-05-23 Claudiu Zissulescu <claziss (a] synopsys.com> 1683 1684 * arc-tbl.h (neg): New instruction variant. 1685 1686 2016-05-23 Cupertino Miranda <cmiranda (a] synopsys.com> 1687 1688 * arc-dis.c (find_format, find_format, get_auxreg) 1689 (print_insn_arc): Changed. 1690 * arc-ext.h (INSERT_XOP): Likewise. 1691 1692 2016-05-23 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org> 1693 1694 * tic54x-dis.c (sprint_mmr): Adjust. 1695 * tic54x-opc.c: Likewise. 1696 1697 2016-05-19 Alan Modra <amodra (a] gmail.com> 1698 1699 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi. 1700 1701 2016-05-19 Alan Modra <amodra (a] gmail.com> 1702 1703 * ppc-opc.c: Formatting. 1704 (NSISIGNOPT): Define. 1705 (powerpc_opcodes <subis>): Use NSISIGNOPT. 1706 1707 2016-05-18 Maciej W. Rozycki <macro (a] imgtec.com> 1708 1709 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand, 1710 replacing references to `micromips_ase' throughout. 1711 (_print_insn_mips): Don't use file-level microMIPS annotation to 1712 determine the disassembly mode with the symbol table. 1713 1714 2016-05-13 Peter Bergner <bergner (a] vnet.ibm.com> 1715 1716 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT. 1717 1718 2016-05-11 Andrew Bennett <andrew.bennett (a] imgtec.com> 1719 1720 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and 1721 mips64r6. 1722 * mips-opc.c (D34): New macro. 1723 (mips_builtin_opcodes): Define bposge32c for DSPr3. 1724 1725 2016-05-10 Alexander Fomin <alexander.fomin (a] intel.com> 1726 1727 * i386-dis.c (prefix_table): Add RDPID instruction. 1728 * i386-gen.c (cpu_flag_init): Add RDPID flag. 1729 (cpu_flags): Add RDPID bitfield. 1730 * i386-opc.h (enum): Add RDPID element. 1731 (i386_cpu_flags): Add RDPID field. 1732 * i386-opc.tbl: Add RDPID instruction. 1733 * i386-init.h: Regenerate. 1734 * i386-tbl.h: Regenerate. 1735 1736 2016-05-10 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 1737 1738 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get 1739 branch type of a symbol. 1740 (print_insn): Likewise. 1741 1742 2016-05-10 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 1743 1744 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M 1745 Mainline Security Extensions instructions. 1746 (thumb_opcodes): Add entries for narrow ARMv8-M Security 1747 Extensions instructions. 1748 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions 1749 instructions. 1750 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions 1751 special registers. 1752 1753 2016-05-09 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1754 1755 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai. 1756 1757 2016-05-03 Claudiu Zissulescu <claziss (a] synopsys.com> 1758 1759 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP. 1760 (arcExtMap_genOpcode): Likewise. 1761 * arc-opc.c (arg_32bit_rc): Define new variable. 1762 (arg_32bit_u6): Likewise. 1763 (arg_32bit_limm): Likewise. 1764 1765 2016-05-03 Szabolcs Nagy <szabolcs.nagy (a] arm.com> 1766 1767 * aarch64-gen.c (VERIFIER): Define. 1768 * aarch64-opc.c (VERIFIER): Define. 1769 (verify_ldpsw): Use static linkage. 1770 * aarch64-opc.h (verify_ldpsw): Remove. 1771 * aarch64-tbl.h: Use VERIFIER for verifiers. 1772 1773 2016-04-28 Nick Clifton <nickc (a] redhat.com> 1774 1775 PR target/19722 1776 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present. 1777 * aarch64-opc.c (verify_ldpsw): New function. 1778 * aarch64-opc.h (verify_ldpsw): New prototype. 1779 * aarch64-tbl.h: Add initialiser for verifier field. 1780 (LDPSW): Set verifier to verify_ldpsw. 1781 1782 2016-04-23 H.J. Lu <hongjiu.lu (a] intel.com> 1783 1784 PR binutils/19983 1785 PR binutils/19984 1786 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is 1787 smaller than address size. 1788 1789 2016-04-20 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org> 1790 1791 * alpha-dis.c: Regenerate. 1792 * crx-dis.c: Likewise. 1793 * disassemble.c: Likewise. 1794 * epiphany-opc.c: Likewise. 1795 * fr30-opc.c: Likewise. 1796 * frv-opc.c: Likewise. 1797 * ip2k-opc.c: Likewise. 1798 * iq2000-opc.c: Likewise. 1799 * lm32-opc.c: Likewise. 1800 * lm32-opinst.c: Likewise. 1801 * m32c-opc.c: Likewise. 1802 * m32r-opc.c: Likewise. 1803 * m32r-opinst.c: Likewise. 1804 * mep-opc.c: Likewise. 1805 * mt-opc.c: Likewise. 1806 * or1k-opc.c: Likewise. 1807 * or1k-opinst.c: Likewise. 1808 * tic80-opc.c: Likewise. 1809 * xc16x-opc.c: Likewise. 1810 * xstormy16-opc.c: Likewise. 1811 1812 2016-04-19 Andrew Burgess <andrew.burgess (a] embecosm.com> 1813 1814 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb, 1815 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp, 1816 calcsd, and calcxd instructions. 1817 * arc-opc.c (insert_nps_bitop_size): Delete. 1818 (extract_nps_bitop_size): Delete. 1819 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use. 1820 (extract_nps_qcmp_m3): Define. 1821 (extract_nps_qcmp_m2): Define. 1822 (extract_nps_qcmp_m1): Define. 1823 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL. 1824 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL 1825 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE, 1826 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST, 1827 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and 1828 NPS_QCMP_M3. 1829 1830 2016-04-19 Andrew Burgess <andrew.burgess (a] embecosm.com> 1831 1832 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions. 1833 1834 2016-04-15 H.J. Lu <hongjiu.lu (a] intel.com> 1835 1836 * Makefile.in: Regenerated with automake 1.11.6. 1837 * aclocal.m4: Likewise. 1838 1839 2016-04-14 Andrew Burgess <andrew.burgess (a] embecosm.com> 1840 1841 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst 1842 instructions. 1843 * arc-opc.c (insert_nps_cmem_uimm16): New function. 1844 (extract_nps_cmem_uimm16): New function. 1845 (arc_operands): Add NPS_XLDST_UIMM16 operand. 1846 1847 2016-04-14 Andrew Burgess <andrew.burgess (a] embecosm.com> 1848 1849 * arc-dis.c (arc_insn_length): New function. 1850 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned. 1851 (find_format): Change insnLen parameter to unsigned. 1852 1853 2016-04-13 Nick Clifton <nickc (a] redhat.com> 1854 1855 PR target/19937 1856 * v850-opc.c (v850_opcodes): Correct masks for long versions of 1857 the LD.B and LD.BU instructions. 1858 1859 2016-04-12 Claudiu Zissulescu <claziss (a] synopsys.com> 1860 1861 * arc-dis.c (find_format): Check for extension flags. 1862 (print_flags): New function. 1863 (print_insn_arc): Update for .extCondCode, .extCoreRegister and 1864 .extAuxRegister. 1865 * arc-ext.c (arcExtMap_coreRegName): Use 1866 LAST_EXTENSION_CORE_REGISTER. 1867 (arcExtMap_coreReadWrite): Likewise. 1868 (dump_ARC_extmap): Update printing. 1869 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag. 1870 (arc_aux_regs): Add cpu field. 1871 * arc-regs.h: Add cpu field, lower case name aux registers. 1872 1873 2016-04-12 Claudiu Zissulescu <claziss (a] synopsys.com> 1874 1875 * arc-tbl.h: Add rtsc, sleep with no arguments. 1876 1877 2016-04-12 Claudiu Zissulescu <claziss (a] synopsys.com> 1878 1879 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf): 1880 Initialize. 1881 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc) 1882 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6) 1883 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm) 1884 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm) 1885 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12) 1886 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc) 1887 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm) 1888 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6) 1889 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise. 1890 (arc_opcode arc_opcodes): Null terminate the array. 1891 (arc_num_opcodes): Remove. 1892 * arc-ext.h (INSERT_XOP): Define. 1893 (extInstruction_t): Likewise. 1894 (arcExtMap_instName): Delete. 1895 (arcExtMap_insn): New function. 1896 (arcExtMap_genOpcode): Likewise. 1897 * arc-ext.c (ExtInstruction): Remove. 1898 (create_map): Zero initialize instruction fields. 1899 (arcExtMap_instName): Remove. 1900 (arcExtMap_insn): New function. 1901 (dump_ARC_extmap): More info while debugging. 1902 (arcExtMap_genOpcode): New function. 1903 * arc-dis.c (find_format): New function. 1904 (print_insn_arc): Use find_format. 1905 (arc_get_disassembler): Enable dump_ARC_extmap only when 1906 debugging. 1907 1908 2016-04-11 Maciej W. Rozycki <macro (a] imgtec.com> 1909 1910 * mips-dis.c (print_mips16_insn_arg): Mask unused extended 1911 instruction bits out. 1912 1913 2016-04-07 Andrew Burgess <andrew.burgess (a] embecosm.com> 1914 1915 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions. 1916 * arc-opc.c (arc_flag_operands): Add new flags. 1917 (arc_flag_classes): Add new classes. 1918 1919 2016-04-07 Andrew Burgess <andrew.burgess (a] embecosm.com> 1920 1921 * arc-opc.c (arc_opcodes): Extend comment to discus table layout. 1922 1923 2016-04-05 Andrew Burgess <andrew.burgess (a] embecosm.com> 1924 1925 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0, 1926 encode1, rflt, crc16, and crc32 instructions. 1927 * arc-opc.c (arc_flag_operands): Add F_NPS_R. 1928 (arc_flag_classes): Add C_NPS_R. 1929 (insert_nps_bitop_size_2b): New function. 1930 (extract_nps_bitop_size_2b): Likewise. 1931 (insert_nps_bitop_uimm8): Likewise. 1932 (extract_nps_bitop_uimm8): Likewise. 1933 (arc_operands): Add new operand entries. 1934 1935 2016-04-05 Claudiu Zissulescu <claziss (a] synopsys.com> 1936 1937 * arc-regs.h: Add a new subclass field. Add double assist 1938 accumulator register values. 1939 * arc-tbl.h: Use DPA subclass to mark the double assist 1940 instructions. Use DPX/SPX subclas to mark the FPX instructions. 1941 * arc-opc.c (RSP): Define instead of SP. 1942 (arc_aux_regs): Add the subclass field. 1943 1944 2016-04-05 Jiong Wang <jiong.wang (a] arm.com> 1945 1946 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar). 1947 1948 2016-03-31 Andrew Burgess <andrew.burgess (a] embecosm.com> 1949 1950 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and 1951 NPS_R_SRC1. 1952 1953 2016-03-30 Andrew Burgess <andrew.burgess (a] embecosm.com> 1954 1955 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace 1956 issues. No functional changes. 1957 1958 2016-03-30 Claudiu Zissulescu <claziss (a] synopsys.com> 1959 1960 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0) 1961 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1) 1962 (RTT): Remove duplicate. 1963 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*) 1964 (PCT_CONFIG*): Remove. 1965 (D1L, D1H, D2H, D2L): Define. 1966 1967 2016-03-29 Claudiu Zissulescu <claziss (a] synopsys.com> 1968 1969 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo. 1970 1971 2016-03-29 Claudiu Zissulescu <claziss (a] synopsys.com> 1972 1973 * arc-tbl.h (invld07): Remove. 1974 * arc-ext-tbl.h: New file. 1975 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove. 1976 * arc-opc.c (arc_opcodes): Add ext-tbl include. 1977 1978 2016-03-24 Jan Kratochvil <jan.kratochvil (a] redhat.com> 1979 1980 Fix -Wstack-usage warnings. 1981 * aarch64-dis.c (print_operands): Substitute size. 1982 * aarch64-opc.c (print_register_offset_address): Substitute tblen. 1983 1984 2016-03-22 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1985 1986 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order 1987 to get a proper diagnostic when an invalid ASR register is used. 1988 1989 2016-03-22 Nick Clifton <nickc (a] redhat.com> 1990 1991 * configure: Regenerate. 1992 1993 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com> 1994 1995 * arc-nps400-tbl.h: New file. 1996 * arc-opc.c: Add top level comment. 1997 (insert_nps_3bit_dst): New function. 1998 (extract_nps_3bit_dst): New function. 1999 (insert_nps_3bit_src2): New function. 2000 (extract_nps_3bit_src2): New function. 2001 (insert_nps_bitop_size): New function. 2002 (extract_nps_bitop_size): New function. 2003 (arc_flag_operands): Add nps400 entries. 2004 (arc_flag_classes): Add nps400 entries. 2005 (arc_operands): Add nps400 entries. 2006 (arc_opcodes): Add nps400 include. 2007 2008 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com> 2009 2010 * arc-opc.c (arc_flag_classes): Convert all flag classes to use 2011 the new class enum values. 2012 2013 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com> 2014 2015 * arc-dis.c (print_insn_arc): Handle nps400. 2016 2017 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com> 2018 2019 * arc-opc.c (BASE): Delete. 2020 2021 2016-03-18 Nick Clifton <nickc (a] redhat.com> 2022 2023 PR target/19721 2024 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand 2025 of MOV insn that aliases an ORR insn. 2026 2027 2016-03-16 Jiong Wang <jiong.wang (a] arm.com> 2028 2029 * arm-dis.c (neon_opcodes): Support new FP16 instructions. 2030 2031 2016-03-07 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org> 2032 2033 * mcore-opc.h: Add const qualifiers. 2034 * microblaze-opc.h (struct op_code_struct): Likewise. 2035 * sh-opc.h: Likewise. 2036 * tic4x-dis.c (tic4x_print_indirect): Likewise. 2037 (tic4x_print_op): Likewise. 2038 2039 2016-03-02 Alan Modra <amodra (a] gmail.com> 2040 2041 * or1k-desc.h: Regenerate. 2042 * fr30-ibld.c: Regenerate. 2043 * rl78-decode.c: Regenerate. 2044 2045 2016-03-01 Nick Clifton <nickc (a] redhat.com> 2046 2047 PR target/19747 2048 * rl78-dis.c (print_insn_rl78_common): Fix typo. 2049 2050 2016-02-24 Renlin Li <renlin.li (a] arm.com> 2051 2052 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries. 2053 (print_insn_coprocessor): Support fp16 instructions. 2054 2055 2016-02-24 Renlin Li <renlin.li (a] arm.com> 2056 2057 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm, 2058 vminnm, vrint(mpna). 2059 2060 2016-02-24 Renlin Li <renlin.li (a] arm.com> 2061 2062 * arm-dis.c (print_insn_coprocessor): Check co-processor number for 2063 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2. 2064 2065 2016-02-15 H.J. Lu <hongjiu.lu (a] intel.com> 2066 2067 * i386-dis.c (print_insn): Parenthesize expression to prevent 2068 truncated addresses. 2069 (OP_J): Likewise. 2070 2071 2016-02-10 Claudiu Zissulescu <claziss (a] synopsys.com> 2072 Janek van Oirschot <jvanoirs (a] synopsys.com> 2073 2074 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New 2075 variable. 2076 2077 2016-02-04 Nick Clifton <nickc (a] redhat.com> 2078 2079 PR target/19561 2080 * msp430-dis.c (print_insn_msp430): Add a special case for 2081 decoding an RRC instruction with the ZC bit set in the extension 2082 word. 2083 2084 2016-02-02 Andrew Burgess <andrew.burgess (a] embecosm.com> 2085 2086 * cgen-ibld.in (insert_normal): Rework calculation of shift. 2087 * epiphany-ibld.c: Regenerate. 2088 * fr30-ibld.c: Regenerate. 2089 * frv-ibld.c: Regenerate. 2090 * ip2k-ibld.c: Regenerate. 2091 * iq2000-ibld.c: Regenerate. 2092 * lm32-ibld.c: Regenerate. 2093 * m32c-ibld.c: Regenerate. 2094 * m32r-ibld.c: Regenerate. 2095 * mep-ibld.c: Regenerate. 2096 * mt-ibld.c: Regenerate. 2097 * or1k-ibld.c: Regenerate. 2098 * xc16x-ibld.c: Regenerate. 2099 * xstormy16-ibld.c: Regenerate. 2100 2101 2016-02-02 Andrew Burgess <andrew.burgess (a] embecosm.com> 2102 2103 * epiphany-dis.c: Regenerated from latest cpu files. 2104 2105 2016-02-01 Michael McConville <mmcco (a] mykolab.com> 2106 2107 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask 2108 test bit. 2109 2110 2016-01-25 Renlin Li <renlin.li (a] arm.com> 2111 2112 * arm-dis.c (mapping_symbol_for_insn): New function. 2113 (find_ifthen_state): Call mapping_symbol_for_insn(). 2114 2115 2016-01-20 Matthew Wahab <matthew.wahab (a] arm.com> 2116 2117 * aarch64-opc.c (operand_general_constraint_met_p): Check validity 2118 of MSR UAO immediate operand. 2119 2120 2016-01-18 Maciej W. Rozycki <macro (a] imgtec.com> 2121 2122 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS 2123 instruction support. 2124 2125 2016-01-17 Alan Modra <amodra (a] gmail.com> 2126 2127 * configure: Regenerate. 2128 2129 2016-01-14 Nick Clifton <nickc (a] redhat.com> 2130 2131 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw 2132 instructions that can support stack pointer operations. 2133 * rl78-decode.c: Regenerate. 2134 * rl78-dis.c: Fix display of stack pointer in MOVW based 2135 instructions. 2136 2137 2016-01-14 Matthew Wahab <matthew.wahab (a] arm.com> 2138 2139 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals 2140 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1, 2141 erxtatus_el1 and erxaddr_el1. 2142 2143 2016-01-12 Matthew Wahab <matthew.wahab (a] arm.com> 2144 2145 * arm-dis.c (arm_opcodes): Add "esb". 2146 (thumb_opcodes): Likewise. 2147 2148 2016-01-11 Peter Bergner <bergner (a] vnet.ibm.com> 2149 2150 * ppc-opc.c <xscmpnedp>: Delete. 2151 <xvcmpnedp>: Likewise. 2152 <xvcmpnedp.>: Likewise. 2153 <xvcmpnesp>: Likewise. 2154 <xvcmpnesp.>: Likewise. 2155 2156 2016-01-08 Andreas Schwab <schwab (a] linux-m68k.org> 2157 2158 PR gas/13050 2159 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in 2160 addition to ISA_A. 2161 2162 2016-01-01 Alan Modra <amodra (a] gmail.com> 2163 2164 Update year range in copyright notice of all files. 2165 2166 For older changes see ChangeLog-2015 2167 2169 Copyright (C) 2016 Free Software Foundation, Inc. 2170 2171 Copying and distribution of this file, with or without modification, 2172 are permitted in any medium without royalty provided the copyright 2173 notice and this notice are preserved. 2174 2175 Local Variables: 2176 mode: change-log 2177 left-margin: 8 2178 fill-column: 74 2179 version-control: never 2180 End: 2181
Indexes created Sat May 30 00:24:47 UTC 2026