1 2019-12-30 Alan Modra <amodra (a] gmail.com> 2 3 PR 25319 4 * tic4x-dis.c (tic4x_print_cond): Correct order of xcalloc args. 5 6 2019-12-29 Alan Modra <amodra (a] gmail.com> 7 8 * sparc-dis.c (SEX): Don't use left and right shift to sign extend. 9 (compare_opcodes): Avoid signed shift left overflow. 10 (print_insn_sparc): Likewise. 11 12 2019-12-29 Alan Modra <amodra (a] gmail.com> 13 14 PR 25319 15 * tic4x-dis.c (tic4x_print_cond): Init all of condtable. 16 17 2019-12-27 Jan Beulich <jbeulich (a] suse.com> 18 19 * i386-dis.c (Jdqw): Define. 20 (dqw_mode): Adjust associated comment. 21 (rm_table): Use Jdqw for XBEGIN. 22 (OP_J): Handle dqw_mode. 23 24 2019-12-27 Jan Beulich <jbeulich (a] suse.com> 25 26 * i386-gen.c (process_i386_operand_type): Don't set Disp32 for 27 Cpu64 templates. 28 * i386-opc.tbl (mov): Fold two templates. 29 (jcxz, jecxz, jrcxz, loop, loope, loopne, loopnz, loopz): Drop 30 Disp16, Disp32, and Disp32S. 31 (xbegin): Add Disp32S. 32 * i386-tbl.h: Re-generate. 33 34 2019-12-26 Alan Modra <amodra (a] gmail.com> 35 36 * crx-dis.c (get_number_of_operands): Don't access operands[] 37 out of bounds. 38 39 2019-12-26 Alan Modra <amodra (a] gmail.com> 40 41 * v850-dis.c (disassemble): Avoid signed overflow. Don't use 42 long vars when unsigned int will do. 43 44 2019-12-24 Alan Modra <amodra (a] gmail.com> 45 46 * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var. 47 48 2019-12-23 Jan Beulich <jbeulich (a] suse.com> 49 50 * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces" 51 to "blanks". 52 * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C(). 53 54 2019-12-23 Alan Modra <amodra (a] gmail.com> 55 56 * score-dis.c (print_insn_score32): Avoid signed overflow. 57 (print_insn_score48): Likewise. Don't cast to int when printing 58 hex values. 59 60 2019-12-23 Alan Modra <amodra (a] gmail.com> 61 62 * iq2000-ibld.c: Regenerate. 63 64 2019-12-23 Alan Modra <amodra (a] gmail.com> 65 66 * d30v-dis.c (extract_value): Make num param a uint64_t, constify 67 oper. Use unsigned vars. 68 (print_insn): Make num var uint64_t. Constify oper and remove now 69 unnecessary casts on extract_value calls. 70 (print_insn_d30v): Use unsigned vars. Adjust printf formats. 71 72 2019-12-23 Alan Modra <amodra (a] gmail.com> 73 74 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts. 75 Catch value overflow. Sign extend only on terminating byte. 76 77 2019-12-20 Alan Modra <amodra (a] gmail.com> 78 79 PR 25281 80 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY 81 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word 82 printed. Print .word in more cases. 83 84 2019-12-20 Alan Modra <amodra (a] gmail.com> 85 86 * or1k-ibld.c: Regenerate. 87 88 2019-12-20 Alan Modra <amodra (a] gmail.com> 89 90 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use 91 unsigned variables. 92 93 2019-12-20 Alan Modra <amodra (a] gmail.com> 94 95 * m68hc11-dis.c (read_memory): Delete forward decls. 96 (print_indexed_operand, print_insn): Likewise. 97 (print_indexed_operand): Formatting. Don't rely on short being 98 exactly 16 bits, make sign extension explicit. 99 (print_insn): Likewise. Avoid signed overflow. 100 101 2019-12-19 Alan Modra <amodra (a] gmail.com> 102 103 * vax-dis.c (print_insn_mode): Stop index mode recursion. 104 105 2019-12-19 Dr N.W. Filardo <nwf20 (a] cam.ac.uk> 106 107 PR 25277 108 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and 109 fdiv with "mbi_". 110 * microblaze-opc.h (opcodes): Adjust to suit. 111 112 2019-12-18 Alan Modra <amodra (a] gmail.com> 113 114 * alpha-opc.c (OP): Avoid signed overflow. 115 * arm-dis.c (print_insn): Likewise. 116 * mcore-dis.c (print_insn_mcore): Likewise. 117 * pj-dis.c (get_int): Likewise. 118 * ppc-opc.c (EBD15, EBD15BI): Likewise. 119 * score7-dis.c (s7_print_insn): Likewise. 120 * tic30-dis.c (print_insn_tic30): Likewise. 121 * v850-opc.c (insert_SELID): Likewise. 122 * vax-dis.c (print_insn_vax): Likewise. 123 * arc-ext.c (create_map): Likewise. 124 (struct ExtAuxRegister): Make "address" field unsigned int. 125 (arcExtMap_auxRegName): Pass unsigned address. 126 (dump_ARC_extmap): Adjust. 127 * arc-ext.h (arcExtMap_auxRegName): Update prototype. 128 129 2019-12-17 Alan Modra <amodra (a] gmail.com> 130 131 * visium-dis.c (print_insn_visium): Avoid signed overflow. 132 133 2019-12-17 Alan Modra <amodra (a] gmail.com> 134 135 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow. 136 (value_fit_unsigned_field_p): Likewise. 137 (aarch64_wide_constant_p): Likewise. 138 (operand_general_constraint_met_p): Likewise. 139 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype. 140 141 2019-12-17 Alan Modra <amodra (a] gmail.com> 142 143 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow. 144 (print_insn_nds32): Use uint64_t for "given" and "given1". 145 146 2019-12-17 Alan Modra <amodra (a] gmail.com> 147 148 * tic80-dis.c: Delete file. 149 * tic80-opc.c: Delete file. 150 * disassemble.c: Remove tic80 support. 151 * disassemble.h: Likewise. 152 * Makefile.am: Likewise. 153 * configure.ac: Likewise. 154 * Makefile.in: Regenerate. 155 * configure: Regenerate. 156 * po/POTFILES.in: Regenerate. 157 158 2019-12-17 Alan Modra <amodra (a] gmail.com> 159 160 * bpf-ibld.c: Regenerate. 161 162 2019-12-16 Alan Modra <amodra (a] gmail.com> 163 164 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without 165 conditional. 166 (aarch64_ext_imm): Avoid signed overflow. 167 168 2019-12-16 Alan Modra <amodra (a] gmail.com> 169 170 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow. 171 172 2019-12-16 Alan Modra <amodra (a] gmail.com> 173 174 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow 175 176 2019-12-16 Alan Modra <amodra (a] gmail.com> 177 178 * xstormy16-ibld.c: Regenerate. 179 180 2019-12-16 Alan Modra <amodra (a] gmail.com> 181 182 * score-dis.c (print_insn_score16): Move rpush/rpop imm field 183 value adjustment so that it doesn't affect reg field too. 184 185 2019-12-16 Alan Modra <amodra (a] gmail.com> 186 187 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow. 188 (get_number_of_operands, getargtype, getbits, getregname), 189 (getcopregname, getprocregname, gettrapstring, getcinvstring), 190 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask), 191 (powerof2, match_opcode, make_instruction, print_arguments), 192 (print_arg): Delete forward declarations, moving static to.. 193 (getregname, getcopregname, getregliststring): ..these definitions. 194 (build_mask): Return unsigned int mask. 195 (match_opcode): Use unsigned int vars. 196 197 2019-12-16 Alan Modra <amodra (a] gmail.com> 198 199 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow. 200 201 2019-12-16 Alan Modra <amodra (a] gmail.com> 202 203 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls. 204 (struct objdump_disasm_info): Delete. 205 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of 206 N32_IMMS to unsigned before shifting left. 207 208 2019-12-16 Alan Modra <amodra (a] gmail.com> 209 210 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value. 211 (print_insn_moxie): Remove unnecessary cast. 212 213 2019-12-12 Alan Modra <amodra (a] gmail.com> 214 215 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary 216 mask. 217 218 2019-12-11 Alan Modra <amodra (a] gmail.com> 219 220 * arc-dis.c (BITS): Don't truncate high bits with shifts. 221 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts. 222 * tic54x-dis.c (print_instruction): Likewise. 223 * tilegx-opc.c (parse_insn_tilegx): Likewise. 224 * tilepro-opc.c (parse_insn_tilepro): Likewise. 225 * visium-dis.c (disassem_class0): Likewise. 226 * pdp11-dis.c (sign_extend): Likewise. 227 (SIGN_BITS): Delete. 228 * epiphany-ibld.c: Regenerate. 229 * lm32-ibld.c: Regenerate. 230 * m32c-ibld.c: Regenerate. 231 232 2019-12-11 Alan Modra <amodra (a] gmail.com> 233 234 * ns32k-dis.c (sign_extend): Correct last patch. 235 236 2019-12-11 Alan Modra <amodra (a] gmail.com> 237 238 * vax-dis.c (NEXTLONG): Avoid signed overflow. 239 240 2019-12-11 Alan Modra <amodra (a] gmail.com> 241 242 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't 243 sign extend using shifts. 244 245 2019-12-11 Alan Modra <amodra (a] gmail.com> 246 247 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow. 248 249 2019-12-11 Alan Modra <amodra (a] gmail.com> 250 251 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault 252 on NULL registertable entry. 253 (tic4x_hash_opcode): Use unsigned arithmetic. 254 255 2019-12-11 Alan Modra <amodra (a] gmail.com> 256 257 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow. 258 259 2019-12-11 Alan Modra <amodra (a] gmail.com> 260 261 * ns32k-dis.c (bit_extract): Use unsigned arithmetic. 262 (bit_extract_simple, sign_extend): Likewise. 263 264 2019-12-11 Alan Modra <amodra (a] gmail.com> 265 266 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31. 267 268 2019-12-11 Alan Modra <amodra (a] gmail.com> 269 270 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts. 271 272 2019-12-11 Alan Modra <amodra (a] gmail.com> 273 274 * m68k-dis.c (COERCE32): Cast value first. 275 (NEXTLONG, NEXTULONG): Avoid signed overflow. 276 277 2019-12-11 Alan Modra <amodra (a] gmail.com> 278 279 * h8300-dis.c (extract_immediate): Avoid signed overflow. 280 (bfd_h8_disassemble): Likewise. 281 282 2019-12-11 Alan Modra <amodra (a] gmail.com> 283 284 * d30v-dis.c (print_insn): Make opind unsigned. Don't access 285 past end of operands array. 286 287 2019-12-11 Alan Modra <amodra (a] gmail.com> 288 289 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed 290 overflow when collecting bytes of a number. 291 292 2019-12-11 Alan Modra <amodra (a] gmail.com> 293 294 * cris-dis.c (print_with_operands): Avoid signed integer 295 overflow when collecting bytes of a 32-bit integer. 296 297 2019-12-11 Alan Modra <amodra (a] gmail.com> 298 299 * cr16-dis.c (EXTRACT, SBM): Rewrite. 300 (cr16_match_opcode): Delete duplicate bcond test. 301 302 2019-12-11 Alan Modra <amodra (a] gmail.com> 303 304 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete. 305 (SIGNBIT): New. 306 (MASKBITS, SIGNEXTEND): Rewrite. 307 (fmtconst): Don't use ? expression now that SIGNEXTEND uses 308 unsigned arithmetic, instead assign result of SIGNEXTEND back 309 to x. 310 (fmtconst_val): Use 1u in shift expression. 311 312 2019-12-11 Alan Modra <amodra (a] gmail.com> 313 314 * arc-dis.c (find_format_from_table): Use ull constant when 315 shifting by up to 32. 316 317 2019-12-11 Alan Modra <amodra (a] gmail.com> 318 319 PR 25270 320 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return 321 false when field is zero for sve_size_tsz_bhs. 322 323 2019-12-11 Alan Modra <amodra (a] gmail.com> 324 325 * epiphany-ibld.c: Regenerate. 326 327 2019-12-10 Alan Modra <amodra (a] gmail.com> 328 329 PR 24960 330 * disassemble.c (disassemble_free_target): New function. 331 332 2019-12-10 Alan Modra <amodra (a] gmail.com> 333 334 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data. 335 * disassemble.c (disassemble_init_for_target): Likewise. 336 * bpf-dis.c: Regenerate. 337 * epiphany-dis.c: Regenerate. 338 * fr30-dis.c: Regenerate. 339 * frv-dis.c: Regenerate. 340 * ip2k-dis.c: Regenerate. 341 * iq2000-dis.c: Regenerate. 342 * lm32-dis.c: Regenerate. 343 * m32c-dis.c: Regenerate. 344 * m32r-dis.c: Regenerate. 345 * mep-dis.c: Regenerate. 346 * mt-dis.c: Regenerate. 347 * or1k-dis.c: Regenerate. 348 * xc16x-dis.c: Regenerate. 349 * xstormy16-dis.c: Regenerate. 350 351 2019-12-10 Alan Modra <amodra (a] gmail.com> 352 353 * ppc-dis.c (private): Delete variable. 354 (get_powerpc_dialect): Don't segfault on NULL info->private_data. 355 (powerpc_init_dialect): Don't use global private. 356 357 2019-12-10 Alan Modra <amodra (a] gmail.com> 358 359 * s12z-opc.c: Formatting. 360 361 2019-12-08 Alan Modra <amodra (a] gmail.com> 362 363 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid 364 registers. 365 366 2019-12-05 Jan Beulich <jbeulich (a] suse.com> 367 368 * aarch64-tbl.h (aarch64_feature_crypto, 369 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN, 370 CRYPTO_V8_2_INSN): Delete. 371 372 2019-12-05 Alan Modra <amodra (a] gmail.com> 373 374 PR 25249 375 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define. 376 (struct string_buf): New. 377 (strbuf): New function. 378 (get_field): Use strbuf rather than strdup of local temp. 379 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise. 380 (get_field_rfsl, get_field_imm15): Likewise. 381 (get_field_rd, get_field_r1, get_field_r2): Update macros. 382 (get_field_special): Likewise. Don't strcpy spr. Formatting. 383 (print_insn_microblaze): Formatting. Init and pass string_buf to 384 get_field functions. 385 386 2019-12-04 Jan Beulich <jbeulich (a] suse.com> 387 388 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf. 389 * i386-tbl.h: Re-generate. 390 391 2019-12-04 Jan Beulich <jbeulich (a] suse.com> 392 393 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri. 394 395 2019-12-04 Jan Beulich <jbeulich (a] suse.com> 396 397 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only 398 forms. 399 (xbegin): Drop DefaultSize. 400 * i386-tbl.h: Re-generate. 401 402 2019-11-22 Mihail Ionescu <mihail.ionescu (a] arm.com> 403 404 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes): 405 Change the coproc CRC conditions to use the extension 406 feature set, second word, base on ARM_EXT2_CRC. 407 408 2019-11-14 Jan Beulich <jbeulich (a] suse.com> 409 410 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms. 411 * i386-tbl.h: Re-generate. 412 413 2019-11-14 Jan Beulich <jbeulich (a] suse.com> 414 415 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte, 416 JumpInterSegment, and JumpAbsolute entries. 417 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT, 418 JUMP_ABSOLUTE): Define. 419 (struct i386_opcode_modifier): Extend jump field to 3 bits. 420 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute 421 fields. 422 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute, 423 JumpInterSegment): Define. 424 * i386-tbl.h: Re-generate. 425 426 2019-11-14 Jan Beulich <jbeulich (a] suse.com> 427 428 * i386-gen.c (operand_type_init): Remove 429 OPERAND_TYPE_JUMPABSOLUTE entry. 430 (opcode_modifiers): Add JumpAbsolute entry. 431 (operand_types): Remove JumpAbsolute entry. 432 * i386-opc.h (JumpAbsolute): Move between enums. 433 (struct i386_opcode_modifier): Add jumpabsolute field. 434 (union i386_operand_type): Remove jumpabsolute field. 435 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute. 436 * i386-init.h, i386-tbl.h: Re-generate. 437 438 2019-11-14 Jan Beulich <jbeulich (a] suse.com> 439 440 * i386-gen.c (opcode_modifiers): Add AnySize entry. 441 (operand_types): Remove AnySize entry. 442 * i386-opc.h (AnySize): Move between enums. 443 (struct i386_opcode_modifier): Add anysize field. 444 (OTUnused): Un-comment. 445 (union i386_operand_type): Remove anysize field. 446 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0, 447 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, 448 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move 449 AnySize. 450 * i386-tbl.h: Re-generate. 451 452 2019-11-12 Nelson Chu <nelson.chu (a] sifive.com> 453 454 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with 455 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we 456 use the floating point register (FPR). 457 458 2019-11-12 Mihail Ionescu <mihail.ionescu (a] arm.com> 459 460 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with 461 cmode 1101. 462 (is_mve_encoding_conflict): Update cmode conflict checks for 463 MVE_VMVN_IMM. 464 465 2019-11-12 Jan Beulich <jbeulich (a] suse.com> 466 467 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG 468 entry. 469 (operand_types): Remove EsSeg entry. 470 (main): Replace stale use of OTMax. 471 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define. 472 (struct i386_opcode_modifier): Expand isstring field to 2 bits. 473 (EsSeg): Delete. 474 (OTUnused): Comment out. 475 (union i386_operand_type): Remove esseg field. 476 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define. 477 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0. 478 (ins, movs, smov, movsd): Add IsStringEsOpOp1. 479 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1. 480 * i386-init.h, i386-tbl.h: Re-generate. 481 482 2019-11-12 Jan Beulich <jbeulich (a] suse.com> 483 484 * i386-gen.c (operand_instances): Add RegB entry. 485 * i386-opc.h (enum operand_instance): Add RegB. 486 * i386-opc.tbl (RegC, RegD, RegB): Define. 487 (Acc, ShiftCount, InOutPortReg): Adjust definitions. 488 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero, 489 monitorx, mwaitx): Drop ImmExt and convert encodings 490 accordingly. 491 * i386-reg.tbl (ecx, rcx): Add Instance=RegC. 492 (edx, rdx): Add Instance=RegD. 493 (ebx, rbx): Add Instance=RegB. 494 * i386-tbl.h: Re-generate. 495 496 2019-11-12 Jan Beulich <jbeulich (a] suse.com> 497 498 * i386-gen.c (operand_type_init): Adjust 499 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT, 500 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16, 501 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries. 502 (operand_instances): New. 503 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries. 504 (output_operand_type): New parameter "instance". Process it. 505 (process_i386_operand_type): New local variable "instance". 506 (main): Adjust static assertions. 507 * i386-opc.h (INSTANCE_WIDTH): Define. 508 (enum operand_instance): New. 509 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance. 510 (union i386_operand_type): Replace acc, inoutportreg, and 511 shiftcount by instance. 512 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define. 513 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)): 514 Add Instance=. 515 * i386-init.h, i386-tbl.h: Re-generate. 516 517 2019-11-11 Jan Beulich <jbeulich (a] suse.com> 518 519 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's 520 smaxp/sminp entries' "tied_operand" field to 2. 521 522 2019-11-11 Jan Beulich <jbeulich (a] suse.com> 523 524 * aarch64-opc.c (operand_general_constraint_met_p): Replace 525 "index" local variable by that of the already existing "num". 526 527 2019-11-08 H.J. Lu <hongjiu.lu (a] intel.com> 528 529 PR gas/25167 530 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd. 531 * i386-tbl.h: Regenerated. 532 533 2019-11-08 Jan Beulich <jbeulich (a] suse.com> 534 535 * i386-gen.c (operand_type_init): Add Class= to 536 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up 537 OPERAND_TYPE_REGBND entry. 538 (operand_classes): Add RegMask and RegBND entries. 539 (operand_types): Drop RegMask and RegBND entry. 540 * i386-opc.h (enum operand_class): Add RegMask and RegBND. 541 (RegMask, RegBND): Delete. 542 (union i386_operand_type): Remove regmask and regbnd fields. 543 * i386-opc.tbl (RegMask, RegBND): Define. 544 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by 545 Class=RegBND. 546 * i386-init.h, i386-tbl.h: Re-generate. 547 548 2019-11-08 Jan Beulich <jbeulich (a] suse.com> 549 550 * i386-gen.c (operand_type_init): Add Class= to 551 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and 552 OPERAND_TYPE_REGZMM entries. 553 (operand_classes): Add RegMMX and RegSIMD entries. 554 (operand_types): Drop RegMMX and RegSIMD entries. 555 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD. 556 (RegMMX, RegSIMD): Delete. 557 (union i386_operand_type): Remove regmmx and regsimd fields. 558 * i386-opc.tbl (RegMMX): Define. 559 (RegXMM, RegYMM, RegZMM): Add Class=. 560 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by 561 Class=RegSIMD. 562 * i386-init.h, i386-tbl.h: Re-generate. 563 564 2019-11-08 Jan Beulich <jbeulich (a] suse.com> 565 566 * i386-gen.c (operand_type_init): Add Class= to 567 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG 568 entries. 569 (operand_classes): Add RegCR, RegDR, and RegTR entries. 570 (operand_types): Drop Control, Debug, and Test entries. 571 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR. 572 (Control, Debug, Test): Delete. 573 (union i386_operand_type): Remove control, debug, and test 574 fields. 575 * i386-opc.tbl (Control, Debug, Test): Define. 576 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by 577 Class=RegDR, and Test by Class=RegTR. 578 * i386-init.h, i386-tbl.h: Re-generate. 579 580 2019-11-08 Jan Beulich <jbeulich (a] suse.com> 581 582 * i386-gen.c (operand_type_init): Add Class= to 583 OPERAND_TYPE_SREG entry. 584 (operand_classes): Add SReg entry. 585 (operand_types): Drop SReg entry. 586 * i386-opc.h (enum operand_class): Add SReg. 587 (SReg): Delete. 588 (union i386_operand_type): Remove sreg field. 589 * i386-opc.tbl (SReg): Define. 590 * i386-reg.tbl: Replace SReg by Class=SReg. 591 * i386-init.h, i386-tbl.h: Re-generate. 592 593 2019-11-08 Jan Beulich <jbeulich (a] suse.com> 594 595 * i386-gen.c (operand_type_init): Add Class=. New 596 OPERAND_TYPE_ANYIMM entry. 597 (operand_classes): New. 598 (operand_types): Drop Reg entry. 599 (output_operand_type): New parameter "class". Process it. 600 (process_i386_operand_type): New local variable "class". 601 (main): Adjust static assertions. 602 * i386-opc.h (CLASS_WIDTH): Define. 603 (enum operand_class): New. 604 (Reg): Replace by Class. Adjust comment. 605 (union i386_operand_type): Replace reg by class. 606 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add 607 Class=. 608 * i386-reg.tbl: Replace Reg by Class=Reg. 609 * i386-init.h: Re-generate. 610 611 2019-11-07 Mihail Ionescu <mihail.ionescu (a] arm.com> 612 613 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions. 614 (aarch64_opcode_table): Add data gathering hint mnemonic. 615 * opcodes/aarch64-dis-2.c: Account for new instruction. 616 617 2019-11-07 Mihail Ionescu <mihail.ionescu (a] arm.com> 618 619 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions. 620 621 622 2019-11-07 Mihail Ionescu <mihail.ionescu (a] arm.com> 623 624 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve, 625 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm, 626 aarch64_feature_f64mm): New feature sets. 627 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN, 628 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply 629 instructions. 630 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set 631 macros. 632 (QL_MMLA64, OP_SVE_SBB): New qualifiers. 633 (OP_SVE_QQQ): New qualifier. 634 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC, 635 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support 636 the movprfx constraint. 637 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32. 638 (aarch64_opcode_table): Define new instructions smmla, 639 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod, 640 uzip{1/2}, trn{1/2}. 641 * aarch64-opc.c (operand_general_constraint_met_p): Handle 642 AARCH64_OPND_SVE_ADDR_RI_S4x32. 643 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32. 644 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode): 645 Account for new instructions. 646 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new 647 S4x32 operand. 648 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand. 649 650 2019-11-07 Mihail Ionescu <mihail.ionescu (a] arm.com> 651 2019-11-07 Matthew Malcomson <matthew.malcomson (a] arm.com> 652 653 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with 654 Armv8.6-A. 655 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}. 656 (neon_opcodes): Add bfloat SIMD instructions. 657 (print_insn_coprocessor): Add new control character %b to print 658 condition code without checking cp_num. 659 (print_insn_neon): Account for BFloat16 instructions that have no 660 special top-byte handling. 661 662 2019-11-07 Mihail Ionescu <mihail.ionescu (a] arm.com> 663 2019-11-07 Matthew Malcomson <matthew.malcomson (a] arm.com> 664 665 * arm-dis.c (print_insn_coprocessor, 666 print_insn_generic_coprocessor): Create wrapper functions around 667 the implementation of the print_insn_coprocessor control codes. 668 (print_insn_coprocessor_1): Original print_insn_coprocessor 669 function that now takes which array to look at as an argument. 670 (print_insn_arm): Use both print_insn_coprocessor and 671 print_insn_generic_coprocessor. 672 (print_insn_thumb32): As above. 673 674 2019-11-07 Mihail Ionescu <mihail.ionescu (a] arm.com> 675 2019-11-07 Matthew Malcomson <matthew.malcomson (a] arm.com> 676 677 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H 678 in reglane special case. 679 * aarch64-dis-2.c (aarch64_opcode_lookup_1, 680 aarch64_find_next_opcode): Account for new instructions. 681 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H 682 in reglane special case. 683 * aarch64-opc.c (struct operand_qualifier_data): Add data for 684 new AARCH64_OPND_QLF_S_2H qualifier. 685 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2, 686 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers. 687 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature 688 sets. 689 (BFLOAT_SVE, BFLOAT): New feature set macros. 690 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16 691 instructions. 692 (aarch64_opcode_table): Define new instructions bfdot, 693 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t] 694 bfcvtn2, bfcvt. 695 696 2019-11-07 Mihail Ionescu <mihail.ionescu (a] arm.com> 697 2019-11-07 Matthew Malcomson <matthew.malcomson (a] arm.com> 698 699 * aarch64-tbl.h (ARMV8_6): New macro. 700 701 2019-11-07 Jan Beulich <jbeulich (a] suse.com> 702 703 * i386-dis.c (prefix_table): Add mcommit. 704 (rm_table): Add rdpru. 705 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add 706 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries. 707 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries. 708 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New. 709 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields. 710 * i386-opc.tbl (mcommit, rdpru): New. 711 * i386-init.h, i386-tbl.h: Re-generate. 712 713 2019-11-07 Jan Beulich <jbeulich (a] suse.com> 714 715 * i386-dis.c (OP_Mwait): Drop local variable "names", use 716 "names32" instead. 717 (OP_Monitor): Drop local variable "op1_names", re-purpose 718 "names" for it instead, and replace former "names" uses by 719 "names32" ones. 720 721 2019-11-07 Jan Beulich <jbeulich (a] suse.com> 722 723 PR/gas 25167 724 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from 725 operand-less forms. 726 * opcodes/i386-tbl.h: Re-generate. 727 728 2019-11-05 Jan Beulich <jbeulich (a] suse.com> 729 730 * i386-dis.c (OP_Mwaitx): Delete. 731 (prefix_table): Use OP_Mwait for mwaitx entry. 732 (OP_Mwait): Also handle mwaitx. 733 734 2019-11-05 Jan Beulich <jbeulich (a] suse.com> 735 736 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2, 737 PREFIX_0F01_REG_7_MOD_3_RM_3): New. 738 (prefix_table): Add respective entries. 739 (rm_table): Link to those entries. 740 741 2019-11-05 Jan Beulich <jbeulich (a] suse.com> 742 743 * i386-dis.c (REG_0F1C_MOD_0): Rename to ... 744 (REG_0F1C_P_0_MOD_0): ... this. 745 (REG_0F1E_MOD_3): Rename to ... 746 (REG_0F1E_P_1_MOD_3): ... this. 747 (RM_0F01_REG_5): Rename to ... 748 (RM_0F01_REG_5_MOD_3): ... this. 749 (RM_0F01_REG_7): Rename to ... 750 (RM_0F01_REG_7_MOD_3): ... this. 751 (RM_0F1E_MOD_3_REG_7): Rename to ... 752 (RM_0F1E_P_1_MOD_3_REG_7): ... this. 753 (RM_0FAE_REG_6): Rename to ... 754 (RM_0FAE_REG_6_MOD_3_P_0): ... this. 755 (RM_0FAE_REG_7): Rename to ... 756 (RM_0FAE_REG_7_MOD_3): ... this. 757 (PREFIX_MOD_0_0F01_REG_5): Rename to ... 758 (PREFIX_0F01_REG_5_MOD_0): ... this. 759 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ... 760 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this. 761 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ... 762 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this. 763 (PREFIX_0FAE_REG_0): Rename to ... 764 (PREFIX_0FAE_REG_0_MOD_3): ... this. 765 (PREFIX_0FAE_REG_1): Rename to ... 766 (PREFIX_0FAE_REG_1_MOD_3): ... this. 767 (PREFIX_0FAE_REG_2): Rename to ... 768 (PREFIX_0FAE_REG_2_MOD_3): ... this. 769 (PREFIX_0FAE_REG_3): Rename to ... 770 (PREFIX_0FAE_REG_3_MOD_3): ... this. 771 (PREFIX_MOD_0_0FAE_REG_4): Rename to ... 772 (PREFIX_0FAE_REG_4_MOD_0): ... this. 773 (PREFIX_MOD_3_0FAE_REG_4): Rename to ... 774 (PREFIX_0FAE_REG_4_MOD_3): ... this. 775 (PREFIX_MOD_0_0FAE_REG_5): Rename to ... 776 (PREFIX_0FAE_REG_5_MOD_0): ... this. 777 (PREFIX_MOD_3_0FAE_REG_5): Rename to ... 778 (PREFIX_0FAE_REG_5_MOD_3): ... this. 779 (PREFIX_MOD_0_0FAE_REG_6): Rename to ... 780 (PREFIX_0FAE_REG_6_MOD_0): ... this. 781 (PREFIX_MOD_1_0FAE_REG_6): Rename to ... 782 (PREFIX_0FAE_REG_6_MOD_3): ... this. 783 (PREFIX_0FAE_REG_7): Rename to ... 784 (PREFIX_0FAE_REG_7_MOD_0): ... this. 785 (PREFIX_MOD_0_0FC3): Rename to ... 786 (PREFIX_0FC3_MOD_0): ... this. 787 (PREFIX_MOD_0_0FC7_REG_6): Rename to ... 788 (PREFIX_0FC7_REG_6_MOD_0): ... this. 789 (PREFIX_MOD_3_0FC7_REG_6): Rename to ... 790 (PREFIX_0FC7_REG_6_MOD_3): ... this. 791 (PREFIX_MOD_3_0FC7_REG_7): Rename to ... 792 (PREFIX_0FC7_REG_7_MOD_3): ... this. 793 (reg_table, prefix_table, mod_table, rm_table): Adjust 794 accordingly. 795 796 2019-11-04 Nick Clifton <nickc (a] redhat.com> 797 798 * v850-dis.c (get_v850_sreg_name): New function. Returns the name 799 of a v850 system register. Move the v850_sreg_names array into 800 this function. 801 (get_v850_reg_name): Likewise for ordinary register names. 802 (get_v850_vreg_name): Likewise for vector register names. 803 (get_v850_cc_name): Likewise for condition codes. 804 * get_v850_float_cc_name): Likewise for floating point condition 805 codes. 806 (get_v850_cacheop_name): Likewise for cache-ops. 807 (get_v850_prefop_name): Likewise for pref-ops. 808 (disassemble): Use the new accessor functions. 809 810 2019-10-30 Delia Burduv <delia.burduv (a] arm.com> 811 812 * aarch64-opc.c (print_immediate_offset_address): Don't print the 813 immediate for the writeback form of ldraa/ldrab if it is 0. 814 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10. 815 * aarch64-opc-2.c: Regenerated. 816 817 2019-10-30 Jan Beulich <jbeulich (a] suse.com> 818 819 * i386-gen.c (operand_type_shorthands): Delete. 820 (operand_type_init): Expand previous shorthands. 821 (set_bitfield_from_shorthand): Rename back to ... 822 (set_bitfield_from_cpu_flag_init): ... this. Drop processing 823 of operand_type_init[]. 824 (set_bitfield): Adjust call to the above function. 825 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg, 826 RegXMM, RegYMM, RegZMM): Define. 827 * i386-reg.tbl: Expand prior shorthands. 828 829 2019-10-30 Jan Beulich <jbeulich (a] suse.com> 830 831 * i386-gen.c (output_i386_opcode): Change order of fields 832 emitted to output. 833 * i386-opc.h (struct insn_template): Move operands field. 834 Convert extension_opcode field to unsigned short. 835 * i386-tbl.h: Re-generate. 836 837 2019-10-30 Jan Beulich <jbeulich (a] suse.com> 838 839 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses 840 of W. 841 * i386-opc.h (W): Extend comment. 842 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of 843 general purpose variants not allowing for byte operands. 844 * i386-tbl.h: Re-generate. 845 846 2019-10-29 Nick Clifton <nickc (a] redhat.com> 847 848 * tic30-dis.c (print_branch): Correct size of operand array. 849 850 2019-10-29 Nick Clifton <nickc (a] redhat.com> 851 852 * d30v-dis.c (print_insn): Check that operand index is valid 853 before attempting to access the operands array. 854 855 2019-10-29 Nick Clifton <nickc (a] redhat.com> 856 857 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when 858 locating the bit to be tested. 859 860 2019-10-29 Nick Clifton <nickc (a] redhat.com> 861 862 * s12z-dis.c (opr_emit_disassembly): Check for illegal register 863 values. 864 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES. 865 (print_insn_s12z): Check for illegal size values. 866 867 2019-10-28 Nick Clifton <nickc (a] redhat.com> 868 869 * csky-dis.c (csky_chars_to_number): Check for a negative 870 count. Use an unsigned integer to construct the return value. 871 872 2019-10-28 Nick Clifton <nickc (a] redhat.com> 873 874 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of 875 operand buffer. Set value to 15 not 13. 876 (get_register_operand): Use OPERAND_BUFFER_LEN. 877 (get_indirect_operand): Likewise. 878 (print_two_operand): Likewise. 879 (print_three_operand): Likewise. 880 (print_oar_insn): Likewise. 881 882 2019-10-28 Nick Clifton <nickc (a] redhat.com> 883 884 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters. 885 (bit_extract_simple): Likewise. 886 (bit_copy): Likewise. 887 (pirnt_insn_ns32k): Ensure that uninitialised elements in the 888 index_offset array are not accessed. 889 890 2019-10-28 Nick Clifton <nickc (a] redhat.com> 891 892 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA 893 operand. 894 895 2019-10-25 Nick Clifton <nickc (a] redhat.com> 896 897 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct 898 access to opcodes.op array element. 899 900 2019-10-23 Nick Clifton <nickc (a] redhat.com> 901 902 * rx-dis.c (get_register_name): Fix spelling typo in error 903 message. 904 (get_condition_name, get_flag_name, get_double_register_name) 905 (get_double_register_high_name, get_double_register_low_name) 906 (get_double_control_register_name, get_double_condition_name) 907 (get_opsize_name, get_size_name): Likewise. 908 909 2019-10-22 Nick Clifton <nickc (a] redhat.com> 910 911 * rx-dis.c (get_size_name): New function. Provides safe 912 access to name array. 913 (get_opsize_name): Likewise. 914 (print_insn_rx): Use the accessor functions. 915 916 2019-10-16 Nick Clifton <nickc (a] redhat.com> 917 918 * rx-dis.c (get_register_name): New function. Provides safe 919 access to name array. 920 (get_condition_name, get_flag_name, get_double_register_name) 921 (get_double_register_high_name, get_double_register_low_name) 922 (get_double_control_register_name, get_double_condition_name): 923 Likewise. 924 (print_insn_rx): Use the accessor functions. 925 926 2019-10-09 Nick Clifton <nickc (a] redhat.com> 927 928 PR 25041 929 * avr-dis.c (avr_operand): Fix construction of address for lds/sts 930 instructions. 931 932 2019-10-07 Jan Beulich <jbeulich (a] suse.com> 933 934 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize. 935 (cmpsd): Likewise. Move EsSeg to other operand. 936 * opcodes/i386-tbl.h: Re-generate. 937 938 2019-09-23 Alan Modra <amodra (a] gmail.com> 939 940 * m68k-dis.c: Include cpu-m68k.h 941 942 2019-09-23 Alan Modra <amodra (a] gmail.com> 943 944 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and 945 "elf/mips.h" earlier. 946 947 2018-09-20 Jan Beulich <jbeulich (a] suse.com> 948 949 PR gas/25012 950 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates 951 with SReg operand. 952 * i386-tbl.h: Re-generate. 953 954 2019-09-18 Alan Modra <amodra (a] gmail.com> 955 956 * arc-ext.c: Update throughout for bfd section macro changes. 957 958 2019-09-18 Simon Marchi <simon.marchi (a] polymtl.ca> 959 960 * Makefile.in: Re-generate. 961 * configure: Re-generate. 962 963 2019-09-17 Maxim Blinov <maxim.blinov (a] embecosm.com> 964 965 * riscv-opc.c (riscv_opcodes): Change subset field 966 to insn_class field for all instructions. 967 (riscv_insn_types): Likewise. 968 969 2019-09-16 Phil Blundell <pb (a] pbcl.net> 970 971 * configure: Regenerated. 972 973 2019-09-10 Miod Vallat <miod (a] online.fr> 974 975 PR 24982 976 * m68k-opc.c: Correct aliases for tdivsl and tdivul. 977 978 2019-09-09 Phil Blundell <pb (a] pbcl.net> 979 980 binutils 2.33 branch created. 981 982 2019-09-03 Nick Clifton <nickc (a] redhat.com> 983 984 PR 24961 985 * tic30-dis.c (get_indirect_operand): Check for bufcnt being 986 greater than zero before indexing via (bufcnt -1). 987 988 2019-09-03 Nick Clifton <nickc (a] redhat.com> 989 990 PR 24958 991 * mmix-dis.c (MAX_REG_NAME_LEN): Define. 992 (MAX_SPEC_REG_NAME_LEN): Define. 993 (struct mmix_dis_info): Use defined constants for array lengths. 994 (get_reg_name): New function. 995 (get_sprec_reg_name): New function. 996 (print_insn_mmix): Use new functions. 997 998 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni (a] arm.com> 999 1000 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC. 1001 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC. 1002 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction. 1003 1004 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov (a] arm.com> 1005 1006 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1, 1007 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12. 1008 (aarch64_sys_reg_supported_p): Update checks for the above. 1009 1010 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni (a] arm.com> 1011 1012 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for 1013 cases MVE_SQRSHRL and MVE_UQRSHLL. 1014 (print_insn_mve): Add case for specifier 'k' to check 1015 specific bit of the instruction. 1016 1017 2019-08-07 Phillipe Antoine <p.antoine (a] catenacyber.fr> 1018 1019 PR 24854 1020 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when 1021 encountering an unknown machine type. 1022 (print_insn_arc): Handle arc_insn_length returning 0. In error 1023 cases return -1 rather than calling abort. 1024 1025 2019-08-07 Jan Beulich <jbeulich (a] suse.com> 1026 1027 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms. 1028 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by 1029 IgnoreSize. 1030 * i386-tbl.h: Re-generate. 1031 1032 2019-08-05 Barnaby Wilks <barnaby.wilks (a] arm.com> 1033 1034 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH 1035 instructions. 1036 1037 2019-07-30 Mel Chen <mel.chen (a] sifive.com> 1038 1039 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, 1040 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. 1041 1042 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, 1043 fscsr. 1044 1045 2019-07-24 Claudiu Zissulescu <claziss (a] synopsys.com> 1046 1047 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, 1048 and MPY class instructions. 1049 (parse_option): Add nps400 option. 1050 (print_arc_disassembler_options): Add nps400 info. 1051 1052 2019-07-24 Claudiu Zissulescu <claziss (a] synopsys.com> 1053 1054 * arc-ext-tbl.h (bspeek): Remove it, added to main table. 1055 (bspop): Likewise. 1056 (modapp): Likewise. 1057 * arc-opc.c (RAD_CHK): Add. 1058 * arc-tbl.h: Regenerate. 1059 1060 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov (a] arm.com> 1061 1062 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry. 1063 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding. 1064 1065 2019-07-22 Barnaby Wilks <barnaby.wilks (a] arm.com> 1066 1067 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE 1068 instructions as UNPREDICTABLE. 1069 1070 2019-07-19 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1071 1072 * bpf-desc.c: Regenerated. 1073 1074 2019-07-17 Jan Beulich <jbeulich (a] suse.com> 1075 1076 * i386-gen.c (static_assert): Define. 1077 (main): Use it. 1078 * i386-opc.h (Opcode_Modifier_Max): Rename to ... 1079 (Opcode_Modifier_Num): ... this. 1080 (Mem): Delete. 1081 1082 2019-07-16 Jan Beulich <jbeulich (a] suse.com> 1083 1084 * i386-gen.c (operand_types): Move RegMem ... 1085 (opcode_modifiers): ... here. 1086 * i386-opc.h (RegMem): Move to opcode modifer enum. 1087 (union i386_operand_type): Move regmem field ... 1088 (struct i386_opcode_modifier): ... here. 1089 * i386-opc.tbl (RegMem): Define. 1090 (mov, movq): Move RegMem on segment, control, debug, and test 1091 register flavors. 1092 (pextrb): Move RegMem on register only flavors. Add IgnoreSize 1093 to non-SSE2AVX flavor. 1094 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw): 1095 Move RegMem on register only flavors. Drop IgnoreSize from 1096 legacy encoding flavors. 1097 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only 1098 flavors. 1099 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on 1100 register only flavors. 1101 (vmovd): Move RegMem and drop IgnoreSize on register only 1102 flavor. Change opcode and operand order to store form. 1103 * opcodes/i386-init.h, i386-tbl.h: Re-generate. 1104 1105 2019-07-16 Jan Beulich <jbeulich (a] suse.com> 1106 1107 * i386-gen.c (operand_type_init, operand_types): Replace SReg 1108 entries. 1109 * i386-opc.h (SReg2, SReg3): Replace by ... 1110 (SReg): ... this. 1111 (union i386_operand_type): Replace sreg fields. 1112 * i386-opc.tbl (mov, ): Use SReg. 1113 (push, pop): Likewies. Drop i386 and x86-64 specific segment 1114 register flavors. 1115 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg. 1116 * opcodes/i386-init.h, i386-tbl.h: Re-generate. 1117 1118 2019-07-15 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1119 1120 * bpf-desc.c: Regenerate. 1121 * bpf-opc.c: Likewise. 1122 * bpf-opc.h: Likewise. 1123 1124 2019-07-14 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1125 1126 * bpf-desc.c: Regenerate. 1127 * bpf-opc.c: Likewise. 1128 1129 2019-07-10 Hans-Peter Nilsson <hp (a] bitrange.com> 1130 1131 * arm-dis.c (print_insn_coprocessor): Rename index to 1132 index_operand. 1133 1134 2019-07-05 Kito Cheng <kito.cheng (a] sifive.com> 1135 1136 * riscv-opc.c (riscv_insn_types): Add r4 type. 1137 1138 * riscv-opc.c (riscv_insn_types): Add b and j type. 1139 1140 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect 1141 format for sb type and correct s type. 1142 1143 2019-07-02 Richard Sandiford <richard.sandiford (a] arm.com> 1144 1145 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the 1146 SVE FMOV alias of FCPY. 1147 1148 2019-07-02 Richard Sandiford <richard.sandiford (a] arm.com> 1149 1150 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags 1151 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries. 1152 1153 2019-07-02 Richard Sandiford <richard.sandiford (a] arm.com> 1154 1155 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the 1156 registers in an instruction prefixed by MOVPRFX. 1157 1158 2019-07-01 Matthew Malcomson <matthew.malcomson (a] arm.com> 1159 1160 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new 1161 sve_size_13 icode to account for variant behaviour of 1162 pmull{t,b}. 1163 * aarch64-dis-2.c: Regenerate. 1164 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new 1165 sve_size_13 icode to account for variant behaviour of 1166 pmull{t,b}. 1167 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier. 1168 (OP_SVE_VVV_Q_D): Add new qualifier. 1169 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier. 1170 (struct aarch64_opcode): Split pmull{t,b} into those requiring 1171 AES and those not. 1172 1173 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1174 1175 * opcodes/i386-gen.c (operand_type_init): Remove 1176 OPERAND_TYPE_VEC_IMM4 entry. 1177 (operand_types): Remove Vec_Imm4. 1178 * opcodes/i386-opc.h (Vec_Imm4): Delete. 1179 (union i386_operand_type): Remove vec_imm4. 1180 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4. 1181 * opcodes/i386-init.h, i386-tbl.h: Re-generate. 1182 1183 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1184 1185 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall, 1186 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs, 1187 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun, 1188 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb, 1189 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac, 1190 monitorx, mwaitx): Drop ImmExt from operand-less forms. 1191 * i386-tbl.h: Re-generate. 1192 1193 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1194 1195 * i386-opc.tbl (and, or): Add Optimize to forms allowing two 1196 register operands. 1197 * i386-tbl.h: Re-generate. 1198 1199 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1200 1201 * i386-opc.tbl (C): New. 1202 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw, 1203 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw, 1204 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss, 1205 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw, 1206 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd, 1207 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd, 1208 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd, 1209 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps, 1210 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd, 1211 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd, 1212 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd, 1213 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd, 1214 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd, 1215 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd, 1216 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss, 1217 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss, 1218 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps, 1219 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps, 1220 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps, 1221 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps, 1222 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss, 1223 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw, 1224 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand, 1225 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd, 1226 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw, 1227 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded 1228 flavors. 1229 * i386-tbl.h: Re-generate. 1230 1231 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1232 1233 * i386-opc.tbl (and, or): Add Optimize to forms allowing two 1234 register operands. 1235 * i386-tbl.h: Re-generate. 1236 1237 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1238 1239 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq. 1240 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq, 1241 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors. 1242 * i386-tbl.h: Re-generate. 1243 1244 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1245 1246 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove 1247 Disp8MemShift from register only templates. 1248 * i386-tbl.h: Re-generate. 1249 1250 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1251 1252 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1, 1253 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, 1254 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0, 1255 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1, 1256 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0, 1257 EVEX_W_0F11_P_3_M_1): Delete. 1258 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1, 1259 EVEX_W_0F11_P_3): New. 1260 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1, 1261 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and 1262 MOD_EVEX_0F11_PREFIX_3 table entries. 1263 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and 1264 PREFIX_EVEX_0F11 table entries. 1265 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1}, 1266 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and 1267 EVEX_W_0F11_P_3_M_{0,1} table entries. 1268 1269 2019-07-01 Jan Beulich <jbeulich (a] suse.com> 1270 1271 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex): 1272 Delete. 1273 1274 2019-06-27 H.J. Lu <hongjiu.lu (a] intel.com> 1275 1276 PR binutils/24719 1277 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, 1278 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, 1279 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, 1280 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, 1281 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, 1282 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and 1283 EVEX_LEN_0F38C7_R_6_P_2_W_1. 1284 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1, 1285 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and 1286 PREFIX_EVEX_0F38C6_REG_6 entries. 1287 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2, 1288 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and 1289 EVEX_W_0F38C7_R_6_P_2 entries. 1290 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2, 1291 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2, 1292 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0, 1293 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0, 1294 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0, 1295 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and 1296 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums. 1297 1298 2019-06-27 Jan Beulich <jbeulich (a] suse.com> 1299 1300 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3, 1301 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1, 1302 VEX_LEN_0F2D_P_3): Delete. 1303 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si, 1304 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ... 1305 (prefix_table): ... here. 1306 1307 2019-06-27 Jan Beulich <jbeulich (a] suse.com> 1308 1309 * i386-dis.c (Iq): Delete. 1310 (Id): New. 1311 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for 1312 TBM insns. 1313 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for 1314 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si. 1315 (OP_E_memory): Also honor needindex when deciding whether an 1316 address size prefix needs printing. 1317 (OP_I): Remove handling of q_mode. Add handling of d_mode. 1318 1319 2019-06-26 Jim Wilson <jimw (a] sifive.com> 1320 1321 PR binutils/24739 1322 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code. 1323 Set info->display_endian to info->endian_code. 1324 1325 2019-06-25 Jan Beulich <jbeulich (a] suse.com> 1326 1327 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG 1328 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and 1329 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and 1330 OPERAND_TYPE_ACC64 entries. 1331 * i386-init.h: Re-generate. 1332 1333 2019-06-25 Jan Beulich <jbeulich (a] suse.com> 1334 1335 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1): 1336 Delete. 1337 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling 1338 of dqa_mode. 1339 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf 1340 entries here. 1341 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1 1342 entries. Use Edq for vcvtsi2sd and vcvtusi2sd. 1343 1344 2019-06-25 Jan Beulich <jbeulich (a] suse.com> 1345 1346 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local 1347 variables. 1348 1349 2019-06-25 Jan Beulich <jbeulich (a] suse.com> 1350 1351 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd. 1352 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and 1353 movnti. 1354 * i386-opc.tbl (movnti): Add IgnoreSize. 1355 * i386-tbl.h: Re-generate. 1356 1357 2019-06-25 Jan Beulich <jbeulich (a] suse.com> 1358 1359 * i386-opc.tbl (and): Mark Imm8S form for optimization. 1360 * i386-tbl.h: Re-generate. 1361 1362 2019-06-21 H.J. Lu <hongjiu.lu (a] intel.com> 1363 1364 * i386-dis-evex.h: Break into ... 1365 * i386-dis-evex-len.h: New file. 1366 * i386-dis-evex-mod.h: Likewise. 1367 * i386-dis-evex-prefix.h: Likewise. 1368 * i386-dis-evex-reg.h: Likewise. 1369 * i386-dis-evex-w.h: Likewise. 1370 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h, 1371 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and 1372 i386-dis-evex-mod.h. 1373 1374 2019-06-19 H.J. Lu <hongjiu.lu (a] intel.com> 1375 1376 PR binutils/24700 1377 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2, 1378 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and 1379 EVEX_W_0F385B_P_2. 1380 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0, 1381 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0, 1382 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0, 1383 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0, 1384 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and 1385 EVEX_LEN_0F385B_P_2_W_1. 1386 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum. 1387 (EVEX_LEN_0F3819_P_2_W_1): Likewise. 1388 (EVEX_LEN_0F381A_P_2_W_0): Likewise. 1389 (EVEX_LEN_0F381A_P_2_W_1): Likewise. 1390 (EVEX_LEN_0F381B_P_2_W_0): Likewise. 1391 (EVEX_LEN_0F381B_P_2_W_1): Likewise. 1392 (EVEX_LEN_0F385A_P_2_W_0): Likewise. 1393 (EVEX_LEN_0F385A_P_2_W_1): Likewise. 1394 (EVEX_LEN_0F385B_P_2_W_0): Likewise. 1395 (EVEX_LEN_0F385B_P_2_W_1): Likewise. 1396 1397 2019-06-17 H.J. Lu <hongjiu.lu (a] intel.com> 1398 1399 PR binutils/24691 1400 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2, 1401 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2, 1402 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2. 1403 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0, 1404 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0, 1405 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0, 1406 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0, 1407 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0, 1408 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and 1409 EVEX_LEN_0F3A43_P_2_W_1. 1410 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum. 1411 (EVEX_LEN_0F3A23_P_2_W_1): Likewise. 1412 (EVEX_LEN_0F3A38_P_2_W_0): Likewise. 1413 (EVEX_LEN_0F3A38_P_2_W_1): Likewise. 1414 (EVEX_LEN_0F3A39_P_2_W_0): Likewise. 1415 (EVEX_LEN_0F3A39_P_2_W_1): Likewise. 1416 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise. 1417 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise. 1418 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise. 1419 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise. 1420 (EVEX_LEN_0F3A43_P_2_W_0): Likewise. 1421 (EVEX_LEN_0F3A43_P_2_W_1): Likewise. 1422 1423 2019-06-14 Nick Clifton <nickc (a] redhat.com> 1424 1425 * po/fr.po; Updated French translation. 1426 1427 2019-06-13 Stafford Horne <shorne (a] gmail.com> 1428 1429 * or1k-asm.c: Regenerated. 1430 * or1k-desc.c: Regenerated. 1431 * or1k-desc.h: Regenerated. 1432 * or1k-dis.c: Regenerated. 1433 * or1k-ibld.c: Regenerated. 1434 * or1k-opc.c: Regenerated. 1435 * or1k-opc.h: Regenerated. 1436 * or1k-opinst.c: Regenerated. 1437 1438 2019-06-12 Peter Bergner <bergner (a] linux.ibm.com> 1439 1440 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic. 1441 1442 2019-06-05 H.J. Lu <hongjiu.lu (a] intel.com> 1443 1444 PR binutils/24633 1445 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, 1446 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. 1447 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, 1448 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, 1449 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, 1450 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, 1451 EVEX_LEN_0F3A1B_P_2_W_1. 1452 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. 1453 (EVEX_LEN_0F3A18_P_2_W_1): Likewise. 1454 (EVEX_LEN_0F3A19_P_2_W_0): Likewise. 1455 (EVEX_LEN_0F3A19_P_2_W_1): Likewise. 1456 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. 1457 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. 1458 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. 1459 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise. 1460 1461 2019-06-04 H.J. Lu <hongjiu.lu (a] intel.com> 1462 1463 PR binutils/24626 1464 * i386-dis.c (print_insn): Check for unused VEX.vvvv and 1465 EVEX.vvvv when disassembling VEX and EVEX instructions. 1466 (OP_VEX): Set vex.register_specifier to 0 after readding 1467 vex.register_specifier. 1468 (OP_Vex_2src_1): Likewise. 1469 (OP_Vex_2src_2): Likewise. 1470 (OP_LWP_E): Likewise. 1471 (OP_EX_Vex): Don't check vex.register_specifier. 1472 (OP_XMM_Vex): Likewise. 1473 1474 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 1475 Lili Cui <lili.cui (a] intel.com> 1476 1477 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. 1478 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT 1479 instructions. 1480 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, 1481 CPU_ANY_AVX512_VP2INTERSECT_FLAGS. 1482 (cpu_flags): Add CpuAVX512_VP2INTERSECT. 1483 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. 1484 (i386_cpu_flags): Add cpuavx512_vp2intersect. 1485 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. 1486 * i386-init.h: Regenerated. 1487 * i386-tbl.h: Likewise. 1488 1489 2019-06-04 Xuepeng Guo <xuepeng.guo (a] intel.com> 1490 Lili Cui <lili.cui (a] intel.com> 1491 1492 * doc/c-i386.texi: Document enqcmd. 1493 * testsuite/gas/i386/enqcmd-intel.d: New file. 1494 * testsuite/gas/i386/enqcmd-inval.l: Likewise. 1495 * testsuite/gas/i386/enqcmd-inval.s: Likewise. 1496 * testsuite/gas/i386/enqcmd.d: Likewise. 1497 * testsuite/gas/i386/enqcmd.s: Likewise. 1498 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. 1499 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. 1500 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. 1501 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. 1502 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. 1503 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, 1504 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, 1505 and x86-64-enqcmd. 1506 1507 2019-06-04 Alan Hayward <alan.hayward (a] arm.com> 1508 1509 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis. 1510 1511 2019-06-03 Alan Modra <amodra (a] gmail.com> 1512 1513 * ppc-dis.c (prefix_opcd_indices): Correct size. 1514 1515 2019-05-28 H.J. Lu <hongjiu.lu (a] intel.com> 1516 1517 PR gas/24625 1518 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with 1519 Disp8ShiftVL. 1520 * i386-tbl.h: Regenerated. 1521 1522 2019-05-24 Alan Modra <amodra (a] gmail.com> 1523 1524 * po/POTFILES.in: Regenerate. 1525 1526 2019-05-24 Peter Bergner <bergner (a] linux.ibm.com> 1527 Alan Modra <amodra (a] gmail.com> 1528 1529 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), 1530 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. 1531 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. 1532 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, 1533 XTOP>): Define and add entries. 1534 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. 1535 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, 1536 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, 1537 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. 1538 1539 2019-05-24 Peter Bergner <bergner (a] linux.ibm.com> 1540 Alan Modra <amodra (a] gmail.com> 1541 1542 * ppc-dis.c (ppc_opts): Add "future" entry. 1543 (PREFIX_OPCD_SEGS): Define. 1544 (prefix_opcd_indices): New array. 1545 (disassemble_init_powerpc): Initialize prefix_opcd_indices. 1546 (lookup_prefix): New function. 1547 (print_insn_powerpc): Handle 64-bit prefix instructions. 1548 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), 1549 (PMRR, POWERXX): Define. 1550 (prefix_opcodes): New instruction table. 1551 (prefix_num_opcodes): New constant. 1552 1553 2019-05-23 Jose E. Marchesi <jose.marchesi (a] oracle.com> 1554 1555 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch. 1556 * configure: Regenerated. 1557 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu 1558 and cpu/bpf.opc. 1559 (HFILES): Add bpf-desc.h and bpf-opc.h. 1560 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c, 1561 bpf-ibld.c and bpf-opc.c. 1562 (BPF_DEPS): Define. 1563 * Makefile.in: Regenerated. 1564 * disassemble.c (ARCH_bpf): Define. 1565 (disassembler): Add case for bfd_arch_bpf. 1566 (disassemble_init_for_target): Likewise. 1567 (enum epbf_isa_attr): Define. 1568 * disassemble.h: extern print_insn_bpf. 1569 * bpf-asm.c: Generated. 1570 * bpf-opc.h: Likewise. 1571 * bpf-opc.c: Likewise. 1572 * bpf-ibld.c: Likewise. 1573 * bpf-dis.c: Likewise. 1574 * bpf-desc.h: Likewise. 1575 * bpf-desc.c: Likewise. 1576 1577 2019-05-21 Sudakshina Das <sudi.das (a] arm.com> 1578 1579 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS 1580 and VMSR with the new operands. 1581 1582 2019-05-21 Sudakshina Das <sudi.das (a] arm.com> 1583 1584 * arm-dis.c (enum mve_instructions): New enum 1585 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv 1586 and cneg. 1587 (mve_opcodes): New instructions as above. 1588 (is_mve_encoding_conflict): Add cases for csinc, csinv, 1589 csneg and csel. 1590 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C. 1591 1592 2019-05-21 Sudakshina Das <sudi.das (a] arm.com> 1593 1594 * arm-dis.c (emun mve_instructions): Updated for new instructions. 1595 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, 1596 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, 1597 uqshl, urshrl and urshr. 1598 (is_mve_okay_in_it): Add new instructions to TRUE list. 1599 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. 1600 (print_insn_mve): Updated to accept new %j, 1601 %<bitfield>m and %<bitfield>n patterns. 1602 1603 2019-05-21 Faraz Shahbazker <fshahbazker (a] wavecomp.com> 1604 1605 * mips-opc.c (mips_builtin_opcodes): Change source register 1606 constraint for DAUI. 1607 1608 2019-05-20 Nick Clifton <nickc (a] redhat.com> 1609 1610 * po/fr.po: Updated French translation. 1611 1612 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1613 Michael Collison <michael.collison (a] arm.com> 1614 1615 * arm-dis.c (thumb32_opcodes): Add new instructions. 1616 (enum mve_instructions): Likewise. 1617 (enum mve_undefined): Add new reasons. 1618 (is_mve_encoding_conflict): Handle new instructions. 1619 (is_mve_undefined): Likewise. 1620 (is_mve_unpredictable): Likewise. 1621 (print_mve_undefined): Likewise. 1622 (print_mve_size): Likewise. 1623 1624 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1625 Michael Collison <michael.collison (a] arm.com> 1626 1627 * arm-dis.c (thumb32_opcodes): Add new instructions. 1628 (enum mve_instructions): Likewise. 1629 (is_mve_encoding_conflict): Handle new instructions. 1630 (is_mve_undefined): Likewise. 1631 (is_mve_unpredictable): Likewise. 1632 (print_mve_size): Likewise. 1633 1634 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1635 Michael Collison <michael.collison (a] arm.com> 1636 1637 * arm-dis.c (thumb32_opcodes): Add new instructions. 1638 (enum mve_instructions): Likewise. 1639 (is_mve_encoding_conflict): Likewise. 1640 (is_mve_unpredictable): Likewise. 1641 (print_mve_size): Likewise. 1642 1643 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1644 Michael Collison <michael.collison (a] arm.com> 1645 1646 * arm-dis.c (thumb32_opcodes): Add new instructions. 1647 (enum mve_instructions): Likewise. 1648 (is_mve_encoding_conflict): Handle new instructions. 1649 (is_mve_undefined): Likewise. 1650 (is_mve_unpredictable): Likewise. 1651 (print_mve_size): Likewise. 1652 1653 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1654 Michael Collison <michael.collison (a] arm.com> 1655 1656 * arm-dis.c (thumb32_opcodes): Add new instructions. 1657 (enum mve_instructions): Likewise. 1658 (is_mve_encoding_conflict): Handle new instructions. 1659 (is_mve_undefined): Likewise. 1660 (is_mve_unpredictable): Likewise. 1661 (print_mve_size): Likewise. 1662 (print_insn_mve): Likewise. 1663 1664 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1665 Michael Collison <michael.collison (a] arm.com> 1666 1667 * arm-dis.c (thumb32_opcodes): Add new instructions. 1668 (print_insn_thumb32): Handle new instructions. 1669 1670 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1671 Michael Collison <michael.collison (a] arm.com> 1672 1673 * arm-dis.c (enum mve_instructions): Add new instructions. 1674 (enum mve_undefined): Add new reasons. 1675 (is_mve_encoding_conflict): Handle new instructions. 1676 (is_mve_undefined): Likewise. 1677 (is_mve_unpredictable): Likewise. 1678 (print_mve_undefined): Likewise. 1679 (print_mve_size): Likewise. 1680 (print_mve_shift_n): Likewise. 1681 (print_insn_mve): Likewise. 1682 1683 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1684 Michael Collison <michael.collison (a] arm.com> 1685 1686 * arm-dis.c (enum mve_instructions): Add new instructions. 1687 (is_mve_encoding_conflict): Handle new instructions. 1688 (is_mve_unpredictable): Likewise. 1689 (print_mve_rotate): Likewise. 1690 (print_mve_size): Likewise. 1691 (print_insn_mve): Likewise. 1692 1693 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1694 Michael Collison <michael.collison (a] arm.com> 1695 1696 * arm-dis.c (enum mve_instructions): Add new instructions. 1697 (is_mve_encoding_conflict): Handle new instructions. 1698 (is_mve_unpredictable): Likewise. 1699 (print_mve_size): Likewise. 1700 (print_insn_mve): Likewise. 1701 1702 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1703 Michael Collison <michael.collison (a] arm.com> 1704 1705 * arm-dis.c (enum mve_instructions): Add new instructions. 1706 (enum mve_undefined): Add new reasons. 1707 (is_mve_encoding_conflict): Handle new instructions. 1708 (is_mve_undefined): Likewise. 1709 (is_mve_unpredictable): Likewise. 1710 (print_mve_undefined): Likewise. 1711 (print_mve_size): Likewise. 1712 (print_insn_mve): Likewise. 1713 1714 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1715 Michael Collison <michael.collison (a] arm.com> 1716 1717 * arm-dis.c (enum mve_instructions): Add new instructions. 1718 (is_mve_encoding_conflict): Handle new instructions. 1719 (is_mve_undefined): Likewise. 1720 (is_mve_unpredictable): Likewise. 1721 (print_mve_size): Likewise. 1722 (print_insn_mve): Likewise. 1723 1724 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1725 Michael Collison <michael.collison (a] arm.com> 1726 1727 * arm-dis.c (enum mve_instructions): Add new instructions. 1728 (enum mve_unpredictable): Add new reasons. 1729 (enum mve_undefined): Likewise. 1730 (is_mve_okay_in_it): Handle new isntructions. 1731 (is_mve_encoding_conflict): Likewise. 1732 (is_mve_undefined): Likewise. 1733 (is_mve_unpredictable): Likewise. 1734 (print_mve_vmov_index): Likewise. 1735 (print_simd_imm8): Likewise. 1736 (print_mve_undefined): Likewise. 1737 (print_mve_unpredictable): Likewise. 1738 (print_mve_size): Likewise. 1739 (print_insn_mve): Likewise. 1740 1741 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1742 Michael Collison <michael.collison (a] arm.com> 1743 1744 * arm-dis.c (enum mve_instructions): Add new instructions. 1745 (enum mve_unpredictable): Add new reasons. 1746 (enum mve_undefined): Likewise. 1747 (is_mve_encoding_conflict): Handle new instructions. 1748 (is_mve_undefined): Likewise. 1749 (is_mve_unpredictable): Likewise. 1750 (print_mve_undefined): Likewise. 1751 (print_mve_unpredictable): Likewise. 1752 (print_mve_rounding_mode): Likewise. 1753 (print_mve_vcvt_size): Likewise. 1754 (print_mve_size): Likewise. 1755 (print_insn_mve): Likewise. 1756 1757 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1758 Michael Collison <michael.collison (a] arm.com> 1759 1760 * arm-dis.c (enum mve_instructions): Add new instructions. 1761 (enum mve_unpredictable): Add new reasons. 1762 (enum mve_undefined): Likewise. 1763 (is_mve_undefined): Handle new instructions. 1764 (is_mve_unpredictable): Likewise. 1765 (print_mve_undefined): Likewise. 1766 (print_mve_unpredictable): Likewise. 1767 (print_mve_size): Likewise. 1768 (print_insn_mve): Likewise. 1769 1770 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1771 Michael Collison <michael.collison (a] arm.com> 1772 1773 * arm-dis.c (enum mve_instructions): Add new instructions. 1774 (enum mve_undefined): Add new reasons. 1775 (insns): Add new instructions. 1776 (is_mve_encoding_conflict): 1777 (print_mve_vld_str_addr): New print function. 1778 (is_mve_undefined): Handle new instructions. 1779 (is_mve_unpredictable): Likewise. 1780 (print_mve_undefined): Likewise. 1781 (print_mve_size): Likewise. 1782 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. 1783 (print_insn_mve): Handle new operands. 1784 1785 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1786 Michael Collison <michael.collison (a] arm.com> 1787 1788 * arm-dis.c (enum mve_instructions): Add new instructions. 1789 (enum mve_unpredictable): Add new reasons. 1790 (is_mve_encoding_conflict): Handle new instructions. 1791 (is_mve_unpredictable): Likewise. 1792 (mve_opcodes): Add new instructions. 1793 (print_mve_unpredictable): Handle new reasons. 1794 (print_mve_register_blocks): New print function. 1795 (print_mve_size): Handle new instructions. 1796 (print_insn_mve): Likewise. 1797 1798 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1799 Michael Collison <michael.collison (a] arm.com> 1800 1801 * arm-dis.c (enum mve_instructions): Add new instructions. 1802 (enum mve_unpredictable): Add new reasons. 1803 (enum mve_undefined): Likewise. 1804 (is_mve_encoding_conflict): Handle new instructions. 1805 (is_mve_undefined): Likewise. 1806 (is_mve_unpredictable): Likewise. 1807 (coprocessor_opcodes): Move NEON VDUP from here... 1808 (neon_opcodes): ... to here. 1809 (mve_opcodes): Add new instructions. 1810 (print_mve_undefined): Handle new reasons. 1811 (print_mve_unpredictable): Likewise. 1812 (print_mve_size): Handle new instructions. 1813 (print_insn_neon): Handle vdup. 1814 (print_insn_mve): Handle new operands. 1815 1816 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1817 Michael Collison <michael.collison (a] arm.com> 1818 1819 * arm-dis.c (enum mve_instructions): Add new instructions. 1820 (enum mve_unpredictable): Add new values. 1821 (mve_opcodes): Add new instructions. 1822 (vec_condnames): New array with vector conditions. 1823 (mve_predicatenames): New array with predicate suffixes. 1824 (mve_vec_sizename): New array with vector sizes. 1825 (enum vpt_pred_state): New enum with vector predication states. 1826 (struct vpt_block): New struct type for vpt blocks. 1827 (vpt_block_state): Global struct to keep track of state. 1828 (mve_extract_pred_mask): New helper function. 1829 (num_instructions_vpt_block): Likewise. 1830 (mark_outside_vpt_block): Likewise. 1831 (mark_inside_vpt_block): Likewise. 1832 (invert_next_predicate_state): Likewise. 1833 (update_next_predicate_state): Likewise. 1834 (update_vpt_block_state): Likewise. 1835 (is_vpt_instruction): Likewise. 1836 (is_mve_encoding_conflict): Add entries for new instructions. 1837 (is_mve_unpredictable): Likewise. 1838 (print_mve_unpredictable): Handle new cases. 1839 (print_instruction_predicate): Likewise. 1840 (print_mve_size): New function. 1841 (print_vec_condition): New function. 1842 (print_insn_mve): Handle vpt blocks and new print operands. 1843 1844 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1845 1846 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors 1847 8, 14 and 15 for Armv8.1-M Mainline. 1848 1849 2019-05-16 Andre Vieira <andre.simoesdiasvieira (a] arm.com> 1850 Michael Collison <michael.collison (a] arm.com> 1851 1852 * arm-dis.c (enum mve_instructions): New enum. 1853 (enum mve_unpredictable): Likewise. 1854 (enum mve_undefined): Likewise. 1855 (struct mopcode32): New struct. 1856 (is_mve_okay_in_it): New function. 1857 (is_mve_architecture): Likewise. 1858 (arm_decode_field): Likewise. 1859 (arm_decode_field_multiple): Likewise. 1860 (is_mve_encoding_conflict): Likewise. 1861 (is_mve_undefined): Likewise. 1862 (is_mve_unpredictable): Likewise. 1863 (print_mve_undefined): Likewise. 1864 (print_mve_unpredictable): Likewise. 1865 (print_insn_coprocessor_1): Use arm_decode_field_multiple. 1866 (print_insn_mve): New function. 1867 (print_insn_thumb32): Handle MVE architecture. 1868 (select_arm_features): Force thumb for Armv8.1-m Mainline. 1869 1870 2019-05-10 Nick Clifton <nickc (a] redhat.com> 1871 1872 PR 24538 1873 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the 1874 end of the table prematurely. 1875 1876 2019-05-10 Faraz Shahbazker <fshahbazker (a] wavecomp.com> 1877 1878 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB 1879 macros for R6. 1880 1881 2019-05-11 Alan Modra <amodra (a] gmail.com> 1882 1883 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands 1884 when -Mraw is in effect. 1885 1886 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1887 1888 * aarch64-dis-2.c: Regenerate. 1889 * aarch64-tbl.h (OP_SVE_BBU): New variant set. 1890 (OP_SVE_BBB): New variant set. 1891 (OP_SVE_DDDD): New variant set. 1892 (OP_SVE_HHH): New variant set. 1893 (OP_SVE_HHHU): New variant set. 1894 (OP_SVE_SSS): New variant set. 1895 (OP_SVE_SSSU): New variant set. 1896 (OP_SVE_SHH): New variant set. 1897 (OP_SVE_SBBU): New variant set. 1898 (OP_SVE_DSS): New variant set. 1899 (OP_SVE_DHHU): New variant set. 1900 (OP_SVE_VMV_HSD_BHS): New variant set. 1901 (OP_SVE_VVU_HSD_BHS): New variant set. 1902 (OP_SVE_VVVU_SD_BH): New variant set. 1903 (OP_SVE_VVVU_BHSD): New variant set. 1904 (OP_SVE_VVV_QHD_DBS): New variant set. 1905 (OP_SVE_VVV_HSD_BHS): New variant set. 1906 (OP_SVE_VVV_HSD_BHS2): New variant set. 1907 (OP_SVE_VVV_BHS_HSD): New variant set. 1908 (OP_SVE_VV_BHS_HSD): New variant set. 1909 (OP_SVE_VVV_SD): New variant set. 1910 (OP_SVE_VVU_BHS_HSD): New variant set. 1911 (OP_SVE_VZVV_SD): New variant set. 1912 (OP_SVE_VZVV_BH): New variant set. 1913 (OP_SVE_VZV_SD): New variant set. 1914 (aarch64_opcode_table): Add sve2 instructions. 1915 1916 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1917 1918 * aarch64-asm-2.c: Regenerated. 1919 * aarch64-dis-2.c: Regenerated. 1920 * aarch64-opc-2.c: Regenerated. 1921 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking 1922 for SVE_SHLIMM_UNPRED_22. 1923 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. 1924 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 1925 operand. 1926 1927 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1928 1929 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle 1930 sve_size_tsz_bhs iclass encode. 1931 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle 1932 sve_size_tsz_bhs iclass decode. 1933 1934 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1935 1936 * aarch64-asm-2.c: Regenerated. 1937 * aarch64-dis-2.c: Regenerated. 1938 * aarch64-opc-2.c: Regenerated. 1939 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking 1940 for SVE_Zm4_11_INDEX. 1941 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. 1942 (fields): Handle SVE_i2h field. 1943 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. 1944 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. 1945 1946 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1947 1948 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle 1949 sve_shift_tsz_bhsd iclass encode. 1950 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle 1951 sve_shift_tsz_bhsd iclass decode. 1952 1953 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1954 1955 * aarch64-asm-2.c: Regenerated. 1956 * aarch64-dis-2.c: Regenerated. 1957 * aarch64-opc-2.c: Regenerated. 1958 * aarch64-asm.c (aarch64_ins_sve_shrimm): 1959 (aarch64_encode_variant_using_iclass): Handle 1960 sve_shift_tsz_hsd iclass encode. 1961 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle 1962 sve_shift_tsz_hsd iclass decode. 1963 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking 1964 for SVE_SHRIMM_UNPRED_22. 1965 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. 1966 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 1967 operand. 1968 1969 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1970 1971 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle 1972 sve_size_013 iclass encode. 1973 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle 1974 sve_size_013 iclass decode. 1975 1976 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1977 1978 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle 1979 sve_size_bh iclass encode. 1980 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle 1981 sve_size_bh iclass decode. 1982 1983 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1984 1985 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle 1986 sve_size_sd2 iclass encode. 1987 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle 1988 sve_size_sd2 iclass decode. 1989 * aarch64-opc.c (fields): Handle SVE_sz2 field. 1990 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. 1991 1992 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 1993 1994 * aarch64-asm-2.c: Regenerated. 1995 * aarch64-dis-2.c: Regenerated. 1996 * aarch64-opc-2.c: Regenerated. 1997 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking 1998 for SVE_ADDR_ZX. 1999 (aarch64_print_operand): Add printing for SVE_ADDR_ZX. 2000 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. 2001 2002 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 2003 2004 * aarch64-asm-2.c: Regenerated. 2005 * aarch64-dis-2.c: Regenerated. 2006 * aarch64-opc-2.c: Regenerated. 2007 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking 2008 for SVE_Zm3_11_INDEX. 2009 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. 2010 (fields): Handle SVE_i3l and SVE_i3h2 fields. 2011 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 2012 fields. 2013 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. 2014 2015 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 2016 2017 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle 2018 sve_size_hsd2 iclass encode. 2019 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle 2020 sve_size_hsd2 iclass decode. 2021 * aarch64-opc.c (fields): Handle SVE_size field. 2022 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. 2023 2024 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 2025 2026 * aarch64-asm-2.c: Regenerated. 2027 * aarch64-dis-2.c: Regenerated. 2028 * aarch64-opc-2.c: Regenerated. 2029 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking 2030 for SVE_IMM_ROT3. 2031 (aarch64_print_operand): Add printing for SVE_IMM_ROT3. 2032 (fields): Handle SVE_rot3 field. 2033 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. 2034 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. 2035 2036 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 2037 2038 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 2039 instructions. 2040 2041 2019-05-09 Matthew Malcomson <matthew.malcomson (a] arm.com> 2042 2043 * aarch64-tbl.h 2044 (aarch64_feature_sve2, aarch64_feature_sve2aes, 2045 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, 2046 aarch64_feature_sve2bitperm): New feature sets. 2047 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros 2048 for feature set addresses. 2049 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, 2050 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. 2051 2052 2019-05-06 Andrew Bennett <andrew.bennett (a] imgtec.com> 2053 Faraz Shahbazker <fshahbazker (a] wavecomp.com> 2054 2055 * mips-dis.c (mips_calculate_combination_ases): Add ISA 2056 argument and set ASE_EVA_R6 appropriately. 2057 (set_default_mips_dis_options): Pass ISA to above. 2058 (parse_mips_dis_option): Likewise. 2059 * mips-opc.c (EVAR6): New macro. 2060 (mips_builtin_opcodes): Add llwpe, scwpe. 2061 2062 2019-05-01 Sudakshina Das <sudi.das (a] arm.com> 2063 2064 * aarch64-asm-2.c: Regenerated. 2065 * aarch64-dis-2.c: Regenerated. 2066 * aarch64-opc-2.c: Regenerated. 2067 * aarch64-opc.c (operand_general_constraint_met_p): Add case for 2068 AARCH64_OPND_TME_UIMM16. 2069 (aarch64_print_operand): Likewise. 2070 * aarch64-tbl.h (QL_IMM_NIL): New. 2071 (TME): New. 2072 (_TME_INSN): New. 2073 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. 2074 2075 2019-04-29 John Darrington <john (a] darrington.wattle.id.au> 2076 2077 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. 2078 2079 2019-04-26 Andrew Bennett <andrew.bennett (a] imgtec.com> 2080 Faraz Shahbazker <fshahbazker (a] wavecomp.com> 2081 2082 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. 2083 2084 2019-04-24 John Darrington <john (a] darrington.wattle.id.au> 2085 2086 * s12z-opc.h: Add extern "C" bracketing to help 2087 users who wish to use this interface in c++ code. 2088 2089 2019-04-24 John Darrington <john (a] darrington.wattle.id.au> 2090 2091 * s12z-opc.c (bm_decode): Handle bit map operations with the 2092 "reserved0" mode. 2093 2094 2019-04-15 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 2095 2096 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format 2097 specifier. Add entries for VLDR and VSTR of system registers. 2098 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in 2099 coprocessor instructions on Armv8.1-M Mainline targets. Add handling 2100 of %J and %K format specifier. 2101 2102 2019-04-15 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 2103 2104 * arm-dis.c (coprocessor_opcodes): Document new %C format control code. 2105 Add new entries for VSCCLRM instruction. 2106 (print_insn_coprocessor): Handle new %C format control code. 2107 2108 2019-04-15 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 2109 2110 * arm-dis.c (enum isa): New enum. 2111 (struct sopcode32): New structure. 2112 (coprocessor_opcodes): change type of entries to struct sopcode32 and 2113 set isa field of all current entries to ANY. 2114 (print_insn_coprocessor): Change type of insn to struct sopcode32. 2115 Only match an entry if its isa field allows the current mode. 2116 2117 2019-04-15 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 2118 2119 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for 2120 CLRM. 2121 (print_insn_thumb32): Add logic to print %n CLRM register list. 2122 2123 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2124 2125 * arm-dis.c (print_insn_thumb32): Updated to accept new %P 2126 and %Q patterns. 2127 2128 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2129 2130 * arm-dis.c (thumb32_opcodes): New instruction bfcsel. 2131 (print_insn_thumb32): Edit the switch case for %Z. 2132 2133 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2134 2135 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. 2136 2137 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2138 2139 * arm-dis.c (thumb32_opcodes): New instruction bfl. 2140 2141 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2142 2143 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. 2144 2145 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2146 2147 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an 2148 Arm register with r13 and r15 unpredictable. 2149 (thumb32_opcodes): New instructions for bfx and bflx. 2150 2151 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2152 2153 * arm-dis.c (thumb32_opcodes): New instructions for bf. 2154 2155 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2156 2157 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. 2158 2159 2019-04-15 Sudakshina Das <sudi.das (a] arm.com> 2160 2161 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. 2162 2163 2019-04-15 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 2164 2165 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. 2166 2167 2019-04-12 John Darrington <john (a] darrington.wattle.id.au> 2168 2169 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with 2170 "optr". ("operator" is a reserved word in c++). 2171 2172 2019-04-11 Sudakshina Das <sudi.das (a] arm.com> 2173 2174 * aarch64-opc.c (aarch64_print_operand): Add case for 2175 AARCH64_OPND_Rt_SP. 2176 (verify_constraints): Likewise. 2177 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. 2178 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions 2179 to accept Rt|SP as first operand. 2180 (AARCH64_OPERANDS): Add new Rt_SP. 2181 * aarch64-asm-2.c: Regenerated. 2182 * aarch64-dis-2.c: Regenerated. 2183 * aarch64-opc-2.c: Regenerated. 2184 2185 2019-04-11 Sudakshina Das <sudi.das (a] arm.com> 2186 2187 * aarch64-asm-2.c: Regenerated. 2188 * aarch64-dis-2.c: Likewise. 2189 * aarch64-opc-2.c: Likewise. 2190 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. 2191 2192 2019-04-09 Robert Suchanek <robert.suchanek (a] mips.com> 2193 2194 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. 2195 2196 2019-04-08 H.J. Lu <hongjiu.lu (a] intel.com> 2197 2198 * i386-opc.tbl: Consolidate AVX512 BF16 entries. 2199 * i386-init.h: Regenerated. 2200 2201 2019-04-07 Alan Modra <amodra (a] gmail.com> 2202 2203 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine 2204 op_separator to control printing of spaces, comma and parens 2205 rather than need_comma, need_paren and spaces vars. 2206 2207 2019-04-07 Alan Modra <amodra (a] gmail.com> 2208 2209 PR 24421 2210 * arm-dis.c (print_insn_coprocessor): Correct bracket placement. 2211 (print_insn_neon, print_insn_arm): Likewise. 2212 2213 2019-04-05 Xuepeng Guo <xuepeng.guo (a] intel.com> 2214 2215 * i386-dis-evex.h (evex_table): Updated to support BF16 2216 instructions. 2217 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 2218 and EVEX_W_0F3872_P_3. 2219 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. 2220 (cpu_flags): Add bitfield for CpuAVX512_BF16. 2221 * i386-opc.h (enum): Add CpuAVX512_BF16. 2222 (i386_cpu_flags): Add bitfield for cpuavx512_bf16. 2223 * i386-opc.tbl: Add AVX512 BF16 instructions. 2224 * i386-init.h: Regenerated. 2225 * i386-tbl.h: Likewise. 2226 2227 2019-04-05 Alan Modra <amodra (a] gmail.com> 2228 2229 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. 2230 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics 2231 to favour printing of "-" branch hint when using the "y" bit. 2232 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. 2233 2234 2019-04-05 Alan Modra <amodra (a] gmail.com> 2235 2236 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after 2237 opcode until first operand is output. 2238 2239 2019-04-04 Peter Bergner <bergner (a] linux.ibm.com> 2240 2241 PR gas/24349 2242 * ppc-opc.c (valid_bo_pre_v2): Add comments. 2243 (valid_bo_post_v2): Add support for 'at' branch hints. 2244 (insert_bo): Only error on branch on ctr. 2245 (get_bo_hint_mask): New function. 2246 (insert_boe): Add new 'branch_taken' formal argument. Add support 2247 for inserting 'at' branch hints. 2248 (extract_boe): Add new 'branch_taken' formal argument. Add support 2249 for extracting 'at' branch hints. 2250 (insert_bom, extract_bom, insert_bop, extract_bop): New functions. 2251 (BOE): Delete operand. 2252 (BOM, BOP): New operands. 2253 (RM): Update value. 2254 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. 2255 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, 2256 bcctrl-, bctar-, bctarl->: Replace BOE with BOM. 2257 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, 2258 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. 2259 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, 2260 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, 2261 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, 2262 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, 2263 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, 2264 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, 2265 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, 2266 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, 2267 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, 2268 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, 2269 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, 2270 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, 2271 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, 2272 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, 2273 bttarl+>: New extended mnemonics. 2274 2275 2019-03-28 Alan Modra <amodra (a] gmail.com> 2276 2277 PR 24390 2278 * ppc-opc.c (BTF): Define. 2279 (powerpc_opcodes): Use for mtfsb*. 2280 * ppc-dis.c (print_insn_powerpc): Print fields with both 2281 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. 2282 2283 2019-03-25 Tamar Christina <tamar.christina (a] arm.com> 2284 2285 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. 2286 (mapping_symbol_for_insn): Implement new algorithm. 2287 (print_insn): Remove duplicate code. 2288 2289 2019-03-25 Tamar Christina <tamar.christina (a] arm.com> 2290 2291 * aarch64-dis.c (print_insn_aarch64): 2292 Implement override. 2293 2294 2019-03-25 Tamar Christina <tamar.christina (a] arm.com> 2295 2296 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search 2297 order. 2298 2299 2019-03-25 Tamar Christina <tamar.christina (a] arm.com> 2300 2301 * aarch64-dis.c (last_stop_offset): New. 2302 (print_insn_aarch64): Use stop_offset. 2303 2304 2019-03-19 H.J. Lu <hongjiu.lu (a] intel.com> 2305 2306 PR gas/24359 2307 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to 2308 CPU_ANY_AVX2_FLAGS. 2309 * i386-init.h: Regenerated. 2310 2311 2019-03-18 H.J. Lu <hongjiu.lu (a] intel.com> 2312 2313 PR gas/24348 2314 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, 2315 vmovdqu16, vmovdqu32 and vmovdqu64. 2316 * i386-tbl.h: Regenerated. 2317 2318 2019-03-12 Andreas Krebbel <krebbel (a] linux.ibm.com> 2319 2320 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand 2321 from vstrszb, vstrszh, and vstrszf. 2322 2323 2019-03-12 Andreas Krebbel <krebbel (a] linux.ibm.com> 2324 2325 * s390-opc.txt: Add instruction descriptions. 2326 2327 2019-02-08 Jim Wilson <jimw (a] sifive.com> 2328 2329 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. 2330 <bne>: Likewise. 2331 2332 2019-02-07 Tamar Christina <tamar.christina (a] arm.com> 2333 2334 * arm-dis.c (arm_opcodes): Redefine hlt to armv1. 2335 2336 2019-02-07 Tamar Christina <tamar.christina (a] arm.com> 2337 2338 PR binutils/23212 2339 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. 2340 * aarch64-opc.c (verify_elem_sd): New. 2341 (fields): Add FLD_sz entr. 2342 * aarch64-tbl.h (_SIMD_INSN): New. 2343 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and 2344 fmulx scalar and vector by element isns. 2345 2346 2019-02-07 Nick Clifton <nickc (a] redhat.com> 2347 2348 * po/sv.po: Updated Swedish translation. 2349 2350 2019-01-31 Andreas Krebbel <krebbel (a] linux.ibm.com> 2351 2352 * s390-mkopc.c (main): Accept arch13 as cpu string. 2353 * s390-opc.c: Add new instruction formats and instruction opcode 2354 masks. 2355 * s390-opc.txt: Add new arch13 instructions. 2356 2357 2019-01-25 Sudakshina Das <sudi.das (a] arm.com> 2358 2359 * aarch64-tbl.h (QL_LDST_AT): Update macro. 2360 (aarch64_opcode): Change encoding for stg, stzg 2361 st2g and st2zg. 2362 * aarch64-asm-2.c: Regenerated. 2363 * aarch64-dis-2.c: Regenerated. 2364 * aarch64-opc-2.c: Regenerated. 2365 2366 2019-01-25 Sudakshina Das <sudi.das (a] arm.com> 2367 2368 * aarch64-asm-2.c: Regenerated. 2369 * aarch64-dis-2.c: Likewise. 2370 * aarch64-opc-2.c: Likewise. 2371 * aarch64-tbl.h (aarch64_opcode): Add new stzgm. 2372 2373 2019-01-25 Sudakshina Das <sudi.das (a] arm.com> 2374 Ramana Radhakrishnan <ramana.radhakrishnan (a] arm.com> 2375 2376 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. 2377 * aarch64-asm.h (ins_addr_simple_2): Likeiwse. 2378 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. 2379 * aarch64-dis.h (ext_addr_simple_2): Likewise. 2380 * aarch64-opc.c (operand_general_constraint_met_p): Remove 2381 case for ldstgv_indexed. 2382 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. 2383 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. 2384 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. 2385 * aarch64-asm-2.c: Regenerated. 2386 * aarch64-dis-2.c: Regenerated. 2387 * aarch64-opc-2.c: Regenerated. 2388 2389 2019-01-23 Nick Clifton <nickc (a] redhat.com> 2390 2391 * po/pt_BR.po: Updated Brazilian Portuguese translation. 2392 2393 2019-01-21 Nick Clifton <nickc (a] redhat.com> 2394 2395 * po/de.po: Updated German translation. 2396 * po/uk.po: Updated Ukranian translation. 2397 2398 2019-01-20 Chenghua Xu <paul.hua.gm (a] gmail.com> 2399 * mips-dis.c (mips_arch_choices): Fix typo in 2400 gs464, gs464e and gs264e descriptors. 2401 2402 2019-01-19 Nick Clifton <nickc (a] redhat.com> 2403 2404 * configure: Regenerate. 2405 * po/opcodes.pot: Regenerate. 2406 2407 2018-06-24 Nick Clifton <nickc (a] redhat.com> 2408 2409 2.32 branch created. 2410 2411 2019-01-09 John Darrington <john (a] darrington.wattle.id.au> 2412 2413 * s12z-dis.c (print_insn_s12z): Do not dereference an operand 2414 if it is null. 2415 -dis.c (opr_emit_disassembly): Do not omit an index if it is 2416 zero. 2417 2418 2019-01-09 Andrew Paprocki <andrew (a] ishiboo.com> 2419 2420 * configure: Regenerate. 2421 2422 2019-01-07 Alan Modra <amodra (a] gmail.com> 2423 2424 * configure: Regenerate. 2425 * po/POTFILES.in: Regenerate. 2426 2427 2019-01-03 John Darrington <john (a] darrington.wattle.id.au> 2428 2429 * s12z-opc.c: New file. 2430 * s12z-opc.h: New file. 2431 * s12z-dis.c: Removed all code not directly related to display 2432 of instructions. Used the interface provided by the new files 2433 instead. 2434 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. 2435 * Makefile.in: Regenerate. 2436 * configure.ac (bfd_s12z_arch): Correct the dependencies. 2437 * configure: Regenerate. 2438 2439 2019-01-01 Alan Modra <amodra (a] gmail.com> 2440 2441 Update year range in copyright notice of all files. 2442 2443 For older changes see ChangeLog-2018 2444 2446 Copyright (C) 2019 Free Software Foundation, Inc. 2447 2448 Copying and distribution of this file, with or without modification, 2449 are permitted in any medium without royalty provided the copyright 2450 notice and this notice are preserved. 2451 2452 Local Variables: 2453 mode: change-log 2454 left-margin: 8 2455 fill-column: 74 2456 version-control: never 2457 End: 2458
Indexes created Sat May 30 00:24:47 UTC 2026