ChangeLog revision 1.11
1 2022-08-05 Nick Clifton <nickc (a] redhat.com> 2 3 2.39 Release. 4 * configure: Regenerate. 5 6 2022-07-21 Peter Bergner <bergner (a] linux.ibm.com> 7 8 Backport from mainline: 9 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines. 10 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, 11 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, 12 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, 13 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, 14 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, 15 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them. 16 17 2022-07-08 Nick Clifton <nickc (a] redhat.com> 18 19 * 2.39 branch created. 20 21 2022-07-04 Marcus Nilsson <brainbomb (a] gmail.com> 22 23 * disassemble.c: (disassemble_init_for_target): Set 24 created_styled_output for AVR based targets. 25 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype 26 instead of fprintf_ftype throughout. 27 (avr_operand): Pass in and fill disassembler_style when 28 parsing operands. 29 30 2022-04-07 Andreas Krebbel <krebbel (a] linux.ibm.com> 31 32 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode 33 table. 34 35 2022-03-16 Simon Marchi <simon.marchi (a] efficios.com> 36 37 * configure.ac: Handle bfd_amdgcn_arch. 38 * configure: Re-generate. 39 40 2022-03-06 Sagar Patel <sagarmp (a] cs.unc.edu> 41 Maciej W. Rozycki <macro (a] orcam.me.uk> 42 43 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation 44 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions. 45 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and 46 "bnez" instructions. 47 48 2022-02-17 Nick Clifton <nickc (a] redhat.com> 49 50 * po/sr.po: Updated Serbian translation. 51 52 2022-02-14 Sergei Trofimovich <siarheit (a] google.com> 53 54 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'. 55 * microblaze-opc.h: Follow 'fsqrt' rename. 56 57 2022-01-24 Nick Clifton <nickc (a] redhat.com> 58 59 * po/ro.po: Updated Romanian translation. 60 * po/uk.po: Updated Ukranian translation. 61 62 2022-01-22 Nick Clifton <nickc (a] redhat.com> 63 64 * configure: Regenerate. 65 * po/opcodes.pot: Regenerate. 66 67 2022-01-22 Nick Clifton <nickc (a] redhat.com> 68 69 * 2.38 release branch created. 70 71 2022-01-17 Nick Clifton <nickc (a] redhat.com> 72 73 * Makefile.in: Regenerate. 74 * po/opcodes.pot: Regenerate. 75 76 2021-12-02 Marcus Nilsson <brainbomb (a] gmail.com> 77 78 * avr-dis.c (avr_operand); Pass in disassemble_info and fill 79 in insn_type on branching instructions. 80 81 2021-11-25 Andrew Burgess <aburgess (a] redhat.com> 82 Simon Cook <simon.cook (a] embecosm.com> 83 84 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef. 85 (riscv_options): New static global. 86 (disassembler_options_riscv): New function. 87 (print_riscv_disassembler_options): Rewrite to use 88 disassembler_options_riscv. 89 90 2021-11-25 Nick Clifton <nickc (a] redhat.com> 91 92 PR 28614 93 * aarch64-asm.c: Replace assert(0) with real code. 94 * aarch64-dis.c: Likewise. 95 * aarch64-opc.c: Likewise. 96 97 2021-11-25 Nick Clifton <nickc (a] redhat.com> 98 99 * po/fr.po; Updated French translation. 100 101 2021-10-27 Maciej W. Rozycki <macro (a] embecosm.com> 102 103 * Makefile.am: Remove obsolete comment. 104 * configure.ac: Refer `libbfd.la' to link shared BFD library 105 except for Cygwin. 106 * Makefile.in: Regenerate. 107 * configure: Regenerate. 108 109 2021-09-27 Nick Alcock <nick.alcock (a] oracle.com> 110 111 * configure: Regenerate. 112 113 2021-09-25 Peter Bergner <bergner (a] linux.ibm.com> 114 115 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable 116 on POWER5 and later. 117 118 2021-09-20 Andrew Burgess <andrew.burgess (a] embecosm.com> 119 120 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode 121 before an unknown instruction, '%d' is replaced with the 122 instruction length. 123 124 2021-09-02 Nick Clifton <nickc (a] redhat.com> 125 126 PR 28292 127 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place 128 of BFD_RELOC_16. 129 130 2021-08-17 Shahab Vahedi <shahab (a] synopsys.com> 131 132 * arc-regs.h (DEF): Fix the register numbers. 133 134 2021-08-10 Nick Clifton <nickc (a] redhat.com> 135 136 * po/sr.po: Updated Serbian translation. 137 138 2021-07-26 Chenghua Xu <xuchenghua (a] loongson.cn> 139 140 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach. 141 142 2021-06-07 Andreas Krebbel <krebbel (a] linux.ibm.com> 143 144 * s390-opc.txt: Add qpaci. 145 146 2021-07-03 Nick Clifton <nickc (a] redhat.com> 147 148 * configure: Regenerate. 149 * po/opcodes.pot: Regenerate. 150 151 2021-07-03 Nick Clifton <nickc (a] redhat.com> 152 153 * 2.37 release branch created. 154 155 2021-07-02 Alan Modra <amodra (a] gmail.com> 156 157 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return. 158 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg. 159 (nds32_field_table, nds32_opcode_table, nds32_keyword_table), 160 (nds32_opcodes, nds32_operand_fields, nds32_keywords), 161 (nds32_keyword_gpr): Move declarations to.. 162 * nds32-asm.h: ..here, constifying to match definitions. 163 164 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 165 166 * Makefile.am (GUILE): New variable. 167 (CGEN): Use $(GUILE). 168 * Makefile.in: Regenerate. 169 170 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 171 172 * mep-asm.c (macros): Mark static & const. 173 (lookup_macro): Change return & m to const. 174 (expand_macro): Change mac to const. 175 (expand_string): Change pmacro to const. 176 177 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 178 179 * nds32-asm.c (operand_fields): Rename to ... 180 (nds32_operand_fields): ... this. 181 (keyword_gpr): Rename to ... 182 (nds32_keyword_gpr): ... this. 183 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr, 184 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, 185 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st, 186 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator, 187 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx): 188 Mark static. 189 (keywords): Rename to ... 190 (nds32_keywords): ... this. 191 * nds32-dis.c: Rename operand_fields to nds32_operand_fields, 192 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr. 193 194 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 195 196 * z80-dis.c (opc_ed): Make const. 197 (pref_ed): Make p const. 198 199 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 200 201 * microblaze-dis.c (get_field_special): Make op const. 202 (read_insn_microblaze): Make opr & op const. Rename opcodes to 203 microblaze_opcodes. 204 (print_insn_microblaze): Make op & pop const. 205 (get_insn_microblaze): Make op const. Rename opcodes to 206 microblaze_opcodes. 207 (microblaze_get_target_address): Likewise. 208 * microblaze-opc.h (struct op_code_struct): Make const. 209 Rename opcodes to microblaze_opcodes. 210 211 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 212 213 * aarch64-gen.c (aarch64_opcode_table): Add const. 214 * aarch64-tbl.h (aarch64_opcode_table): Likewise. 215 216 2021-06-22 Andrew Burgess <andrew.burgess (a] embecosm.com> 217 218 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when 219 available. 220 221 2021-06-22 Alan Modra <amodra (a] gmail.com> 222 223 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do 224 print separator for pcrel insns. 225 226 2021-06-19 Alan Modra <amodra (a] gmail.com> 227 228 * vax-dis.c (print_insn_vax): Avoid pointer overflow. 229 230 2021-06-19 Alan Modra <amodra (a] gmail.com> 231 232 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill 233 entire buffer. 234 235 2021-06-17 Alan Modra <amodra (a] gmail.com> 236 237 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location 238 in table. 239 240 2021-06-03 Alan Modra <amodra (a] gmail.com> 241 242 PR 1202 243 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. 244 Use unsigned int for inst. 245 246 2021-06-02 Shahab Vahedi <shahab (a] synopsys.com> 247 248 * arc-dis.c (arc_option_arg_t): New enumeration. 249 (arc_options): New variable. 250 (disassembler_options_arc): New function. 251 (print_arc_disassembler_options): Reimplement in terms of 252 "disassembler_options_arc". 253 254 2021-05-29 Alan Modra <amodra (a] gmail.com> 255 256 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. 257 Don't special case PPC_OPCODE_RAW. 258 (lookup_prefix): Likewise. 259 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. 260 (print_insn_powerpc): ..update caller. 261 * ppc-opc.c (EXT): Define. 262 (powerpc_opcodes): Mark extended mnemonics with EXT. 263 (prefix_opcodes, vle_opcodes): Likewise. 264 (XISEL, XISEL_MASK): Add cr field and simplify. 265 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort 266 all isel variants to where the base mnemonic belongs. Sort dstt, 267 dststt and dssall. 268 269 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 270 271 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2, 272 COP3 opcode instructions. 273 274 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 275 276 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for 277 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", 278 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", 279 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", 280 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", 281 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", 282 "cop2", and "cop3" entries. 283 284 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 285 286 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" 287 entries and associated comments. 288 289 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 290 291 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead 292 of "c0". 293 294 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 295 296 * mips-dis.c (mips_cp1_names_mips): New variable. 297 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' 298 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", 299 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", 300 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", 301 "r12000", "r14000", "r16000", "mips5", "loongson2e", and 302 "loongson2f". 303 304 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 305 306 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register 307 handling code over to... 308 <OP_REG_CONTROL>: ... this new case. 309 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. 310 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", 311 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries 312 replacing the `G' operand code with `g'. Update "cftc1" and 313 "cftc2" entries replacing the `E' operand code with `y'. 314 * micromips-opc.c (decode_micromips_operand) <'g'>: New case. 315 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" 316 entries replacing the `G' operand code with `g'. 317 318 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 319 320 * mips-dis.c (mips_cp0_names_r3900): New variable. 321 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' 322 for "r3900". 323 324 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 325 326 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", 327 and "mtthc2" to using the `G' rather than `g' operand code for 328 the coprocessor control register referred. 329 330 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 331 332 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" 333 entries with each other. 334 335 2021-05-27 Peter Bergner <bergner (a] linux.ibm.com> 336 337 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. 338 339 2021-05-25 Alan Modra <amodra (a] gmail.com> 340 341 * cris-desc.c: Regenerate. 342 * cris-desc.h: Regenerate. 343 * cris-opc.h: Regenerate. 344 * po/POTFILES.in: Regenerate. 345 346 2021-05-24 Mike Frysinger <vapier (a] gentoo.org> 347 348 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h. 349 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c. 350 (CGEN_CPUS): Add cris. 351 (CRIS_DEPS): Define. 352 (stamp-cris): New rule. 353 * cgen.sh: Handle desc action. 354 * configure.ac (bfd_cris_arch): Add cris-desc.lo. 355 * Makefile.in, configure: Regenerate. 356 357 2021-05-18 Job Noorman <mtvec (a] pm.me> 358 359 PR 27814 360 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for 361 the elf objects. 362 363 2021-05-17 Alex Coplan <alex.coplan (a] arm.com> 364 365 * arm-dis.c (mve_opcodes): Fix disassembly of 366 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. 367 (is_mve_encoding_conflict): MVE vector loads should not match 368 when P = W = 0. 369 (is_mve_unpredictable): It's not unpredictable to use the same 370 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE). 371 372 2021-05-11 Nick Clifton <nickc (a] redhat.com> 373 374 PR 27840 375 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond 376 the end of the code buffer. 377 378 2021-05-06 Stafford Horne <shorne (a] gmail.com> 379 380 PR 21464 381 * or1k-asm.c: Regenerate. 382 383 2021-05-01 Max Filippov <jcmvbkbc (a] gmail.com> 384 385 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and 386 info->insn_info_valid. 387 388 2021-04-26 Jan Beulich <jbeulich (a] suse.com> 389 390 * i386-opc.tbl (lea): Add Optimize. 391 * opcodes/i386-tbl.h: Re-generate. 392 393 2020-04-23 Max Filippov <jcmvbkbc (a] gmail.com> 394 395 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand 396 of l32r fetch and display referenced literal value. 397 398 2021-04-23 Max Filippov <jcmvbkbc (a] gmail.com> 399 400 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk 401 to 4 for literal disassembly. 402 403 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 404 405 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support 406 for TLBI instruction. 407 408 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 409 410 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for 411 DC instruction. 412 413 2021-04-19 Jan Beulich <jbeulich (a] suse.com> 414 415 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for 416 "qualifier". 417 (convert_mov_to_movewide): Add initializer for "value". 418 419 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 420 421 * aarch64-opc.c: Add RME system registers. 422 423 2021-04-16 Lifang Xia <lifang_xia (a] c-sky.com> 424 425 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress 426 "addi d,CV,z" to "c.mv d,CV". 427 428 2021-04-12 Alan Modra <amodra (a] gmail.com> 429 430 * configure.ac (--enable-checking): Add support. 431 * config.in: Regenerate. 432 * configure: Regenerate. 433 434 2021-04-09 Tejas Belagod <tejas.belagod (a] arm.com> 435 436 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify 437 LD64/ST64 instructions to lse_atomic instead of ldstexcl. 438 439 2021-04-09 Alan Modra <amodra (a] gmail.com> 440 441 * ppc-dis.c (struct dis_private): Add "special". 442 (POWERPC_DIALECT): Delete. Replace uses with.. 443 (private_data): ..this. New inline function. 444 (disassemble_init_powerpc): Init "special" names. 445 (skip_optional_operands): Add is_pcrel arg, set when detecting R 446 field of prefix instructions. 447 (bsearch_reloc, print_got_plt): New functions. 448 (print_insn_powerpc): For pcrel instructions, print target address 449 and symbol if known, and decode plt and got loads too. 450 451 2021-04-08 Alan Modra <amodra (a] gmail.com> 452 453 PR 27684 454 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir. 455 456 2021-04-08 Alan Modra <amodra (a] gmail.com> 457 458 PR 27676 459 * ppc-opc.c (DCBT_EO): Move earlier. 460 (insert_thct, extract_thct, insert_thds, extract_thds): New functions. 461 (powerpc_operands): Add THCT and THDS entries. 462 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. 463 464 2021-04-06 Alan Modra <amodra (a] gmail.com> 465 466 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL. 467 * s12z-dis.c (decode_possible_symbol): Use symbol returned from 468 symbol_at_address_func. 469 470 2021-04-05 Alan Modra <amodra (a] gmail.com> 471 472 * configure.ac: Don't check for limits.h, string.h, strings.h or 473 stdlib.h. 474 (AC_ISC_POSIX): Don't invoke. 475 * sysdep.h: Include stdlib.h and string.h unconditionally. 476 * i386-opc.h: Include limits.h unconditionally. 477 * wasm32-dis.c: Likewise. 478 * cgen-opc.c: Don't include alloca-conf.h. 479 * config.in: Regenerate. 480 * configure: Regenerate. 481 482 2021-04-01 Martin Liska <mliska (a] suse.cz> 483 484 * arm-dis.c (strneq): Remove strneq and use startswith. 485 * cr16-dis.c (print_insn_cr16): Likewise. 486 * score-dis.c (streq): Likewise. 487 (strneq): Likewise. 488 * score7-dis.c (strneq): Likewise. 489 490 2021-04-01 Alan Modra <amodra (a] gmail.com> 491 492 PR 27675 493 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2. 494 495 2021-03-31 Alan Modra <amodra (a] gmail.com> 496 497 * sysdep.h (POISON_BFD_BOOLEAN): Define. 498 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, 499 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, 500 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, 501 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, 502 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, 503 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, 504 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, 505 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, 506 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, 507 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, 508 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, 509 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, 510 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, 511 and TRUE with true throughout. 512 513 2021-03-31 Alan Modra <amodra (a] gmail.com> 514 515 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. 516 * aarch64-dis.h: Likewise. 517 * aarch64-opc.c: Likewise. 518 * avr-dis.c: Likewise. 519 * csky-dis.c: Likewise. 520 * nds32-asm.c: Likewise. 521 * nds32-dis.c: Likewise. 522 * nfp-dis.c: Likewise. 523 * riscv-dis.c: Likewise. 524 * s12z-dis.c: Likewise. 525 * wasm32-dis.c: Likewise. 526 527 2021-03-30 Jan Beulich <jbeulich (a] suse.com> 528 529 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete. 530 (i386_seg_prefixes): New. 531 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete. 532 (i386_seg_prefixes): Declare. 533 534 2021-03-30 Jan Beulich <jbeulich (a] suse.com> 535 536 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete. 537 538 2021-03-30 Jan Beulich <jbeulich (a] suse.com> 539 540 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values. 541 * i386-reg.tbl (st): Move down. 542 (st(0)): Delete. Extend comment. 543 * i386-tbl.h: Re-generate. 544 545 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 546 547 * i386-opc.tbl (movq, movabs): Move next to mov counterparts. 548 (cmpsd): Move next to cmps. 549 (movsd): Move next to movs. 550 (cmpxchg16b): Move to separate section. 551 (fisttp, fisttpll): Likewise. 552 (monitor, mwait): Likewise. 553 * i386-tbl.h: Re-generate. 554 555 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 556 557 * i386-opc.tbl (psadbw): Add <sse2:comm>. 558 (vpsadbw): Add C. 559 * i386-tbl.h: Re-generate. 560 561 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 562 563 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes, 564 pclmul, gfni): New templates. Use them wherever possible. Move 565 SSE4.1 pextrw into respective section. 566 * i386-tbl.h: Re-generate. 567 568 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 569 570 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use 571 strtoull(). Bump upper loop bound. Widen masks. Sanity check 572 "length". 573 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete. 574 Convert all of their uses to representation in opcode. 575 576 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 577 578 * i386-opc.h (struct insn_template): Shrink base_opcode to 16 579 bits. Shrink extension_opcode to 9 bits. Make it signed. Change 580 value of None. Shrink operands to 3 bits. 581 582 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 583 584 * i386-gen.c (process_i386_opcode_modifier): New parameter 585 "space". 586 (output_i386_opcode): New local variable "space". Adjust 587 process_i386_opcode_modifier() invocation. 588 (process_i386_opcodes): Adjust process_i386_opcode_modifier() 589 invocation. 590 * i386-tbl.h: Re-generate. 591 592 2021-03-29 Alan Modra <amodra (a] gmail.com> 593 594 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. 595 (fp_qualifier_p, get_data_pattern): Likewise. 596 (aarch64_get_operand_modifier_from_value): Likewise. 597 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. 598 (operand_variant_qualifier_p): Likewise. 599 (qualifier_value_in_range_constraint_p): Likewise. 600 (aarch64_get_qualifier_esize): Likewise. 601 (aarch64_get_qualifier_nelem): Likewise. 602 (aarch64_get_qualifier_standard_value): Likewise. 603 (get_lower_bound, get_upper_bound): Likewise. 604 (aarch64_find_best_match, match_operands_qualifier): Likewise. 605 (aarch64_print_operand): Likewise. 606 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. 607 (operand_need_sign_extension, operand_need_shift_by_two): Likewise. 608 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. 609 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. 610 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. 611 (print_insn_tic6x): Likewise. 612 613 2021-03-29 Alan Modra <amodra (a] gmail.com> 614 615 * arc-dis.c (extract_operand_value): Correct NULL cast. 616 * frv-opc.h: Regenerate. 617 618 2021-03-26 Jan Beulich <jbeulich (a] suse.com> 619 620 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to 621 MMX form. 622 * i386-tbl.h: Re-generate. 623 624 2021-03-25 Abid Qadeer <abidh (a] codesourcery.com> 625 626 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of 627 immediate in br.n instruction. 628 629 2021-03-25 Jan Beulich <jbeulich (a] suse.com> 630 631 * i386-dis.c (XMGatherD, VexGatherD): New. 632 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*. 633 (print_insn): Check masking for S/G insns. 634 (OP_E_memory): New local variable check_gather. Extend mandatory 635 SIB check. Check register conflicts for (EVEX-encoded) gathers. 636 Extend check for disallowed 16-bit addressing. 637 (OP_VEX): New local variables modrm_reg and sib_index. Convert 638 if()s to switch(). Check register conflicts for (VEX-encoded) 639 gathers. Drop no longer reachable cases. 640 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and 641 vgatherdp*. 642 643 2021-03-25 Jan Beulich <jbeulich (a] suse.com> 644 645 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying 646 zeroing-masking without masking. 647 648 2021-03-25 Jan Beulich <jbeulich (a] suse.com> 649 650 * i386-opc.tbl (invlpgb): Fix multi-operand form. 651 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark 652 single-operand forms as deprecated. 653 * i386-tbl.h: Re-generate. 654 655 2021-03-25 Alan Modra <amodra (a] gmail.com> 656 657 PR 27647 658 * ppc-opc.c (XLOCB_MASK): Delete. 659 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using 660 XLBH_MASK. 661 (powerpc_opcodes): Accept a BH field on all extended forms of 662 bclr, bclrl, bcctr, bcctrl, bctar, bctarl. 663 664 2021-03-24 Jan Beulich <jbeulich (a] suse.com> 665 666 * i386-gen.c (output_i386_opcode): Drop processing of 667 opcode_length. Calculate length from base_opcode. Adjust prefix 668 encoding determination. 669 (process_i386_opcodes): Drop output of fake opcode_length. 670 * i386-opc.h (struct insn_template): Drop opcode_length field. 671 * i386-opc.tbl: Drop opcode length field from all templates. 672 * i386-tbl.h: Re-generate. 673 674 2021-03-24 Jan Beulich <jbeulich (a] suse.com> 675 676 * i386-gen.c (process_i386_opcode_modifier): Return void. New 677 parameter "prefix". Drop local variable "regular_encoding". 678 Record prefix setting / check for consistency. 679 (output_i386_opcode): Parse opcode_length and base_opcode 680 earlier. Derive prefix encoding. Drop no longer applicable 681 consistency checking. Adjust process_i386_opcode_modifier() 682 invocation. 683 (process_i386_opcodes): Adjust process_i386_opcode_modifier() 684 invocation. 685 * i386-tbl.h: Re-generate. 686 687 2021-03-24 Jan Beulich <jbeulich (a] suse.com> 688 689 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix 690 check. 691 * i386-opc.h (Prefix_*): Move #define-s. 692 * i386-opc.tbl: Move pseudo prefix enumerator values to 693 extension opcode field. Introduce pseudopfx template. 694 * i386-tbl.h: Re-generate. 695 696 2021-03-23 Jan Beulich <jbeulich (a] suse.com> 697 698 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend 699 comment. 700 * i386-tbl.h: Re-generate. 701 702 2021-03-23 Jan Beulich <jbeulich (a] suse.com> 703 704 * i386-opc.h (struct insn_template): Move cpu_flags field past 705 opcode_modifier one. 706 * i386-tbl.h: Re-generate. 707 708 2021-03-23 Jan Beulich <jbeulich (a] suse.com> 709 710 * i386-gen.c (opcode_modifiers): New OpcodeSpace element. 711 * i386-opc.h (OpcodeSpace): New enumerator. 712 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ... 713 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08, 714 SPACE_XOP09, SPACE_XOP0A): ... respectively. 715 (struct i386_opcode_modifier): New field opcodespace. Shrink 716 opcodeprefix field. 717 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08, 718 SpaceXOP09, SpaceXOP0A): Define. Use them to replace 719 OpcodePrefix uses. 720 * i386-tbl.h: Re-generate. 721 722 2021-03-22 Martin Liska <mliska (a] suse.cz> 723 724 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. 725 * arc-dis.c (parse_option): Likewise. 726 * arm-dis.c (parse_arm_disassembler_options): Likewise. 727 * cris-dis.c (print_with_operands): Likewise. 728 * h8300-dis.c (bfd_h8_disassemble): Likewise. 729 * i386-dis.c (print_insn): Likewise. 730 * ia64-gen.c (fetch_insn_class): Likewise. 731 (parse_resource_users): Likewise. 732 (in_iclass): Likewise. 733 (lookup_specifier): Likewise. 734 (insert_opcode_dependencies): Likewise. 735 * mips-dis.c (parse_mips_ase_option): Likewise. 736 (parse_mips_dis_option): Likewise. 737 * s390-dis.c (disassemble_init_s390): Likewise. 738 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise. 739 740 2021-03-16 Kuan-Lin Chen <kuanlinchentw (a] gmail.com> 741 742 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions. 743 744 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 745 746 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, 747 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers. 748 749 2021-03-12 Alan Modra <amodra (a] gmail.com> 750 751 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo. 752 753 2021-03-11 Jan Beulich <jbeulich (a] suse.com> 754 755 * i386-dis.c (OP_XMM): Re-order checks. 756 757 2021-03-11 Jan Beulich <jbeulich (a] suse.com> 758 759 * i386-dis.c (putop): Drop need_vex check when also checking 760 vex.evex. 761 (intel_operand_size, OP_E_memory): Drop vex.evex check when also 762 checking vex.b. 763 764 2021-03-11 Jan Beulich <jbeulich (a] suse.com> 765 766 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast 767 checks. Move case label past broadcast check. 768 769 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 770 771 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX, 772 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode, 773 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1, 774 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3, 775 EVEX_W_0F38C7_M_0_L_2): Delete. 776 (REG_EVEX_0F38C7_M_0_L_2): New. 777 (intel_operand_size): Handle VEX and EVEX the same for 778 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop 779 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases. 780 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and 781 vex_vsib_q_w_d_mode uses. 782 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893, 783 0F38A1, and 0F38A3 entries. 784 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7 785 entry. 786 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries. 787 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and 788 0F38A3 entries. 789 790 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 791 792 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0, 793 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0, 794 MOD_VEX_0FXOP_09_12): Rename to ... 795 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0, 796 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these. 797 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT, 798 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26, 799 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, 800 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move. 801 (reg_table): Adjust comments. 802 (x86_64_table): Move X86_64_0F24, X86_64_0F26, 803 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, 804 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries. 805 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries. 806 (vex_len_table): Adjust opcode 0A_12 entry. 807 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, 808 MOD_C5_32BIT, and MOD_XOP_09_12 entries. 809 (rm_table): Move hreset entry. 810 811 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 812 813 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1, 814 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6, 815 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15, 816 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20, 817 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete. 818 (EVEX_LEN_0F3816, EVEX_W_0FD6): New. 819 (get_valid_dis386): Also handle 512-bit vector length when 820 vectoring into vex_len_table[]. 821 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5, 822 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 823 entries. 824 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6, 825 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries. 826 * i386-dis-evex-prefix.h: Adjust 0F7E entry. 827 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21 828 entries. 829 830 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 831 832 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1): 833 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively. 834 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete. 835 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01 836 entries. 837 * i386-dis-evex-len.h (evex_len_table): Likewise. 838 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries. 839 840 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 841 842 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7, 843 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, 844 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, 845 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1, 846 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, 847 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, 848 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, 849 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6 850 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1, 851 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0, 852 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0, 853 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0, 854 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0, 855 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0, 856 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0, 857 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1, 858 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1, 859 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1, 860 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1, 861 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0, 862 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1, 863 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0, 864 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1, 865 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0, 866 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1, 867 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819, 868 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B, 869 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0, 870 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0, 871 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B, 872 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A, 873 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete. 874 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0, 875 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A, 876 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B, 877 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819, 878 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0, 879 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0, 880 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0, 881 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A, 882 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38, 883 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B, 884 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n, 885 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n, 886 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2, 887 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2, 888 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n, 889 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2, 890 EVEX_W_0F3A43_L_n): New. 891 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A, 892 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 893 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries. 894 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[] 895 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7, 896 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 897 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6. 898 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A, 899 0F385B, 0F38C6, and 0F38C7 entries. 900 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes 901 0F38C6 and 0F38C7. 902 * i386-dis-evex-w.h: No longer link to evex_len_table[] for 903 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 904 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to 905 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B. 906 907 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 908 909 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1, 910 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, 911 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, 912 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, 913 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, 914 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, 915 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, 916 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, 917 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, 918 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, 919 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, 920 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, 921 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, 922 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, 923 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, 924 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, 925 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, 926 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, 927 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, 928 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, 929 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0, 930 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, 931 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, 932 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, 933 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, 934 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, 935 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, 936 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, 937 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, 938 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0, 939 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2, 940 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0, 941 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2, 942 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, 943 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, 944 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0, 945 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2, 946 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2, 947 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2, 948 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1, 949 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, 950 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0, 951 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1, 952 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1, 953 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1, 954 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, 955 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, 956 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, 957 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, 958 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, 959 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0, 960 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0, 961 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, 962 VEX_W_0F99_P_2_LEN_0): Delete. 963 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0, 964 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1, 965 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0, 966 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0, 967 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0, 968 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0, 969 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0, 970 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0, 971 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0, 972 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0, 973 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0, 974 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0, 975 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0, 976 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0, 977 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0, 978 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0, 979 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0, 980 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0, 981 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42, 982 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47, 983 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91, 984 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99, 985 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1, 986 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1, 987 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0, 988 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1, 989 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New. 990 (prefix_table): No longer link to vex_len_table[] for opcodes 991 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 992 0F92, 0F93, 0F98, and 0F99. 993 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42, 994 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 995 0F98, and 0F99. 996 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42, 997 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 998 0F98, and 0F99. 999 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42, 1000 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1001 0F98, and 0F99. 1002 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42, 1003 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1004 0F98, and 0F99. 1005 1006 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1007 1008 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73): 1009 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and 1010 REG_VEX_0F73_M_0 respectively. 1011 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6, 1012 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6, 1013 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, 1014 MOD_VEX_0F73_REG_7): Delete. 1015 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New. 1016 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7, 1017 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0, 1018 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, 1019 PREFIX_VEX_0F3AF0_L_0 respectively. 1020 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3, 1021 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3, 1022 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1, 1023 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete. 1024 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6, 1025 VEX_LEN_0F38F7): New. 1026 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0. 1027 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71, 1028 0F72, and 0F73. No longer link to vex_len_table[] for opcode 1029 0F38F3. 1030 (prefix_table): No longer link to vex_len_table[] for opcodes 1031 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. 1032 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and 1033 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5, 1034 0F38F6, 0F38F7, and 0F3AF0. 1035 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to 1036 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. 1037 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and 1038 0F73. 1039 1040 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1041 1042 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to 1043 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively. 1044 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2, 1045 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3, 1046 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete. 1047 (MOD_0F71, MOD_0F72, MOD_0F73): New. 1048 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and 1049 73. 1050 (reg_table): No longer link to mod_table[] for opcodes 0F71, 1051 0F72, and 0F73. 1052 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and 1053 0F73. 1054 1055 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1056 1057 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5, 1058 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete. 1059 (reg_table): Don't link to mod_table[] where not needed. Add 1060 PREFIX_IGNORED to nop entries. 1061 (prefix_table): Replace PREFIX_OPCODE in nop entries. 1062 (mod_table): Add nop entries next to prefetch ones. Drop 1063 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and 1064 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries. 1065 (rm_table): Add PREFIX_IGNORED to nop entries. Drop 1066 PREFIX_OPCODE from endbr* entries. 1067 (get_valid_dis386): Also consider entry's name when zapping 1068 vindex. 1069 (print_insn): Handle PREFIX_IGNORED. 1070 1071 2021-03-09 Jan Beulich <jbeulich (a] suse.com> 1072 1073 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk, 1074 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk 1075 element. 1076 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone, 1077 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete. 1078 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack, 1079 PrefixLock, PrefixHLELock, PrefixHLEAny): Define. 1080 (struct i386_opcode_modifier): Delete notrackprefixok, 1081 islockable, hleprefixok, and repprefixok fields. Add prefixok 1082 field. 1083 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny, 1084 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define. 1085 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg, 1086 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b): 1087 Replace HLEPrefixOk. 1088 * opcodes/i386-tbl.h: Re-generate. 1089 1090 2021-03-09 Jan Beulich <jbeulich (a] suse.com> 1091 1092 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit. 1093 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from 1094 64-bit form. 1095 * opcodes/i386-tbl.h: Re-generate. 1096 1097 2021-03-03 Jan Beulich <jbeulich (a] suse.com> 1098 1099 * i386-gen.c (output_i386_opcode): Don't get operand count. Look 1100 for {} instead of {0}. Don't look for '0'. 1101 * i386-opc.tbl: Drop operand count field. Drop redundant operand 1102 size specifiers. 1103 1104 2021-02-19 Nelson Chu <nelson.chu (a] sifive.com> 1105 1106 PR 27158 1107 * riscv-dis.c (print_insn_args): Updated encoding macros. 1108 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. 1109 (match_c_addi16sp): Updated encoding macros. 1110 (match_c_lui): Likewise. 1111 (match_c_lui_with_hint): Likewise. 1112 (match_c_addi4spn): Likewise. 1113 (match_c_slli): Likewise. 1114 (match_slli_as_c_slli): Likewise. 1115 (match_c_slli64): Likewise. 1116 (match_srxi_as_c_srxi): Likewise. 1117 (riscv_insn_types): Added .insn css/cl/cs. 1118 1119 2021-02-18 Nelson Chu <nelson.chu (a] sifive.com> 1120 1121 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. 1122 (default_priv_spec): Updated type to riscv_spec_class. 1123 (parse_riscv_dis_option): Updated. 1124 * riscv-opc.c: Moved stuff and make the file tidy. 1125 1126 2021-02-17 Alan Modra <amodra (a] gmail.com> 1127 1128 * wasm32-dis.c: Include limits.h. 1129 (CHAR_BIT): Provide backup define. 1130 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. 1131 Correct signed overflow checking. 1132 1133 2021-02-16 Jan Beulich <jbeulich (a] suse.com> 1134 1135 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant. 1136 * i386-tbl.h: Re-generate. 1137 1138 2021-02-16 Jan Beulich <jbeulich (a] suse.com> 1139 1140 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor 1141 Oword. 1142 * i386-opc.tbl (CpuFP, Mmword, Oword): Define. 1143 1144 2021-02-15 Andreas Krebbel <krebbel (a] linux.ibm.com> 1145 1146 * s390-mkopc.c (main): Accept arch14 as cpu string. 1147 * s390-opc.txt: Add new arch14 instructions. 1148 1149 2021-02-04 Nick Alcock <nick.alcock (a] oracle.com> 1150 1151 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in 1152 favour of LIBINTL. 1153 * configure: Regenerated. 1154 1155 2021-02-08 Mike Frysinger <vapier (a] gentoo.org> 1156 1157 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs. 1158 * tic54x-opc.c (regs): Rename to ... 1159 (tic54x_regs): ... this. 1160 (mmregs): Rename to ... 1161 (tic54x_mmregs): ... this. 1162 (condition_codes): Rename to ... 1163 (tic54x_condition_codes): ... this. 1164 (cc2_codes): Rename to ... 1165 (tic54x_cc2_codes): ... this. 1166 (cc3_codes): Rename to ... 1167 (tic54x_cc3_codes): ... this. 1168 (status_bits): Rename to ... 1169 (tic54x_status_bits): ... this. 1170 (misc_symbols): Rename to ... 1171 (tic54x_misc_symbols): ... this. 1172 1173 2021-02-04 Nelson Chu <nelson.chu (a] sifive.com> 1174 1175 * riscv-opc.c (MASK_RVB_IMM): Removed. 1176 (riscv_opcodes): Removed zb* instructions. 1177 (riscv_ext_version_table): Removed versions for zb*. 1178 1179 2021-01-26 Alan Modra <amodra (a] gmail.com> 1180 1181 * i386-gen.c (parse_template): Ensure entire template_instance 1182 is initialised. 1183 1184 2021-01-15 Nelson Chu <nelson.chu (a] sifive.com> 1185 1186 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. 1187 (riscv_fpr_names_abi): Likewise. 1188 (riscv_opcodes): Likewise. 1189 (riscv_insn_types): Likewise. 1190 1191 2021-01-15 Nelson Chu <nelson.chu (a] sifive.com> 1192 1193 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message. 1194 1195 2021-01-15 Nelson Chu <nelson.chu (a] sifive.com> 1196 1197 * riscv-dis.c: Comments tidy and improvement. 1198 * riscv-opc.c: Likewise. 1199 1200 2021-01-13 Alan Modra <amodra (a] gmail.com> 1201 1202 * Makefile.in: Regenerate. 1203 1204 2021-01-12 H.J. Lu <hongjiu.lu (a] intel.com> 1205 1206 PR binutils/26792 1207 * configure.ac: Use GNU_MAKE_JOBSERVER. 1208 * aclocal.m4: Regenerated. 1209 * configure: Likewise. 1210 1211 2021-01-12 Nick Clifton <nickc (a] redhat.com> 1212 1213 * po/sr.po: Updated Serbian translation. 1214 1215 2021-01-11 H.J. Lu <hongjiu.lu (a] intel.com> 1216 1217 PR ld/27173 1218 * configure: Regenerated. 1219 1220 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov (a] arm.com> 1221 1222 * aarch64-asm-2.c: Regenerate. 1223 * aarch64-dis-2.c: Likewise. 1224 * aarch64-opc-2.c: Likewise. 1225 * aarch64-opc.c (aarch64_print_operand): 1226 Delete handling of AARCH64_OPND_CSRE_CSR. 1227 * aarch64-tbl.h (aarch64_feature_csre): Delete. 1228 (CSRE): Likewise. 1229 (_CSRE_INSN): Likewise. 1230 (aarch64_opcode_table): Delete csr. 1231 1232 2021-01-11 Nick Clifton <nickc (a] redhat.com> 1233 1234 * po/de.po: Updated German translation. 1235 * po/fr.po: Updated French translation. 1236 * po/pt_BR.po: Updated Brazilian Portuguese translation. 1237 * po/sv.po: Updated Swedish translation. 1238 * po/uk.po: Updated Ukranian translation. 1239 1240 2021-01-09 H.J. Lu <hongjiu.lu (a] intel.com> 1241 1242 * configure: Regenerated. 1243 1244 2021-01-09 Nick Clifton <nickc (a] redhat.com> 1245 1246 * configure: Regenerate. 1247 * po/opcodes.pot: Regenerate. 1248 1249 2021-01-09 Nick Clifton <nickc (a] redhat.com> 1250 1251 * 2.36 release branch crated. 1252 1253 2021-01-08 Peter Bergner <bergner (a] linux.ibm.com> 1254 1255 * ppc-opc.c (insert_dw, (extract_dw): New functions. 1256 (DW, (XRC_MASK): Define. 1257 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. 1258 1259 2021-01-09 Alan Modra <amodra (a] gmail.com> 1260 1261 * configure: Regenerate. 1262 1263 2021-01-08 Nick Clifton <nickc (a] redhat.com> 1264 1265 * po/sv.po: Updated Swedish translation. 1266 1267 2021-01-08 Nick Clifton <nickc (a] redhat.com> 1268 1269 PR 27129 1270 * aarch64-dis.c (determine_disassembling_preference): Move call to 1271 aarch64_match_operands_constraint outside of the assertion. 1272 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. 1273 Replace with a return of FALSE. 1274 1275 PR 27139 1276 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a 1277 core system register. 1278 1279 2021-01-07 Samuel Thibault <samuel.thibault (a] gnu.org> 1280 1281 * configure: Regenerate. 1282 1283 2021-01-07 Nick Clifton <nickc (a] redhat.com> 1284 1285 * po/fr.po: Updated French translation. 1286 1287 2021-01-07 Fredrik Noring <noring (a] nocrew.org> 1288 1289 * m68k-opc.c (chkl): Change minimum architecture requirement to 1290 m68020. 1291 1292 2021-01-07 Philipp Tomsich <prt (a] gnu.org> 1293 1294 * riscv-opc.c (riscv_opcodes): Add pause hint instruction. 1295 1296 2021-01-07 Claire Xenia Wolf <claire (a] symbioticeda.com> 1297 Jim Wilson <jimw (a] sifive.com> 1298 Andrew Waterman <andrew (a] sifive.com> 1299 Maxim Blinov <maxim.blinov (a] embecosm.com> 1300 Kito Cheng <kito.cheng (a] sifive.com> 1301 Nelson Chu <nelson.chu (a] sifive.com> 1302 1303 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. 1304 (MASK_RVB_IMM): Used for rev8 and orc.b encoding. 1305 1306 2021-01-01 Alan Modra <amodra (a] gmail.com> 1307 1308 Update year range in copyright notice of all files. 1309 1310 For older changes see ChangeLog-2020 1311 1313 Copyright (C) 2021-2022 Free Software Foundation, Inc. 1314 1315 Copying and distribution of this file, with or without modification, 1316 are permitted in any medium without royalty provided the copyright 1317 notice and this notice are preserved. 1318 1319 Local Variables: 1320 mode: change-log 1321 left-margin: 8 1322 fill-column: 74 1323 version-control: never 1324 End: 1325
Indexes created Tue Oct 27 00:25:24 UTC 2026