ChangeLog revision 1.12
1 2024-01-15 Nick Clifton <nickc (a] redhat.com> 2 3 * configure: Regenerate. 4 * po/opcodes.pot: Regenerate. 5 6 2024-01-15 Nick Clifton <nickc (a] redhat.com> 7 8 * 2.42 branch point. 9 10 2023-11-15 Arsen Arsenovi <arsen (a] aarsen.me> 11 12 * aclocal.m4: Regenerate. 13 * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot 14 temporary file to suppress xgettext checking charset names. 15 * configure.ac (SHARED_LIBADD): Use LTLIBINTL rather than 16 LIBINTL. 17 * configure: Regenerate. 18 * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot 19 temporary file, to suppress xgettext checking charset names. 20 21 2023-10-05 Neal frager <neal.frager (a] amd.com> 22 23 * microblaze-opcm.h (struct op_code_struct): Tidy and remove 24 redundant entries. 25 * microblaze-opc.h (MAX_OPCODES): Increase to 300. 26 (op_code_struct): Add address extension instructions. 27 28 2023-10-04 Neal frager <neal.frager (a] amd.com> 29 30 * microblaze-opc.h (struct op_code_struct): Add hiberante 31 and suspend entries. 32 * microblaze-opcm.h (enum microblaze_instr): Add microblaze_sleep, 33 hibernate, suspend entries. 34 35 2023-08-24 Tom Tromey <tom (a] tromey.com> 36 37 * cgen.sh: Don't pass "-s" to cgen. 38 * Makefile.in: Rebuild. 39 * Makefile.am (GUILE): Simplify. 40 41 2023-07-31 Jose E. Marchesi <jose.marchesi (a] oracle.com> 42 43 PR 30705 44 * bpf-dis.c (print_insn_bpf): Check that info->section->owner is 45 actually available before using it. 46 47 2023-07-30 Jose E. Marchesi <jose.marchesi (a] oracle.com> 48 49 * bpf-dis.c: Initialize asm_bpf_version to -1. 50 (print_insn_bpf): Set BPF ISA version from the cpu version ELF 51 header flags if no explicit version set in the command line. 52 * disassemble.c (disassemble_init_for_target): Remove unused code. 53 54 2023-07-26 Jose E. Marchesi <jose.marchesi (a] oracle.com> 55 56 * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src 57 register. 58 59 2023-07-24 Jose E. Marchesi <jose.marchesi (a] oracle.com> 60 61 * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP* 62 instructions. 63 64 2023-07-24 Jose E. Marchesi <jose.marchesi (a] oracle.com> 65 66 * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS* 67 instructions. 68 69 2023-07-23 Jose E. Marchesi <jose.marchesi (a] oracle.com> 70 71 * bpf-opc.c (bpf_opcodes): Add entry for jal. 72 73 2023-07-21 Jose E. Marchesi <jose.marchesi (a] oracle.com> 74 75 * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW} 76 instructions. 77 78 2023-07-21 Jose E. Marchesi <jose.marchesi (a] oracle.com> 79 80 * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and 81 MOVS32{8,16,32}R instructions. and MOVS32I instructions. 82 83 2023-07-21 Jose E. Marchesi <jose.marchesi (a] oracle.com> 84 85 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c 86 * Makefile.in: Regenerate. 87 88 2023-07-03 Nick Clifton <nickc (a] redhat.com> 89 90 * configure: Regenerate. 91 * po/opcodes.pot: Regenerate. 92 93 2023-07-03 Nick Clifton <nickc (a] redhat.com> 94 95 2.41 Branch Point. 96 97 2023-05-23 Nick Clifton <nickc (a] redhat.com> 98 99 * po/sv.po: Updated translation. 100 101 2023-04-21 Tom Tromey <tromey (a] adacore.com> 102 103 * i386-dis.c (OP_J): Check result of get16. 104 105 2023-04-12 Claudiu Zissulescu <claziss (a] synopsys.com> 106 107 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs, 108 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2, 109 vsubs2h, and vsubs4h instructions. 110 111 2023-04-11 Nick Clifton <nickc (a] redhat.com> 112 113 PR 30310 114 * nfp-dis.c (init_nfp6000_priv): Check that the output section 115 exists. 116 117 2023-03-15 Nick Clifton <nickc (a] redhat.com> 118 119 PR 30231 120 * mep-dis.c: Regenerate. 121 122 2023-03-15 Nick Clifton <nickc (a] redhat.com> 123 124 PR 30230 125 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols. 126 127 2023-02-28 Richard Ball <richard.ball (a] arm.com> 128 129 * aarch64-opc.c: Add MEC system registers. 130 131 2023-01-03 Nick Clifton <nickc (a] redhat.com> 132 133 * po/de.po: Updated German translation. 134 * po/ro.po: Updated Romainian translation. 135 * po/uk.po: Updated Ukrainian translation. 136 137 2022-12-31 Nick Clifton <nickc (a] redhat.com> 138 139 * 2.40 branch created. 140 141 2022-11-22 Shahab Vahedi <shahab (a] synopsys.com> 142 143 * arc-regs.h: Change isa_config address to 0xc1. 144 isa_config exists for ARC700 and ARCV2 and not ARCALL. 145 146 2022-10-31 Yoshinori Sato <ysato (a] users.sourceforge.jp> 147 148 * rx-decode.opc: Switch arguments of the MVTACGU insn. 149 * rx-decode.c: Regenerate. 150 151 2022-09-22 Yoshinori Sato <ysato (a] users.sourceforge.jp> 152 153 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC 154 Rm_BANK,Rn is always 1. 155 156 2022-07-21 Peter Bergner <bergner (a] linux.ibm.com> 157 158 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines. 159 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, 160 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, 161 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, 162 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, 163 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, 164 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them. 165 166 2022-07-18 Claudiu Zissulescu <claziss (a] synopsys.com> 167 168 * disassemble.c (disassemble_init_for_target): Set 169 created_styled_output for ARC based targets. 170 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype 171 instead of fprintf_ftype throughout. 172 (find_format): Likewise. 173 (print_flags): Likewise. 174 (print_insn_arc): Likewise. 175 176 2022-07-08 Nick Clifton <nickc (a] redhat.com> 177 178 * 2.39 branch created. 179 180 2022-07-04 Marcus Nilsson <brainbomb (a] gmail.com> 181 182 * disassemble.c: (disassemble_init_for_target): Set 183 created_styled_output for AVR based targets. 184 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype 185 instead of fprintf_ftype throughout. 186 (avr_operand): Pass in and fill disassembler_style when 187 parsing operands. 188 189 2022-04-07 Andreas Krebbel <krebbel (a] linux.ibm.com> 190 191 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode 192 table. 193 194 2022-03-16 Simon Marchi <simon.marchi (a] efficios.com> 195 196 * configure.ac: Handle bfd_amdgcn_arch. 197 * configure: Re-generate. 198 199 2022-03-06 Sagar Patel <sagarmp (a] cs.unc.edu> 200 Maciej W. Rozycki <macro (a] orcam.me.uk> 201 202 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation 203 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions. 204 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and 205 "bnez" instructions. 206 207 2022-02-17 Nick Clifton <nickc (a] redhat.com> 208 209 * po/sr.po: Updated Serbian translation. 210 211 2022-02-14 Sergei Trofimovich <siarheit (a] google.com> 212 213 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'. 214 * microblaze-opc.h: Follow 'fsqrt' rename. 215 216 2022-01-24 Nick Clifton <nickc (a] redhat.com> 217 218 * po/ro.po: Updated Romanian translation. 219 * po/uk.po: Updated Ukranian translation. 220 221 2022-01-22 Nick Clifton <nickc (a] redhat.com> 222 223 * configure: Regenerate. 224 * po/opcodes.pot: Regenerate. 225 226 2022-01-22 Nick Clifton <nickc (a] redhat.com> 227 228 * 2.38 release branch created. 229 230 2022-01-17 Nick Clifton <nickc (a] redhat.com> 231 232 * Makefile.in: Regenerate. 233 * po/opcodes.pot: Regenerate. 234 235 2021-12-02 Marcus Nilsson <brainbomb (a] gmail.com> 236 237 * avr-dis.c (avr_operand); Pass in disassemble_info and fill 238 in insn_type on branching instructions. 239 240 2021-11-25 Andrew Burgess <aburgess (a] redhat.com> 241 Simon Cook <simon.cook (a] embecosm.com> 242 243 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef. 244 (riscv_options): New static global. 245 (disassembler_options_riscv): New function. 246 (print_riscv_disassembler_options): Rewrite to use 247 disassembler_options_riscv. 248 249 2021-11-25 Nick Clifton <nickc (a] redhat.com> 250 251 PR 28614 252 * aarch64-asm.c: Replace assert(0) with real code. 253 * aarch64-dis.c: Likewise. 254 * aarch64-opc.c: Likewise. 255 256 2021-11-25 Nick Clifton <nickc (a] redhat.com> 257 258 * po/fr.po; Updated French translation. 259 260 2021-10-27 Maciej W. Rozycki <macro (a] embecosm.com> 261 262 * Makefile.am: Remove obsolete comment. 263 * configure.ac: Refer `libbfd.la' to link shared BFD library 264 except for Cygwin. 265 * Makefile.in: Regenerate. 266 * configure: Regenerate. 267 268 2021-09-27 Nick Alcock <nick.alcock (a] oracle.com> 269 270 * configure: Regenerate. 271 272 2021-09-25 Peter Bergner <bergner (a] linux.ibm.com> 273 274 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable 275 on POWER5 and later. 276 277 2021-09-20 Andrew Burgess <andrew.burgess (a] embecosm.com> 278 279 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode 280 before an unknown instruction, '%d' is replaced with the 281 instruction length. 282 283 2021-09-02 Nick Clifton <nickc (a] redhat.com> 284 285 PR 28292 286 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place 287 of BFD_RELOC_16. 288 289 2021-08-17 Shahab Vahedi <shahab (a] synopsys.com> 290 291 * arc-regs.h (DEF): Fix the register numbers. 292 293 2021-08-10 Nick Clifton <nickc (a] redhat.com> 294 295 * po/sr.po: Updated Serbian translation. 296 297 2021-07-26 Chenghua Xu <xuchenghua (a] loongson.cn> 298 299 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach. 300 301 2021-06-07 Andreas Krebbel <krebbel (a] linux.ibm.com> 302 303 * s390-opc.txt: Add qpaci. 304 305 2021-07-03 Nick Clifton <nickc (a] redhat.com> 306 307 * configure: Regenerate. 308 * po/opcodes.pot: Regenerate. 309 310 2021-07-03 Nick Clifton <nickc (a] redhat.com> 311 312 * 2.37 release branch created. 313 314 2021-07-02 Alan Modra <amodra (a] gmail.com> 315 316 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return. 317 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg. 318 (nds32_field_table, nds32_opcode_table, nds32_keyword_table), 319 (nds32_opcodes, nds32_operand_fields, nds32_keywords), 320 (nds32_keyword_gpr): Move declarations to.. 321 * nds32-asm.h: ..here, constifying to match definitions. 322 323 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 324 325 * Makefile.am (GUILE): New variable. 326 (CGEN): Use $(GUILE). 327 * Makefile.in: Regenerate. 328 329 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 330 331 * mep-asm.c (macros): Mark static & const. 332 (lookup_macro): Change return & m to const. 333 (expand_macro): Change mac to const. 334 (expand_string): Change pmacro to const. 335 336 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 337 338 * nds32-asm.c (operand_fields): Rename to ... 339 (nds32_operand_fields): ... this. 340 (keyword_gpr): Rename to ... 341 (nds32_keyword_gpr): ... this. 342 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr, 343 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, 344 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st, 345 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator, 346 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx): 347 Mark static. 348 (keywords): Rename to ... 349 (nds32_keywords): ... this. 350 * nds32-dis.c: Rename operand_fields to nds32_operand_fields, 351 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr. 352 353 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 354 355 * z80-dis.c (opc_ed): Make const. 356 (pref_ed): Make p const. 357 358 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 359 360 * microblaze-dis.c (get_field_special): Make op const. 361 (read_insn_microblaze): Make opr & op const. Rename opcodes to 362 microblaze_opcodes. 363 (print_insn_microblaze): Make op & pop const. 364 (get_insn_microblaze): Make op const. Rename opcodes to 365 microblaze_opcodes. 366 (microblaze_get_target_address): Likewise. 367 * microblaze-opc.h (struct op_code_struct): Make const. 368 Rename opcodes to microblaze_opcodes. 369 370 2021-07-01 Mike Frysinger <vapier (a] gentoo.org> 371 372 * aarch64-gen.c (aarch64_opcode_table): Add const. 373 * aarch64-tbl.h (aarch64_opcode_table): Likewise. 374 375 2021-06-22 Andrew Burgess <andrew.burgess (a] embecosm.com> 376 377 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when 378 available. 379 380 2021-06-22 Alan Modra <amodra (a] gmail.com> 381 382 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do 383 print separator for pcrel insns. 384 385 2021-06-19 Alan Modra <amodra (a] gmail.com> 386 387 * vax-dis.c (print_insn_vax): Avoid pointer overflow. 388 389 2021-06-19 Alan Modra <amodra (a] gmail.com> 390 391 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill 392 entire buffer. 393 394 2021-06-17 Alan Modra <amodra (a] gmail.com> 395 396 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location 397 in table. 398 399 2021-06-03 Alan Modra <amodra (a] gmail.com> 400 401 PR 1202 402 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. 403 Use unsigned int for inst. 404 405 2021-06-02 Shahab Vahedi <shahab (a] synopsys.com> 406 407 * arc-dis.c (arc_option_arg_t): New enumeration. 408 (arc_options): New variable. 409 (disassembler_options_arc): New function. 410 (print_arc_disassembler_options): Reimplement in terms of 411 "disassembler_options_arc". 412 413 2021-05-29 Alan Modra <amodra (a] gmail.com> 414 415 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. 416 Don't special case PPC_OPCODE_RAW. 417 (lookup_prefix): Likewise. 418 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. 419 (print_insn_powerpc): ..update caller. 420 * ppc-opc.c (EXT): Define. 421 (powerpc_opcodes): Mark extended mnemonics with EXT. 422 (prefix_opcodes, vle_opcodes): Likewise. 423 (XISEL, XISEL_MASK): Add cr field and simplify. 424 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort 425 all isel variants to where the base mnemonic belongs. Sort dstt, 426 dststt and dssall. 427 428 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 429 430 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2, 431 COP3 opcode instructions. 432 433 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 434 435 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for 436 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", 437 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", 438 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", 439 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", 440 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", 441 "cop2", and "cop3" entries. 442 443 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 444 445 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" 446 entries and associated comments. 447 448 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 449 450 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead 451 of "c0". 452 453 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 454 455 * mips-dis.c (mips_cp1_names_mips): New variable. 456 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' 457 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", 458 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", 459 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", 460 "r12000", "r14000", "r16000", "mips5", "loongson2e", and 461 "loongson2f". 462 463 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 464 465 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register 466 handling code over to... 467 <OP_REG_CONTROL>: ... this new case. 468 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. 469 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", 470 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries 471 replacing the `G' operand code with `g'. Update "cftc1" and 472 "cftc2" entries replacing the `E' operand code with `y'. 473 * micromips-opc.c (decode_micromips_operand) <'g'>: New case. 474 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" 475 entries replacing the `G' operand code with `g'. 476 477 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 478 479 * mips-dis.c (mips_cp0_names_r3900): New variable. 480 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' 481 for "r3900". 482 483 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 484 485 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", 486 and "mtthc2" to using the `G' rather than `g' operand code for 487 the coprocessor control register referred. 488 489 2021-05-29 Maciej W. Rozycki <macro (a] orcam.me.uk> 490 491 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" 492 entries with each other. 493 494 2021-05-27 Peter Bergner <bergner (a] linux.ibm.com> 495 496 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. 497 498 2021-05-25 Alan Modra <amodra (a] gmail.com> 499 500 * cris-desc.c: Regenerate. 501 * cris-desc.h: Regenerate. 502 * cris-opc.h: Regenerate. 503 * po/POTFILES.in: Regenerate. 504 505 2021-05-24 Mike Frysinger <vapier (a] gentoo.org> 506 507 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h. 508 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c. 509 (CGEN_CPUS): Add cris. 510 (CRIS_DEPS): Define. 511 (stamp-cris): New rule. 512 * cgen.sh: Handle desc action. 513 * configure.ac (bfd_cris_arch): Add cris-desc.lo. 514 * Makefile.in, configure: Regenerate. 515 516 2021-05-18 Job Noorman <mtvec (a] pm.me> 517 518 PR 27814 519 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for 520 the elf objects. 521 522 2021-05-17 Alex Coplan <alex.coplan (a] arm.com> 523 524 * arm-dis.c (mve_opcodes): Fix disassembly of 525 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. 526 (is_mve_encoding_conflict): MVE vector loads should not match 527 when P = W = 0. 528 (is_mve_unpredictable): It's not unpredictable to use the same 529 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE). 530 531 2021-05-11 Nick Clifton <nickc (a] redhat.com> 532 533 PR 27840 534 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond 535 the end of the code buffer. 536 537 2021-05-06 Stafford Horne <shorne (a] gmail.com> 538 539 PR 21464 540 * or1k-asm.c: Regenerate. 541 542 2021-05-01 Max Filippov <jcmvbkbc (a] gmail.com> 543 544 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and 545 info->insn_info_valid. 546 547 2021-04-26 Jan Beulich <jbeulich (a] suse.com> 548 549 * i386-opc.tbl (lea): Add Optimize. 550 * opcodes/i386-tbl.h: Re-generate. 551 552 2020-04-23 Max Filippov <jcmvbkbc (a] gmail.com> 553 554 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand 555 of l32r fetch and display referenced literal value. 556 557 2021-04-23 Max Filippov <jcmvbkbc (a] gmail.com> 558 559 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk 560 to 4 for literal disassembly. 561 562 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 563 564 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support 565 for TLBI instruction. 566 567 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 568 569 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for 570 DC instruction. 571 572 2021-04-19 Jan Beulich <jbeulich (a] suse.com> 573 574 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for 575 "qualifier". 576 (convert_mov_to_movewide): Add initializer for "value". 577 578 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 579 580 * aarch64-opc.c: Add RME system registers. 581 582 2021-04-16 Lifang Xia <lifang_xia (a] c-sky.com> 583 584 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress 585 "addi d,CV,z" to "c.mv d,CV". 586 587 2021-04-12 Alan Modra <amodra (a] gmail.com> 588 589 * configure.ac (--enable-checking): Add support. 590 * config.in: Regenerate. 591 * configure: Regenerate. 592 593 2021-04-09 Tejas Belagod <tejas.belagod (a] arm.com> 594 595 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify 596 LD64/ST64 instructions to lse_atomic instead of ldstexcl. 597 598 2021-04-09 Alan Modra <amodra (a] gmail.com> 599 600 * ppc-dis.c (struct dis_private): Add "special". 601 (POWERPC_DIALECT): Delete. Replace uses with.. 602 (private_data): ..this. New inline function. 603 (disassemble_init_powerpc): Init "special" names. 604 (skip_optional_operands): Add is_pcrel arg, set when detecting R 605 field of prefix instructions. 606 (bsearch_reloc, print_got_plt): New functions. 607 (print_insn_powerpc): For pcrel instructions, print target address 608 and symbol if known, and decode plt and got loads too. 609 610 2021-04-08 Alan Modra <amodra (a] gmail.com> 611 612 PR 27684 613 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir. 614 615 2021-04-08 Alan Modra <amodra (a] gmail.com> 616 617 PR 27676 618 * ppc-opc.c (DCBT_EO): Move earlier. 619 (insert_thct, extract_thct, insert_thds, extract_thds): New functions. 620 (powerpc_operands): Add THCT and THDS entries. 621 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. 622 623 2021-04-06 Alan Modra <amodra (a] gmail.com> 624 625 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL. 626 * s12z-dis.c (decode_possible_symbol): Use symbol returned from 627 symbol_at_address_func. 628 629 2021-04-05 Alan Modra <amodra (a] gmail.com> 630 631 * configure.ac: Don't check for limits.h, string.h, strings.h or 632 stdlib.h. 633 (AC_ISC_POSIX): Don't invoke. 634 * sysdep.h: Include stdlib.h and string.h unconditionally. 635 * i386-opc.h: Include limits.h unconditionally. 636 * wasm32-dis.c: Likewise. 637 * cgen-opc.c: Don't include alloca-conf.h. 638 * config.in: Regenerate. 639 * configure: Regenerate. 640 641 2021-04-01 Martin Liska <mliska (a] suse.cz> 642 643 * arm-dis.c (strneq): Remove strneq and use startswith. 644 * cr16-dis.c (print_insn_cr16): Likewise. 645 * score-dis.c (streq): Likewise. 646 (strneq): Likewise. 647 * score7-dis.c (strneq): Likewise. 648 649 2021-04-01 Alan Modra <amodra (a] gmail.com> 650 651 PR 27675 652 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2. 653 654 2021-03-31 Alan Modra <amodra (a] gmail.com> 655 656 * sysdep.h (POISON_BFD_BOOLEAN): Define. 657 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, 658 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, 659 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, 660 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, 661 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, 662 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, 663 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, 664 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, 665 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, 666 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, 667 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, 668 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, 669 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, 670 and TRUE with true throughout. 671 672 2021-03-31 Alan Modra <amodra (a] gmail.com> 673 674 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. 675 * aarch64-dis.h: Likewise. 676 * aarch64-opc.c: Likewise. 677 * avr-dis.c: Likewise. 678 * csky-dis.c: Likewise. 679 * nds32-asm.c: Likewise. 680 * nds32-dis.c: Likewise. 681 * nfp-dis.c: Likewise. 682 * riscv-dis.c: Likewise. 683 * s12z-dis.c: Likewise. 684 * wasm32-dis.c: Likewise. 685 686 2021-03-30 Jan Beulich <jbeulich (a] suse.com> 687 688 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete. 689 (i386_seg_prefixes): New. 690 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete. 691 (i386_seg_prefixes): Declare. 692 693 2021-03-30 Jan Beulich <jbeulich (a] suse.com> 694 695 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete. 696 697 2021-03-30 Jan Beulich <jbeulich (a] suse.com> 698 699 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values. 700 * i386-reg.tbl (st): Move down. 701 (st(0)): Delete. Extend comment. 702 * i386-tbl.h: Re-generate. 703 704 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 705 706 * i386-opc.tbl (movq, movabs): Move next to mov counterparts. 707 (cmpsd): Move next to cmps. 708 (movsd): Move next to movs. 709 (cmpxchg16b): Move to separate section. 710 (fisttp, fisttpll): Likewise. 711 (monitor, mwait): Likewise. 712 * i386-tbl.h: Re-generate. 713 714 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 715 716 * i386-opc.tbl (psadbw): Add <sse2:comm>. 717 (vpsadbw): Add C. 718 * i386-tbl.h: Re-generate. 719 720 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 721 722 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes, 723 pclmul, gfni): New templates. Use them wherever possible. Move 724 SSE4.1 pextrw into respective section. 725 * i386-tbl.h: Re-generate. 726 727 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 728 729 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use 730 strtoull(). Bump upper loop bound. Widen masks. Sanity check 731 "length". 732 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete. 733 Convert all of their uses to representation in opcode. 734 735 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 736 737 * i386-opc.h (struct insn_template): Shrink base_opcode to 16 738 bits. Shrink extension_opcode to 9 bits. Make it signed. Change 739 value of None. Shrink operands to 3 bits. 740 741 2021-03-29 Jan Beulich <jbeulich (a] suse.com> 742 743 * i386-gen.c (process_i386_opcode_modifier): New parameter 744 "space". 745 (output_i386_opcode): New local variable "space". Adjust 746 process_i386_opcode_modifier() invocation. 747 (process_i386_opcodes): Adjust process_i386_opcode_modifier() 748 invocation. 749 * i386-tbl.h: Re-generate. 750 751 2021-03-29 Alan Modra <amodra (a] gmail.com> 752 753 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. 754 (fp_qualifier_p, get_data_pattern): Likewise. 755 (aarch64_get_operand_modifier_from_value): Likewise. 756 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. 757 (operand_variant_qualifier_p): Likewise. 758 (qualifier_value_in_range_constraint_p): Likewise. 759 (aarch64_get_qualifier_esize): Likewise. 760 (aarch64_get_qualifier_nelem): Likewise. 761 (aarch64_get_qualifier_standard_value): Likewise. 762 (get_lower_bound, get_upper_bound): Likewise. 763 (aarch64_find_best_match, match_operands_qualifier): Likewise. 764 (aarch64_print_operand): Likewise. 765 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. 766 (operand_need_sign_extension, operand_need_shift_by_two): Likewise. 767 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. 768 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. 769 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. 770 (print_insn_tic6x): Likewise. 771 772 2021-03-29 Alan Modra <amodra (a] gmail.com> 773 774 * arc-dis.c (extract_operand_value): Correct NULL cast. 775 * frv-opc.h: Regenerate. 776 777 2021-03-26 Jan Beulich <jbeulich (a] suse.com> 778 779 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to 780 MMX form. 781 * i386-tbl.h: Re-generate. 782 783 2021-03-25 Abid Qadeer <abidh (a] codesourcery.com> 784 785 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of 786 immediate in br.n instruction. 787 788 2021-03-25 Jan Beulich <jbeulich (a] suse.com> 789 790 * i386-dis.c (XMGatherD, VexGatherD): New. 791 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*. 792 (print_insn): Check masking for S/G insns. 793 (OP_E_memory): New local variable check_gather. Extend mandatory 794 SIB check. Check register conflicts for (EVEX-encoded) gathers. 795 Extend check for disallowed 16-bit addressing. 796 (OP_VEX): New local variables modrm_reg and sib_index. Convert 797 if()s to switch(). Check register conflicts for (VEX-encoded) 798 gathers. Drop no longer reachable cases. 799 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and 800 vgatherdp*. 801 802 2021-03-25 Jan Beulich <jbeulich (a] suse.com> 803 804 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying 805 zeroing-masking without masking. 806 807 2021-03-25 Jan Beulich <jbeulich (a] suse.com> 808 809 * i386-opc.tbl (invlpgb): Fix multi-operand form. 810 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark 811 single-operand forms as deprecated. 812 * i386-tbl.h: Re-generate. 813 814 2021-03-25 Alan Modra <amodra (a] gmail.com> 815 816 PR 27647 817 * ppc-opc.c (XLOCB_MASK): Delete. 818 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using 819 XLBH_MASK. 820 (powerpc_opcodes): Accept a BH field on all extended forms of 821 bclr, bclrl, bcctr, bcctrl, bctar, bctarl. 822 823 2021-03-24 Jan Beulich <jbeulich (a] suse.com> 824 825 * i386-gen.c (output_i386_opcode): Drop processing of 826 opcode_length. Calculate length from base_opcode. Adjust prefix 827 encoding determination. 828 (process_i386_opcodes): Drop output of fake opcode_length. 829 * i386-opc.h (struct insn_template): Drop opcode_length field. 830 * i386-opc.tbl: Drop opcode length field from all templates. 831 * i386-tbl.h: Re-generate. 832 833 2021-03-24 Jan Beulich <jbeulich (a] suse.com> 834 835 * i386-gen.c (process_i386_opcode_modifier): Return void. New 836 parameter "prefix". Drop local variable "regular_encoding". 837 Record prefix setting / check for consistency. 838 (output_i386_opcode): Parse opcode_length and base_opcode 839 earlier. Derive prefix encoding. Drop no longer applicable 840 consistency checking. Adjust process_i386_opcode_modifier() 841 invocation. 842 (process_i386_opcodes): Adjust process_i386_opcode_modifier() 843 invocation. 844 * i386-tbl.h: Re-generate. 845 846 2021-03-24 Jan Beulich <jbeulich (a] suse.com> 847 848 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix 849 check. 850 * i386-opc.h (Prefix_*): Move #define-s. 851 * i386-opc.tbl: Move pseudo prefix enumerator values to 852 extension opcode field. Introduce pseudopfx template. 853 * i386-tbl.h: Re-generate. 854 855 2021-03-23 Jan Beulich <jbeulich (a] suse.com> 856 857 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend 858 comment. 859 * i386-tbl.h: Re-generate. 860 861 2021-03-23 Jan Beulich <jbeulich (a] suse.com> 862 863 * i386-opc.h (struct insn_template): Move cpu_flags field past 864 opcode_modifier one. 865 * i386-tbl.h: Re-generate. 866 867 2021-03-23 Jan Beulich <jbeulich (a] suse.com> 868 869 * i386-gen.c (opcode_modifiers): New OpcodeSpace element. 870 * i386-opc.h (OpcodeSpace): New enumerator. 871 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ... 872 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08, 873 SPACE_XOP09, SPACE_XOP0A): ... respectively. 874 (struct i386_opcode_modifier): New field opcodespace. Shrink 875 opcodeprefix field. 876 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08, 877 SpaceXOP09, SpaceXOP0A): Define. Use them to replace 878 OpcodePrefix uses. 879 * i386-tbl.h: Re-generate. 880 881 2021-03-22 Martin Liska <mliska (a] suse.cz> 882 883 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. 884 * arc-dis.c (parse_option): Likewise. 885 * arm-dis.c (parse_arm_disassembler_options): Likewise. 886 * cris-dis.c (print_with_operands): Likewise. 887 * h8300-dis.c (bfd_h8_disassemble): Likewise. 888 * i386-dis.c (print_insn): Likewise. 889 * ia64-gen.c (fetch_insn_class): Likewise. 890 (parse_resource_users): Likewise. 891 (in_iclass): Likewise. 892 (lookup_specifier): Likewise. 893 (insert_opcode_dependencies): Likewise. 894 * mips-dis.c (parse_mips_ase_option): Likewise. 895 (parse_mips_dis_option): Likewise. 896 * s390-dis.c (disassemble_init_s390): Likewise. 897 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise. 898 899 2021-03-16 Kuan-Lin Chen <kuanlinchentw (a] gmail.com> 900 901 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions. 902 903 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus (a] arm.com> 904 905 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, 906 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers. 907 908 2021-03-12 Alan Modra <amodra (a] gmail.com> 909 910 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo. 911 912 2021-03-11 Jan Beulich <jbeulich (a] suse.com> 913 914 * i386-dis.c (OP_XMM): Re-order checks. 915 916 2021-03-11 Jan Beulich <jbeulich (a] suse.com> 917 918 * i386-dis.c (putop): Drop need_vex check when also checking 919 vex.evex. 920 (intel_operand_size, OP_E_memory): Drop vex.evex check when also 921 checking vex.b. 922 923 2021-03-11 Jan Beulich <jbeulich (a] suse.com> 924 925 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast 926 checks. Move case label past broadcast check. 927 928 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 929 930 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX, 931 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode, 932 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1, 933 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3, 934 EVEX_W_0F38C7_M_0_L_2): Delete. 935 (REG_EVEX_0F38C7_M_0_L_2): New. 936 (intel_operand_size): Handle VEX and EVEX the same for 937 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop 938 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases. 939 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and 940 vex_vsib_q_w_d_mode uses. 941 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893, 942 0F38A1, and 0F38A3 entries. 943 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7 944 entry. 945 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries. 946 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and 947 0F38A3 entries. 948 949 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 950 951 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0, 952 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0, 953 MOD_VEX_0FXOP_09_12): Rename to ... 954 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0, 955 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these. 956 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT, 957 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26, 958 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, 959 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move. 960 (reg_table): Adjust comments. 961 (x86_64_table): Move X86_64_0F24, X86_64_0F26, 962 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, 963 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries. 964 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries. 965 (vex_len_table): Adjust opcode 0A_12 entry. 966 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, 967 MOD_C5_32BIT, and MOD_XOP_09_12 entries. 968 (rm_table): Move hreset entry. 969 970 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 971 972 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1, 973 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6, 974 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15, 975 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20, 976 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete. 977 (EVEX_LEN_0F3816, EVEX_W_0FD6): New. 978 (get_valid_dis386): Also handle 512-bit vector length when 979 vectoring into vex_len_table[]. 980 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5, 981 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 982 entries. 983 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6, 984 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries. 985 * i386-dis-evex-prefix.h: Adjust 0F7E entry. 986 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21 987 entries. 988 989 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 990 991 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1): 992 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively. 993 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete. 994 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01 995 entries. 996 * i386-dis-evex-len.h (evex_len_table): Likewise. 997 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries. 998 999 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1000 1001 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7, 1002 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, 1003 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, 1004 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1, 1005 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, 1006 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, 1007 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, 1008 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6 1009 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1, 1010 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0, 1011 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0, 1012 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0, 1013 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0, 1014 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0, 1015 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0, 1016 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1, 1017 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1, 1018 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1, 1019 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1, 1020 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0, 1021 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1, 1022 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0, 1023 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1, 1024 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0, 1025 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1, 1026 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819, 1027 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B, 1028 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0, 1029 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0, 1030 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B, 1031 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A, 1032 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete. 1033 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0, 1034 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A, 1035 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B, 1036 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819, 1037 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0, 1038 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0, 1039 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0, 1040 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A, 1041 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38, 1042 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B, 1043 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n, 1044 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n, 1045 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2, 1046 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2, 1047 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n, 1048 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2, 1049 EVEX_W_0F3A43_L_n): New. 1050 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A, 1051 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 1052 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries. 1053 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[] 1054 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7, 1055 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 1056 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6. 1057 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A, 1058 0F385B, 0F38C6, and 0F38C7 entries. 1059 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes 1060 0F38C6 and 0F38C7. 1061 * i386-dis-evex-w.h: No longer link to evex_len_table[] for 1062 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 1063 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to 1064 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B. 1065 1066 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1067 1068 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1, 1069 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, 1070 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, 1071 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, 1072 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, 1073 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, 1074 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, 1075 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, 1076 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, 1077 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, 1078 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, 1079 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, 1080 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, 1081 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, 1082 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, 1083 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, 1084 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, 1085 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, 1086 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, 1087 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, 1088 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0, 1089 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, 1090 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, 1091 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, 1092 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, 1093 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, 1094 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, 1095 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, 1096 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, 1097 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0, 1098 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2, 1099 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0, 1100 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2, 1101 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, 1102 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, 1103 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0, 1104 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2, 1105 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2, 1106 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2, 1107 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1, 1108 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, 1109 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0, 1110 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1, 1111 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1, 1112 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1, 1113 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, 1114 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, 1115 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, 1116 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, 1117 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, 1118 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0, 1119 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0, 1120 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, 1121 VEX_W_0F99_P_2_LEN_0): Delete. 1122 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0, 1123 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1, 1124 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0, 1125 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0, 1126 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0, 1127 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0, 1128 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0, 1129 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0, 1130 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0, 1131 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0, 1132 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0, 1133 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0, 1134 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0, 1135 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0, 1136 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0, 1137 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0, 1138 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0, 1139 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0, 1140 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42, 1141 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47, 1142 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91, 1143 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99, 1144 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1, 1145 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1, 1146 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0, 1147 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1, 1148 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New. 1149 (prefix_table): No longer link to vex_len_table[] for opcodes 1150 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 1151 0F92, 0F93, 0F98, and 0F99. 1152 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42, 1153 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1154 0F98, and 0F99. 1155 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42, 1156 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1157 0F98, and 0F99. 1158 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42, 1159 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1160 0F98, and 0F99. 1161 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42, 1162 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1163 0F98, and 0F99. 1164 1165 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1166 1167 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73): 1168 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and 1169 REG_VEX_0F73_M_0 respectively. 1170 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6, 1171 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6, 1172 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, 1173 MOD_VEX_0F73_REG_7): Delete. 1174 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New. 1175 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7, 1176 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0, 1177 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, 1178 PREFIX_VEX_0F3AF0_L_0 respectively. 1179 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3, 1180 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3, 1181 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1, 1182 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete. 1183 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6, 1184 VEX_LEN_0F38F7): New. 1185 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0. 1186 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71, 1187 0F72, and 0F73. No longer link to vex_len_table[] for opcode 1188 0F38F3. 1189 (prefix_table): No longer link to vex_len_table[] for opcodes 1190 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. 1191 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and 1192 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5, 1193 0F38F6, 0F38F7, and 0F3AF0. 1194 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to 1195 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. 1196 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and 1197 0F73. 1198 1199 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1200 1201 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to 1202 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively. 1203 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2, 1204 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3, 1205 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete. 1206 (MOD_0F71, MOD_0F72, MOD_0F73): New. 1207 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and 1208 73. 1209 (reg_table): No longer link to mod_table[] for opcodes 0F71, 1210 0F72, and 0F73. 1211 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and 1212 0F73. 1213 1214 2021-03-10 Jan Beulich <jbeulich (a] suse.com> 1215 1216 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5, 1217 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete. 1218 (reg_table): Don't link to mod_table[] where not needed. Add 1219 PREFIX_IGNORED to nop entries. 1220 (prefix_table): Replace PREFIX_OPCODE in nop entries. 1221 (mod_table): Add nop entries next to prefetch ones. Drop 1222 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and 1223 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries. 1224 (rm_table): Add PREFIX_IGNORED to nop entries. Drop 1225 PREFIX_OPCODE from endbr* entries. 1226 (get_valid_dis386): Also consider entry's name when zapping 1227 vindex. 1228 (print_insn): Handle PREFIX_IGNORED. 1229 1230 2021-03-09 Jan Beulich <jbeulich (a] suse.com> 1231 1232 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk, 1233 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk 1234 element. 1235 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone, 1236 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete. 1237 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack, 1238 PrefixLock, PrefixHLELock, PrefixHLEAny): Define. 1239 (struct i386_opcode_modifier): Delete notrackprefixok, 1240 islockable, hleprefixok, and repprefixok fields. Add prefixok 1241 field. 1242 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny, 1243 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define. 1244 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg, 1245 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b): 1246 Replace HLEPrefixOk. 1247 * opcodes/i386-tbl.h: Re-generate. 1248 1249 2021-03-09 Jan Beulich <jbeulich (a] suse.com> 1250 1251 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit. 1252 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from 1253 64-bit form. 1254 * opcodes/i386-tbl.h: Re-generate. 1255 1256 2021-03-03 Jan Beulich <jbeulich (a] suse.com> 1257 1258 * i386-gen.c (output_i386_opcode): Don't get operand count. Look 1259 for {} instead of {0}. Don't look for '0'. 1260 * i386-opc.tbl: Drop operand count field. Drop redundant operand 1261 size specifiers. 1262 1263 2021-02-19 Nelson Chu <nelson.chu (a] sifive.com> 1264 1265 PR 27158 1266 * riscv-dis.c (print_insn_args): Updated encoding macros. 1267 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. 1268 (match_c_addi16sp): Updated encoding macros. 1269 (match_c_lui): Likewise. 1270 (match_c_lui_with_hint): Likewise. 1271 (match_c_addi4spn): Likewise. 1272 (match_c_slli): Likewise. 1273 (match_slli_as_c_slli): Likewise. 1274 (match_c_slli64): Likewise. 1275 (match_srxi_as_c_srxi): Likewise. 1276 (riscv_insn_types): Added .insn css/cl/cs. 1277 1278 2021-02-18 Nelson Chu <nelson.chu (a] sifive.com> 1279 1280 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. 1281 (default_priv_spec): Updated type to riscv_spec_class. 1282 (parse_riscv_dis_option): Updated. 1283 * riscv-opc.c: Moved stuff and make the file tidy. 1284 1285 2021-02-17 Alan Modra <amodra (a] gmail.com> 1286 1287 * wasm32-dis.c: Include limits.h. 1288 (CHAR_BIT): Provide backup define. 1289 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. 1290 Correct signed overflow checking. 1291 1292 2021-02-16 Jan Beulich <jbeulich (a] suse.com> 1293 1294 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant. 1295 * i386-tbl.h: Re-generate. 1296 1297 2021-02-16 Jan Beulich <jbeulich (a] suse.com> 1298 1299 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor 1300 Oword. 1301 * i386-opc.tbl (CpuFP, Mmword, Oword): Define. 1302 1303 2021-02-15 Andreas Krebbel <krebbel (a] linux.ibm.com> 1304 1305 * s390-mkopc.c (main): Accept arch14 as cpu string. 1306 * s390-opc.txt: Add new arch14 instructions. 1307 1308 2021-02-04 Nick Alcock <nick.alcock (a] oracle.com> 1309 1310 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in 1311 favour of LIBINTL. 1312 * configure: Regenerated. 1313 1314 2021-02-08 Mike Frysinger <vapier (a] gentoo.org> 1315 1316 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs. 1317 * tic54x-opc.c (regs): Rename to ... 1318 (tic54x_regs): ... this. 1319 (mmregs): Rename to ... 1320 (tic54x_mmregs): ... this. 1321 (condition_codes): Rename to ... 1322 (tic54x_condition_codes): ... this. 1323 (cc2_codes): Rename to ... 1324 (tic54x_cc2_codes): ... this. 1325 (cc3_codes): Rename to ... 1326 (tic54x_cc3_codes): ... this. 1327 (status_bits): Rename to ... 1328 (tic54x_status_bits): ... this. 1329 (misc_symbols): Rename to ... 1330 (tic54x_misc_symbols): ... this. 1331 1332 2021-02-04 Nelson Chu <nelson.chu (a] sifive.com> 1333 1334 * riscv-opc.c (MASK_RVB_IMM): Removed. 1335 (riscv_opcodes): Removed zb* instructions. 1336 (riscv_ext_version_table): Removed versions for zb*. 1337 1338 2021-01-26 Alan Modra <amodra (a] gmail.com> 1339 1340 * i386-gen.c (parse_template): Ensure entire template_instance 1341 is initialised. 1342 1343 2021-01-15 Nelson Chu <nelson.chu (a] sifive.com> 1344 1345 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. 1346 (riscv_fpr_names_abi): Likewise. 1347 (riscv_opcodes): Likewise. 1348 (riscv_insn_types): Likewise. 1349 1350 2021-01-15 Nelson Chu <nelson.chu (a] sifive.com> 1351 1352 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message. 1353 1354 2021-01-15 Nelson Chu <nelson.chu (a] sifive.com> 1355 1356 * riscv-dis.c: Comments tidy and improvement. 1357 * riscv-opc.c: Likewise. 1358 1359 2021-01-13 Alan Modra <amodra (a] gmail.com> 1360 1361 * Makefile.in: Regenerate. 1362 1363 2021-01-12 H.J. Lu <hongjiu.lu (a] intel.com> 1364 1365 PR binutils/26792 1366 * configure.ac: Use GNU_MAKE_JOBSERVER. 1367 * aclocal.m4: Regenerated. 1368 * configure: Likewise. 1369 1370 2021-01-12 Nick Clifton <nickc (a] redhat.com> 1371 1372 * po/sr.po: Updated Serbian translation. 1373 1374 2021-01-11 H.J. Lu <hongjiu.lu (a] intel.com> 1375 1376 PR ld/27173 1377 * configure: Regenerated. 1378 1379 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov (a] arm.com> 1380 1381 * aarch64-asm-2.c: Regenerate. 1382 * aarch64-dis-2.c: Likewise. 1383 * aarch64-opc-2.c: Likewise. 1384 * aarch64-opc.c (aarch64_print_operand): 1385 Delete handling of AARCH64_OPND_CSRE_CSR. 1386 * aarch64-tbl.h (aarch64_feature_csre): Delete. 1387 (CSRE): Likewise. 1388 (_CSRE_INSN): Likewise. 1389 (aarch64_opcode_table): Delete csr. 1390 1391 2021-01-11 Nick Clifton <nickc (a] redhat.com> 1392 1393 * po/de.po: Updated German translation. 1394 * po/fr.po: Updated French translation. 1395 * po/pt_BR.po: Updated Brazilian Portuguese translation. 1396 * po/sv.po: Updated Swedish translation. 1397 * po/uk.po: Updated Ukranian translation. 1398 1399 2021-01-09 H.J. Lu <hongjiu.lu (a] intel.com> 1400 1401 * configure: Regenerated. 1402 1403 2021-01-09 Nick Clifton <nickc (a] redhat.com> 1404 1405 * configure: Regenerate. 1406 * po/opcodes.pot: Regenerate. 1407 1408 2021-01-09 Nick Clifton <nickc (a] redhat.com> 1409 1410 * 2.36 release branch crated. 1411 1412 2021-01-08 Peter Bergner <bergner (a] linux.ibm.com> 1413 1414 * ppc-opc.c (insert_dw, (extract_dw): New functions. 1415 (DW, (XRC_MASK): Define. 1416 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. 1417 1418 2021-01-09 Alan Modra <amodra (a] gmail.com> 1419 1420 * configure: Regenerate. 1421 1422 2021-01-08 Nick Clifton <nickc (a] redhat.com> 1423 1424 * po/sv.po: Updated Swedish translation. 1425 1426 2021-01-08 Nick Clifton <nickc (a] redhat.com> 1427 1428 PR 27129 1429 * aarch64-dis.c (determine_disassembling_preference): Move call to 1430 aarch64_match_operands_constraint outside of the assertion. 1431 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. 1432 Replace with a return of FALSE. 1433 1434 PR 27139 1435 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a 1436 core system register. 1437 1438 2021-01-07 Samuel Thibault <samuel.thibault (a] gnu.org> 1439 1440 * configure: Regenerate. 1441 1442 2021-01-07 Nick Clifton <nickc (a] redhat.com> 1443 1444 * po/fr.po: Updated French translation. 1445 1446 2021-01-07 Fredrik Noring <noring (a] nocrew.org> 1447 1448 * m68k-opc.c (chkl): Change minimum architecture requirement to 1449 m68020. 1450 1451 2021-01-07 Philipp Tomsich <prt (a] gnu.org> 1452 1453 * riscv-opc.c (riscv_opcodes): Add pause hint instruction. 1454 1455 2021-01-07 Claire Xenia Wolf <claire (a] symbioticeda.com> 1456 Jim Wilson <jimw (a] sifive.com> 1457 Andrew Waterman <andrew (a] sifive.com> 1458 Maxim Blinov <maxim.blinov (a] embecosm.com> 1459 Kito Cheng <kito.cheng (a] sifive.com> 1460 Nelson Chu <nelson.chu (a] sifive.com> 1461 1462 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. 1463 (MASK_RVB_IMM): Used for rev8 and orc.b encoding. 1464 1465 2021-01-01 Alan Modra <amodra (a] gmail.com> 1466 1467 Update year range in copyright notice of all files. 1468 1469 For older changes see ChangeLog-2020 1470 1472 Copyright (C) 2021-2024 Free Software Foundation, Inc. 1473 1474 Copying and distribution of this file, with or without modification, 1475 are permitted in any medium without royalty provided the copyright 1476 notice and this notice are preserved. 1477 1478 Local Variables: 1479 mode: change-log 1480 left-margin: 8 1481 fill-column: 74 1482 version-control: never 1483 End: 1484
Indexes created Mon Oct 26 00:26:21 UTC 2026