ChangeLog revision 1.7 1 2016-08-03 Tristan Gingold <gingold (a] adacore.com>
2
3 * configure: Regenerate.
4
5 2016-07-01 Tristan Gingold <gingold (a] adacore.com>
6
7 * configure: Regenerate.
8
9 2016-07-01 Tristan Gingold <gingold (a] adacore.com>
10
11 * configure: Regenerate.
12
13 2016-07-01 Jan Beulich <jbeulich (a] suse.com>
14
15 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
16 (movzb): Adjust to cover all permitted suffixes.
17 (movzw): New.
18 * i386-tbl.h: Re-generate.
19
20 2016-07-01 Jan Beulich <jbeulich (a] suse.com>
21
22 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
23 (lgdt): Remove Tbyte from non-64-bit variant.
24 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
25 xsaves64, xsavec64): Remove Disp16.
26 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
27 Remove Disp32S from non-64-bit variants. Remove Disp16 from
28 64-bit variants.
29 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
30 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
31 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
32 64-bit variants.
33 * i386-tbl.h: Re-generate.
34
35 2016-07-01 Jan Beulich <jbeulich (a] suse.com>
36
37 * i386-opc.tbl (xlat): Remove RepPrefixOk.
38 * i386-tbl.h: Re-generate.
39
40 2016-06-30 Yao Qi <yao.qi (a] linaro.org>
41
42 * arm-dis.c (print_insn): Fix typo in comment.
43
44 2016-06-28 Richard Sandiford <richard.sandiford (a] arm.com>
45
46 * aarch64-opc.c (operand_general_constraint_met_p): Check the
47 range of ldst_elemlist operands.
48 (print_register_list): Use PRIi64 to print the index.
49 (aarch64_print_operand): Likewise.
50
51 2016-06-25 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org>
52
53 * mcore-opc.h: Remove sentinal.
54 * mcore-dis.c (print_insn_mcore): Adjust.
55
56 2016-06-23 Graham Markall <graham.markall (a] embecosm.com>
57
58 * arc-opc.c: Correct description of availability of NPS400
59 features.
60
61 2016-06-22 Peter Bergner <bergner (a] vnet.ibm.com>
62
63 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
64 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
65 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
66 xor3>: New mnemonics.
67 <setb>: Change to a VX form instruction.
68 (insert_sh6): Add support for rldixor.
69 (extract_sh6): Likewise.
70
71 2016-06-22 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org>
72
73 * arc-ext.h: Wrap in extern C.
74
75 2016-06-21 Graham Markall <graham.markall (a] embecosm.com>
76
77 * arc-dis.c (arc_insn_length): Add comment on instruction length.
78 Use same method for determining instruction length on ARC700 and
79 NPS-400.
80 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
81 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
82 with the NPS400 subclass.
83 * arc-opc.c: Likewise.
84
85 2016-06-17 Jose E. Marchesi <jose.marchesi (a] oracle.com>
86
87 * sparc-opc.c (rdasr): New macro.
88 (wrasr): Likewise.
89 (rdpr): Likewise.
90 (wrpr): Likewise.
91 (rdhpr): Likewise.
92 (wrhpr): Likewise.
93 (sparc_opcodes): Use the macros above to fix and expand the
94 definition of read/write instructions from/to
95 asr/privileged/hyperprivileged instructions.
96 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
97 %hva_mask_nz. Prefer softint_set and softint_clear over
98 set_softint and clear_softint.
99 (print_insn_sparc): Support %ver in Rd.
100
101 2016-06-17 Jose E. Marchesi <jose.marchesi (a] oracle.com>
102
103 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
104 architecture according to the hardware capabilities they require.
105
106 2016-06-17 Jose E. Marchesi <jose.marchesi (a] oracle.com>
107
108 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
109 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
110 bfd_mach_sparc_v9{c,d,e,v,m}.
111 * sparc-opc.c (MASK_V9C): Define.
112 (MASK_V9D): Likewise.
113 (MASK_V9E): Likewise.
114 (MASK_V9V): Likewise.
115 (MASK_V9M): Likewise.
116 (v6): Add MASK_V9{C,D,E,V,M}.
117 (v6notlet): Likewise.
118 (v7): Likewise.
119 (v8): Likewise.
120 (v9): Likewise.
121 (v9andleon): Likewise.
122 (v9a): Likewise.
123 (v9b): Likewise.
124 (v9c): Define.
125 (v9d): Likewise.
126 (v9e): Likewise.
127 (v9v): Likewise.
128 (v9m): Likewise.
129 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
130
131 2016-06-15 Nick Clifton <nickc (a] redhat.com>
132
133 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
134 constants to match expected behaviour.
135 (nds32_parse_opcode): Likewise. Also for whitespace.
136
137 2016-06-15 Andrew Burgess <andrew.burgess (a] embecosm.com>
138
139 * arc-opc.c (extract_rhv1): Extract value from insn.
140
141 2016-06-14 Graham Markall <graham.markall (a] embecosm.com>
142
143 * arc-nps400-tbl.h: Add ldbit instruction.
144 * arc-opc.c: Add flag classes required for ldbit.
145
146 2016-06-14 Graham Markall <graham.markall (a] embecosm.com>
147
148 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
149 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
150 support the above instructions.
151
152 2016-06-14 Graham Markall <graham.markall (a] embecosm.com>
153
154 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
155 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
156 csma, cbba, zncv, and hofs.
157 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
158 support the above instructions.
159
160 2016-06-06 Graham Markall <graham.markall (a] embecosm.com>
161
162 * arc-nps400-tbl.h: Add andab and orab instructions.
163
164 2016-06-06 Graham Markall <graham.markall (a] embecosm.com>
165
166 * arc-nps400-tbl.h: Add addl-like instructions.
167
168 2016-06-06 Graham Markall <graham.markall (a] embecosm.com>
169
170 * arc-nps400-tbl.h: Add mxb and imxb instructions.
171
172 2016-06-06 Graham Markall <graham.markall (a] embecosm.com>
173
174 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
175 instructions.
176
177 2016-06-10 Andreas Krebbel <krebbel (a] linux.vnet.ibm.com>
178
179 * s390-dis.c (option_use_insn_len_bits_p): New file scope
180 variable.
181 (init_disasm): Handle new command line option "insnlength".
182 (print_s390_disassembler_options): Mention new option in help
183 output.
184 (print_insn_s390): Use the encoded insn length when dumping
185 unknown instructions.
186
187 2016-06-03 Pitchumani Sivanupandi <pitchumani.s (a] atmel.com>
188
189 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
190 to the address and set as symbol address for LDS/ STS immediate operands.
191
192 2016-06-07 Alan Modra <amodra (a] gmail.com>
193
194 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
195 cpu for "vle" to e500.
196 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
197 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
198 (PPCNONE): Delete, substitute throughout.
199 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
200 except for major opcode 4 and 31.
201 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
202
203 2016-06-07 Matthew Wahab <matthew.wahab (a] arm.com>
204
205 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
206 ARM_EXT_RAS in relevant entries.
207
208 2016-06-03 Peter Bergner <bergner (a] vnet.ibm.com>
209
210 PR binutils/20196
211 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
212 opcodes for E6500.
213
214 2016-06-03 H.J. Lu <hongjiu.lu (a] intel.com>
215
216 PR binutis/18386
217 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
218 (indir_v_mode): New.
219 Add comments for '&'.
220 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
221 (putop): Handle '&'.
222 (intel_operand_size): Handle indir_v_mode.
223 (OP_E_register): Likewise.
224 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
225 64-bit indirect call/jmp for AMD64.
226 * i386-tbl.h: Regenerated
227
228 2016-06-02 Andrew Burgess <andrew.burgess (a] embecosm.com>
229
230 * arc-dis.c (struct arc_operand_iterator): New structure.
231 (find_format_from_table): All the old content from find_format,
232 with some minor adjustments, and parameter renaming.
233 (find_format_long_instructions): New function.
234 (find_format): Rewritten.
235 (arc_insn_length): Add LSB parameter.
236 (extract_operand_value): New function.
237 (operand_iterator_next): New function.
238 (print_insn_arc): Use new functions to find opcode, and iterator
239 over operands.
240 * arc-opc.c (insert_nps_3bit_dst_short): New function.
241 (extract_nps_3bit_dst_short): New function.
242 (insert_nps_3bit_src2_short): New function.
243 (extract_nps_3bit_src2_short): New function.
244 (insert_nps_bitop1_size): New function.
245 (extract_nps_bitop1_size): New function.
246 (insert_nps_bitop2_size): New function.
247 (extract_nps_bitop2_size): New function.
248 (insert_nps_bitop_mod4_msb): New function.
249 (extract_nps_bitop_mod4_msb): New function.
250 (insert_nps_bitop_mod4_lsb): New function.
251 (extract_nps_bitop_mod4_lsb): New function.
252 (insert_nps_bitop_dst_pos3_pos4): New function.
253 (extract_nps_bitop_dst_pos3_pos4): New function.
254 (insert_nps_bitop_ins_ext): New function.
255 (extract_nps_bitop_ins_ext): New function.
256 (arc_operands): Add new operands.
257 (arc_long_opcodes): New global array.
258 (arc_num_long_opcodes): New global.
259 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
260
261 2016-06-01 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org>
262
263 * nds32-asm.h: Add extern "C".
264 * sh-opc.h: Likewise.
265
266 2016-06-01 Graham Markall <graham.markall (a] embecosm.com>
267
268 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
269 0,b,limm to the rflt instruction.
270
271 2016-05-31 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org>
272
273 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
274 constant.
275
276 2016-05-29 H.J. Lu <hongjiu.lu (a] intel.com>
277
278 PR gas/20145
279 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
280 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
281 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
282 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
283 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
284 * i386-init.h: Regenerated.
285
286 2016-05-27 H.J. Lu <hongjiu.lu (a] intel.com>
287
288 PR gas/20145
289 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
290 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
291 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
292 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
293 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
294 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
295 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
296 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
297 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
298 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
299 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
300 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
301 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
302 CpuRegMask for AVX512.
303 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
304 and CpuRegMask.
305 (set_bitfield_from_cpu_flag_init): New function.
306 (set_bitfield): Remove const on f. Call
307 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
308 * i386-opc.h (CpuRegMMX): New.
309 (CpuRegXMM): Likewise.
310 (CpuRegYMM): Likewise.
311 (CpuRegZMM): Likewise.
312 (CpuRegMask): Likewise.
313 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
314 and cpuregmask.
315 * i386-init.h: Regenerated.
316 * i386-tbl.h: Likewise.
317
318 2016-05-27 H.J. Lu <hongjiu.lu (a] intel.com>
319
320 PR gas/20154
321 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
322 (opcode_modifiers): Add AMD64 and Intel64.
323 (main): Properly verify CpuMax.
324 * i386-opc.h (CpuAMD64): Removed.
325 (CpuIntel64): Likewise.
326 (CpuMax): Set to CpuNo64.
327 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
328 (AMD64): New.
329 (Intel64): Likewise.
330 (i386_opcode_modifier): Add amd64 and intel64.
331 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
332 on call and jmp.
333 * i386-init.h: Regenerated.
334 * i386-tbl.h: Likewise.
335
336 2016-05-27 H.J. Lu <hongjiu.lu (a] intel.com>
337
338 PR gas/20154
339 * i386-gen.c (main): Fail if CpuMax is incorrect.
340 * i386-opc.h (CpuMax): Set to CpuIntel64.
341 * i386-tbl.h: Regenerated.
342
343 2016-05-27 Nick Clifton <nickc (a] redhat.com>
344
345 PR target/20150
346 * msp430-dis.c (msp430dis_read_two_bytes): New function.
347 (msp430dis_opcode_unsigned): New function.
348 (msp430dis_opcode_signed): New function.
349 (msp430_singleoperand): Use the new opcode reading functions.
350 Only disassenmble bytes if they were successfully read.
351 (msp430_doubleoperand): Likewise.
352 (msp430_branchinstr): Likewise.
353 (msp430x_callx_instr): Likewise.
354 (print_insn_msp430): Check that it is safe to read bytes before
355 attempting disassembly. Use the new opcode reading functions.
356
357 2016-05-26 Peter Bergner <bergner (a] vnet.ibm.com>
358
359 * ppc-opc.c (CY): New define. Document it.
360 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
361
362 2016-05-25 H.J. Lu <hongjiu.lu (a] intel.com>
363
364 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
365 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
366 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
367 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
368 CPU_ANY_AVX_FLAGS.
369 * i386-init.h: Regenerated.
370
371 2016-05-25 H.J. Lu <hongjiu.lu (a] intel.com>
372
373 PR gas/20141
374 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
375 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
376 * i386-init.h: Regenerated.
377
378 2016-05-25 H.J. Lu <hongjiu.lu (a] intel.com>
379
380 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
381 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
382 * i386-init.h: Regenerated.
383
384 2016-05-23 Claudiu Zissulescu <claziss (a] synopsys.com>
385
386 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
387 information.
388 (print_insn_arc): Set insn_type information.
389 * arc-opc.c (C_CC): Add F_CLASS_COND.
390 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
391 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
392 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
393 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
394 (brne, brne_s, jeq_s, jne_s): Likewise.
395
396 2016-05-23 Claudiu Zissulescu <claziss (a] synopsys.com>
397
398 * arc-tbl.h (neg): New instruction variant.
399
400 2016-05-23 Cupertino Miranda <cmiranda (a] synopsys.com>
401
402 * arc-dis.c (find_format, find_format, get_auxreg)
403 (print_insn_arc): Changed.
404 * arc-ext.h (INSERT_XOP): Likewise.
405
406 2016-05-23 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org>
407
408 * tic54x-dis.c (sprint_mmr): Adjust.
409 * tic54x-opc.c: Likewise.
410
411 2016-05-19 Alan Modra <amodra (a] gmail.com>
412
413 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
414
415 2016-05-19 Alan Modra <amodra (a] gmail.com>
416
417 * ppc-opc.c: Formatting.
418 (NSISIGNOPT): Define.
419 (powerpc_opcodes <subis>): Use NSISIGNOPT.
420
421 2016-05-18 Maciej W. Rozycki <macro (a] imgtec.com>
422
423 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
424 replacing references to `micromips_ase' throughout.
425 (_print_insn_mips): Don't use file-level microMIPS annotation to
426 determine the disassembly mode with the symbol table.
427
428 2016-05-13 Peter Bergner <bergner (a] vnet.ibm.com>
429
430 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
431
432 2016-05-11 Andrew Bennett <andrew.bennett (a] imgtec.com>
433
434 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
435 mips64r6.
436 * mips-opc.c (D34): New macro.
437 (mips_builtin_opcodes): Define bposge32c for DSPr3.
438
439 2016-05-10 Alexander Fomin <alexander.fomin (a] intel.com>
440
441 * i386-dis.c (prefix_table): Add RDPID instruction.
442 * i386-gen.c (cpu_flag_init): Add RDPID flag.
443 (cpu_flags): Add RDPID bitfield.
444 * i386-opc.h (enum): Add RDPID element.
445 (i386_cpu_flags): Add RDPID field.
446 * i386-opc.tbl: Add RDPID instruction.
447 * i386-init.h: Regenerate.
448 * i386-tbl.h: Regenerate.
449
450 2016-05-10 Thomas Preud'homme <thomas.preudhomme (a] arm.com>
451
452 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
453 branch type of a symbol.
454 (print_insn): Likewise.
455
456 2016-05-10 Thomas Preud'homme <thomas.preudhomme (a] arm.com>
457
458 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
459 Mainline Security Extensions instructions.
460 (thumb_opcodes): Add entries for narrow ARMv8-M Security
461 Extensions instructions.
462 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
463 instructions.
464 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
465 special registers.
466
467 2016-05-09 Jose E. Marchesi <jose.marchesi (a] oracle.com>
468
469 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
470
471 2016-05-03 Claudiu Zissulescu <claziss (a] synopsys.com>
472
473 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
474 (arcExtMap_genOpcode): Likewise.
475 * arc-opc.c (arg_32bit_rc): Define new variable.
476 (arg_32bit_u6): Likewise.
477 (arg_32bit_limm): Likewise.
478
479 2016-05-03 Szabolcs Nagy <szabolcs.nagy (a] arm.com>
480
481 * aarch64-gen.c (VERIFIER): Define.
482 * aarch64-opc.c (VERIFIER): Define.
483 (verify_ldpsw): Use static linkage.
484 * aarch64-opc.h (verify_ldpsw): Remove.
485 * aarch64-tbl.h: Use VERIFIER for verifiers.
486
487 2016-04-28 Nick Clifton <nickc (a] redhat.com>
488
489 PR target/19722
490 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
491 * aarch64-opc.c (verify_ldpsw): New function.
492 * aarch64-opc.h (verify_ldpsw): New prototype.
493 * aarch64-tbl.h: Add initialiser for verifier field.
494 (LDPSW): Set verifier to verify_ldpsw.
495
496 2016-04-23 H.J. Lu <hongjiu.lu (a] intel.com>
497
498 PR binutils/19983
499 PR binutils/19984
500 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
501 smaller than address size.
502
503 2016-04-20 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org>
504
505 * alpha-dis.c: Regenerate.
506 * crx-dis.c: Likewise.
507 * disassemble.c: Likewise.
508 * epiphany-opc.c: Likewise.
509 * fr30-opc.c: Likewise.
510 * frv-opc.c: Likewise.
511 * ip2k-opc.c: Likewise.
512 * iq2000-opc.c: Likewise.
513 * lm32-opc.c: Likewise.
514 * lm32-opinst.c: Likewise.
515 * m32c-opc.c: Likewise.
516 * m32r-opc.c: Likewise.
517 * m32r-opinst.c: Likewise.
518 * mep-opc.c: Likewise.
519 * mt-opc.c: Likewise.
520 * or1k-opc.c: Likewise.
521 * or1k-opinst.c: Likewise.
522 * tic80-opc.c: Likewise.
523 * xc16x-opc.c: Likewise.
524 * xstormy16-opc.c: Likewise.
525
526 2016-04-19 Andrew Burgess <andrew.burgess (a] embecosm.com>
527
528 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
529 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
530 calcsd, and calcxd instructions.
531 * arc-opc.c (insert_nps_bitop_size): Delete.
532 (extract_nps_bitop_size): Delete.
533 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
534 (extract_nps_qcmp_m3): Define.
535 (extract_nps_qcmp_m2): Define.
536 (extract_nps_qcmp_m1): Define.
537 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
538 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
539 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
540 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
541 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
542 NPS_QCMP_M3.
543
544 2016-04-19 Andrew Burgess <andrew.burgess (a] embecosm.com>
545
546 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
547
548 2016-04-15 H.J. Lu <hongjiu.lu (a] intel.com>
549
550 * Makefile.in: Regenerated with automake 1.11.6.
551 * aclocal.m4: Likewise.
552
553 2016-04-14 Andrew Burgess <andrew.burgess (a] embecosm.com>
554
555 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
556 instructions.
557 * arc-opc.c (insert_nps_cmem_uimm16): New function.
558 (extract_nps_cmem_uimm16): New function.
559 (arc_operands): Add NPS_XLDST_UIMM16 operand.
560
561 2016-04-14 Andrew Burgess <andrew.burgess (a] embecosm.com>
562
563 * arc-dis.c (arc_insn_length): New function.
564 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
565 (find_format): Change insnLen parameter to unsigned.
566
567 2016-04-13 Nick Clifton <nickc (a] redhat.com>
568
569 PR target/19937
570 * v850-opc.c (v850_opcodes): Correct masks for long versions of
571 the LD.B and LD.BU instructions.
572
573 2016-04-12 Claudiu Zissulescu <claziss (a] synopsys.com>
574
575 * arc-dis.c (find_format): Check for extension flags.
576 (print_flags): New function.
577 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
578 .extAuxRegister.
579 * arc-ext.c (arcExtMap_coreRegName): Use
580 LAST_EXTENSION_CORE_REGISTER.
581 (arcExtMap_coreReadWrite): Likewise.
582 (dump_ARC_extmap): Update printing.
583 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
584 (arc_aux_regs): Add cpu field.
585 * arc-regs.h: Add cpu field, lower case name aux registers.
586
587 2016-04-12 Claudiu Zissulescu <claziss (a] synopsys.com>
588
589 * arc-tbl.h: Add rtsc, sleep with no arguments.
590
591 2016-04-12 Claudiu Zissulescu <claziss (a] synopsys.com>
592
593 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
594 Initialize.
595 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
596 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
597 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
598 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
599 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
600 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
601 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
602 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
603 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
604 (arc_opcode arc_opcodes): Null terminate the array.
605 (arc_num_opcodes): Remove.
606 * arc-ext.h (INSERT_XOP): Define.
607 (extInstruction_t): Likewise.
608 (arcExtMap_instName): Delete.
609 (arcExtMap_insn): New function.
610 (arcExtMap_genOpcode): Likewise.
611 * arc-ext.c (ExtInstruction): Remove.
612 (create_map): Zero initialize instruction fields.
613 (arcExtMap_instName): Remove.
614 (arcExtMap_insn): New function.
615 (dump_ARC_extmap): More info while debuging.
616 (arcExtMap_genOpcode): New function.
617 * arc-dis.c (find_format): New function.
618 (print_insn_arc): Use find_format.
619 (arc_get_disassembler): Enable dump_ARC_extmap only when
620 debugging.
621
622 2016-04-11 Maciej W. Rozycki <macro (a] imgtec.com>
623
624 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
625 instruction bits out.
626
627 2016-04-07 Andrew Burgess <andrew.burgess (a] embecosm.com>
628
629 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
630 * arc-opc.c (arc_flag_operands): Add new flags.
631 (arc_flag_classes): Add new classes.
632
633 2016-04-07 Andrew Burgess <andrew.burgess (a] embecosm.com>
634
635 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
636
637 2016-04-05 Andrew Burgess <andrew.burgess (a] embecosm.com>
638
639 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
640 encode1, rflt, crc16, and crc32 instructions.
641 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
642 (arc_flag_classes): Add C_NPS_R.
643 (insert_nps_bitop_size_2b): New function.
644 (extract_nps_bitop_size_2b): Likewise.
645 (insert_nps_bitop_uimm8): Likewise.
646 (extract_nps_bitop_uimm8): Likewise.
647 (arc_operands): Add new operand entries.
648
649 2016-04-05 Claudiu Zissulescu <claziss (a] synopsys.com>
650
651 * arc-regs.h: Add a new subclass field. Add double assist
652 accumulator register values.
653 * arc-tbl.h: Use DPA subclass to mark the double assist
654 instructions. Use DPX/SPX subclas to mark the FPX instructions.
655 * arc-opc.c (RSP): Define instead of SP.
656 (arc_aux_regs): Add the subclass field.
657
658 2016-04-05 Jiong Wang <jiong.wang (a] arm.com>
659
660 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
661
662 2016-03-31 Andrew Burgess <andrew.burgess (a] embecosm.com>
663
664 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
665 NPS_R_SRC1.
666
667 2016-03-30 Andrew Burgess <andrew.burgess (a] embecosm.com>
668
669 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
670 issues. No functional changes.
671
672 2016-03-30 Claudiu Zissulescu <claziss (a] synopsys.com>
673
674 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
675 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
676 (RTT): Remove duplicate.
677 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
678 (PCT_CONFIG*): Remove.
679 (D1L, D1H, D2H, D2L): Define.
680
681 2016-03-29 Claudiu Zissulescu <claziss (a] synopsys.com>
682
683 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
684
685 2016-03-29 Claudiu Zissulescu <claziss (a] synopsys.com>
686
687 * arc-tbl.h (invld07): Remove.
688 * arc-ext-tbl.h: New file.
689 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
690 * arc-opc.c (arc_opcodes): Add ext-tbl include.
691
692 2016-03-24 Jan Kratochvil <jan.kratochvil (a] redhat.com>
693
694 Fix -Wstack-usage warnings.
695 * aarch64-dis.c (print_operands): Substitute size.
696 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
697
698 2016-03-22 Jose E. Marchesi <jose.marchesi (a] oracle.com>
699
700 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
701 to get a proper diagnostic when an invalid ASR register is used.
702
703 2016-03-22 Nick Clifton <nickc (a] redhat.com>
704
705 * configure: Regenerate.
706
707 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com>
708
709 * arc-nps400-tbl.h: New file.
710 * arc-opc.c: Add top level comment.
711 (insert_nps_3bit_dst): New function.
712 (extract_nps_3bit_dst): New function.
713 (insert_nps_3bit_src2): New function.
714 (extract_nps_3bit_src2): New function.
715 (insert_nps_bitop_size): New function.
716 (extract_nps_bitop_size): New function.
717 (arc_flag_operands): Add nps400 entries.
718 (arc_flag_classes): Add nps400 entries.
719 (arc_operands): Add nps400 entries.
720 (arc_opcodes): Add nps400 include.
721
722 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com>
723
724 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
725 the new class enum values.
726
727 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com>
728
729 * arc-dis.c (print_insn_arc): Handle nps400.
730
731 2016-03-21 Andrew Burgess <andrew.burgess (a] embecosm.com>
732
733 * arc-opc.c (BASE): Delete.
734
735 2016-03-18 Nick Clifton <nickc (a] redhat.com>
736
737 PR target/19721
738 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
739 of MOV insn that aliases an ORR insn.
740
741 2016-03-16 Jiong Wang <jiong.wang (a] arm.com>
742
743 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
744
745 2016-03-07 Trevor Saunders <tbsaunde+binutils (a] tbsaunde.org>
746
747 * mcore-opc.h: Add const qualifiers.
748 * microblaze-opc.h (struct op_code_struct): Likewise.
749 * sh-opc.h: Likewise.
750 * tic4x-dis.c (tic4x_print_indirect): Likewise.
751 (tic4x_print_op): Likewise.
752
753 2016-03-02 Alan Modra <amodra (a] gmail.com>
754
755 * or1k-desc.h: Regenerate.
756 * fr30-ibld.c: Regenerate.
757 * rl78-decode.c: Regenerate.
758
759 2016-03-01 Nick Clifton <nickc (a] redhat.com>
760
761 PR target/19747
762 * rl78-dis.c (print_insn_rl78_common): Fix typo.
763
764 2016-02-24 Renlin Li <renlin.li (a] arm.com>
765
766 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
767 (print_insn_coprocessor): Support fp16 instructions.
768
769 2016-02-24 Renlin Li <renlin.li (a] arm.com>
770
771 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
772 vminnm, vrint(mpna).
773
774 2016-02-24 Renlin Li <renlin.li (a] arm.com>
775
776 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
777 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
778
779 2016-02-15 H.J. Lu <hongjiu.lu (a] intel.com>
780
781 * i386-dis.c (print_insn): Parenthesize expression to prevent
782 truncated addresses.
783 (OP_J): Likewise.
784
785 2016-02-10 Claudiu Zissulescu <claziss (a] synopsys.com>
786 Janek van Oirschot <jvanoirs (a] synopsys.com>
787
788 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
789 variable.
790
791 2016-02-04 Nick Clifton <nickc (a] redhat.com>
792
793 PR target/19561
794 * msp430-dis.c (print_insn_msp430): Add a special case for
795 decoding an RRC instruction with the ZC bit set in the extension
796 word.
797
798 2016-02-02 Andrew Burgess <andrew.burgess (a] embecosm.com>
799
800 * cgen-ibld.in (insert_normal): Rework calculation of shift.
801 * epiphany-ibld.c: Regenerate.
802 * fr30-ibld.c: Regenerate.
803 * frv-ibld.c: Regenerate.
804 * ip2k-ibld.c: Regenerate.
805 * iq2000-ibld.c: Regenerate.
806 * lm32-ibld.c: Regenerate.
807 * m32c-ibld.c: Regenerate.
808 * m32r-ibld.c: Regenerate.
809 * mep-ibld.c: Regenerate.
810 * mt-ibld.c: Regenerate.
811 * or1k-ibld.c: Regenerate.
812 * xc16x-ibld.c: Regenerate.
813 * xstormy16-ibld.c: Regenerate.
814
815 2016-02-02 Andrew Burgess <andrew.burgess (a] embecosm.com>
816
817 * epiphany-dis.c: Regenerated from latest cpu files.
818
819 2016-02-01 Michael McConville <mmcco (a] mykolab.com>
820
821 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
822 test bit.
823
824 2016-01-25 Renlin Li <renlin.li (a] arm.com>
825
826 * arm-dis.c (mapping_symbol_for_insn): New function.
827 (find_ifthen_state): Call mapping_symbol_for_insn().
828
829 2016-01-20 Matthew Wahab <matthew.wahab (a] arm.com>
830
831 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
832 of MSR UAO immediate operand.
833
834 2016-01-18 Maciej W. Rozycki <macro (a] imgtec.com>
835
836 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
837 instruction support.
838
839 2016-01-17 Alan Modra <amodra (a] gmail.com>
840
841 * configure: Regenerate.
842
843 2016-01-14 Nick Clifton <nickc (a] redhat.com>
844
845 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
846 instructions that can support stack pointer operations.
847 * rl78-decode.c: Regenerate.
848 * rl78-dis.c: Fix display of stack pointer in MOVW based
849 instructions.
850
851 2016-01-14 Matthew Wahab <matthew.wahab (a] arm.com>
852
853 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
854 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
855 erxtatus_el1 and erxaddr_el1.
856
857 2016-01-12 Matthew Wahab <matthew.wahab (a] arm.com>
858
859 * arm-dis.c (arm_opcodes): Add "esb".
860 (thumb_opcodes): Likewise.
861
862 2016-01-11 Peter Bergner <bergner (a] vnet.ibm.com>
863
864 * ppc-opc.c <xscmpnedp>: Delete.
865 <xvcmpnedp>: Likewise.
866 <xvcmpnedp.>: Likewise.
867 <xvcmpnesp>: Likewise.
868 <xvcmpnesp.>: Likewise.
869
870 2016-01-08 Andreas Schwab <schwab (a] linux-m68k.org>
871
872 PR gas/13050
873 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
874 addition to ISA_A.
875
876 2016-01-01 Alan Modra <amodra (a] gmail.com>
877
878 Update year range in copyright notice of all files.
879
880 For older changes see ChangeLog-2015
881
883 Copyright (C) 2016 Free Software Foundation, Inc.
884
885 Copying and distribution of this file, with or without modification,
886 are permitted in any medium without royalty provided the copyright
887 notice and this notice are preserved.
888
889 Local Variables:
890 mode: change-log
891 left-margin: 8
892 fill-column: 74
893 version-control: never
894 End:
895