ChangeLog revision 1.9
1 2018-07-18 Nick Clifton <nickc (a] redhat.com> 2 3 2.31.1 Release point. 4 * configure: Regenerate. 5 * po/opcodes.pot: Regenerate. 6 7 2018-07-14 Nick Clifton <nickc (a] redhat.com> 8 9 * configure: Regenerate. 10 * po/opcodes.pot: Regenerate. 11 12 2018-07-14 Nick Clifton <nickc (a] redhat.com> 13 14 2.31 Release point. 15 * configure: Regenerate. 16 17 2018-07-12 Sudakshina Das <sudi.das (a] arm.com> 18 19 * aarch64-tbl.h (aarch64_opcode_table): Add entry for 20 ssbb and pssbb and update dsb flags to F_HAS_ALIAS. 21 * aarch64-asm-2.c: Regenerate. 22 * aarch64-dis-2.c: Regenerate. 23 * aarch64-opc-2.c: Regenerate. 24 25 2018-07-11 Sudakshina Das <sudi.das (a] arm.com> 26 27 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move 28 csdb together with them. 29 (thumb32_opcodes): Likewise. 30 31 2018-07-12 Tamar Christina <tamar.christina (a] arm.com> 32 33 PR binutils/23192 34 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2, 35 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal, 36 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull, 37 sqdmulh, sqrdmulh): Use Em16. 38 39 2018-07-06 Tamar Christina <tamar.christina (a] arm.com> 40 41 PR binutils/23242 42 * aarch64-tbl.h (ldarh): Fix disassembly mask. 43 44 2018-07-06 Tamar Christina <tamar.christina (a] arm.com> 45 46 PR binutils/23369 47 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, 48 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. 49 50 2018-06-29 Tamar Christina <tamar.christina (a] arm.com> 51 52 PR binutils/23192 53 * aarch64-asm-2.c: Regenerate. 54 * aarch64-dis-2.c: Likewise. 55 * aarch64-opc-2.c: Likewise. 56 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint. 57 * aarch64-opc.c (operand_general_constraint_met_p, 58 aarch64_print_operand): Likewise. 59 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal, 60 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl, 61 fmlal2, fmlsl2. 62 (AARCH64_OPERANDS): Add Em2. 63 64 2018-06-26 Nick Clifton <nickc (a] redhat.com> 65 66 * po/uk.po: Updated Ukranian translation. 67 * po/de.po: Updated German translation. 68 * po/pt_BR.po: Updated Brazilian Portuguese translation. 69 70 2018-06-26 Nick Clifton <nickc (a] redhat.com> 71 72 * nfp-dis.c: Fix spelling mistake. 73 74 2018-06-24 Nick Clifton <nickc (a] redhat.com> 75 76 * configure: Regenerate. 77 * po/opcodes.pot: Regenerate. 78 79 2018-06-24 Nick Clifton <nickc (a] redhat.com> 80 81 2.31 branch created. 82 83 2018-06-19 Tamar Christina <tamar.christina (a] arm.com> 84 85 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs 86 * aarch64-asm-2.c: Regenerate. 87 * aarch64-dis-2.c: Likewise. 88 89 2018-06-21 Maciej W. Rozycki <macro (a] mips.com> 90 91 * mips-dis.c (print_mips_disassembler_options): Fix a typo in 92 `-M ginv' option description. 93 94 2018-06-20 Sebastian Huber <sebastian.huber (a] embedded-brains.de> 95 96 PR gas/23305 97 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for 98 la and lla. 99 100 2018-06-19 Simon Marchi <simon.marchi (a] ericsson.com> 101 102 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11. 103 * configure.ac: Remove AC_PREREQ. 104 * Makefile.in: Re-generate. 105 * aclocal.m4: Re-generate. 106 * configure: Re-generate. 107 108 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker (a] mips.com> 109 110 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and 111 mips64r6 descriptors. 112 (parse_mips_ase_option): Handle -Mginv option. 113 (print_mips_disassembler_options): Document -Mginv. 114 * mips-opc.c (decode_mips_operand) <+\>: New operand format. 115 (GINV): New macro. 116 (mips_opcodes): Define ginvi and ginvt. 117 118 2018-06-13 Scott Egerton <scott.egerton (a] imgtec.com> 119 Faraz Shahbazker <Faraz.Shahbazker (a] mips.com> 120 121 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs. 122 * mips-opc.c (CRC, CRC64): New macros. 123 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w, 124 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and 125 crc32cd for CRC64. 126 127 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu (a] oracle.com> 128 129 PR 20319 130 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV. 131 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV. 132 133 2018-06-06 Alan Modra <amodra (a] gmail.com> 134 135 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after 136 setjmp. Move init for some other vars later too. 137 138 2018-06-04 Max Filippov <jcmvbkbc (a] gmail.com> 139 140 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes. 141 (dis_private): Add new fields for property section tracking. 142 (xtensa_coalesce_insn_tables, xtensa_find_table_entry) 143 (xtensa_instruction_fits): New functions. 144 (fetch_data): Bump minimal fetch size to 4. 145 (print_insn_xtensa): Make struct dis_private static. 146 Load and prepare property table on section change. 147 Don't disassemble literals. Don't disassemble instructions that 148 cross property table boundaries. 149 150 2018-06-01 H.J. Lu <hongjiu.lu (a] intel.com> 151 152 * configure: Regenerated. 153 154 2018-06-01 Jan Beulich <jbeulich (a] suse.com> 155 156 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms. 157 * i386-tbl.h: Re-generate. 158 159 2018-06-01 Jan Beulich <jbeulich (a] suse.com> 160 161 * i386-opc.tbl (sldt, str): Add NoRex64. 162 * i386-tbl.h: Re-generate. 163 164 2018-06-01 Jan Beulich <jbeulich (a] suse.com> 165 166 * i386-opc.tbl (invpcid): Add Oword. 167 * i386-tbl.h: Re-generate. 168 169 2018-06-01 Alan Modra <amodra (a] gmail.com> 170 171 * sysdep.h (_bfd_error_handler): Don't declare. 172 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here. 173 * rl78-decode.opc: Likewise. 174 * msp430-decode.c: Regenerate. 175 * rl78-decode.c: Regenerate. 176 177 2018-05-30 Amit Pawar <Amit.Pawar (a] amd.com> 178 179 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS. 180 * i386-init.h : Regenerated. 181 182 2018-05-25 Alan Modra <amodra (a] gmail.com> 183 184 * Makefile.in: Regenerate. 185 * po/POTFILES.in: Regenerate. 186 187 2018-05-21 Peter Bergner <bergner (a] vnet.ibm.com.com> 188 189 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba, 190 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions. 191 (insert_bab, extract_bab, insert_btab, extract_btab, 192 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions. 193 (BAT, BBA VBA RBS XB6S): Delete macros. 194 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros. 195 (BB, BD, RBX, XC6): Update for new macros. 196 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset, 197 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp, 198 e_crnot, e_crclr, e_crset, e_crmove>: Likewise. 199 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands. 200 201 2018-05-18 John Darrington <john (a] darrington.wattle.id.au> 202 203 * Makefile.am: Add support for s12z architecture. 204 * configure.ac: Likewise. 205 * disassemble.c: Likewise. 206 * disassemble.h: Likewise. 207 * Makefile.in: Regenerate. 208 * configure: Regenerate. 209 * s12z-dis.c: New file. 210 * s12z.h: New file. 211 212 2018-05-18 Alan Modra <amodra (a] gmail.com> 213 214 * nfp-dis.c: Don't #include libbfd.h. 215 (init_nfp3200_priv): Use bfd_get_section_contents. 216 (nit_nfp6000_mecsr_sec): Likewise. 217 218 2018-05-17 Nick Clifton <nickc (a] redhat.com> 219 220 * po/zh_CN.po: Updated simplified Chinese translation. 221 222 2018-05-16 Tamar Christina <tamar.christina (a] arm.com> 223 224 PR binutils/23109 225 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot. 226 * aarch64-dis-2.c: Regenerate. 227 228 2018-05-15 Tamar Christina <tamar.christina (a] arm.com> 229 230 PR binutils/21446 231 * aarch64-asm.c (opintl.h): Include. 232 (aarch64_ins_sysreg): Enforce read/write constraints. 233 * aarch64-dis.c (aarch64_ext_sysreg): Likewise. 234 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here. 235 (F_REG_READ, F_REG_WRITE): New. 236 * aarch64-opc.c (aarch64_print_operand): Generate notes for 237 AARCH64_OPND_SYSREG. 238 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h. 239 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0, 240 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1, 241 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1, 242 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1, 243 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1, 244 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1, 245 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1, 246 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1, 247 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1, 248 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2, 249 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0, 250 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1, 251 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1, 252 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0. 253 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to 254 msr (F_SYS_WRITE), mrs (F_SYS_READ). 255 256 2018-05-15 Tamar Christina <tamar.christina (a] arm.com> 257 258 PR binutils/21446 259 * aarch64-dis.c (no_notes: New. 260 (parse_aarch64_dis_option): Support notes. 261 (aarch64_decode_insn, print_operands): Likewise. 262 (print_aarch64_disassembler_options): Document notes. 263 * aarch64-opc.c (aarch64_print_operand): Support notes. 264 265 2018-05-15 Tamar Christina <tamar.christina (a] arm.com> 266 267 PR binutils/21446 268 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean 269 and take error struct. 270 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane, 271 aarch64_ins_reglist, aarch64_ins_ldst_reglist, 272 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist, 273 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half, 274 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm, 275 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits, 276 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm, 277 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple, 278 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm, 279 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12, 280 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg, 281 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier, 282 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended, 283 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl, 284 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl, 285 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6, 286 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw, 287 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, 288 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw, 289 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm, 290 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov, 291 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist, 292 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm, 293 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two, 294 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise. 295 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise. 296 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane, 297 aarch64_ext_reglist, aarch64_ext_ldst_reglist, 298 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist, 299 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half, 300 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm, 301 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits, 302 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm, 303 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple, 304 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm, 305 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12, 306 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg, 307 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier, 308 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended, 309 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl, 310 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl, 311 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6, 312 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw, 313 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz, 314 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw, 315 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm, 316 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov, 317 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist, 318 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm, 319 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two, 320 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise. 321 (determine_disassembling_preference, aarch64_decode_insn, 322 print_insn_aarch64_word, print_insn_data): Take errors struct. 323 (print_insn_aarch64): Use errors. 324 * aarch64-asm-2.c: Regenerate. 325 * aarch64-dis-2.c: Regenerate. 326 * aarch64-gen.c (print_operand_inserter): Use errors and change type to 327 boolean in aarch64_insert_operan. 328 (print_operand_extractor): Likewise. 329 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct. 330 331 2018-05-15 Francois H. Theron <francois.theron (a] netronome.com> 332 333 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma. 334 335 2018-05-09 H.J. Lu <hongjiu.lu (a] intel.com> 336 337 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}. 338 339 2018-05-09 Sebastian Rasmussen <sebras (a] gmail.com> 340 341 * cr16-opc.c (cr16_instruction): Comment typo fix. 342 * hppa-dis.c (print_insn_hppa): Likewise. 343 344 2018-05-08 Jim Wilson <jimw (a] sifive.com> 345 346 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New. 347 (match_c_slli64, match_srxi_as_c_srxi): New. 348 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli. 349 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi. 350 <c.slli, c.srli, c.srai>: Use match_s_slli. 351 <c.slli64, c.srli64, c.srai64>: New. 352 353 2018-05-08 Alan Modra <amodra (a] gmail.com> 354 355 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP. 356 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to 357 partition opcode space for index lookup. 358 359 2018-05-07 Peter Bergner <bergner (a] vnet.ibm.com.com> 360 361 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this... 362 <insn_length>: ...with this. Update usage. 363 Remove duplicate call to *info->memory_error_func. 364 365 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 366 H.J. Lu <hongjiu.lu (a] intel.com> 367 368 * i386-dis.c (Gva): New. 369 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9, 370 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0. 371 (prefix_table): New instructions (see prefix above). 372 (mod_table): New instructions (see prefix above). 373 (OP_G): Handle va_mode. 374 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS, 375 CPU_MOVDIR64B_FLAGS. 376 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B. 377 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B. 378 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b. 379 * i386-opc.tbl: Add movidir{i,64b}. 380 * i386-init.h: Regenerated. 381 * i386-tbl.h: Likewise. 382 383 2018-05-07 H.J. Lu <hongjiu.lu (a] intel.com> 384 385 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with 386 AddrPrefixOpReg. 387 * i386-opc.h (AddrPrefixOp0): Renamed to ... 388 (AddrPrefixOpReg): This. 389 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg. 390 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg. 391 392 2018-05-07 Peter Bergner <bergner (a] vnet.ibm.com.com> 393 394 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned. 395 (vle_num_opcodes): Likewise. 396 (spe2_num_opcodes): Likewise. 397 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite 398 initialization loop. 399 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise. 400 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize 401 only once. 402 403 2018-05-01 Tamar Christina <tamar.christina (a] arm.com> 404 405 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code. 406 407 2018-04-30 Francois H. Theron <francois.theron (a] netronome.com> 408 409 Makefile.am: Added nfp-dis.c. 410 configure.ac: Added bfd_nfp_arch. 411 disassemble.h: Added print_insn_nfp prototype. 412 disassemble.c: Added ARCH_nfp and call to print_insn_nfp 413 nfp-dis.c: New, for NFP support. 414 po/POTFILES.in: Added nfp-dis.c to the list. 415 Makefile.in: Regenerate. 416 configure: Regenerate. 417 418 2018-04-26 Jan Beulich <jbeulich (a] suse.com> 419 420 * i386-opc.tbl: Fold various non-memory operand AVX512VL 421 templates into their base ones. 422 * i386-tlb.h: Re-generate. 423 424 2018-04-26 Jan Beulich <jbeulich (a] suse.com> 425 426 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for 427 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use 428 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to 429 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS. 430 * i386-init.h: Re-generate. 431 432 2018-04-26 Jan Beulich <jbeulich (a] suse.com> 433 434 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX, 435 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use 436 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment. 437 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus 438 comment. 439 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM, 440 and CpuRegMask. 441 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM, 442 CpuRegMask: Delete. 443 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm, 444 cpuregzmm, and cpuregmask. 445 * i386-init.h: Re-generate. 446 * i386-tbl.h: Re-generate. 447 448 2018-04-26 Jan Beulich <jbeulich (a] suse.com> 449 450 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only. 451 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only. 452 * i386-init.h: Re-generate. 453 454 2018-04-26 Jan Beulich <jbeulich (a] suse.com> 455 456 * i386-gen.c (VexImmExt): Delete. 457 * i386-opc.h (VexImmExt, veximmext): Delete. 458 * i386-opc.tbl: Drop all VexImmExt uses. 459 * i386-tlb.h: Re-generate. 460 461 2018-04-25 Jan Beulich <jbeulich (a] suse.com> 462 463 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL 464 register-only forms. 465 * i386-tlb.h: Re-generate. 466 467 2018-04-25 Tamar Christina <tamar.christina (a] arm.com> 468 469 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks. 470 471 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 472 473 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0, 474 PREFIX_0F1C. 475 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS, 476 (cpu_flags): Add CpuCLDEMOTE. 477 * i386-init.h: Regenerate. 478 * i386-opc.h (enum): Add CpuCLDEMOTE, 479 (i386_cpu_flags): Add cpucldemote. 480 * i386-opc.tbl: Add cldemote. 481 * i386-tbl.h: Regenerate. 482 483 2018-04-16 Alan Modra <amodra (a] gmail.com> 484 485 * Makefile.am: Remove sh5 and sh64 support. 486 * configure.ac: Likewise. 487 * disassemble.c: Likewise. 488 * disassemble.h: Likewise. 489 * sh-dis.c: Likewise. 490 * sh64-dis.c: Delete. 491 * sh64-opc.c: Delete. 492 * sh64-opc.h: Delete. 493 * Makefile.in: Regenerate. 494 * configure: Regenerate. 495 * po/POTFILES.in: Regenerate. 496 497 2018-04-16 Alan Modra <amodra (a] gmail.com> 498 499 * Makefile.am: Remove w65 support. 500 * configure.ac: Likewise. 501 * disassemble.c: Likewise. 502 * disassemble.h: Likewise. 503 * w65-dis.c: Delete. 504 * w65-opc.h: Delete. 505 * Makefile.in: Regenerate. 506 * configure: Regenerate. 507 * po/POTFILES.in: Regenerate. 508 509 2018-04-16 Alan Modra <amodra (a] gmail.com> 510 511 * configure.ac: Remove we32k support. 512 * configure: Regenerate. 513 514 2018-04-16 Alan Modra <amodra (a] gmail.com> 515 516 * Makefile.am: Remove m88k support. 517 * configure.ac: Likewise. 518 * disassemble.c: Likewise. 519 * disassemble.h: Likewise. 520 * m88k-dis.c: Delete. 521 * Makefile.in: Regenerate. 522 * configure: Regenerate. 523 * po/POTFILES.in: Regenerate. 524 525 2018-04-16 Alan Modra <amodra (a] gmail.com> 526 527 * Makefile.am: Remove i370 support. 528 * configure.ac: Likewise. 529 * disassemble.c: Likewise. 530 * disassemble.h: Likewise. 531 * i370-dis.c: Delete. 532 * i370-opc.c: Delete. 533 * Makefile.in: Regenerate. 534 * configure: Regenerate. 535 * po/POTFILES.in: Regenerate. 536 537 2018-04-16 Alan Modra <amodra (a] gmail.com> 538 539 * Makefile.am: Remove h8500 support. 540 * configure.ac: Likewise. 541 * disassemble.c: Likewise. 542 * disassemble.h: Likewise. 543 * h8500-dis.c: Delete. 544 * h8500-opc.h: Delete. 545 * Makefile.in: Regenerate. 546 * configure: Regenerate. 547 * po/POTFILES.in: Regenerate. 548 549 2018-04-16 Alan Modra <amodra (a] gmail.com> 550 551 * configure.ac: Remove tahoe support. 552 * configure: Regenerate. 553 554 2018-04-15 H.J. Lu <hongjiu.lu (a] intel.com> 555 556 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and 557 umwait. 558 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in 559 64-bit mode. 560 * i386-tbl.h: Regenerated. 561 562 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 563 564 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6, 565 PREFIX_MOD_1_0FAE_REG_6. 566 (va_mode): New. 567 (OP_E_register): Use va_mode. 568 * i386-dis-evex.h (prefix_table): 569 New instructions (see prefixes above). 570 * i386-gen.c (cpu_flag_init): Add WAITPKG. 571 (cpu_flags): Likewise. 572 * i386-opc.h (enum): Likewise. 573 (i386_cpu_flags): Likewise. 574 * i386-opc.tbl: Add umonitor, umwait, tpause. 575 * i386-init.h: Regenerate. 576 * i386-tbl.h: Likewise. 577 578 2018-04-11 Alan Modra <amodra (a] gmail.com> 579 580 * opcodes/i860-dis.c: Delete. 581 * opcodes/i960-dis.c: Delete. 582 * Makefile.am: Remove i860 and i960 support. 583 * configure.ac: Likewise. 584 * disassemble.c: Likewise. 585 * disassemble.h: Likewise. 586 * Makefile.in: Regenerate. 587 * configure: Regenerate. 588 * po/POTFILES.in: Regenerate. 589 590 2018-04-04 H.J. Lu <hongjiu.lu (a] intel.com> 591 592 PR binutils/23025 593 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w 594 to 0. 595 (print_insn): Clear vex instead of vex.evex. 596 597 2018-04-04 Nick Clifton <nickc (a] redhat.com> 598 599 * po/es.po: Updated Spanish translation. 600 601 2018-03-28 Jan Beulich <jbeulich (a] suse.com> 602 603 * i386-gen.c (opcode_modifiers): Delete VecESize. 604 * i386-opc.h (VecESize): Delete. 605 (struct i386_opcode_modifier): Delete vecesize. 606 * i386-opc.tbl: Drop VecESize. 607 * i386-tlb.h: Re-generate. 608 609 2018-03-28 Jan Beulich <jbeulich (a] suse.com> 610 611 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8, 612 BROADCAST_1TO4, BROADCAST_1TO2): Delete. 613 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit. 614 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast. 615 * i386-tlb.h: Re-generate. 616 617 2018-03-28 Jan Beulich <jbeulich (a] suse.com> 618 619 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi): 620 Fold AVX512 forms 621 * i386-tlb.h: Re-generate. 622 623 2018-03-28 Jan Beulich <jbeulich (a] suse.com> 624 625 * i386-dis.c (prefix_table): Drop Y for cvt*2si. 626 (vex_len_table): Drop Y for vcvt*2si. 627 (putop): Replace plain 'Y' handling by abort(). 628 629 2018-03-28 Nick Clifton <nickc (a] redhat.com> 630 631 PR 22988 632 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx 633 instructions with only a base address register. 634 * aarch64-opc.c (operand_general_constraint_met_p): Add code to 635 handle AARHC64_OPND_SVE_ADDR_R. 636 (aarch64_print_operand): Likewise. 637 * aarch64-asm-2.c: Regenerate. 638 * aarch64_dis-2.c: Regenerate. 639 * aarch64-opc-2.c: Regenerate. 640 641 2018-03-22 Jan Beulich <jbeulich (a] suse.com> 642 643 * i386-opc.tbl: Drop VecESize from register only insn forms and 644 memory forms not allowing broadcast. 645 * i386-tlb.h: Re-generate. 646 647 2018-03-22 Jan Beulich <jbeulich (a] suse.com> 648 649 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*, 650 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*, 651 sha256*): Drop Disp<N>. 652 653 2018-03-22 Jan Beulich <jbeulich (a] suse.com> 654 655 * i386-dis.c (EbndS, bnd_swap_mode): New. 656 (prefix_table): Use EbndS. 657 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode. 658 * i386-opc.tbl (bndmov): Move misplaced Load. 659 * i386-tlb.h: Re-generate. 660 661 2018-03-22 Jan Beulich <jbeulich (a] suse.com> 662 663 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate 664 templates allowing memory operands and folded ones for register 665 only flavors. 666 * i386-tlb.h: Re-generate. 667 668 2018-03-22 Jan Beulich <jbeulich (a] suse.com> 669 670 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and 671 256-bit templates. Drop redundant leftover Disp<N>. 672 * i386-tlb.h: Re-generate. 673 674 2018-03-14 Kito Cheng <kito.cheng (a] gmail.com> 675 676 * riscv-opc.c (riscv_insn_types): New. 677 678 2018-03-13 Nick Clifton <nickc (a] redhat.com> 679 680 * po/pt_BR.po: Updated Brazilian Portuguese translation. 681 682 2018-03-08 H.J. Lu <hongjiu.lu (a] intel.com> 683 684 * i386-opc.tbl: Add Optimize to clr. 685 * i386-tbl.h: Regenerated. 686 687 2018-03-08 H.J. Lu <hongjiu.lu (a] intel.com> 688 689 * i386-gen.c (opcode_modifiers): Remove OldGcc. 690 * i386-opc.h (OldGcc): Removed. 691 (i386_opcode_modifier): Remove oldgcc. 692 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp 693 instructions for old (<= 2.8.1) versions of gcc. 694 * i386-tbl.h: Regenerated. 695 696 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 697 698 * i386-opc.h (EVEXDYN): New. 699 * i386-opc.tbl: Fold various AVX512VL templates. 700 * i386-tlb.h: Re-generate. 701 702 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 703 704 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps, 705 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups, 706 vpexpandd, vpexpandq): Fold AFX512VF templates. 707 * i386-tlb.h: Re-generate. 708 709 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 710 711 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb): 712 Fold 128- and 256-bit VEX-encoded templates. 713 * i386-tlb.h: Re-generate. 714 715 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 716 717 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps, 718 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups, 719 vpexpandd, vpexpandq): Fold AVX512F templates. 720 * i386-tlb.h: Re-generate. 721 722 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 723 724 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and 725 64-bit templates. Drop Disp<N>. 726 * i386-tlb.h: Re-generate. 727 728 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 729 730 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128- 731 and 256-bit templates. 732 * i386-tlb.h: Re-generate. 733 734 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 735 736 * i386-opc.tbl (cmpxchg8b): Add NoRex64. 737 * i386-tlb.h: Re-generate. 738 739 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 740 741 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx): 742 Drop NoAVX. 743 * i386-tlb.h: Re-generate. 744 745 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 746 747 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX. 748 * i386-tlb.h: Re-generate. 749 750 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 751 752 * i386-gen.c (opcode_modifiers): Delete FloatD. 753 * i386-opc.h (FloatD): Delete. 754 (struct i386_opcode_modifier): Delete floatd. 755 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace 756 FloatD by D. 757 * i386-tlb.h: Re-generate. 758 759 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 760 761 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns. 762 763 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 764 765 * i386-opc.tbl (vmovd): Disallow Qword memory operands. 766 * i386-tlb.h: Re-generate. 767 768 2018-03-08 Jan Beulich <jbeulich (a] suse.com> 769 770 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory 771 forms. 772 * i386-tlb.h: Re-generate. 773 774 2018-03-07 Alan Modra <amodra (a] gmail.com> 775 776 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for 777 bfd_arch_rs6000. 778 * disassemble.h (print_insn_rs6000): Delete. 779 * ppc-dis.c (powerpc_init_dialect): Handle rs6000. 780 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000. 781 (print_insn_rs6000): Delete. 782 783 2018-03-03 Alan Modra <amodra (a] gmail.com> 784 785 * sysdep.h (opcodes_error_handler): Define. 786 (_bfd_error_handler): Declare. 787 * Makefile.am: Remove stray #. 788 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT 789 EDIT" comment. 790 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, 791 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, 792 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use 793 opcodes_error_handler to print errors. Standardize error messages. 794 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, 795 and include opintl.h. 796 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. 797 * i386-gen.c: Standardize error messages. 798 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. 799 * Makefile.in: Regenerate. 800 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, 801 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, 802 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, 803 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, 804 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, 805 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, 806 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, 807 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, 808 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, 809 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, 810 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, 811 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, 812 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate. 813 814 2018-03-01 H.J. Lu <hongjiu.lu (a] intel.com> 815 816 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512 817 vpsub[bwdq] instructions. 818 * i386-tbl.h: Regenerated. 819 820 2018-03-01 Alan Modra <amodra (a] gmail.com> 821 822 * configure.ac (ALL_LINGUAS): Sort. 823 * configure: Regenerate. 824 825 2018-02-27 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 826 827 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY 828 macro by assignements. 829 830 2018-02-27 H.J. Lu <hongjiu.lu (a] intel.com> 831 832 PR gas/22871 833 * i386-gen.c (opcode_modifiers): Add Optimize. 834 * i386-opc.h (Optimize): New enum. 835 (i386_opcode_modifier): Add optimize. 836 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg", 837 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem", 838 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem", 839 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps, 840 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor, 841 vpxord and vpxorq. 842 * i386-tbl.h: Regenerated. 843 844 2018-02-26 Alan Modra <amodra (a] gmail.com> 845 846 * crx-dis.c (getregliststring): Allocate a large enough buffer 847 to silence false positive gcc8 warning. 848 849 2018-02-22 Shea Levy <shea (a] shealevy.com> 850 851 * disassemble.c (ARCH_riscv): Define if ARCH_all. 852 853 2018-02-22 H.J. Lu <hongjiu.lu (a] intel.com> 854 855 * i386-opc.tbl: Add {rex}, 856 * i386-tbl.h: Regenerated. 857 858 2018-02-20 Maciej W. Rozycki <macro (a] mips.com> 859 860 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case. 861 (mips16_opcodes): Replace `M' with `m' for "restore". 862 863 2018-02-19 Thomas Preud'homme <thomas.preudhomme (a] arm.com> 864 865 * arm-dis.c (thumb_opcodes): Fix BXNS mask. 866 867 2018-02-13 Maciej W. Rozycki <macro (a] mips.com> 868 869 * wasm32-dis.c (print_insn_wasm32): Rename `index' local 870 variable to `function_index'. 871 872 2018-02-13 Nick Clifton <nickc (a] redhat.com> 873 874 PR 22823 875 * metag-dis.c (print_fmmov): Double buffer size to avoid warning 876 about truncation of printing. 877 878 2018-02-12 Henry Wong <henry (a] stuffedcow.net> 879 880 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding. 881 882 2018-02-05 Nick Clifton <nickc (a] redhat.com> 883 884 * po/pt_BR.po: Updated Brazilian Portuguese translation. 885 886 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 887 888 * i386-dis.c (enum): Add pconfig. 889 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS. 890 (cpu_flags): Add CpuPCONFIG. 891 * i386-opc.h (enum): Add CpuPCONFIG. 892 (i386_cpu_flags): Add cpupconfig. 893 * i386-opc.tbl: Add PCONFIG instruction. 894 * i386-init.h: Regenerate. 895 * i386-tbl.h: Likewise. 896 897 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 898 899 * i386-dis.c (enum): Add PREFIX_0F09. 900 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS. 901 (cpu_flags): Add CpuWBNOINVD. 902 * i386-opc.h (enum): Add CpuWBNOINVD. 903 (i386_cpu_flags): Add cpuwbnoinvd. 904 * i386-opc.tbl: Add WBNOINVD instruction. 905 * i386-init.h: Regenerate. 906 * i386-tbl.h: Likewise. 907 908 2018-01-17 Jim Wilson <jimw (a] sifive.com> 909 910 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0. 911 912 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 913 914 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET. 915 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS, 916 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK. 917 (cpu_flags): Add CpuIBT, CpuSHSTK. 918 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK. 919 (i386_cpu_flags): Add cpuibt, cpushstk. 920 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT. 921 * i386-init.h: Regenerate. 922 * i386-tbl.h: Likewise. 923 924 2018-01-16 Nick Clifton <nickc (a] redhat.com> 925 926 * po/pt_BR.po: Updated Brazilian Portugese translation. 927 * po/de.po: Updated German translation. 928 929 2018-01-15 Jim Wilson <jimw (a] sifive.com> 930 931 * riscv-opc.c (match_c_nop): New. 932 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop. 933 934 2018-01-15 Nick Clifton <nickc (a] redhat.com> 935 936 * po/uk.po: Updated Ukranian translation. 937 938 2018-01-13 Nick Clifton <nickc (a] redhat.com> 939 940 * po/opcodes.pot: Regenerated. 941 942 2018-01-13 Nick Clifton <nickc (a] redhat.com> 943 944 * configure: Regenerate. 945 946 2018-01-13 Nick Clifton <nickc (a] redhat.com> 947 948 2.30 branch created. 949 950 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist (a] intel.com> 951 952 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns. 953 * i386-tbl.h: Regenerate. 954 955 2018-01-10 Jan Beulich <jbeulich (a] suse.com> 956 957 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift. 958 * i386-tbl.h: Re-generate. 959 960 2018-01-10 Jan Beulich <jbeulich (a] suse.com> 961 962 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, 963 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub, 964 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew, 965 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw, 966 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust 967 Disp8MemShift of AVX512VL forms. 968 * i386-tbl.h: Re-generate. 969 970 2018-01-09 Jim Wilson <jimw (a] sifive.com> 971 972 * riscv-dis.c (maybe_print_address): If base_reg is zero, 973 then the hi_addr value is zero. 974 975 2018-01-09 James Greenhalgh <james.greenhalgh (a] arm.com> 976 977 * arm-dis.c (arm_opcodes): Add csdb. 978 (thumb32_opcodes): Add csdb. 979 980 2018-01-09 James Greenhalgh <james.greenhalgh (a] arm.com> 981 982 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". 983 * aarch64-asm-2.c: Regenerate. 984 * aarch64-dis-2.c: Regenerate. 985 * aarch64-opc-2.c: Regenerate. 986 987 2018-01-08 H.J. Lu <hongjiu.lu (a] intel.com> 988 989 PR gas/22681 990 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand. 991 Remove AVX512 vmovd with 64-bit operands. 992 * i386-tbl.h: Regenerated. 993 994 2018-01-05 Jim Wilson <jimw (a] sifive.com> 995 996 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a 997 jalr. 998 999 2018-01-03 Alan Modra <amodra (a] gmail.com> 1000 1001 Update year range in copyright notice of all files. 1002 1003 2018-01-02 Jan Beulich <jbeulich (a] suse.com> 1004 1005 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM 1006 and OPERAND_TYPE_REGZMM entries. 1007 1008 For older changes see ChangeLog-2017 1009 1011 Copyright (C) 2018 Free Software Foundation, Inc. 1012 1013 Copying and distribution of this file, with or without modification, 1014 are permitted in any medium without royalty provided the copyright 1015 notice and this notice are preserved. 1016 1017 Local Variables: 1018 mode: change-log 1019 left-margin: 8 1020 fill-column: 74 1021 version-control: never 1022 End: 1023
Indexes created Mon Oct 26 00:26:21 UTC 2026