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      1 /* This file is automatically generated by aarch64-gen.  Do not edit!  */
      2 /* Copyright (C) 2012-2026 Free Software Foundation, Inc.
      3    Contributed by Arm Ltd.
      4 
      5    This file is part of the GNU opcodes library.
      6 
      7    This library is free software; you can redistribute it and/or modify
      8    it under the terms of the GNU General Public License as published by
      9    the Free Software Foundation; either version 3, or (at your option)
     10    any later version.
     11 
     12    It is distributed in the hope that it will be useful, but WITHOUT
     13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     15    License for more details.
     16 
     17    You should have received a copy of the GNU General Public License
     18    along with this program; see the file COPYING3. If not,
     19    see <http://www.gnu.org/licenses/>.  */
     20 
     21 #include "sysdep.h"
     22 #include "aarch64-tbl-2.h"
     23 #include "aarch64-asm.h"
     24 
     25 
     26 const aarch64_opcode *
     27 aarch64_find_real_opcode (const aarch64_opcode *opcode)
     28 {
     29   /* Use the index as the key to locate the real opcode.  */
     30   enum aarch64_opcode_idx key = opcode - aarch64_opcode_table;
     31   enum aarch64_opcode_idx value;
     32   switch (key)
     33     {
     34     case A64_OPID_5a0003e0_ngc_Rd_Rm:
     35     case A64_OPID_5a000000_sbc_Rd_Rn_Rm:
     36       value = A64_OPID_5a000000_sbc_Rd_Rn_Rm;
     37       break;
     38     case A64_OPID_7a0003e0_ngcs_Rd_Rm:
     39     case A64_OPID_7a000000_sbcs_Rd_Rn_Rm:
     40       value = A64_OPID_7a000000_sbcs_Rd_Rn_Rm;
     41       break;
     42     case A64_OPID_2b20001f_cmn_Rn_SP_Rm_EXT:
     43     case A64_OPID_2b200000_adds_Rd_Rn_SP_Rm_EXT:
     44       value = A64_OPID_2b200000_adds_Rd_Rn_SP_Rm_EXT;
     45       break;
     46     case A64_OPID_6b20001f_cmp_Rn_SP_Rm_EXT:
     47     case A64_OPID_6b200000_subs_Rd_Rn_SP_Rm_EXT:
     48       value = A64_OPID_6b200000_subs_Rd_Rn_SP_Rm_EXT;
     49       break;
     50     case A64_OPID_11000000_mov_Rd_SP_Rn_SP:
     51     case A64_OPID_11000000_add_Rd_SP_Rn_SP_AIMM:
     52       value = A64_OPID_11000000_add_Rd_SP_Rn_SP_AIMM;
     53       break;
     54     case A64_OPID_3100001f_cmn_Rn_SP_AIMM:
     55     case A64_OPID_31000000_adds_Rd_Rn_SP_AIMM:
     56       value = A64_OPID_31000000_adds_Rd_Rn_SP_AIMM;
     57       break;
     58     case A64_OPID_7100001f_cmp_Rn_SP_AIMM:
     59     case A64_OPID_71000000_subs_Rd_Rn_SP_AIMM:
     60       value = A64_OPID_71000000_subs_Rd_Rn_SP_AIMM;
     61       break;
     62     case A64_OPID_2b00001f_cmn_Rn_Rm_SFT:
     63     case A64_OPID_2b000000_adds_Rd_Rn_Rm_SFT:
     64       value = A64_OPID_2b000000_adds_Rd_Rn_Rm_SFT;
     65       break;
     66     case A64_OPID_4b0003e0_neg_Rd_Rm_SFT:
     67     case A64_OPID_4b000000_sub_Rd_Rn_Rm_SFT:
     68       value = A64_OPID_4b000000_sub_Rd_Rn_Rm_SFT;
     69       break;
     70     case A64_OPID_6b00001f_cmp_Rn_Rm_SFT:
     71     case A64_OPID_6b0003e0_negs_Rd_Rm_SFT:
     72     case A64_OPID_6b000000_subs_Rd_Rn_Rm_SFT:
     73       value = A64_OPID_6b000000_subs_Rd_Rn_Rm_SFT;
     74       break;
     75     case A64_OPID_0e003c00_mov_Rd_En:
     76     case A64_OPID_0e003c00_umov_Rd_En:
     77       value = A64_OPID_0e003c00_umov_Rd_En;
     78       break;
     79     case A64_OPID_4e001c00_mov_Ed_Rn:
     80     case A64_OPID_4e001c00_ins_Ed_Rn:
     81       value = A64_OPID_4e001c00_ins_Ed_Rn;
     82       break;
     83     case A64_OPID_6e000400_mov_Ed_En:
     84     case A64_OPID_6e000400_ins_Ed_En:
     85       value = A64_OPID_6e000400_ins_Ed_En;
     86       break;
     87     case A64_OPID_2e205800_mvn_Vd_Vn:
     88     case A64_OPID_2e205800_not_Vd_Vn:
     89       value = A64_OPID_2e205800_not_Vd_Vn;
     90       break;
     91     case A64_OPID_0ea01c00_mov_Vd_Vn:
     92     case A64_OPID_0ea01c00_orr_Vd_Vn_Vm:
     93       value = A64_OPID_0ea01c00_orr_Vd_Vn_Vm;
     94       break;
     95     case A64_OPID_0f00a400_sxtl_Vd_Vn:
     96     case A64_OPID_0f00a400_sshll_Vd_Vn_IMM_VLSL:
     97       value = A64_OPID_0f00a400_sshll_Vd_Vn_IMM_VLSL;
     98       break;
     99     case A64_OPID_4f00a400_sxtl2_Vd_Vn:
    100     case A64_OPID_4f00a400_sshll2_Vd_Vn_IMM_VLSL:
    101       value = A64_OPID_4f00a400_sshll2_Vd_Vn_IMM_VLSL;
    102       break;
    103     case A64_OPID_2f00a400_uxtl_Vd_Vn:
    104     case A64_OPID_2f00a400_ushll_Vd_Vn_IMM_VLSL:
    105       value = A64_OPID_2f00a400_ushll_Vd_Vn_IMM_VLSL;
    106       break;
    107     case A64_OPID_6f00a400_uxtl2_Vd_Vn:
    108     case A64_OPID_6f00a400_ushll2_Vd_Vn_IMM_VLSL:
    109       value = A64_OPID_6f00a400_ushll2_Vd_Vn_IMM_VLSL;
    110       break;
    111     case A64_OPID_5e000400_mov_Sd_En:
    112     case A64_OPID_5e000400_dup_Sd_En:
    113       value = A64_OPID_5e000400_dup_Sd_En;
    114       break;
    115     case A64_OPID_93407c00_sxtw_Rd_Rn:
    116     case A64_OPID_13003c00_sxth_Rd_Rn:
    117     case A64_OPID_13001c00_sxtb_Rd_Rn:
    118     case A64_OPID_13000000_asr_Rd_Rn_IMM:
    119     case A64_OPID_13000000_sbfx_Rd_Rn_IMM_WIDTH:
    120     case A64_OPID_13000000_sbfiz_Rd_Rn_IMM_WIDTH:
    121     case A64_OPID_13000000_sbfm_Rd_Rn_IMMR_IMMS:
    122       value = A64_OPID_13000000_sbfm_Rd_Rn_IMMR_IMMS;
    123       break;
    124     case A64_OPID_330003e0_bfc_Rd_IMM_WIDTH:
    125     case A64_OPID_33000000_bfxil_Rd_Rn_IMM_WIDTH:
    126     case A64_OPID_33000000_bfi_Rd_Rn_IMM_WIDTH:
    127     case A64_OPID_33000000_bfm_Rd_Rn_IMMR_IMMS:
    128       value = A64_OPID_33000000_bfm_Rd_Rn_IMMR_IMMS;
    129       break;
    130     case A64_OPID_53003c00_uxth_Rd_Rn:
    131     case A64_OPID_53001c00_uxtb_Rd_Rn:
    132     case A64_OPID_53000000_lsr_Rd_Rn_IMM:
    133     case A64_OPID_53000000_lsl_Rd_Rn_IMM:
    134     case A64_OPID_53000000_ubfx_Rd_Rn_IMM_WIDTH:
    135     case A64_OPID_53000000_ubfiz_Rd_Rn_IMM_WIDTH:
    136     case A64_OPID_53000000_ubfm_Rd_Rn_IMMR_IMMS:
    137       value = A64_OPID_53000000_ubfm_Rd_Rn_IMMR_IMMS;
    138       break;
    139     case A64_OPID_74000000_cblt_Rm_Rt_ADDR_PCREL9:
    140     case A64_OPID_74000000_cbgt_Rt_Rm_ADDR_PCREL9:
    141       value = A64_OPID_74000000_cbgt_Rt_Rm_ADDR_PCREL9;
    142       break;
    143     case A64_OPID_74200000_cble_Rm_Rt_ADDR_PCREL9:
    144     case A64_OPID_74200000_cbge_Rt_Rm_ADDR_PCREL9:
    145       value = A64_OPID_74200000_cbge_Rt_Rm_ADDR_PCREL9;
    146       break;
    147     case A64_OPID_74400000_cblo_Rm_Rt_ADDR_PCREL9:
    148     case A64_OPID_74400000_cbhi_Rt_Rm_ADDR_PCREL9:
    149       value = A64_OPID_74400000_cbhi_Rt_Rm_ADDR_PCREL9;
    150       break;
    151     case A64_OPID_74600000_cbls_Rm_Rt_ADDR_PCREL9:
    152     case A64_OPID_74600000_cbhs_Rt_Rm_ADDR_PCREL9:
    153       value = A64_OPID_74600000_cbhs_Rt_Rm_ADDR_PCREL9;
    154       break;
    155     case A64_OPID_75000000_cbge_Rt_IMMP1_2_ADDR_PCREL9:
    156     case A64_OPID_75000000_cbgt_Rt_IMM_2_ADDR_PCREL9:
    157       value = A64_OPID_75000000_cbgt_Rt_IMM_2_ADDR_PCREL9;
    158       break;
    159     case A64_OPID_75200000_cble_Rt_IMMS1_2_ADDR_PCREL9:
    160     case A64_OPID_75200000_cblt_Rt_IMM_2_ADDR_PCREL9:
    161       value = A64_OPID_75200000_cblt_Rt_IMM_2_ADDR_PCREL9;
    162       break;
    163     case A64_OPID_75400000_cbhs_Rt_IMMP1_2_ADDR_PCREL9:
    164     case A64_OPID_75400000_cbhi_Rt_IMM_2_ADDR_PCREL9:
    165       value = A64_OPID_75400000_cbhi_Rt_IMM_2_ADDR_PCREL9;
    166       break;
    167     case A64_OPID_75600000_cbls_Rt_IMMS1_2_ADDR_PCREL9:
    168     case A64_OPID_75600000_cblo_Rt_IMM_2_ADDR_PCREL9:
    169       value = A64_OPID_75600000_cblo_Rt_IMM_2_ADDR_PCREL9;
    170       break;
    171     case A64_OPID_74008000_cbblt_Rm_Rt_ADDR_PCREL9:
    172     case A64_OPID_74008000_cbbgt_Rt_Rm_ADDR_PCREL9:
    173       value = A64_OPID_74008000_cbbgt_Rt_Rm_ADDR_PCREL9;
    174       break;
    175     case A64_OPID_74208000_cbble_Rm_Rt_ADDR_PCREL9:
    176     case A64_OPID_74208000_cbbge_Rt_Rm_ADDR_PCREL9:
    177       value = A64_OPID_74208000_cbbge_Rt_Rm_ADDR_PCREL9;
    178       break;
    179     case A64_OPID_74408000_cbblo_Rm_Rt_ADDR_PCREL9:
    180     case A64_OPID_74408000_cbbhi_Rt_Rm_ADDR_PCREL9:
    181       value = A64_OPID_74408000_cbbhi_Rt_Rm_ADDR_PCREL9;
    182       break;
    183     case A64_OPID_74608000_cbbls_Rm_Rt_ADDR_PCREL9:
    184     case A64_OPID_74608000_cbbhs_Rt_Rm_ADDR_PCREL9:
    185       value = A64_OPID_74608000_cbbhs_Rt_Rm_ADDR_PCREL9;
    186       break;
    187     case A64_OPID_7400c000_cbhlt_Rm_Rt_ADDR_PCREL9:
    188     case A64_OPID_7400c000_cbhgt_Rt_Rm_ADDR_PCREL9:
    189       value = A64_OPID_7400c000_cbhgt_Rt_Rm_ADDR_PCREL9;
    190       break;
    191     case A64_OPID_7420c000_cbhle_Rm_Rt_ADDR_PCREL9:
    192     case A64_OPID_7420c000_cbhge_Rt_Rm_ADDR_PCREL9:
    193       value = A64_OPID_7420c000_cbhge_Rt_Rm_ADDR_PCREL9;
    194       break;
    195     case A64_OPID_7440c000_cbhlo_Rm_Rt_ADDR_PCREL9:
    196     case A64_OPID_7440c000_cbhhi_Rt_Rm_ADDR_PCREL9:
    197       value = A64_OPID_7440c000_cbhhi_Rt_Rm_ADDR_PCREL9;
    198       break;
    199     case A64_OPID_7460c000_cbhls_Rm_Rt_ADDR_PCREL9:
    200     case A64_OPID_7460c000_cbhhs_Rt_Rm_ADDR_PCREL9:
    201       value = A64_OPID_7460c000_cbhhs_Rt_Rm_ADDR_PCREL9;
    202       break;
    203     case A64_OPID_1a9f07e0_cset_Rd_COND1:
    204     case A64_OPID_1a800400_cinc_Rd_Rn_COND1:
    205     case A64_OPID_1a800400_csinc_Rd_Rn_Rm_COND:
    206       value = A64_OPID_1a800400_csinc_Rd_Rn_Rm_COND;
    207       break;
    208     case A64_OPID_5a9f03e0_csetm_Rd_COND1:
    209     case A64_OPID_5a800000_cinv_Rd_Rn_COND1:
    210     case A64_OPID_5a800000_csinv_Rd_Rn_Rm_COND:
    211       value = A64_OPID_5a800000_csinv_Rd_Rn_Rm_COND;
    212       break;
    213     case A64_OPID_5a800400_cneg_Rd_Rn_COND1:
    214     case A64_OPID_5a800400_csneg_Rd_Rn_Rm_COND:
    215       value = A64_OPID_5a800400_csneg_Rd_Rn_Rm_COND;
    216       break;
    217     case A64_OPID_dac00c00_rev64_Rd_Rn:
    218     case A64_OPID_dac00c00_rev_Rd_Rn:
    219       value = A64_OPID_dac00c00_rev_Rd_Rn;
    220       break;
    221     case A64_OPID_1ac02000_lsl_Rd_Rn_Rm:
    222     case A64_OPID_1ac02000_lslv_Rd_Rn_Rm:
    223       value = A64_OPID_1ac02000_lslv_Rd_Rn_Rm;
    224       break;
    225     case A64_OPID_1ac02400_lsr_Rd_Rn_Rm:
    226     case A64_OPID_1ac02400_lsrv_Rd_Rn_Rm:
    227       value = A64_OPID_1ac02400_lsrv_Rd_Rn_Rm;
    228       break;
    229     case A64_OPID_1ac02800_asr_Rd_Rn_Rm:
    230     case A64_OPID_1ac02800_asrv_Rd_Rn_Rm:
    231       value = A64_OPID_1ac02800_asrv_Rd_Rn_Rm;
    232       break;
    233     case A64_OPID_1ac02c00_ror_Rd_Rn_Rm:
    234     case A64_OPID_1ac02c00_rorv_Rd_Rn_Rm:
    235       value = A64_OPID_1ac02c00_rorv_Rd_Rn_Rm;
    236       break;
    237     case A64_OPID_bac0001f_cmpp_Rn_SP_Rm_SP:
    238     case A64_OPID_bac00000_subps_Rd_Rn_SP_Rm_SP:
    239       value = A64_OPID_bac00000_subps_Rd_Rn_SP_Rm_SP;
    240       break;
    241     case A64_OPID_1b007c00_mul_Rd_Rn_Rm:
    242     case A64_OPID_1b000000_madd_Rd_Rn_Rm_Ra:
    243       value = A64_OPID_1b000000_madd_Rd_Rn_Rm_Ra;
    244       break;
    245     case A64_OPID_1b00fc00_mneg_Rd_Rn_Rm:
    246     case A64_OPID_1b008000_msub_Rd_Rn_Rm_Ra:
    247       value = A64_OPID_1b008000_msub_Rd_Rn_Rm_Ra;
    248       break;
    249     case A64_OPID_9b207c00_smull_Rd_Rn_Rm:
    250     case A64_OPID_9b200000_smaddl_Rd_Rn_Rm_Ra:
    251       value = A64_OPID_9b200000_smaddl_Rd_Rn_Rm_Ra;
    252       break;
    253     case A64_OPID_9b20fc00_smnegl_Rd_Rn_Rm:
    254     case A64_OPID_9b208000_smsubl_Rd_Rn_Rm_Ra:
    255       value = A64_OPID_9b208000_smsubl_Rd_Rn_Rm_Ra;
    256       break;
    257     case A64_OPID_9ba07c00_umull_Rd_Rn_Rm:
    258     case A64_OPID_9ba00000_umaddl_Rd_Rn_Rm_Ra:
    259       value = A64_OPID_9ba00000_umaddl_Rd_Rn_Rm_Ra;
    260       break;
    261     case A64_OPID_9ba0fc00_umnegl_Rd_Rn_Rm:
    262     case A64_OPID_9ba08000_umsubl_Rd_Rn_Rm_Ra:
    263       value = A64_OPID_9ba08000_umsubl_Rd_Rn_Rm_Ra;
    264       break;
    265     case A64_OPID_13800000_ror_Rd_Rm_IMMS:
    266     case A64_OPID_13800000_extr_Rd_Rn_Rm_IMMS:
    267       value = A64_OPID_13800000_extr_Rd_Rn_Rm_IMMS;
    268       break;
    269     case A64_OPID_12000000_bic_Rd_SP_Rn_LIMM:
    270     case A64_OPID_12000000_and_Rd_SP_Rn_LIMM:
    271       value = A64_OPID_12000000_and_Rd_SP_Rn_LIMM;
    272       break;
    273     case A64_OPID_320003e0_mov_Rd_SP_IMM_MOV:
    274     case A64_OPID_32000000_orr_Rd_SP_Rn_LIMM:
    275       value = A64_OPID_32000000_orr_Rd_SP_Rn_LIMM;
    276       break;
    277     case A64_OPID_7200001f_tst_Rn_LIMM:
    278     case A64_OPID_72000000_ands_Rd_Rn_LIMM:
    279       value = A64_OPID_72000000_ands_Rd_Rn_LIMM;
    280       break;
    281     case A64_OPID_2a0003e0_uxtw_Rd_Rm:
    282     case A64_OPID_2a0003e0_mov_Rd_Rm_SFT:
    283     case A64_OPID_2a000000_orr_Rd_Rn_Rm_SFT:
    284       value = A64_OPID_2a000000_orr_Rd_Rn_Rm_SFT;
    285       break;
    286     case A64_OPID_2a2003e0_mvn_Rd_Rm_SFT:
    287     case A64_OPID_2a200000_orn_Rd_Rn_Rm_SFT:
    288       value = A64_OPID_2a200000_orn_Rd_Rn_Rm_SFT;
    289       break;
    290     case A64_OPID_6a00001f_tst_Rn_Rm_SFT:
    291     case A64_OPID_6a000000_ands_Rd_Rn_Rm_SFT:
    292       value = A64_OPID_6a000000_ands_Rd_Rn_Rm_SFT;
    293       break;
    294     case A64_OPID_3820001f_staddb_Rs_ADDR_SIMPLE:
    295     case A64_OPID_38200000_ldaddb_Rs_Rt_ADDR_SIMPLE:
    296       value = A64_OPID_38200000_ldaddb_Rs_Rt_ADDR_SIMPLE;
    297       break;
    298     case A64_OPID_7820001f_staddh_Rs_ADDR_SIMPLE:
    299     case A64_OPID_78200000_ldaddh_Rs_Rt_ADDR_SIMPLE:
    300       value = A64_OPID_78200000_ldaddh_Rs_Rt_ADDR_SIMPLE;
    301       break;
    302     case A64_OPID_b820001f_stadd_Rs_ADDR_SIMPLE:
    303     case A64_OPID_b8200000_ldadd_Rs_Rt_ADDR_SIMPLE:
    304       value = A64_OPID_b8200000_ldadd_Rs_Rt_ADDR_SIMPLE;
    305       break;
    306     case A64_OPID_3860001f_staddlb_Rs_ADDR_SIMPLE:
    307     case A64_OPID_38600000_ldaddlb_Rs_Rt_ADDR_SIMPLE:
    308       value = A64_OPID_38600000_ldaddlb_Rs_Rt_ADDR_SIMPLE;
    309       break;
    310     case A64_OPID_7860001f_staddlh_Rs_ADDR_SIMPLE:
    311     case A64_OPID_78600000_ldaddlh_Rs_Rt_ADDR_SIMPLE:
    312       value = A64_OPID_78600000_ldaddlh_Rs_Rt_ADDR_SIMPLE;
    313       break;
    314     case A64_OPID_b860001f_staddl_Rs_ADDR_SIMPLE:
    315     case A64_OPID_b8600000_ldaddl_Rs_Rt_ADDR_SIMPLE:
    316       value = A64_OPID_b8600000_ldaddl_Rs_Rt_ADDR_SIMPLE;
    317       break;
    318     case A64_OPID_3820101f_stclrb_Rs_ADDR_SIMPLE:
    319     case A64_OPID_38201000_ldclrb_Rs_Rt_ADDR_SIMPLE:
    320       value = A64_OPID_38201000_ldclrb_Rs_Rt_ADDR_SIMPLE;
    321       break;
    322     case A64_OPID_7820101f_stclrh_Rs_ADDR_SIMPLE:
    323     case A64_OPID_78201000_ldclrh_Rs_Rt_ADDR_SIMPLE:
    324       value = A64_OPID_78201000_ldclrh_Rs_Rt_ADDR_SIMPLE;
    325       break;
    326     case A64_OPID_b820101f_stclr_Rs_ADDR_SIMPLE:
    327     case A64_OPID_b8201000_ldclr_Rs_Rt_ADDR_SIMPLE:
    328       value = A64_OPID_b8201000_ldclr_Rs_Rt_ADDR_SIMPLE;
    329       break;
    330     case A64_OPID_3860101f_stclrlb_Rs_ADDR_SIMPLE:
    331     case A64_OPID_38601000_ldclrlb_Rs_Rt_ADDR_SIMPLE:
    332       value = A64_OPID_38601000_ldclrlb_Rs_Rt_ADDR_SIMPLE;
    333       break;
    334     case A64_OPID_7860101f_stclrlh_Rs_ADDR_SIMPLE:
    335     case A64_OPID_78601000_ldclrlh_Rs_Rt_ADDR_SIMPLE:
    336       value = A64_OPID_78601000_ldclrlh_Rs_Rt_ADDR_SIMPLE;
    337       break;
    338     case A64_OPID_b860101f_stclrl_Rs_ADDR_SIMPLE:
    339     case A64_OPID_b8601000_ldclrl_Rs_Rt_ADDR_SIMPLE:
    340       value = A64_OPID_b8601000_ldclrl_Rs_Rt_ADDR_SIMPLE;
    341       break;
    342     case A64_OPID_3820201f_steorb_Rs_ADDR_SIMPLE:
    343     case A64_OPID_38202000_ldeorb_Rs_Rt_ADDR_SIMPLE:
    344       value = A64_OPID_38202000_ldeorb_Rs_Rt_ADDR_SIMPLE;
    345       break;
    346     case A64_OPID_7820201f_steorh_Rs_ADDR_SIMPLE:
    347     case A64_OPID_78202000_ldeorh_Rs_Rt_ADDR_SIMPLE:
    348       value = A64_OPID_78202000_ldeorh_Rs_Rt_ADDR_SIMPLE;
    349       break;
    350     case A64_OPID_b820201f_steor_Rs_ADDR_SIMPLE:
    351     case A64_OPID_b8202000_ldeor_Rs_Rt_ADDR_SIMPLE:
    352       value = A64_OPID_b8202000_ldeor_Rs_Rt_ADDR_SIMPLE;
    353       break;
    354     case A64_OPID_3860201f_steorlb_Rs_ADDR_SIMPLE:
    355     case A64_OPID_38602000_ldeorlb_Rs_Rt_ADDR_SIMPLE:
    356       value = A64_OPID_38602000_ldeorlb_Rs_Rt_ADDR_SIMPLE;
    357       break;
    358     case A64_OPID_7860201f_steorlh_Rs_ADDR_SIMPLE:
    359     case A64_OPID_78602000_ldeorlh_Rs_Rt_ADDR_SIMPLE:
    360       value = A64_OPID_78602000_ldeorlh_Rs_Rt_ADDR_SIMPLE;
    361       break;
    362     case A64_OPID_b860201f_steorl_Rs_ADDR_SIMPLE:
    363     case A64_OPID_b8602000_ldeorl_Rs_Rt_ADDR_SIMPLE:
    364       value = A64_OPID_b8602000_ldeorl_Rs_Rt_ADDR_SIMPLE;
    365       break;
    366     case A64_OPID_3820301f_stsetb_Rs_ADDR_SIMPLE:
    367     case A64_OPID_38203000_ldsetb_Rs_Rt_ADDR_SIMPLE:
    368       value = A64_OPID_38203000_ldsetb_Rs_Rt_ADDR_SIMPLE;
    369       break;
    370     case A64_OPID_7820301f_stseth_Rs_ADDR_SIMPLE:
    371     case A64_OPID_78203000_ldseth_Rs_Rt_ADDR_SIMPLE:
    372       value = A64_OPID_78203000_ldseth_Rs_Rt_ADDR_SIMPLE;
    373       break;
    374     case A64_OPID_b820301f_stset_Rs_ADDR_SIMPLE:
    375     case A64_OPID_b8203000_ldset_Rs_Rt_ADDR_SIMPLE:
    376       value = A64_OPID_b8203000_ldset_Rs_Rt_ADDR_SIMPLE;
    377       break;
    378     case A64_OPID_3860301f_stsetlb_Rs_ADDR_SIMPLE:
    379     case A64_OPID_38603000_ldsetlb_Rs_Rt_ADDR_SIMPLE:
    380       value = A64_OPID_38603000_ldsetlb_Rs_Rt_ADDR_SIMPLE;
    381       break;
    382     case A64_OPID_7860301f_stsetlh_Rs_ADDR_SIMPLE:
    383     case A64_OPID_78603000_ldsetlh_Rs_Rt_ADDR_SIMPLE:
    384       value = A64_OPID_78603000_ldsetlh_Rs_Rt_ADDR_SIMPLE;
    385       break;
    386     case A64_OPID_b860301f_stsetl_Rs_ADDR_SIMPLE:
    387     case A64_OPID_b8603000_ldsetl_Rs_Rt_ADDR_SIMPLE:
    388       value = A64_OPID_b8603000_ldsetl_Rs_Rt_ADDR_SIMPLE;
    389       break;
    390     case A64_OPID_3820401f_stsmaxb_Rs_ADDR_SIMPLE:
    391     case A64_OPID_38204000_ldsmaxb_Rs_Rt_ADDR_SIMPLE:
    392       value = A64_OPID_38204000_ldsmaxb_Rs_Rt_ADDR_SIMPLE;
    393       break;
    394     case A64_OPID_7820401f_stsmaxh_Rs_ADDR_SIMPLE:
    395     case A64_OPID_78204000_ldsmaxh_Rs_Rt_ADDR_SIMPLE:
    396       value = A64_OPID_78204000_ldsmaxh_Rs_Rt_ADDR_SIMPLE;
    397       break;
    398     case A64_OPID_b820401f_stsmax_Rs_ADDR_SIMPLE:
    399     case A64_OPID_b8204000_ldsmax_Rs_Rt_ADDR_SIMPLE:
    400       value = A64_OPID_b8204000_ldsmax_Rs_Rt_ADDR_SIMPLE;
    401       break;
    402     case A64_OPID_3860401f_stsmaxlb_Rs_ADDR_SIMPLE:
    403     case A64_OPID_38604000_ldsmaxlb_Rs_Rt_ADDR_SIMPLE:
    404       value = A64_OPID_38604000_ldsmaxlb_Rs_Rt_ADDR_SIMPLE;
    405       break;
    406     case A64_OPID_7860401f_stsmaxlh_Rs_ADDR_SIMPLE:
    407     case A64_OPID_78604000_ldsmaxlh_Rs_Rt_ADDR_SIMPLE:
    408       value = A64_OPID_78604000_ldsmaxlh_Rs_Rt_ADDR_SIMPLE;
    409       break;
    410     case A64_OPID_b860401f_stsmaxl_Rs_ADDR_SIMPLE:
    411     case A64_OPID_b8604000_ldsmaxl_Rs_Rt_ADDR_SIMPLE:
    412       value = A64_OPID_b8604000_ldsmaxl_Rs_Rt_ADDR_SIMPLE;
    413       break;
    414     case A64_OPID_3820501f_stsminb_Rs_ADDR_SIMPLE:
    415     case A64_OPID_38205000_ldsminb_Rs_Rt_ADDR_SIMPLE:
    416       value = A64_OPID_38205000_ldsminb_Rs_Rt_ADDR_SIMPLE;
    417       break;
    418     case A64_OPID_7820501f_stsminh_Rs_ADDR_SIMPLE:
    419     case A64_OPID_78205000_ldsminh_Rs_Rt_ADDR_SIMPLE:
    420       value = A64_OPID_78205000_ldsminh_Rs_Rt_ADDR_SIMPLE;
    421       break;
    422     case A64_OPID_b820501f_stsmin_Rs_ADDR_SIMPLE:
    423     case A64_OPID_b8205000_ldsmin_Rs_Rt_ADDR_SIMPLE:
    424       value = A64_OPID_b8205000_ldsmin_Rs_Rt_ADDR_SIMPLE;
    425       break;
    426     case A64_OPID_3860501f_stsminlb_Rs_ADDR_SIMPLE:
    427     case A64_OPID_38605000_ldsminlb_Rs_Rt_ADDR_SIMPLE:
    428       value = A64_OPID_38605000_ldsminlb_Rs_Rt_ADDR_SIMPLE;
    429       break;
    430     case A64_OPID_7860501f_stsminlh_Rs_ADDR_SIMPLE:
    431     case A64_OPID_78605000_ldsminlh_Rs_Rt_ADDR_SIMPLE:
    432       value = A64_OPID_78605000_ldsminlh_Rs_Rt_ADDR_SIMPLE;
    433       break;
    434     case A64_OPID_b860501f_stsminl_Rs_ADDR_SIMPLE:
    435     case A64_OPID_b8605000_ldsminl_Rs_Rt_ADDR_SIMPLE:
    436       value = A64_OPID_b8605000_ldsminl_Rs_Rt_ADDR_SIMPLE;
    437       break;
    438     case A64_OPID_3820601f_stumaxb_Rs_ADDR_SIMPLE:
    439     case A64_OPID_38206000_ldumaxb_Rs_Rt_ADDR_SIMPLE:
    440       value = A64_OPID_38206000_ldumaxb_Rs_Rt_ADDR_SIMPLE;
    441       break;
    442     case A64_OPID_7820601f_stumaxh_Rs_ADDR_SIMPLE:
    443     case A64_OPID_78206000_ldumaxh_Rs_Rt_ADDR_SIMPLE:
    444       value = A64_OPID_78206000_ldumaxh_Rs_Rt_ADDR_SIMPLE;
    445       break;
    446     case A64_OPID_b820601f_stumax_Rs_ADDR_SIMPLE:
    447     case A64_OPID_b8206000_ldumax_Rs_Rt_ADDR_SIMPLE:
    448       value = A64_OPID_b8206000_ldumax_Rs_Rt_ADDR_SIMPLE;
    449       break;
    450     case A64_OPID_3860601f_stumaxlb_Rs_ADDR_SIMPLE:
    451     case A64_OPID_38606000_ldumaxlb_Rs_Rt_ADDR_SIMPLE:
    452       value = A64_OPID_38606000_ldumaxlb_Rs_Rt_ADDR_SIMPLE;
    453       break;
    454     case A64_OPID_7860601f_stumaxlh_Rs_ADDR_SIMPLE:
    455     case A64_OPID_78606000_ldumaxlh_Rs_Rt_ADDR_SIMPLE:
    456       value = A64_OPID_78606000_ldumaxlh_Rs_Rt_ADDR_SIMPLE;
    457       break;
    458     case A64_OPID_b860601f_stumaxl_Rs_ADDR_SIMPLE:
    459     case A64_OPID_b8606000_ldumaxl_Rs_Rt_ADDR_SIMPLE:
    460       value = A64_OPID_b8606000_ldumaxl_Rs_Rt_ADDR_SIMPLE;
    461       break;
    462     case A64_OPID_3820701f_stuminb_Rs_ADDR_SIMPLE:
    463     case A64_OPID_38207000_lduminb_Rs_Rt_ADDR_SIMPLE:
    464       value = A64_OPID_38207000_lduminb_Rs_Rt_ADDR_SIMPLE;
    465       break;
    466     case A64_OPID_7820701f_stuminh_Rs_ADDR_SIMPLE:
    467     case A64_OPID_78207000_lduminh_Rs_Rt_ADDR_SIMPLE:
    468       value = A64_OPID_78207000_lduminh_Rs_Rt_ADDR_SIMPLE;
    469       break;
    470     case A64_OPID_b820701f_stumin_Rs_ADDR_SIMPLE:
    471     case A64_OPID_b8207000_ldumin_Rs_Rt_ADDR_SIMPLE:
    472       value = A64_OPID_b8207000_ldumin_Rs_Rt_ADDR_SIMPLE;
    473       break;
    474     case A64_OPID_3860701f_stuminlb_Rs_ADDR_SIMPLE:
    475     case A64_OPID_38607000_lduminlb_Rs_Rt_ADDR_SIMPLE:
    476       value = A64_OPID_38607000_lduminlb_Rs_Rt_ADDR_SIMPLE;
    477       break;
    478     case A64_OPID_7860701f_stuminlh_Rs_ADDR_SIMPLE:
    479     case A64_OPID_78607000_lduminlh_Rs_Rt_ADDR_SIMPLE:
    480       value = A64_OPID_78607000_lduminlh_Rs_Rt_ADDR_SIMPLE;
    481       break;
    482     case A64_OPID_b860701f_stuminl_Rs_ADDR_SIMPLE:
    483     case A64_OPID_b8607000_lduminl_Rs_Rt_ADDR_SIMPLE:
    484       value = A64_OPID_b8607000_lduminl_Rs_Rt_ADDR_SIMPLE;
    485       break;
    486     case A64_OPID_1920041f_sttadd_Rs_ADDR_SIMPLE:
    487     case A64_OPID_19200400_ldtadd_Rs_Rt_ADDR_SIMPLE:
    488       value = A64_OPID_19200400_ldtadd_Rs_Rt_ADDR_SIMPLE;
    489       break;
    490     case A64_OPID_1960041f_sttaddl_Rs_ADDR_SIMPLE:
    491     case A64_OPID_19600400_ldtaddl_Rs_Rt_ADDR_SIMPLE:
    492       value = A64_OPID_19600400_ldtaddl_Rs_Rt_ADDR_SIMPLE;
    493       break;
    494     case A64_OPID_1920141f_sttclr_Rs_ADDR_SIMPLE:
    495     case A64_OPID_19201400_ldtclr_Rs_Rt_ADDR_SIMPLE:
    496       value = A64_OPID_19201400_ldtclr_Rs_Rt_ADDR_SIMPLE;
    497       break;
    498     case A64_OPID_1960141f_sttclrl_Rs_ADDR_SIMPLE:
    499     case A64_OPID_19601400_ldtclrl_Rs_Rt_ADDR_SIMPLE:
    500       value = A64_OPID_19601400_ldtclrl_Rs_Rt_ADDR_SIMPLE;
    501       break;
    502     case A64_OPID_1920341f_sttset_Rs_ADDR_SIMPLE:
    503     case A64_OPID_19203400_ldtset_Rs_Rt_ADDR_SIMPLE:
    504       value = A64_OPID_19203400_ldtset_Rs_Rt_ADDR_SIMPLE;
    505       break;
    506     case A64_OPID_1960341f_sttsetl_Rs_ADDR_SIMPLE:
    507     case A64_OPID_19603400_ldtsetl_Rs_Rt_ADDR_SIMPLE:
    508       value = A64_OPID_19603400_ldtsetl_Rs_Rt_ADDR_SIMPLE;
    509       break;
    510     case A64_OPID_12800000_mov_Rd_IMM_MOV:
    511     case A64_OPID_12800000_movn_Rd_HALF:
    512       value = A64_OPID_12800000_movn_Rd_HALF;
    513       break;
    514     case A64_OPID_52800000_mov_Rd_IMM_MOV:
    515     case A64_OPID_52800000_movz_Rd_HALF:
    516       value = A64_OPID_52800000_movz_Rd_HALF;
    517       break;
    518     case A64_OPID_d50322df_clrbhb:
    519     case A64_OPID_d50323ff_autibsp:
    520     case A64_OPID_d50323df_autibz:
    521     case A64_OPID_d50323bf_autiasp:
    522     case A64_OPID_d503239f_autiaz:
    523     case A64_OPID_d503237f_pacibsp:
    524     case A64_OPID_d503235f_pacibz:
    525     case A64_OPID_d503233f_paciasp:
    526     case A64_OPID_d503231f_paciaz:
    527     case A64_OPID_d503227f_gcsb_BARRIER_GCSB:
    528     case A64_OPID_d50322df_clearbhb:
    529     case A64_OPID_d503225f_tsb_BARRIER_PSB:
    530     case A64_OPID_d503223f_psb_BARRIER_PSB:
    531     case A64_OPID_d503221f_esb:
    532     case A64_OPID_d50321df_autib1716:
    533     case A64_OPID_d503219f_autia1716:
    534     case A64_OPID_d503215f_pacib1716:
    535     case A64_OPID_d503211f_pacia1716:
    536     case A64_OPID_d50320ff_xpaclri:
    537     case A64_OPID_d50320df_dgh:
    538     case A64_OPID_d50320bf_sevl:
    539     case A64_OPID_d503209f_sev:
    540     case A64_OPID_d503207f_wfi:
    541     case A64_OPID_d503205f_wfe:
    542     case A64_OPID_d503203f_yield:
    543     case A64_OPID_d503241f_bti_BTI_TARGET:
    544     case A64_OPID_d503229f_csdb:
    545     case A64_OPID_d503201f_nop:
    546     case A64_OPID_d503265f_shuh_SHUH_PHINT:
    547     case A64_OPID_d503269f_stcph:
    548     case A64_OPID_d503261f_stshh_STSHH_POLICY:
    549     case A64_OPID_d503201f_hint_UIMM7:
    550       value = A64_OPID_d503201f_hint_UIMM7;
    551       break;
    552     case A64_OPID_d503349f_pssbb:
    553     case A64_OPID_d503309f_ssbb:
    554     case A64_OPID_d5033c9f_dfb:
    555     case A64_OPID_d503309f_dsb_BARRIER:
    556       value = A64_OPID_d503309f_dsb_BARRIER;
    557       break;
    558     case A64_OPID_d503323f_dsb_BARRIER_DSB_NXS:
    559       value = A64_OPID_d503323f_dsb_BARRIER_DSB_NXS;
    560       break;
    561     case A64_OPID_d5080000_plbi_SYSREG_PLBI_Rt_SYS:
    562     case A64_OPID_d508001f_gsb_GSB:
    563     case A64_OPID_d5080000_gicr_Rd_GICR:
    564     case A64_OPID_d5080000_gic_GIC_Rd:
    565     case A64_OPID_d50b72e0_trcit_Rt:
    566     case A64_OPID_d5097280_brb_BRBOP_Rt_IN_SYS_ALIASES:
    567     case A64_OPID_d50b73c0_cosp_SYSREG_SR_Rt:
    568     case A64_OPID_d50b73e0_cpp_SYSREG_SR_Rt:
    569     case A64_OPID_d50b73a0_dvp_SYSREG_SR_Rt:
    570     case A64_OPID_d50b7380_cfp_SYSREG_SR_Rt:
    571     case A64_OPID_d5080000_tlbi_SYSREG_TLBI_Rt_SYS:
    572     case A64_OPID_d5080000_ic_SYSREG_IC_Rt_SYS:
    573     case A64_OPID_d5080000_dc_SYSREG_DC_Rt:
    574     case A64_OPID_d5080000_at_SYSREG_AT_Rt:
    575     case A64_OPID_d5080000_mlbi_SYSREG_MLBI_Rt_SYS:
    576     case A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt:
    577       value = A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt;
    578       break;
    579     case A64_OPID_d5480000_tlbip_SYSREG_TLBIP_Rt_SYS_PAIRREG_OR_XZR:
    580     case A64_OPID_d5480000_sysp_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR:
    581       value = A64_OPID_d5480000_sysp_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR;
    582       break;
    583     case A64_OPID_d5031000_wfet_Rd:
    584       value = A64_OPID_d5031000_wfet_Rd;
    585       break;
    586     case A64_OPID_d5031020_wfit_Rd:
    587       value = A64_OPID_d5031020_wfit_Rd;
    588       break;
    589     case A64_OPID_05800000_bic_SVE_Zd_SVE_Zd_SVE_INV_LIMM:
    590     case A64_OPID_05800000_and_SVE_Zd_SVE_Zd_SVE_LIMM:
    591       value = A64_OPID_05800000_and_SVE_Zd_SVE_Zd_SVE_LIMM;
    592       break;
    593     case A64_OPID_25004000_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn:
    594     case A64_OPID_25004000_and_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm:
    595       value = A64_OPID_25004000_and_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm;
    596       break;
    597     case A64_OPID_25404000_movs_SVE_Pd_SVE_Pg4_10_SVE_Pn:
    598     case A64_OPID_25404000_ands_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm:
    599       value = A64_OPID_25404000_ands_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm;
    600       break;
    601     case A64_OPID_24008000_cmple_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    602     case A64_OPID_24008000_cmpge_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    603       value = A64_OPID_24008000_cmpge_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    604       break;
    605     case A64_OPID_24008010_cmplt_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    606     case A64_OPID_24008010_cmpgt_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    607       value = A64_OPID_24008010_cmpgt_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    608       break;
    609     case A64_OPID_24000010_cmplo_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    610     case A64_OPID_24000010_cmphi_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    611       value = A64_OPID_24000010_cmphi_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    612       break;
    613     case A64_OPID_24000000_cmpls_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    614     case A64_OPID_24000000_cmphs_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    615       value = A64_OPID_24000000_cmphs_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    616       break;
    617     case A64_OPID_05208000_mov_SVE_Zd_SVE_Pg3_SVE_Vn:
    618     case A64_OPID_05208000_cpy_SVE_Zd_SVE_Pg3_SVE_Vn:
    619       value = A64_OPID_05208000_cpy_SVE_Zd_SVE_Pg3_SVE_Vn;
    620       break;
    621     case A64_OPID_0528a000_mov_SVE_Zd_SVE_Pg3_Rn_SP:
    622     case A64_OPID_0528a000_cpy_SVE_Zd_SVE_Pg3_Rn_SP:
    623       value = A64_OPID_0528a000_cpy_SVE_Zd_SVE_Pg3_Rn_SP;
    624       break;
    625     case A64_OPID_05104000_fmov_SVE_Zd_SVE_Pg4_16_FPIMM0:
    626     case A64_OPID_05100000_mov_SVE_Zd_SVE_Pg4_16_SVE_ASIMM:
    627     case A64_OPID_05100000_cpy_SVE_Zd_SVE_Pg4_16_SVE_ASIMM:
    628       value = A64_OPID_05100000_cpy_SVE_Zd_SVE_Pg4_16_SVE_ASIMM;
    629       break;
    630     case A64_OPID_05203800_mov_SVE_Zd_Rn_SP:
    631     case A64_OPID_05203800_dup_SVE_Zd_Rn_SP:
    632       value = A64_OPID_05203800_dup_SVE_Zd_Rn_SP;
    633       break;
    634     case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX:
    635     case A64_OPID_05202000_mov_SVE_Zd_SVE_VZn:
    636     case A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX:
    637       value = A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX;
    638       break;
    639     case A64_OPID_2538c000_fmov_SVE_Zd_FPIMM0:
    640     case A64_OPID_2538c000_mov_SVE_Zd_SVE_ASIMM:
    641     case A64_OPID_2538c000_dup_SVE_Zd_SVE_ASIMM:
    642       value = A64_OPID_2538c000_dup_SVE_Zd_SVE_ASIMM;
    643       break;
    644     case A64_OPID_05c00000_mov_SVE_Zd_SVE_LIMM_MOV:
    645     case A64_OPID_05c00000_dupm_SVE_Zd_SVE_LIMM:
    646       value = A64_OPID_05c00000_dupm_SVE_Zd_SVE_LIMM;
    647       break;
    648     case A64_OPID_05400000_eon_SVE_Zd_SVE_Zd_SVE_INV_LIMM:
    649     case A64_OPID_05400000_eor_SVE_Zd_SVE_Zd_SVE_LIMM:
    650       value = A64_OPID_05400000_eor_SVE_Zd_SVE_Zd_SVE_LIMM;
    651       break;
    652     case A64_OPID_25004200_not_SVE_Pd_SVE_Pg4_10_SVE_Pn:
    653     case A64_OPID_25004200_eor_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm:
    654       value = A64_OPID_25004200_eor_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm;
    655       break;
    656     case A64_OPID_25404200_nots_SVE_Pd_SVE_Pg4_10_SVE_Pn:
    657     case A64_OPID_25404200_eors_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm:
    658       value = A64_OPID_25404200_eors_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm;
    659       break;
    660     case A64_OPID_6500c010_facle_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    661     case A64_OPID_6500c010_facge_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    662       value = A64_OPID_6500c010_facge_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    663       break;
    664     case A64_OPID_6500e010_faclt_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    665     case A64_OPID_6500e010_facgt_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    666       value = A64_OPID_6500e010_facgt_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    667       break;
    668     case A64_OPID_65004000_fcmle_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    669     case A64_OPID_65004000_fcmge_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    670       value = A64_OPID_65004000_fcmge_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    671       break;
    672     case A64_OPID_65004010_fcmlt_SVE_Pd_SVE_Pg3_SVE_Zm_16_SVE_Zn:
    673     case A64_OPID_65004010_fcmgt_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16:
    674       value = A64_OPID_65004010_fcmgt_SVE_Pd_SVE_Pg3_SVE_Zn_SVE_Zm_16;
    675       break;
    676     case A64_OPID_0510c000_fmov_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8:
    677     case A64_OPID_0510c000_fcpy_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8:
    678       value = A64_OPID_0510c000_fcpy_SVE_Zd_SVE_Pg4_16_SVE_FPIMM8;
    679       break;
    680     case A64_OPID_2539c000_fmov_SVE_Zd_SVE_FPIMM8:
    681     case A64_OPID_2539c000_fdup_SVE_Zd_SVE_FPIMM8:
    682       value = A64_OPID_2539c000_fdup_SVE_Zd_SVE_FPIMM8;
    683       break;
    684     case A64_OPID_85800000_ldr_SVE_PNt_SVE_ADDR_RI_S9xVL:
    685     case A64_OPID_85800000_ldr_SVE_Pt_SVE_ADDR_RI_S9xVL:
    686       value = A64_OPID_85800000_ldr_SVE_Pt_SVE_ADDR_RI_S9xVL;
    687       break;
    688     case A64_OPID_04603000_mov_SVE_Zd_SVE_Zn:
    689     case A64_OPID_04603000_orr_SVE_Zd_SVE_Zn_SVE_Zm_16:
    690       value = A64_OPID_04603000_orr_SVE_Zd_SVE_Zn_SVE_Zm_16;
    691       break;
    692     case A64_OPID_05000000_orn_SVE_Zd_SVE_Zd_SVE_INV_LIMM:
    693     case A64_OPID_05000000_orr_SVE_Zd_SVE_Zd_SVE_LIMM:
    694       value = A64_OPID_05000000_orr_SVE_Zd_SVE_Zd_SVE_LIMM;
    695       break;
    696     case A64_OPID_25804000_mov_SVE_PNd_SVE_PNn:
    697     case A64_OPID_25804000_mov_SVE_Pd_SVE_Pn:
    698     case A64_OPID_25804000_orr_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm:
    699       value = A64_OPID_25804000_orr_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm;
    700       break;
    701     case A64_OPID_25c04000_movs_SVE_Pd_SVE_Pn:
    702     case A64_OPID_25c04000_orrs_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm:
    703       value = A64_OPID_25c04000_orrs_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm;
    704       break;
    705     case A64_OPID_2518e400_pfalse_SVE_PNd:
    706     case A64_OPID_2518e400_pfalse_SVE_Pd:
    707       value = A64_OPID_2518e400_pfalse_SVE_Pd;
    708       break;
    709     case A64_OPID_0520c000_mov_SVE_Zd_SVE_Pg4_10_SVE_Zn:
    710     case A64_OPID_0520c000_sel_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16:
    711       value = A64_OPID_0520c000_sel_SVE_Zd_SVE_Pg4_10_SVE_Zn_SVE_Zm_16;
    712       break;
    713     case A64_OPID_25004210_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn:
    714     case A64_OPID_25004210_sel_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm:
    715       value = A64_OPID_25004210_sel_SVE_Pd_SVE_Pg4_10_SVE_Pn_SVE_Pm;
    716       break;
    717     case A64_OPID_e5800000_str_SVE_PNt_SVE_ADDR_RI_S9xVL:
    718     case A64_OPID_e5800000_str_SVE_Pt_SVE_ADDR_RI_S9xVL:
    719       value = A64_OPID_e5800000_str_SVE_Pt_SVE_ADDR_RI_S9xVL;
    720       break;
    721     case A64_OPID_c0020000_mov_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src:
    722     case A64_OPID_c0020000_mova_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src:
    723       value = A64_OPID_c0020000_mova_SVE_Zd_SVE_Pg3_SME_ZA_HV_idx_src;
    724       break;
    725     case A64_OPID_c0000000_mov_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn:
    726     case A64_OPID_c0000000_mova_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn:
    727       value = A64_OPID_c0000000_mova_SME_ZA_HV_idx_dest_SVE_Pg3_SVE_Zn;
    728       break;
    729     case A64_OPID_25204000_psel_SVE_PNd_SVE_PNg4_10_SME_PnT_Wm_imm:
    730     case A64_OPID_25204000_psel_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm:
    731       value = A64_OPID_25204000_psel_SVE_Pd_SVE_Pg4_10_SME_PnT_Wm_imm;
    732       break;
    733     case A64_OPID_c0060800_mov_SME_Zdnx2_SME_ZA_array_off3_5:
    734     case A64_OPID_c0060800_mova_SME_Zdnx2_SME_ZA_array_off3_5:
    735       value = A64_OPID_c0060800_mova_SME_Zdnx2_SME_ZA_array_off3_5;
    736       break;
    737     case A64_OPID_c0060c00_mov_SME_Zdnx4_SME_ZA_array_off3_5:
    738     case A64_OPID_c0060c00_mova_SME_Zdnx4_SME_ZA_array_off3_5:
    739       value = A64_OPID_c0060c00_mova_SME_Zdnx4_SME_ZA_array_off3_5;
    740       break;
    741     case A64_OPID_c0060000_mov_SME_Zdnx2_SME_ZA_HV_idx_srcxN:
    742     case A64_OPID_c0060000_mova_SME_Zdnx2_SME_ZA_HV_idx_srcxN:
    743       value = A64_OPID_c0060000_mova_SME_Zdnx2_SME_ZA_HV_idx_srcxN;
    744       break;
    745     case A64_OPID_c0060400_mov_SME_Zdnx4_SME_ZA_HV_idx_srcxN:
    746     case A64_OPID_c0060400_mova_SME_Zdnx4_SME_ZA_HV_idx_srcxN:
    747       value = A64_OPID_c0060400_mova_SME_Zdnx4_SME_ZA_HV_idx_srcxN;
    748       break;
    749     case A64_OPID_c0040800_mov_SME_ZA_array_off3_0_SME_Znx2:
    750     case A64_OPID_c0040800_mova_SME_ZA_array_off3_0_SME_Znx2:
    751       value = A64_OPID_c0040800_mova_SME_ZA_array_off3_0_SME_Znx2;
    752       break;
    753     case A64_OPID_c0040c00_mov_SME_ZA_array_off3_0_SME_Znx4:
    754     case A64_OPID_c0040c00_mova_SME_ZA_array_off3_0_SME_Znx4:
    755       value = A64_OPID_c0040c00_mova_SME_ZA_array_off3_0_SME_Znx4;
    756       break;
    757     case A64_OPID_c0040000_mov_SME_ZA_HV_idx_destxN_SME_Znx2:
    758     case A64_OPID_c0040000_mova_SME_ZA_HV_idx_destxN_SME_Znx2:
    759       value = A64_OPID_c0040000_mova_SME_ZA_HV_idx_destxN_SME_Znx2;
    760       break;
    761     case A64_OPID_c0040400_mov_SME_ZA_HV_idx_destxN_SME_Znx4:
    762     case A64_OPID_c0040400_mova_SME_ZA_HV_idx_destxN_SME_Znx4:
    763       value = A64_OPID_c0040400_mova_SME_ZA_HV_idx_destxN_SME_Znx4;
    764       break;
    765     default: return NULL;
    766     }
    767 
    768   return aarch64_opcode_table + value;
    769 }
    770 
    771 bool
    772 aarch64_insert_operand (const aarch64_operand *self,
    773 			   const aarch64_opnd_info *info,
    774 			   aarch64_insn *code, const aarch64_inst *inst,
    775 			   aarch64_operand_error *errors)
    776 {
    777   /* Use the index as the key.  */
    778   enum aarch64_opnd key = self - aarch64_operands;
    779   switch (key)
    780     {
    781     case AARCH64_OPND_Rd:
    782     case AARCH64_OPND_Rn:
    783     case AARCH64_OPND_Rm:
    784     case AARCH64_OPND_Rt:
    785     case AARCH64_OPND_Rt2:
    786     case AARCH64_OPND_Rt_LS64:
    787     case AARCH64_OPND_Rt_SP:
    788     case AARCH64_OPND_Rs:
    789     case AARCH64_OPND_Ra:
    790     case AARCH64_OPND_Rt_SYS:
    791     case AARCH64_OPND_Rd_SP:
    792     case AARCH64_OPND_Rn_SP:
    793     case AARCH64_OPND_Rm_SP:
    794     case AARCH64_OPND_Fd:
    795     case AARCH64_OPND_Fn:
    796     case AARCH64_OPND_Fm:
    797     case AARCH64_OPND_Fa:
    798     case AARCH64_OPND_Ft2:
    799     case AARCH64_OPND_Sd:
    800     case AARCH64_OPND_Sn:
    801     case AARCH64_OPND_Sm:
    802     case AARCH64_OPND_Va:
    803     case AARCH64_OPND_Vd:
    804     case AARCH64_OPND_Vn:
    805     case AARCH64_OPND_Vm:
    806     case AARCH64_OPND_VdD1:
    807     case AARCH64_OPND_VnD1:
    808     case AARCH64_OPND_Rt_IN_SYS_ALIASES:
    809     case AARCH64_OPND_LSE128_Rt:
    810     case AARCH64_OPND_LSE128_Rt2:
    811     case AARCH64_OPND_SVE_Pd:
    812     case AARCH64_OPND_SVE_PNd:
    813     case AARCH64_OPND_SVE_Pg3:
    814     case AARCH64_OPND_SVE_Pg4_5:
    815     case AARCH64_OPND_SVE_Pg4_10:
    816     case AARCH64_OPND_SVE_PNg4_10:
    817     case AARCH64_OPND_SVE_Pg4_16:
    818     case AARCH64_OPND_SVE_Pm:
    819     case AARCH64_OPND_SVE_Pn:
    820     case AARCH64_OPND_SVE_PNn:
    821     case AARCH64_OPND_SVE_Pt:
    822     case AARCH64_OPND_SVE_PNt:
    823     case AARCH64_OPND_SVE_Rm:
    824     case AARCH64_OPND_SVE_Rn_SP:
    825     case AARCH64_OPND_SVE_VZn:
    826     case AARCH64_OPND_SVE_Vd:
    827     case AARCH64_OPND_SVE_Vm:
    828     case AARCH64_OPND_SVE_Vn:
    829     case AARCH64_OPND_SVE_Za_5:
    830     case AARCH64_OPND_SVE_Za_16:
    831     case AARCH64_OPND_SVE_Zd:
    832     case AARCH64_OPND_SVE_Zm_5:
    833     case AARCH64_OPND_SVE_Zm_16:
    834     case AARCH64_OPND_SVE_Zn:
    835     case AARCH64_OPND_SVE_Zt:
    836     case AARCH64_OPND_SME_Zm:
    837     case AARCH64_OPND_SME_Zm_17:
    838     case AARCH64_OPND_SME_Zn_6_3:
    839     case AARCH64_OPND_SME_Zm_17_3:
    840     case AARCH64_OPND_SME_ZAda_1b:
    841     case AARCH64_OPND_SME_ZAda_2b:
    842     case AARCH64_OPND_SME_ZAda_3b:
    843     case AARCH64_OPND_SME_Pm:
    844     case AARCH64_OPND_SME_PNd3:
    845     case AARCH64_OPND_SME_PNg3:
    846     case AARCH64_OPND_SME_PNn:
    847     case AARCH64_OPND_SVE_Zn0_INDEX:
    848     case AARCH64_OPND_SVE_Zd0_INDEX:
    849       return aarch64_ins_regno (self, info, code, inst, errors);
    850     case AARCH64_OPND_X16:
    851     case AARCH64_OPND_BARRIER_PSB:
    852     case AARCH64_OPND_BARRIER_GCSB:
    853     case AARCH64_OPND_SME_ZT0:
    854     case AARCH64_OPND_SME_ZT0_LIST:
    855       return aarch64_ins_none (self, info, code, inst, errors);
    856     case AARCH64_OPND_Rm_EXT:
    857       return aarch64_ins_reg_extended (self, info, code, inst, errors);
    858     case AARCH64_OPND_Rm_SFT:
    859       return aarch64_ins_reg_shifted (self, info, code, inst, errors);
    860     case AARCH64_OPND_Rm_LSL:
    861       return aarch64_ins_reg_lsl_shifted (self, info, code, inst, errors);
    862     case AARCH64_OPND_Ft:
    863       return aarch64_ins_ft (self, info, code, inst, errors);
    864     case AARCH64_OPND_Ed:
    865     case AARCH64_OPND_En:
    866     case AARCH64_OPND_Em:
    867     case AARCH64_OPND_Em16:
    868     case AARCH64_OPND_Em8:
    869     case AARCH64_OPND_SM3_IMM2:
    870       return aarch64_ins_reglane (self, info, code, inst, errors);
    871     case AARCH64_OPND_Em_INDEX1_14:
    872     case AARCH64_OPND_Em_INDEX2_13:
    873     case AARCH64_OPND_Em_INDEX3_12:
    874     case AARCH64_OPND_SVE_Zm1_23_INDEX:
    875     case AARCH64_OPND_SVE_Zm2_22_INDEX:
    876     case AARCH64_OPND_SVE_Zm3_12_INDEX:
    877     case AARCH64_OPND_SME_PNn3_INDEX1:
    878     case AARCH64_OPND_SME_PNn3_INDEX2:
    879     case AARCH64_OPND_SME_Zk_INDEX:
    880     case AARCH64_OPND_SME_Zm_INDEX1:
    881     case AARCH64_OPND_SME_Zm_INDEX2:
    882     case AARCH64_OPND_SME_Zm_INDEX2_3:
    883     case AARCH64_OPND_SME_Zm_INDEX3_1:
    884     case AARCH64_OPND_SME_Zm_INDEX3_2:
    885     case AARCH64_OPND_SME_Zm_INDEX3_3:
    886     case AARCH64_OPND_SME_Zm_INDEX3_10:
    887     case AARCH64_OPND_SME_Zm_INDEX4_1:
    888     case AARCH64_OPND_SME_Zm_INDEX4_2:
    889     case AARCH64_OPND_SME_Zm_INDEX4_3:
    890     case AARCH64_OPND_SME_Zm_INDEX4_10:
    891     case AARCH64_OPND_SME_Zn_INDEX1_16:
    892     case AARCH64_OPND_SME_Zn_INDEX2_15:
    893     case AARCH64_OPND_SME_Zn_INDEX2_16:
    894     case AARCH64_OPND_SME_Zn_INDEX2_19:
    895     case AARCH64_OPND_SME_Zn_INDEX3_14:
    896     case AARCH64_OPND_SME_Zn_INDEX3_15:
    897     case AARCH64_OPND_SME_Zn_INDEX4_14:
    898     case AARCH64_OPND_SVE_Zn1_17_INDEX:
    899     case AARCH64_OPND_SVE_Zn2_18_INDEX:
    900     case AARCH64_OPND_SVE_Zn3_22_INDEX:
    901     case AARCH64_OPND_SVE_Zd1_17_INDEX:
    902     case AARCH64_OPND_SVE_Zd2_18_INDEX:
    903     case AARCH64_OPND_SVE_Zd3_22_INDEX:
    904       return aarch64_ins_simple_index (self, info, code, inst, errors);
    905     case AARCH64_OPND_LVn:
    906       return aarch64_ins_reglist (self, info, code, inst, errors);
    907     case AARCH64_OPND_LVt:
    908       return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
    909     case AARCH64_OPND_LVt_AL:
    910       return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
    911     case AARCH64_OPND_LVn_LUT:
    912       return aarch64_ins_lut_reglist (self, info, code, inst, errors);
    913     case AARCH64_OPND_LEt:
    914       return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
    915     case AARCH64_OPND_CRn:
    916     case AARCH64_OPND_CRm:
    917     case AARCH64_OPND_IDX:
    918     case AARCH64_OPND_MASK:
    919     case AARCH64_OPND_IMMR:
    920     case AARCH64_OPND_IMMS:
    921     case AARCH64_OPND_WIDTH:
    922     case AARCH64_OPND_IMM:
    923     case AARCH64_OPND_IMM_2:
    924     case AARCH64_OPND_IMMP1_2:
    925     case AARCH64_OPND_IMMS1_2:
    926     case AARCH64_OPND_UIMM3_OP1:
    927     case AARCH64_OPND_UIMM3_OP2:
    928     case AARCH64_OPND_UIMM4:
    929     case AARCH64_OPND_UIMM4_ADDG:
    930     case AARCH64_OPND_UIMM7:
    931     case AARCH64_OPND_UIMM10:
    932     case AARCH64_OPND_BIT_NUM:
    933     case AARCH64_OPND_EXCEPTION:
    934     case AARCH64_OPND_UNDEFINED:
    935     case AARCH64_OPND_CCMP_IMM:
    936     case AARCH64_OPND_SIMM5:
    937     case AARCH64_OPND_NOT_BALANCED_10:
    938     case AARCH64_OPND_NOT_BALANCED_17:
    939     case AARCH64_OPND_NZCV:
    940     case AARCH64_OPND_ADDR_PCREL9:
    941     case AARCH64_OPND_ADDR_PCREL14:
    942     case AARCH64_OPND_ADDR_PCREL19:
    943     case AARCH64_OPND_ADDR_PCREL21:
    944     case AARCH64_OPND_ADDR_PCREL26:
    945     case AARCH64_OPND_RPRFMOP:
    946     case AARCH64_OPND_BRBOP:
    947     case AARCH64_OPND_SVE_PATTERN:
    948     case AARCH64_OPND_SVE_PRFOP:
    949     case AARCH64_OPND_SVE_SIMM5:
    950     case AARCH64_OPND_SVE_SIMM5B:
    951     case AARCH64_OPND_SVE_SIMM6:
    952     case AARCH64_OPND_SVE_SIMM8:
    953     case AARCH64_OPND_SVE_UIMM3:
    954     case AARCH64_OPND_SVE_UIMM7:
    955     case AARCH64_OPND_SVE_UIMM8:
    956     case AARCH64_OPND_SVE_UIMM8_53:
    957     case AARCH64_OPND_SVE_UIMM4:
    958     case AARCH64_OPND_SME_list_of_64bit_tiles:
    959     case AARCH64_OPND_SME_VLxN_10:
    960     case AARCH64_OPND_SME_VLxN_13:
    961     case AARCH64_OPND_SME_ZT0_INDEX:
    962     case AARCH64_OPND_SME_ZT0_INDEX_MUL_VL:
    963     case AARCH64_OPND_TME_UIMM16:
    964     case AARCH64_OPND_CSSC_SIMM8:
    965     case AARCH64_OPND_CSSC_UIMM8:
    966       return aarch64_ins_imm (self, info, code, inst, errors);
    967     case AARCH64_OPND_IMM_VLSL:
    968     case AARCH64_OPND_IMM_VLSR:
    969       return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
    970     case AARCH64_OPND_SIMD_IMM:
    971     case AARCH64_OPND_SIMD_IMM_SFT:
    972     case AARCH64_OPND_SIMD_FPIMM:
    973       return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
    974     case AARCH64_OPND_FPIMM:
    975     case AARCH64_OPND_SVE_FPIMM8:
    976       return aarch64_ins_fpimm (self, info, code, inst, errors);
    977     case AARCH64_OPND_LIMM:
    978     case AARCH64_OPND_SVE_LIMM:
    979       return aarch64_ins_limm (self, info, code, inst, errors);
    980     case AARCH64_OPND_AIMM:
    981       return aarch64_ins_aimm (self, info, code, inst, errors);
    982     case AARCH64_OPND_HALF:
    983       return aarch64_ins_imm_half (self, info, code, inst, errors);
    984     case AARCH64_OPND_FBITS:
    985       return aarch64_ins_fbits (self, info, code, inst, errors);
    986     case AARCH64_OPND_IMM_ROT1:
    987     case AARCH64_OPND_IMM_ROT2:
    988     case AARCH64_OPND_SVE_IMM_ROT2:
    989       return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
    990     case AARCH64_OPND_IMM_ROT3:
    991     case AARCH64_OPND_SVE_IMM_ROT1:
    992     case AARCH64_OPND_SVE_IMM_ROT3:
    993       return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
    994     case AARCH64_OPND_COND:
    995     case AARCH64_OPND_COND1:
    996       return aarch64_ins_cond (self, info, code, inst, errors);
    997     case AARCH64_OPND_ADDR_SIMPLE:
    998     case AARCH64_OPND_SIMD_ADDR_SIMPLE:
    999       return aarch64_ins_addr_simple (self, info, code, inst, errors);
   1000     case AARCH64_OPND_ADDR_REGOFF:
   1001       return aarch64_ins_addr_regoff (self, info, code, inst, errors);
   1002     case AARCH64_OPND_ADDR_SIMM7:
   1003     case AARCH64_OPND_ADDR_SIMM9:
   1004     case AARCH64_OPND_ADDR_SIMM9_2:
   1005     case AARCH64_OPND_ADDR_SIMM11:
   1006     case AARCH64_OPND_ADDR_SIMM13:
   1007       return aarch64_ins_addr_simm (self, info, code, inst, errors);
   1008     case AARCH64_OPND_ADDR_SIMM10:
   1009       return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
   1010     case AARCH64_OPND_ADDR_UIMM12:
   1011       return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
   1012     case AARCH64_OPND_ADDR_OFFSET:
   1013       return aarch64_ins_addr_offset (self, info, code, inst, errors);
   1014     case AARCH64_OPND_SIMD_ADDR_POST:
   1015       return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
   1016     case AARCH64_OPND_SYSREG:
   1017     case AARCH64_OPND_SYSREG128:
   1018       return aarch64_ins_sysreg (self, info, code, inst, errors);
   1019     case AARCH64_OPND_PSTATEFIELD:
   1020       return aarch64_ins_pstatefield (self, info, code, inst, errors);
   1021     case AARCH64_OPND_SYSREG_AT:
   1022     case AARCH64_OPND_SYSREG_DC:
   1023     case AARCH64_OPND_SYSREG_IC:
   1024     case AARCH64_OPND_SYSREG_TLBI:
   1025     case AARCH64_OPND_SYSREG_TLBIP:
   1026     case AARCH64_OPND_SYSREG_PLBI:
   1027     case AARCH64_OPND_SYSREG_MLBI:
   1028     case AARCH64_OPND_SYSREG_SR:
   1029     case AARCH64_OPND_GIC:
   1030     case AARCH64_OPND_GICR:
   1031     case AARCH64_OPND_GSB:
   1032       return aarch64_ins_sysins_op (self, info, code, inst, errors);
   1033     case AARCH64_OPND_BARRIER:
   1034     case AARCH64_OPND_BARRIER_ISB:
   1035       return aarch64_ins_barrier (self, info, code, inst, errors);
   1036     case AARCH64_OPND_BARRIER_DSB_NXS:
   1037       return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
   1038     case AARCH64_OPND_PRFOP:
   1039       return aarch64_ins_prfop (self, info, code, inst, errors);
   1040     case AARCH64_OPND_BTI_TARGET:
   1041     case AARCH64_OPND_STSHH_POLICY:
   1042     case AARCH64_OPND_SHUH_PHINT:
   1043       return aarch64_ins_hint (self, info, code, inst, errors);
   1044     case AARCH64_OPND_SVE_ADDR_RI_S4x16:
   1045     case AARCH64_OPND_SVE_ADDR_RI_S4x32:
   1046       return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
   1047     case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
   1048     case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
   1049     case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
   1050     case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
   1051       return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
   1052     case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
   1053       return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
   1054     case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
   1055       return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
   1056     case AARCH64_OPND_SVE_ADDR_RI_U6:
   1057     case AARCH64_OPND_SVE_ADDR_RI_U6x2:
   1058     case AARCH64_OPND_SVE_ADDR_RI_U6x4:
   1059     case AARCH64_OPND_SVE_ADDR_RI_U6x8:
   1060       return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
   1061     case AARCH64_OPND_SVE_ADDR_RR:
   1062     case AARCH64_OPND_SVE_ADDR_RR_LSL1:
   1063     case AARCH64_OPND_SVE_ADDR_RR_LSL2:
   1064     case AARCH64_OPND_SVE_ADDR_RR_LSL3:
   1065     case AARCH64_OPND_SVE_ADDR_RR_LSL4:
   1066     case AARCH64_OPND_SVE_ADDR_RM:
   1067     case AARCH64_OPND_SVE_ADDR_RM_LSL1:
   1068     case AARCH64_OPND_SVE_ADDR_RM_LSL2:
   1069     case AARCH64_OPND_SVE_ADDR_RM_LSL3:
   1070     case AARCH64_OPND_SVE_ADDR_RM_LSL4:
   1071     case AARCH64_OPND_SVE_ADDR_RX:
   1072     case AARCH64_OPND_SVE_ADDR_RX_LSL1:
   1073     case AARCH64_OPND_SVE_ADDR_RX_LSL2:
   1074     case AARCH64_OPND_SVE_ADDR_RX_LSL3:
   1075     case AARCH64_OPND_SVE_ADDR_RX_LSL4:
   1076     case AARCH64_OPND_SVE_ADDR_ZX:
   1077     case AARCH64_OPND_SVE_ADDR_RZ:
   1078     case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
   1079     case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
   1080     case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
   1081       return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
   1082     case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
   1083     case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
   1084     case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
   1085     case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
   1086     case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
   1087     case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
   1088     case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
   1089     case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
   1090       return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
   1091     case AARCH64_OPND_SVE_ADDR_ZI_U5:
   1092     case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
   1093     case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
   1094     case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
   1095       return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
   1096     case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
   1097       return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
   1098     case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
   1099       return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
   1100     case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
   1101       return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
   1102     case AARCH64_OPND_SVE_AIMM:
   1103       return aarch64_ins_sve_aimm (self, info, code, inst, errors);
   1104     case AARCH64_OPND_SVE_ASIMM:
   1105       return aarch64_ins_sve_asimm (self, info, code, inst, errors);
   1106     case AARCH64_OPND_SVE_I1_HALF_ONE:
   1107       return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
   1108     case AARCH64_OPND_SVE_I1_HALF_TWO:
   1109       return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
   1110     case AARCH64_OPND_SVE_I1_ZERO_ONE:
   1111       return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
   1112     case AARCH64_OPND_SVE_INV_LIMM:
   1113       return aarch64_ins_inv_limm (self, info, code, inst, errors);
   1114     case AARCH64_OPND_SVE_LIMM_MOV:
   1115       return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
   1116     case AARCH64_OPND_SVE_PATTERN_SCALED:
   1117       return aarch64_ins_sve_scale (self, info, code, inst, errors);
   1118     case AARCH64_OPND_SVE_SHLIMM_PRED:
   1119     case AARCH64_OPND_SVE_SHLIMM_UNPRED:
   1120     case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
   1121       return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
   1122     case AARCH64_OPND_SVE_SHRIMM_PRED:
   1123     case AARCH64_OPND_SVE_SHRIMM_UNPRED:
   1124     case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
   1125     case AARCH64_OPND_SME_SHRIMM5:
   1126       return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
   1127     case AARCH64_OPND_SME_ZA_array_vrsb_1:
   1128     case AARCH64_OPND_SME_ZA_array_vrsh_1:
   1129     case AARCH64_OPND_SME_ZA_array_vrss_1:
   1130     case AARCH64_OPND_SME_ZA_array_vrsd_1:
   1131       return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
   1132     case AARCH64_OPND_SME_ZA_array_vrsb_2:
   1133     case AARCH64_OPND_SME_ZA_array_vrsh_2:
   1134     case AARCH64_OPND_SME_ZA_array_vrss_2:
   1135     case AARCH64_OPND_SME_ZA_array_vrsd_2:
   1136       return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
   1137     case AARCH64_OPND_SME_ZA_ARRAY4:
   1138       return aarch64_ins_sme_za_tile_to_vec (self, info, code, inst, errors);
   1139     case AARCH64_OPND_SVE_Zm3_INDEX:
   1140     case AARCH64_OPND_SVE_Zm3_11_INDEX:
   1141     case AARCH64_OPND_SVE_Zm3_19_INDEX:
   1142     case AARCH64_OPND_SVE_Zm3_22_INDEX:
   1143     case AARCH64_OPND_SVE_Zm3_10_INDEX:
   1144     case AARCH64_OPND_SVE_Zm4_11_INDEX:
   1145     case AARCH64_OPND_SVE_Zm4_INDEX:
   1146       return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
   1147     case AARCH64_OPND_SVE_Zn_INDEX:
   1148     case AARCH64_OPND_SVE_Zn_5_INDEX:
   1149       return aarch64_ins_sve_index (self, info, code, inst, errors);
   1150     case AARCH64_OPND_SVE_ZnxN:
   1151     case AARCH64_OPND_SVE_ZtxN:
   1152     case AARCH64_OPND_SME_Zn7xN_UNTYPED:
   1153     case AARCH64_OPND_SME_PdxN:
   1154       return aarch64_ins_sve_reglist (self, info, code, inst, errors);
   1155     case AARCH64_OPND_SME_Zdnx2:
   1156     case AARCH64_OPND_SME_Zdnx4:
   1157     case AARCH64_OPND_SME_Znx2_6_3:
   1158     case AARCH64_OPND_SME_Zmx2_17_3:
   1159     case AARCH64_OPND_SME_Zmx2:
   1160     case AARCH64_OPND_SME_Zmx4:
   1161     case AARCH64_OPND_SME_Znx2:
   1162     case AARCH64_OPND_SME_Znx2_BIT_INDEX:
   1163     case AARCH64_OPND_SME_Znx4:
   1164     case AARCH64_OPND_SME_Pdx2:
   1165       return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
   1166     case AARCH64_OPND_SME_Zmx2_INDEX_22:
   1167       return aarch64_ins_sve_reglist_index (self, info, code, inst, errors);
   1168     case AARCH64_OPND_SME_Ztx2_STRIDED:
   1169     case AARCH64_OPND_SME_Ztx4_STRIDED:
   1170       return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
   1171     case AARCH64_OPND_SME_ZA_HV_idx_src:
   1172     case AARCH64_OPND_SME_ZA_HV_idx_dest:
   1173     case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
   1174       return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
   1175     case AARCH64_OPND_SME_ZA_HV_idx_srcxN:
   1176     case AARCH64_OPND_SME_ZA_HV_idx_destxN:
   1177       return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
   1178     case AARCH64_OPND_SME_ZA_array_off1x4:
   1179     case AARCH64_OPND_SME_ZA_array_off2x2:
   1180     case AARCH64_OPND_SME_ZA_array_off2x4:
   1181     case AARCH64_OPND_SME_ZA_array_off3_0:
   1182     case AARCH64_OPND_SME_ZA_array_off3_5:
   1183     case AARCH64_OPND_SME_ZA_array_off3x2:
   1184     case AARCH64_OPND_SME_ZA_array_off4:
   1185       return aarch64_ins_sme_za_array (self, info, code, inst, errors);
   1186     case AARCH64_OPND_SME_ADDR_RI_U4xVL:
   1187       return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
   1188     case AARCH64_OPND_SME_SM_ZA:
   1189       return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
   1190     case AARCH64_OPND_SME_PnT_Wm_imm:
   1191       return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
   1192     case AARCH64_OPND_SME_SHRIMM3:
   1193     case AARCH64_OPND_SME_SHRIMM4:
   1194       return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
   1195     case AARCH64_OPND_MOPS_ADDR_Rd:
   1196     case AARCH64_OPND_MOPS_ADDR_Rs:
   1197     case AARCH64_OPND_MOPS_WB_Rn:
   1198       return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
   1199     case AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND:
   1200     case AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB:
   1201     case AARCH64_OPND_RCPC3_ADDR_POSTIND:
   1202     case AARCH64_OPND_RCPC3_ADDR_PREIND_WB:
   1203       return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
   1204     case AARCH64_OPND_RCPC3_ADDR_OFFSET:
   1205       return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
   1206     default: assert (0); abort ();
   1207     }
   1208 }
   1209