1 ;; Copyright (C) 2011-2022 Free Software Foundation, Inc. 2 ;; 3 ;; This file is part of GCC. 4 ;; 5 ;; GCC is free software; you can redistribute it and/or modify it 6 ;; under the terms of the GNU General Public License as published 7 ;; by the Free Software Foundation; either version 3, or (at your 8 ;; option) any later version. 9 ;; 10 ;; GCC is distributed in the hope that it will be useful, but WITHOUT 11 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 13 ;; License for more details. 14 ;; 15 ;; You should have received a copy of the GNU General Public License 16 ;; along with GCC; see the file COPYING3. If not see 17 ;; <http://www.gnu.org/licenses/>. 18 ;; 19 ;; This file contains ARM instructions that support fixed-point operations. 20 21 (define_insn "add<mode>3" 22 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") 23 (plus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") 24 (match_operand:FIXED 2 "s_register_operand" "l,r")))] 25 "TARGET_32BIT" 26 "add%?\\t%0, %1, %2" 27 [(set_attr "predicable" "yes") 28 (set_attr "predicable_short_it" "yes,no") 29 (set_attr "type" "alu_sreg")]) 30 31 (define_expand "add<mode>3" 32 [(set (match_operand:ADDSUB 0 "s_register_operand") 33 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand") 34 (match_operand:ADDSUB 2 "s_register_operand")))] 35 "TARGET_INT_SIMD" 36 { 37 if (ARM_GE_BITS_READ) 38 FAIL; 39 } 40 ) 41 42 (define_insn "*arm_add<mode>3" 43 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") 44 (plus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r") 45 (match_operand:ADDSUB 2 "s_register_operand" "r")))] 46 "TARGET_INT_SIMD && !ARM_GE_BITS_READ" 47 "sadd<qaddsub_suf>%?\\t%0, %1, %2" 48 [(set_attr "predicable" "yes") 49 (set_attr "type" "alu_dsp_reg")]) 50 51 (define_insn "usadd<mode>3" 52 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") 53 (us_plus:UQADDSUB (match_operand:UQADDSUB 1 "s_register_operand" "r") 54 (match_operand:UQADDSUB 2 "s_register_operand" "r")))] 55 "TARGET_INT_SIMD" 56 "uqadd<qaddsub_suf>%?\\t%0, %1, %2" 57 [(set_attr "predicable" "yes") 58 (set_attr "type" "alu_dsp_reg")]) 59 60 (define_expand "ssadd<mode>3" 61 [(set (match_operand:QADDSUB 0 "s_register_operand") 62 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand") 63 (match_operand:QADDSUB 2 "s_register_operand")))] 64 "TARGET_INT_SIMD" 65 { 66 if (<qaddsub_clob_q>) 67 FAIL; 68 } 69 ) 70 71 (define_insn "*arm_ssadd<mode>3" 72 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") 73 (ss_plus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r") 74 (match_operand:QADDSUB 2 "s_register_operand" "r")))] 75 "TARGET_INT_SIMD && !<qaddsub_clob_q>" 76 "qadd<qaddsub_suf>%?\\t%0, %1, %2" 77 [(set_attr "predicable" "yes") 78 (set_attr "type" "alu_dsp_reg")]) 79 80 (define_insn "sub<mode>3" 81 [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") 82 (minus:FIXED (match_operand:FIXED 1 "s_register_operand" "l,r") 83 (match_operand:FIXED 2 "s_register_operand" "l,r")))] 84 "TARGET_32BIT" 85 "sub%?\\t%0, %1, %2" 86 [(set_attr "predicable" "yes") 87 (set_attr "predicable_short_it" "yes,no") 88 (set_attr "type" "alu_sreg")]) 89 90 (define_expand "sub<mode>3" 91 [(set (match_operand:ADDSUB 0 "s_register_operand") 92 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand") 93 (match_operand:ADDSUB 2 "s_register_operand")))] 94 "TARGET_INT_SIMD" 95 { 96 if (ARM_GE_BITS_READ) 97 FAIL; 98 } 99 ) 100 101 (define_insn "*arm_sub<mode>3" 102 [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") 103 (minus:ADDSUB (match_operand:ADDSUB 1 "s_register_operand" "r") 104 (match_operand:ADDSUB 2 "s_register_operand" "r")))] 105 "TARGET_INT_SIMD && !ARM_GE_BITS_READ" 106 "ssub<qaddsub_suf>%?\\t%0, %1, %2" 107 [(set_attr "predicable" "yes") 108 (set_attr "type" "alu_dsp_reg")]) 109 110 (define_insn "ussub<mode>3" 111 [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") 112 (us_minus:UQADDSUB 113 (match_operand:UQADDSUB 1 "s_register_operand" "r") 114 (match_operand:UQADDSUB 2 "s_register_operand" "r")))] 115 "TARGET_INT_SIMD" 116 "uqsub<qaddsub_suf>%?\\t%0, %1, %2" 117 [(set_attr "predicable" "yes") 118 (set_attr "type" "alu_dsp_reg")]) 119 120 (define_expand "sssub<mode>3" 121 [(set (match_operand:QADDSUB 0 "s_register_operand") 122 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand") 123 (match_operand:QADDSUB 2 "s_register_operand")))] 124 "TARGET_INT_SIMD" 125 { 126 if (<qaddsub_clob_q>) 127 FAIL; 128 } 129 ) 130 131 (define_insn "*arm_sssub<mode>3" 132 [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") 133 (ss_minus:QADDSUB (match_operand:QADDSUB 1 "s_register_operand" "r") 134 (match_operand:QADDSUB 2 "s_register_operand" "r")))] 135 "TARGET_INT_SIMD && !<qaddsub_clob_q>" 136 "qsub<qaddsub_suf>%?\\t%0, %1, %2" 137 [(set_attr "predicable" "yes") 138 (set_attr "type" "alu_dsp_reg")]) 139 140 ;; Fractional multiplies. 141 142 ; Note: none of these do any rounding. 143 144 (define_expand "mulqq3" 145 [(set (match_operand:QQ 0 "s_register_operand") 146 (mult:QQ (match_operand:QQ 1 "s_register_operand") 147 (match_operand:QQ 2 "s_register_operand")))] 148 "TARGET_DSP_MULTIPLY && arm_arch_thumb2" 149 { 150 rtx tmp1 = gen_reg_rtx (HImode); 151 rtx tmp2 = gen_reg_rtx (HImode); 152 rtx tmp3 = gen_reg_rtx (SImode); 153 154 emit_insn (gen_extendqihi2 (tmp1, gen_lowpart (QImode, operands[1]))); 155 emit_insn (gen_extendqihi2 (tmp2, gen_lowpart (QImode, operands[2]))); 156 emit_insn (gen_mulhisi3 (tmp3, tmp1, tmp2)); 157 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp3, GEN_INT (8), 158 GEN_INT (7))); 159 DONE; 160 }) 161 162 (define_expand "mulhq3" 163 [(set (match_operand:HQ 0 "s_register_operand") 164 (mult:HQ (match_operand:HQ 1 "s_register_operand") 165 (match_operand:HQ 2 "s_register_operand")))] 166 "TARGET_DSP_MULTIPLY && arm_arch_thumb2" 167 { 168 rtx tmp = gen_reg_rtx (SImode); 169 170 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), 171 gen_lowpart (HImode, operands[2]))); 172 /* We're doing a s.15 * s.15 multiplication, getting an s.30 result. Extract 173 an s.15 value from that. This won't overflow/saturate for _Fract 174 values. */ 175 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, 176 GEN_INT (16), GEN_INT (15))); 177 DONE; 178 }) 179 180 (define_expand "mulsq3" 181 [(set (match_operand:SQ 0 "s_register_operand") 182 (mult:SQ (match_operand:SQ 1 "s_register_operand") 183 (match_operand:SQ 2 "s_register_operand")))] 184 "TARGET_32BIT" 185 { 186 rtx tmp1 = gen_reg_rtx (DImode); 187 rtx tmp2 = gen_reg_rtx (SImode); 188 rtx tmp3 = gen_reg_rtx (SImode); 189 190 /* s.31 * s.31 -> s.62 multiplication. */ 191 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), 192 gen_lowpart (SImode, operands[2]))); 193 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (31))); 194 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (1))); 195 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3)); 196 197 DONE; 198 }) 199 200 ;; Accumulator multiplies. 201 202 (define_expand "mulsa3" 203 [(set (match_operand:SA 0 "s_register_operand") 204 (mult:SA (match_operand:SA 1 "s_register_operand") 205 (match_operand:SA 2 "s_register_operand")))] 206 "TARGET_32BIT" 207 { 208 rtx tmp1 = gen_reg_rtx (DImode); 209 rtx tmp2 = gen_reg_rtx (SImode); 210 rtx tmp3 = gen_reg_rtx (SImode); 211 212 emit_insn (gen_mulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), 213 gen_lowpart (SImode, operands[2]))); 214 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (15))); 215 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (17))); 216 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3)); 217 218 DONE; 219 }) 220 221 (define_expand "mulusa3" 222 [(set (match_operand:USA 0 "s_register_operand") 223 (mult:USA (match_operand:USA 1 "s_register_operand") 224 (match_operand:USA 2 "s_register_operand")))] 225 "TARGET_32BIT" 226 { 227 rtx tmp1 = gen_reg_rtx (DImode); 228 rtx tmp2 = gen_reg_rtx (SImode); 229 rtx tmp3 = gen_reg_rtx (SImode); 230 231 emit_insn (gen_umulsidi3 (tmp1, gen_lowpart (SImode, operands[1]), 232 gen_lowpart (SImode, operands[2]))); 233 emit_insn (gen_lshrsi3 (tmp2, gen_lowpart (SImode, tmp1), GEN_INT (16))); 234 emit_insn (gen_ashlsi3 (tmp3, gen_highpart (SImode, tmp1), GEN_INT (16))); 235 emit_insn (gen_iorsi3 (gen_lowpart (SImode, operands[0]), tmp2, tmp3)); 236 237 DONE; 238 }) 239 240 ;; The code sequence emitted by this insn pattern uses the Q flag, so we need 241 ;; to bail out when ARM_Q_BIT_READ and resort to a library sequence instead. 242 243 (define_expand "ssmulsa3" 244 [(parallel [(set (match_operand:SA 0 "s_register_operand") 245 (ss_mult:SA (match_operand:SA 1 "s_register_operand") 246 (match_operand:SA 2 "s_register_operand"))) 247 (clobber (match_scratch:DI 3)) 248 (clobber (match_scratch:SI 4)) 249 (clobber (reg:CC CC_REGNUM))])] 250 "TARGET_32BIT && arm_arch6" 251 { 252 if (ARM_Q_BIT_READ) 253 FAIL; 254 } 255 ) 256 257 (define_insn "*arm_ssmulsa3" 258 [(set (match_operand:SA 0 "s_register_operand" "=r") 259 (ss_mult:SA (match_operand:SA 1 "s_register_operand" "r") 260 (match_operand:SA 2 "s_register_operand" "r"))) 261 (clobber (match_scratch:DI 3 "=r")) 262 (clobber (match_scratch:SI 4 "=r")) 263 (clobber (reg:CC CC_REGNUM))] 264 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ" 265 { 266 /* s16.15 * s16.15 -> s32.30. */ 267 output_asm_insn ("smull\\t%Q3, %R3, %1, %2", operands); 268 269 if (TARGET_ARM) 270 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands); 271 else 272 { 273 output_asm_insn ("mov\\t%4, #0", operands); 274 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands); 275 } 276 277 /* We have: 278 31 high word 0 31 low word 0 279 280 [ S i i .... i i i ] [ i f f f ... f f ] 281 | 282 v 283 [ S i ... i f ... f f ] 284 285 Need 16 integral bits, so saturate at 15th bit of high word. */ 286 287 output_asm_insn ("ssat\\t%R3, #15, %R3", operands); 288 output_asm_insn ("mrs\\t%4, APSR", operands); 289 output_asm_insn ("tst\\t%4, #1<<27", operands); 290 if (arm_restrict_it) 291 { 292 output_asm_insn ("mvn\\t%4, %R3, asr #32", operands); 293 output_asm_insn ("it\\tne", operands); 294 output_asm_insn ("movne\\t%Q3, %4", operands); 295 } 296 else 297 { 298 if (TARGET_THUMB2) 299 output_asm_insn ("it\\tne", operands); 300 output_asm_insn ("mvnne\\t%Q3, %R3, asr #32", operands); 301 } 302 output_asm_insn ("mov\\t%0, %Q3, lsr #15", operands); 303 output_asm_insn ("orr\\t%0, %0, %R3, asl #17", operands); 304 return ""; 305 } 306 [(set_attr "conds" "clob") 307 (set_attr "type" "multiple") 308 (set (attr "length") 309 (if_then_else (eq_attr "is_thumb" "yes") 310 (if_then_else (match_test "arm_restrict_it") 311 (const_int 40) 312 (const_int 38)) 313 (const_int 32)))]) 314 315 (define_expand "usmulusa3" 316 [(parallel [(set (match_operand:USA 0 "s_register_operand") 317 (us_mult:USA (match_operand:USA 1 "s_register_operand") 318 (match_operand:USA 2 "s_register_operand"))) 319 (clobber (match_scratch:DI 3)) 320 (clobber (match_scratch:SI 4)) 321 (clobber (reg:CC CC_REGNUM))])] 322 "TARGET_32BIT && arm_arch6" 323 { 324 if (ARM_Q_BIT_READ) 325 FAIL; 326 } 327 ) 328 329 (define_insn "*arm_usmulusa3" 330 [(set (match_operand:USA 0 "s_register_operand" "=r") 331 (us_mult:USA (match_operand:USA 1 "s_register_operand" "r") 332 (match_operand:USA 2 "s_register_operand" "r"))) 333 (clobber (match_scratch:DI 3 "=r")) 334 (clobber (match_scratch:SI 4 "=r")) 335 (clobber (reg:CC CC_REGNUM))] 336 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ" 337 { 338 /* 16.16 * 16.16 -> 32.32. */ 339 output_asm_insn ("umull\\t%Q3, %R3, %1, %2", operands); 340 341 if (TARGET_ARM) 342 output_asm_insn ("msr\\tAPSR_nzcvq, #0", operands); 343 else 344 { 345 output_asm_insn ("mov\\t%4, #0", operands); 346 output_asm_insn ("msr\\tAPSR_nzcvq, %4", operands); 347 } 348 349 /* We have: 350 31 high word 0 31 low word 0 351 352 [ i i i .... i i i ] [ f f f f ... f f ] 353 | 354 v 355 [ i i ... i f ... f f ] 356 357 Need 16 integral bits, so saturate at 16th bit of high word. */ 358 359 output_asm_insn ("usat\\t%R3, #16, %R3", operands); 360 output_asm_insn ("mrs\\t%4, APSR", operands); 361 output_asm_insn ("tst\\t%4, #1<<27", operands); 362 if (arm_restrict_it) 363 { 364 output_asm_insn ("sbfx\\t%4, %R3, #15, #1", operands); 365 output_asm_insn ("it\\tne", operands); 366 output_asm_insn ("movne\\t%Q3, %4", operands); 367 } 368 else 369 { 370 if (TARGET_THUMB2) 371 output_asm_insn ("it\\tne", operands); 372 output_asm_insn ("sbfxne\\t%Q3, %R3, #15, #1", operands); 373 } 374 output_asm_insn ("lsr\\t%0, %Q3, #16", operands); 375 output_asm_insn ("orr\\t%0, %0, %R3, asl #16", operands); 376 return ""; 377 } 378 [(set_attr "conds" "clob") 379 (set_attr "type" "multiple") 380 (set (attr "length") 381 (if_then_else (eq_attr "is_thumb" "yes") 382 (if_then_else (match_test "arm_restrict_it") 383 (const_int 40) 384 (const_int 38)) 385 (const_int 32)))]) 386 387 (define_expand "mulha3" 388 [(set (match_operand:HA 0 "s_register_operand") 389 (mult:HA (match_operand:HA 1 "s_register_operand") 390 (match_operand:HA 2 "s_register_operand")))] 391 "TARGET_DSP_MULTIPLY && arm_arch_thumb2" 392 { 393 rtx tmp = gen_reg_rtx (SImode); 394 395 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), 396 gen_lowpart (HImode, operands[2]))); 397 emit_insn (gen_extv (gen_lowpart (SImode, operands[0]), tmp, GEN_INT (16), 398 GEN_INT (7))); 399 400 DONE; 401 }) 402 403 (define_expand "muluha3" 404 [(set (match_operand:UHA 0 "s_register_operand") 405 (mult:UHA (match_operand:UHA 1 "s_register_operand") 406 (match_operand:UHA 2 "s_register_operand")))] 407 "TARGET_DSP_MULTIPLY" 408 { 409 rtx tmp1 = gen_reg_rtx (SImode); 410 rtx tmp2 = gen_reg_rtx (SImode); 411 rtx tmp3 = gen_reg_rtx (SImode); 412 413 /* 8.8 * 8.8 -> 16.16 multiply. */ 414 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1]))); 415 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2]))); 416 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2)); 417 emit_insn (gen_extzv (gen_lowpart (SImode, operands[0]), tmp3, 418 GEN_INT (16), GEN_INT (8))); 419 420 DONE; 421 }) 422 423 (define_expand "ssmulha3" 424 [(set (match_operand:HA 0 "s_register_operand") 425 (ss_mult:HA (match_operand:HA 1 "s_register_operand") 426 (match_operand:HA 2 "s_register_operand")))] 427 "TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6" 428 { 429 if (ARM_Q_BIT_READ) 430 FAIL; 431 rtx tmp = gen_reg_rtx (SImode); 432 rtx rshift; 433 434 emit_insn (gen_mulhisi3 (tmp, gen_lowpart (HImode, operands[1]), 435 gen_lowpart (HImode, operands[2]))); 436 437 rshift = gen_rtx_ASHIFTRT (SImode, tmp, GEN_INT (7)); 438 439 emit_insn (gen_rtx_SET (gen_lowpart (HImode, operands[0]), 440 gen_rtx_SS_TRUNCATE (HImode, rshift))); 441 442 DONE; 443 }) 444 445 (define_expand "usmuluha3" 446 [(set (match_operand:UHA 0 "s_register_operand") 447 (us_mult:UHA (match_operand:UHA 1 "s_register_operand") 448 (match_operand:UHA 2 "s_register_operand")))] 449 "TARGET_INT_SIMD" 450 { 451 if (ARM_Q_BIT_READ) 452 FAIL; 453 454 rtx tmp1 = gen_reg_rtx (SImode); 455 rtx tmp2 = gen_reg_rtx (SImode); 456 rtx tmp3 = gen_reg_rtx (SImode); 457 rtx rshift_tmp = gen_reg_rtx (SImode); 458 459 /* Note: there's no smul[bt][bt] equivalent for unsigned multiplies. Use a 460 normal 32x32->32-bit multiply instead. */ 461 emit_insn (gen_zero_extendhisi2 (tmp1, gen_lowpart (HImode, operands[1]))); 462 emit_insn (gen_zero_extendhisi2 (tmp2, gen_lowpart (HImode, operands[2]))); 463 464 emit_insn (gen_mulsi3 (tmp3, tmp1, tmp2)); 465 466 /* The operand to "usat" is signed, so we cannot use the "..., asr #8" 467 form of that instruction since the multiplication result TMP3 may have the 468 top bit set, thus be negative and saturate to zero. Use a separate 469 logical right-shift instead. */ 470 emit_insn (gen_lshrsi3 (rshift_tmp, tmp3, GEN_INT (8))); 471 emit_insn (gen_arm_usatsihi (gen_lowpart (HImode, operands[0]), rshift_tmp)); 472 473 DONE; 474 }) 475 476 (define_insn "arm_ssatsihi_shift" 477 [(set (match_operand:HI 0 "s_register_operand" "=r") 478 (ss_truncate:HI (match_operator:SI 1 "sat_shift_operator" 479 [(match_operand:SI 2 "s_register_operand" "r") 480 (match_operand:SI 3 "immediate_operand" "I")])))] 481 "TARGET_32BIT && arm_arch6 && !ARM_Q_BIT_READ" 482 "ssat%?\\t%0, #16, %2%S1" 483 [(set_attr "predicable" "yes") 484 (set_attr "shift" "1") 485 (set_attr "autodetect_type" "alu_shift_operator1")]) 486 487 (define_insn "arm_usatsihi" 488 [(set (match_operand:HI 0 "s_register_operand" "=r") 489 (us_truncate:HI (match_operand:SI 1 "s_register_operand")))] 490 "TARGET_INT_SIMD && !ARM_Q_BIT_READ" 491 "usat%?\\t%0, #16, %1" 492 [(set_attr "predicable" "yes") 493 (set_attr "type" "alu_imm")] 494 ) 495
Indexes created Sat Sep 26 00:25:34 UTC 2026