1 1.1 mrg ; Options for the IA-32 and AMD64 ports of the compiler. 2 1.1 mrg 3 1.14 mrg ; Copyright (C) 2005-2022 Free Software Foundation, Inc. 4 1.1 mrg ; 5 1.1 mrg ; This file is part of GCC. 6 1.1 mrg ; 7 1.1 mrg ; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ; version. 11 1.1 mrg ; 12 1.1 mrg ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ; for more details. 16 1.1 mrg ; 17 1.1 mrg ; You should have received a copy of the GNU General Public License 18 1.1 mrg ; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.3 mrg HeaderInclude 22 1.3 mrg config/i386/i386-opts.h 23 1.3 mrg 24 1.3 mrg ; Bit flags that specify the ISA we are compiling for. 25 1.3 mrg Variable 26 1.3 mrg HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 1.3 mrg 28 1.10 mrg Variable 29 1.10 mrg HOST_WIDE_INT ix86_isa_flags2 = 0 30 1.10 mrg 31 1.3 mrg ; A mask of ix86_isa_flags that includes bit X if X was set or cleared 32 1.3 mrg ; on the command line. 33 1.3 mrg Variable 34 1.3 mrg HOST_WIDE_INT ix86_isa_flags_explicit 35 1.3 mrg 36 1.10 mrg Variable 37 1.10 mrg HOST_WIDE_INT ix86_isa_flags2_explicit 38 1.10 mrg 39 1.10 mrg ; Additional target flags 40 1.10 mrg Variable 41 1.10 mrg int ix86_target_flags 42 1.10 mrg 43 1.3 mrg TargetVariable 44 1.3 mrg int recip_mask = RECIP_MASK_DEFAULT 45 1.3 mrg 46 1.3 mrg Variable 47 1.3 mrg int recip_mask_explicit 48 1.3 mrg 49 1.3 mrg TargetSave 50 1.3 mrg int x_recip_mask_explicit 51 1.3 mrg 52 1.13 mrg ;; A copy of flag_excess_precision as a target variable that should 53 1.13 mrg ;; force a different DECL_FUNCTION_SPECIFIC_TARGET upon 54 1.13 mrg ;; flag_excess_precision changes. 55 1.13 mrg TargetVariable 56 1.13 mrg enum excess_precision ix86_excess_precision = EXCESS_PRECISION_DEFAULT 57 1.13 mrg 58 1.13 mrg ;; Similarly for flag_unsafe_math_optimizations. 59 1.13 mrg TargetVariable 60 1.13 mrg bool ix86_unsafe_math_optimizations = false 61 1.13 mrg 62 1.1 mrg ;; Definitions to add to the cl_target_option structure 63 1.1 mrg ;; -march= processor 64 1.1 mrg TargetSave 65 1.1 mrg unsigned char arch 66 1.1 mrg 67 1.1 mrg ;; -mtune= processor 68 1.1 mrg TargetSave 69 1.1 mrg unsigned char tune 70 1.1 mrg 71 1.5 mrg ;; -march= processor-string 72 1.5 mrg TargetSave 73 1.5 mrg const char *x_ix86_arch_string 74 1.5 mrg 75 1.5 mrg ;; -mtune= processor-string 76 1.5 mrg TargetSave 77 1.5 mrg const char *x_ix86_tune_string 78 1.5 mrg 79 1.1 mrg ;; CPU schedule model 80 1.1 mrg TargetSave 81 1.1 mrg unsigned char schedule 82 1.1 mrg 83 1.5 mrg ;; True if processor has SSE prefetch instruction. 84 1.5 mrg TargetSave 85 1.5 mrg unsigned char prefetch_sse 86 1.5 mrg 87 1.1 mrg ;; branch cost 88 1.1 mrg TargetSave 89 1.1 mrg unsigned char branch_cost 90 1.1 mrg 91 1.1 mrg ;; which flags were passed by the user 92 1.1 mrg TargetSave 93 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags2_explicit 94 1.5 mrg 95 1.5 mrg ;; which flags were passed by the user 96 1.1 mrg TargetSave 97 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags_explicit 98 1.1 mrg 99 1.1 mrg ;; whether -mtune was not specified 100 1.1 mrg TargetSave 101 1.1 mrg unsigned char tune_defaulted 102 1.1 mrg 103 1.1 mrg ;; whether -march was specified 104 1.1 mrg TargetSave 105 1.1 mrg unsigned char arch_specified 106 1.1 mrg 107 1.5 mrg ;; -mcmodel= model 108 1.14 mrg TargetVariable 109 1.14 mrg enum cmodel ix86_cmodel = CM_32 110 1.5 mrg 111 1.5 mrg ;; -mabi= 112 1.14 mrg TargetVariable 113 1.14 mrg enum calling_abi ix86_abi = SYSV_ABI 114 1.5 mrg 115 1.5 mrg ;; -masm= 116 1.5 mrg TargetSave 117 1.5 mrg enum asm_dialect x_ix86_asm_dialect 118 1.5 mrg 119 1.5 mrg ;; -mbranch-cost= 120 1.5 mrg TargetSave 121 1.5 mrg int x_ix86_branch_cost 122 1.5 mrg 123 1.8 mrg ;; -mdump-tune-features= 124 1.5 mrg TargetSave 125 1.5 mrg int x_ix86_dump_tunes 126 1.5 mrg 127 1.5 mrg ;; -mstackrealign= 128 1.5 mrg TargetSave 129 1.5 mrg int x_ix86_force_align_arg_pointer 130 1.5 mrg 131 1.8 mrg ;; -mforce-drap= 132 1.5 mrg TargetSave 133 1.5 mrg int x_ix86_force_drap 134 1.5 mrg 135 1.5 mrg ;; -mincoming-stack-boundary= 136 1.14 mrg TargetVariable 137 1.14 mrg int ix86_incoming_stack_boundary_arg 138 1.5 mrg 139 1.5 mrg ;; -maddress-mode= 140 1.14 mrg TargetVariable 141 1.14 mrg enum pmode ix86_pmode = PMODE_SI 142 1.5 mrg 143 1.8 mrg ;; -mpreferred-stack-boundary= 144 1.14 mrg TargetVariable 145 1.14 mrg int ix86_preferred_stack_boundary_arg 146 1.5 mrg 147 1.5 mrg ;; -mrecip= 148 1.5 mrg TargetSave 149 1.5 mrg const char *x_ix86_recip_name 150 1.5 mrg 151 1.5 mrg ;; -mregparm= 152 1.14 mrg TargetVariable 153 1.14 mrg int ix86_regparm 154 1.5 mrg 155 1.5 mrg ;; -mlarge-data-threshold= 156 1.5 mrg TargetSave 157 1.5 mrg int x_ix86_section_threshold 158 1.5 mrg 159 1.5 mrg ;; -msse2avx= 160 1.5 mrg TargetSave 161 1.5 mrg int x_ix86_sse2avx 162 1.5 mrg 163 1.5 mrg ;; -mstack-protector-guard= 164 1.5 mrg TargetSave 165 1.5 mrg enum stack_protector_guard x_ix86_stack_protector_guard 166 1.5 mrg 167 1.5 mrg ;; -mstringop-strategy= 168 1.5 mrg TargetSave 169 1.5 mrg enum stringop_alg x_ix86_stringop_alg 170 1.5 mrg 171 1.5 mrg ;; -mtls-dialect= 172 1.5 mrg TargetSave 173 1.5 mrg enum tls_dialect x_ix86_tls_dialect 174 1.5 mrg 175 1.5 mrg ;; -mtune-ctrl= 176 1.5 mrg TargetSave 177 1.5 mrg const char *x_ix86_tune_ctrl_string 178 1.5 mrg 179 1.5 mrg ;; -mmemcpy-strategy= 180 1.5 mrg TargetSave 181 1.5 mrg const char *x_ix86_tune_memcpy_strategy 182 1.5 mrg 183 1.5 mrg ;; -mmemset-strategy= 184 1.5 mrg TargetSave 185 1.5 mrg const char *x_ix86_tune_memset_strategy 186 1.5 mrg 187 1.5 mrg ;; -mno-default= 188 1.5 mrg TargetSave 189 1.5 mrg int x_ix86_tune_no_default 190 1.5 mrg 191 1.5 mrg ;; -mveclibabi= 192 1.14 mrg TargetVariable 193 1.14 mrg enum ix86_veclibabi ix86_veclibabi_type = ix86_veclibabi_type_none 194 1.5 mrg 195 1.1 mrg ;; x86 options 196 1.1 mrg m128bit-long-double 197 1.14 mrg Target RejectNegative Mask(128BIT_LONG_DOUBLE) Save 198 1.8 mrg sizeof(long double) is 16. 199 1.1 mrg 200 1.1 mrg m80387 201 1.14 mrg Target Mask(80387) Save 202 1.8 mrg Use hardware fp. 203 1.1 mrg 204 1.1 mrg m96bit-long-double 205 1.14 mrg Target RejectNegative InverseMask(128BIT_LONG_DOUBLE) Save 206 1.8 mrg sizeof(long double) is 12. 207 1.1 mrg 208 1.3 mrg mlong-double-80 209 1.14 mrg Target RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save 210 1.8 mrg Use 80-bit long double. 211 1.3 mrg 212 1.3 mrg mlong-double-64 213 1.14 mrg Target RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save 214 1.8 mrg Use 64-bit long double. 215 1.3 mrg 216 1.5 mrg mlong-double-128 217 1.14 mrg Target RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save 218 1.8 mrg Use 128-bit long double. 219 1.5 mrg 220 1.1 mrg maccumulate-outgoing-args 221 1.14 mrg Target Mask(ACCUMULATE_OUTGOING_ARGS) Save 222 1.8 mrg Reserve space for outgoing arguments in the function prologue. 223 1.1 mrg 224 1.1 mrg malign-double 225 1.14 mrg Target Mask(ALIGN_DOUBLE) Save 226 1.8 mrg Align some doubles on dword boundary. 227 1.1 mrg 228 1.1 mrg malign-functions= 229 1.3 mrg Target RejectNegative Joined UInteger 230 1.8 mrg Function starts are aligned to this power of 2. 231 1.1 mrg 232 1.1 mrg malign-jumps= 233 1.3 mrg Target RejectNegative Joined UInteger 234 1.8 mrg Jump targets are aligned to this power of 2. 235 1.1 mrg 236 1.1 mrg malign-loops= 237 1.3 mrg Target RejectNegative Joined UInteger 238 1.8 mrg Loop code aligned to this power of 2. 239 1.1 mrg 240 1.1 mrg malign-stringops 241 1.14 mrg Target RejectNegative InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 242 1.8 mrg Align destination of the string operations. 243 1.1 mrg 244 1.5 mrg malign-data= 245 1.5 mrg Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) 246 1.8 mrg Use the given data alignment. 247 1.5 mrg 248 1.5 mrg Enum 249 1.5 mrg Name(ix86_align_data) Type(enum ix86_align_data) 250 1.5 mrg Known data alignment choices (for use with the -malign-data= option): 251 1.5 mrg 252 1.5 mrg EnumValue 253 1.5 mrg Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat) 254 1.5 mrg 255 1.5 mrg EnumValue 256 1.5 mrg Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi) 257 1.5 mrg 258 1.5 mrg EnumValue 259 1.5 mrg Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) 260 1.5 mrg 261 1.1 mrg march= 262 1.12 mrg Target RejectNegative Negative(march=) Joined Var(ix86_arch_string) 263 1.8 mrg Generate code for given CPU. 264 1.1 mrg 265 1.1 mrg masm= 266 1.3 mrg Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 267 1.8 mrg Use given assembler dialect. 268 1.1 mrg 269 1.3 mrg Enum 270 1.3 mrg Name(asm_dialect) Type(enum asm_dialect) 271 1.10 mrg Known assembler dialects (for use with the -masm= option): 272 1.3 mrg 273 1.3 mrg EnumValue 274 1.3 mrg Enum(asm_dialect) String(intel) Value(ASM_INTEL) 275 1.3 mrg 276 1.3 mrg EnumValue 277 1.3 mrg Enum(asm_dialect) String(att) Value(ASM_ATT) 278 1.3 mrg 279 1.1 mrg mbranch-cost= 280 1.11 mrg Target RejectNegative Joined UInteger Var(ix86_branch_cost) IntegerRange(0, 5) 281 1.11 mrg Branches are this expensive (arbitrary units). 282 1.1 mrg 283 1.1 mrg mlarge-data-threshold= 284 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 285 1.10 mrg -mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model. 286 1.1 mrg 287 1.1 mrg mcmodel= 288 1.3 mrg Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 289 1.8 mrg Use given x86-64 code model. 290 1.1 mrg 291 1.3 mrg Enum 292 1.3 mrg Name(cmodel) Type(enum cmodel) 293 1.3 mrg Known code models (for use with the -mcmodel= option): 294 1.3 mrg 295 1.3 mrg EnumValue 296 1.3 mrg Enum(cmodel) String(small) Value(CM_SMALL) 297 1.3 mrg 298 1.3 mrg EnumValue 299 1.3 mrg Enum(cmodel) String(medium) Value(CM_MEDIUM) 300 1.3 mrg 301 1.3 mrg EnumValue 302 1.3 mrg Enum(cmodel) String(large) Value(CM_LARGE) 303 1.3 mrg 304 1.3 mrg EnumValue 305 1.3 mrg Enum(cmodel) String(32) Value(CM_32) 306 1.3 mrg 307 1.3 mrg EnumValue 308 1.3 mrg Enum(cmodel) String(kernel) Value(CM_KERNEL) 309 1.3 mrg 310 1.3 mrg maddress-mode= 311 1.3 mrg Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 312 1.8 mrg Use given address mode. 313 1.3 mrg 314 1.3 mrg Enum 315 1.3 mrg Name(pmode) Type(enum pmode) 316 1.3 mrg Known address mode (for use with the -maddress-mode= option): 317 1.3 mrg 318 1.3 mrg EnumValue 319 1.3 mrg Enum(pmode) String(short) Value(PMODE_SI) 320 1.3 mrg 321 1.3 mrg EnumValue 322 1.3 mrg Enum(pmode) String(long) Value(PMODE_DI) 323 1.3 mrg 324 1.3 mrg mcpu= 325 1.3 mrg Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 326 1.3 mrg 327 1.1 mrg mfancy-math-387 328 1.14 mrg Target RejectNegative InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 329 1.8 mrg Generate sin, cos, sqrt for FPU. 330 1.1 mrg 331 1.1 mrg mforce-drap 332 1.14 mrg Target Var(ix86_force_drap) 333 1.8 mrg Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. 334 1.1 mrg 335 1.1 mrg mfp-ret-in-387 336 1.14 mrg Target Mask(FLOAT_RETURNS) Save 337 1.8 mrg Return values of functions in FPU registers. 338 1.1 mrg 339 1.1 mrg mfpmath= 340 1.3 mrg Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 341 1.8 mrg Generate floating point mathematics using given instruction set. 342 1.1 mrg 343 1.3 mrg Enum 344 1.3 mrg Name(fpmath_unit) Type(enum fpmath_unit) 345 1.3 mrg Valid arguments to -mfpmath=: 346 1.3 mrg 347 1.3 mrg EnumValue 348 1.3 mrg Enum(fpmath_unit) String(387) Value(FPMATH_387) 349 1.3 mrg 350 1.3 mrg EnumValue 351 1.3 mrg Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 352 1.3 mrg 353 1.3 mrg EnumValue 354 1.3 mrg Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 355 1.3 mrg 356 1.3 mrg EnumValue 357 1.3 mrg Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 358 1.3 mrg 359 1.3 mrg EnumValue 360 1.3 mrg Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 361 1.3 mrg 362 1.3 mrg EnumValue 363 1.3 mrg Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 364 1.3 mrg 365 1.3 mrg EnumValue 366 1.3 mrg Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 367 1.3 mrg 368 1.1 mrg mhard-float 369 1.3 mrg Target RejectNegative Mask(80387) Save 370 1.8 mrg Use hardware fp. 371 1.1 mrg 372 1.1 mrg mieee-fp 373 1.14 mrg Target Mask(IEEE_FP) Save 374 1.8 mrg Use IEEE math for fp comparisons. 375 1.1 mrg 376 1.1 mrg minline-all-stringops 377 1.14 mrg Target Mask(INLINE_ALL_STRINGOPS) Save 378 1.8 mrg Inline all known string operations. 379 1.1 mrg 380 1.1 mrg minline-stringops-dynamically 381 1.14 mrg Target Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 382 1.8 mrg Inline memset/memcpy string operations, but perform inline version only for small blocks. 383 1.1 mrg 384 1.1 mrg mintel-syntax 385 1.3 mrg Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 386 1.1 mrg 387 1.1 mrg mms-bitfields 388 1.14 mrg Target Mask(MS_BITFIELD_LAYOUT) Save 389 1.8 mrg Use native (MS) bitfield layout. 390 1.1 mrg 391 1.1 mrg mno-align-stringops 392 1.14 mrg Target RejectNegative Mask(NO_ALIGN_STRINGOPS) Undocumented Save 393 1.1 mrg 394 1.1 mrg mno-fancy-math-387 395 1.14 mrg Target RejectNegative Mask(NO_FANCY_MATH_387) Undocumented Save 396 1.1 mrg 397 1.1 mrg mno-push-args 398 1.14 mrg Target RejectNegative Mask(NO_PUSH_ARGS) Undocumented Save 399 1.1 mrg 400 1.1 mrg mno-red-zone 401 1.14 mrg Target RejectNegative Mask(NO_RED_ZONE) Undocumented Save 402 1.1 mrg 403 1.1 mrg momit-leaf-frame-pointer 404 1.14 mrg Target Mask(OMIT_LEAF_FRAME_POINTER) Save 405 1.8 mrg Omit the frame pointer in leaf functions. 406 1.1 mrg 407 1.14 mrg mrelax-cmpxchg-loop 408 1.14 mrg Target Mask(RELAX_CMPXCHG_LOOP) Save 409 1.14 mrg Relax cmpxchg loop for atomic_fetch_{or,xor,and,nand} by adding load and cmp before cmpxchg, execute pause and loop back to load and compare if load value is not expected. 410 1.14 mrg 411 1.3 mrg mpc32 412 1.14 mrg Target RejectNegative 413 1.8 mrg Set 80387 floating-point precision to 32-bit. 414 1.3 mrg 415 1.3 mrg mpc64 416 1.14 mrg Target RejectNegative 417 1.8 mrg Set 80387 floating-point precision to 64-bit. 418 1.3 mrg 419 1.3 mrg mpc80 420 1.14 mrg Target RejectNegative 421 1.8 mrg Set 80387 floating-point precision to 80-bit. 422 1.1 mrg 423 1.14 mrg mdaz-ftz 424 1.14 mrg Target 425 1.14 mrg Set the FTZ and DAZ Flags. 426 1.14 mrg 427 1.1 mrg mpreferred-stack-boundary= 428 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 429 1.8 mrg Attempt to keep stack aligned to this power of 2. 430 1.1 mrg 431 1.1 mrg mincoming-stack-boundary= 432 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 433 1.8 mrg Assume incoming stack aligned to this power of 2. 434 1.1 mrg 435 1.1 mrg mpush-args 436 1.14 mrg Target InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 437 1.8 mrg Use push instructions to save outgoing arguments. 438 1.1 mrg 439 1.1 mrg mred-zone 440 1.14 mrg Target RejectNegative InverseMask(NO_RED_ZONE, RED_ZONE) Save 441 1.8 mrg Use red-zone in the x86-64 code. 442 1.1 mrg 443 1.1 mrg mregparm= 444 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_regparm) 445 1.8 mrg Number of registers used to pass integer arguments. 446 1.1 mrg 447 1.1 mrg mrtd 448 1.14 mrg Target Mask(RTD) Save 449 1.8 mrg Alternate calling convention. 450 1.1 mrg 451 1.1 mrg msoft-float 452 1.1 mrg Target InverseMask(80387) Save 453 1.8 mrg Do not use hardware fp. 454 1.1 mrg 455 1.1 mrg msseregparm 456 1.1 mrg Target RejectNegative Mask(SSEREGPARM) Save 457 1.8 mrg Use SSE register passing conventions for SF and DF mode. 458 1.1 mrg 459 1.1 mrg mstackrealign 460 1.14 mrg Target Var(ix86_force_align_arg_pointer) 461 1.8 mrg Realign stack in prologue. 462 1.1 mrg 463 1.1 mrg mstack-arg-probe 464 1.14 mrg Target Mask(STACK_PROBE) Save 465 1.8 mrg Enable stack probing. 466 1.1 mrg 467 1.5 mrg mmemcpy-strategy= 468 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) 469 1.8 mrg Specify memcpy expansion strategy when expected size is known. 470 1.5 mrg 471 1.5 mrg mmemset-strategy= 472 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memset_strategy) 473 1.8 mrg Specify memset expansion strategy when expected size is known. 474 1.5 mrg 475 1.1 mrg mstringop-strategy= 476 1.3 mrg Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 477 1.8 mrg Chose strategy to generate stringop using. 478 1.1 mrg 479 1.3 mrg Enum 480 1.3 mrg Name(stringop_alg) Type(enum stringop_alg) 481 1.3 mrg Valid arguments to -mstringop-strategy=: 482 1.3 mrg 483 1.3 mrg EnumValue 484 1.3 mrg Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 485 1.3 mrg 486 1.3 mrg EnumValue 487 1.3 mrg Enum(stringop_alg) String(libcall) Value(libcall) 488 1.3 mrg 489 1.3 mrg EnumValue 490 1.3 mrg Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 491 1.3 mrg 492 1.3 mrg EnumValue 493 1.3 mrg Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 494 1.3 mrg 495 1.3 mrg EnumValue 496 1.3 mrg Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 497 1.3 mrg 498 1.3 mrg EnumValue 499 1.3 mrg Enum(stringop_alg) String(loop) Value(loop) 500 1.3 mrg 501 1.3 mrg EnumValue 502 1.3 mrg Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 503 1.3 mrg 504 1.5 mrg EnumValue 505 1.5 mrg Enum(stringop_alg) String(vector_loop) Value(vector_loop) 506 1.5 mrg 507 1.1 mrg mtls-dialect= 508 1.3 mrg Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 509 1.8 mrg Use given thread-local storage dialect. 510 1.1 mrg 511 1.3 mrg Enum 512 1.3 mrg Name(tls_dialect) Type(enum tls_dialect) 513 1.3 mrg Known TLS dialects (for use with the -mtls-dialect= option): 514 1.3 mrg 515 1.3 mrg EnumValue 516 1.3 mrg Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 517 1.3 mrg 518 1.3 mrg EnumValue 519 1.3 mrg Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 520 1.3 mrg 521 1.1 mrg mtls-direct-seg-refs 522 1.14 mrg Target Mask(TLS_DIRECT_SEG_REFS) 523 1.8 mrg Use direct references against %gs when accessing tls data. 524 1.1 mrg 525 1.1 mrg mtune= 526 1.12 mrg Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string) 527 1.8 mrg Schedule code for given CPU. 528 1.1 mrg 529 1.5 mrg mtune-ctrl= 530 1.5 mrg Target RejectNegative Joined Var(ix86_tune_ctrl_string) 531 1.8 mrg Fine grain control of tune features. 532 1.5 mrg 533 1.5 mrg mno-default 534 1.11 mrg Target RejectNegative Var(ix86_tune_no_default) 535 1.8 mrg Clear all tune features. 536 1.5 mrg 537 1.5 mrg mdump-tune-features 538 1.11 mrg Target RejectNegative Var(ix86_dump_tunes) 539 1.5 mrg 540 1.8 mrg miamcu 541 1.14 mrg Target Mask(IAMCU) 542 1.8 mrg Generate code that conforms to Intel MCU psABI. 543 1.8 mrg 544 1.1 mrg mabi= 545 1.3 mrg Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 546 1.8 mrg Generate code that conforms to the given ABI. 547 1.1 mrg 548 1.3 mrg Enum 549 1.3 mrg Name(calling_abi) Type(enum calling_abi) 550 1.3 mrg Known ABIs (for use with the -mabi= option): 551 1.3 mrg 552 1.3 mrg EnumValue 553 1.3 mrg Enum(calling_abi) String(sysv) Value(SYSV_ABI) 554 1.3 mrg 555 1.3 mrg EnumValue 556 1.3 mrg Enum(calling_abi) String(ms) Value(MS_ABI) 557 1.3 mrg 558 1.11 mrg mcall-ms2sysv-xlogues 559 1.14 mrg Target Mask(CALL_MS2SYSV_XLOGUES) Save 560 1.11 mrg Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls. 561 1.11 mrg 562 1.1 mrg mveclibabi= 563 1.3 mrg Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 564 1.8 mrg Vector library ABI to use. 565 1.1 mrg 566 1.3 mrg Enum 567 1.3 mrg Name(ix86_veclibabi) Type(enum ix86_veclibabi) 568 1.3 mrg Known vectorization library ABIs (for use with the -mveclibabi= option): 569 1.3 mrg 570 1.3 mrg EnumValue 571 1.3 mrg Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 572 1.3 mrg 573 1.3 mrg EnumValue 574 1.3 mrg Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 575 1.3 mrg 576 1.3 mrg mvect8-ret-in-mem 577 1.14 mrg Target Mask(VECT8_RETURNS) Save 578 1.8 mrg Return 8-byte vectors in memory. 579 1.3 mrg 580 1.1 mrg mrecip 581 1.14 mrg Target Mask(RECIP) Save 582 1.1 mrg Generate reciprocals instead of divss and sqrtss. 583 1.1 mrg 584 1.3 mrg mrecip= 585 1.14 mrg Target RejectNegative Joined Var(ix86_recip_name) 586 1.3 mrg Control generation of reciprocal estimates. 587 1.3 mrg 588 1.1 mrg mcld 589 1.14 mrg Target Mask(CLD) Save 590 1.1 mrg Generate cld instruction in the function prologue. 591 1.1 mrg 592 1.3 mrg mvzeroupper 593 1.14 mrg Target Mask(VZEROUPPER) Save 594 1.3 mrg Generate vzeroupper instruction before a transfer of control flow out of 595 1.3 mrg the function. 596 1.3 mrg 597 1.8 mrg mstv 598 1.14 mrg Target Mask(STV) Save 599 1.8 mrg Disable Scalar to Vector optimization pass transforming 64-bit integer 600 1.8 mrg computations into a vector ones. 601 1.8 mrg 602 1.3 mrg mdispatch-scheduler 603 1.3 mrg Target RejectNegative Var(flag_dispatch_scheduler) 604 1.8 mrg Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4 605 1.8 mrg or znver1 and Haifa scheduling is selected. 606 1.3 mrg 607 1.3 mrg mprefer-avx128 608 1.11 mrg Target Alias(mprefer-vector-width=, 128, 256) 609 1.3 mrg Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 610 1.1 mrg 611 1.11 mrg mprefer-vector-width= 612 1.14 mrg Target RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save 613 1.11 mrg Use given register vector width instructions instead of maximum register width in the auto-vectorizer. 614 1.11 mrg 615 1.11 mrg Enum 616 1.11 mrg Name(prefer_vector_width) Type(enum prefer_vector_width) 617 1.12 mrg Known preferred register vector length (to use with the -mprefer-vector-width= option): 618 1.11 mrg 619 1.11 mrg EnumValue 620 1.11 mrg Enum(prefer_vector_width) String(none) Value(PVW_NONE) 621 1.11 mrg 622 1.11 mrg EnumValue 623 1.11 mrg Enum(prefer_vector_width) String(128) Value(PVW_AVX128) 624 1.11 mrg 625 1.11 mrg EnumValue 626 1.11 mrg Enum(prefer_vector_width) String(256) Value(PVW_AVX256) 627 1.11 mrg 628 1.11 mrg EnumValue 629 1.11 mrg Enum(prefer_vector_width) String(512) Value(PVW_AVX512) 630 1.11 mrg 631 1.14 mrg mmove-max= 632 1.14 mrg Target RejectNegative Joined Var(ix86_move_max) Enum(prefer_vector_width) Init(PVW_NONE) Save 633 1.14 mrg Maximum number of bits that can be moved from memory to memory efficiently. 634 1.14 mrg 635 1.14 mrg mstore-max= 636 1.14 mrg Target RejectNegative Joined Var(ix86_store_max) Enum(prefer_vector_width) Init(PVW_NONE) Save 637 1.14 mrg Maximum number of bits that can be stored to memory efficiently. 638 1.14 mrg 639 1.1 mrg ;; ISA support 640 1.1 mrg 641 1.1 mrg m32 642 1.14 mrg Target RejectNegative Negative(m64) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 643 1.8 mrg Generate 32bit i386 code. 644 1.1 mrg 645 1.1 mrg m64 646 1.14 mrg Target RejectNegative Negative(mx32) Mask(ABI_64) Var(ix86_isa_flags) Save 647 1.8 mrg Generate 64bit x86-64 code. 648 1.1 mrg 649 1.3 mrg mx32 650 1.14 mrg Target RejectNegative Negative(m16) Mask(ABI_X32) Var(ix86_isa_flags) Save 651 1.8 mrg Generate 32bit x86-64 code. 652 1.3 mrg 653 1.5 mrg m16 654 1.14 mrg Target RejectNegative Negative(m32) Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 655 1.8 mrg Generate 16bit i386 code. 656 1.5 mrg 657 1.1 mrg mmmx 658 1.14 mrg Target Mask(ISA_MMX) Var(ix86_isa_flags) Save 659 1.8 mrg Support MMX built-in functions. 660 1.1 mrg 661 1.1 mrg m3dnow 662 1.14 mrg Target Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 663 1.8 mrg Support 3DNow! built-in functions. 664 1.1 mrg 665 1.1 mrg m3dnowa 666 1.14 mrg Target Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 667 1.8 mrg Support Athlon 3Dnow! built-in functions. 668 1.1 mrg 669 1.1 mrg msse 670 1.14 mrg Target Mask(ISA_SSE) Var(ix86_isa_flags) Save 671 1.8 mrg Support MMX and SSE built-in functions and code generation. 672 1.1 mrg 673 1.1 mrg msse2 674 1.14 mrg Target Mask(ISA_SSE2) Var(ix86_isa_flags) Save 675 1.8 mrg Support MMX, SSE and SSE2 built-in functions and code generation. 676 1.1 mrg 677 1.1 mrg msse3 678 1.14 mrg Target Mask(ISA_SSE3) Var(ix86_isa_flags) Save 679 1.8 mrg Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. 680 1.1 mrg 681 1.1 mrg mssse3 682 1.14 mrg Target Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 683 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. 684 1.1 mrg 685 1.1 mrg msse4.1 686 1.14 mrg Target Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 687 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. 688 1.1 mrg 689 1.1 mrg msse4.2 690 1.14 mrg Target Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 691 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 692 1.1 mrg 693 1.1 mrg msse4 694 1.14 mrg Target RejectNegative Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 695 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 696 1.1 mrg 697 1.1 mrg mno-sse4 698 1.14 mrg Target RejectNegative InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 699 1.8 mrg Do not support SSE4.1 and SSE4.2 built-in functions and code generation. 700 1.1 mrg 701 1.3 mrg msse5 702 1.3 mrg Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 703 1.3 mrg ;; Deprecated 704 1.3 mrg 705 1.1 mrg mavx 706 1.14 mrg Target Mask(ISA_AVX) Var(ix86_isa_flags) Save 707 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. 708 1.1 mrg 709 1.3 mrg mavx2 710 1.14 mrg Target Mask(ISA_AVX2) Var(ix86_isa_flags) Save 711 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. 712 1.3 mrg 713 1.5 mrg mavx512f 714 1.14 mrg Target Mask(ISA_AVX512F) Var(ix86_isa_flags) Save 715 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. 716 1.5 mrg 717 1.5 mrg mavx512pf 718 1.14 mrg Target Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save 719 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. 720 1.5 mrg 721 1.5 mrg mavx512er 722 1.14 mrg Target Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save 723 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. 724 1.5 mrg 725 1.5 mrg mavx512cd 726 1.14 mrg Target Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save 727 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. 728 1.5 mrg 729 1.5 mrg mavx512dq 730 1.14 mrg Target Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save 731 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. 732 1.5 mrg 733 1.5 mrg mavx512bw 734 1.14 mrg Target Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save 735 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. 736 1.5 mrg 737 1.5 mrg mavx512vl 738 1.14 mrg Target Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save 739 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. 740 1.5 mrg 741 1.5 mrg mavx512ifma 742 1.14 mrg Target Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save 743 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. 744 1.5 mrg 745 1.5 mrg mavx512vbmi 746 1.14 mrg Target Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save 747 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. 748 1.5 mrg 749 1.10 mrg mavx5124fmaps 750 1.14 mrg Target Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save 751 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. 752 1.10 mrg 753 1.10 mrg mavx5124vnniw 754 1.14 mrg Target Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save 755 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. 756 1.10 mrg 757 1.10 mrg mavx512vpopcntdq 758 1.14 mrg Target Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save 759 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation. 760 1.10 mrg 761 1.11 mrg mavx512vbmi2 762 1.14 mrg Target Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save 763 1.11 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation. 764 1.11 mrg 765 1.11 mrg mavx512vnni 766 1.14 mrg Target Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save 767 1.11 mrg Support AVX512VNNI built-in functions and code generation. 768 1.11 mrg 769 1.11 mrg mavx512bitalg 770 1.14 mrg Target Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save 771 1.11 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation. 772 1.11 mrg 773 1.13 mrg mavx512vp2intersect 774 1.14 mrg Target Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save 775 1.13 mrg Support AVX512VP2INTERSECT built-in functions and code generation. 776 1.13 mrg 777 1.1 mrg mfma 778 1.14 mrg Target Mask(ISA_FMA) Var(ix86_isa_flags) Save 779 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. 780 1.1 mrg 781 1.1 mrg msse4a 782 1.14 mrg Target Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 783 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. 784 1.1 mrg 785 1.1 mrg mfma4 786 1.14 mrg Target Mask(ISA_FMA4) Var(ix86_isa_flags) Save 787 1.8 mrg Support FMA4 built-in functions and code generation. 788 1.1 mrg 789 1.1 mrg mxop 790 1.14 mrg Target Mask(ISA_XOP) Var(ix86_isa_flags) Save 791 1.8 mrg Support XOP built-in functions and code generation. 792 1.1 mrg 793 1.1 mrg mlwp 794 1.14 mrg Target Mask(ISA_LWP) Var(ix86_isa_flags) Save 795 1.8 mrg Support LWP built-in functions and code generation. 796 1.1 mrg 797 1.1 mrg mabm 798 1.14 mrg Target Mask(ISA_ABM) Var(ix86_isa_flags) Save 799 1.1 mrg Support code generation of Advanced Bit Manipulation (ABM) instructions. 800 1.1 mrg 801 1.1 mrg mpopcnt 802 1.14 mrg Target Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 803 1.1 mrg Support code generation of popcnt instruction. 804 1.1 mrg 805 1.11 mrg mpconfig 806 1.14 mrg Target Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save 807 1.11 mrg Support PCONFIG built-in functions and code generation. 808 1.11 mrg 809 1.11 mrg mwbnoinvd 810 1.14 mrg Target Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save 811 1.11 mrg Support WBNOINVD built-in functions and code generation. 812 1.11 mrg 813 1.12 mrg mptwrite 814 1.14 mrg Target Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save 815 1.12 mrg Support PTWRITE built-in functions and code generation. 816 1.12 mrg 817 1.14 mrg muintr 818 1.14 mrg Target Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save 819 1.14 mrg Support UINTR built-in functions and code generation. 820 1.14 mrg 821 1.10 mrg msgx 822 1.14 mrg Target Mask(ISA2_SGX) Var(ix86_isa_flags2) Save 823 1.10 mrg Support SGX built-in functions and code generation. 824 1.10 mrg 825 1.10 mrg mrdpid 826 1.14 mrg Target Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save 827 1.10 mrg Support RDPID built-in functions and code generation. 828 1.10 mrg 829 1.11 mrg mgfni 830 1.14 mrg Target Mask(ISA_GFNI) Var(ix86_isa_flags) Save 831 1.11 mrg Support GFNI built-in functions and code generation. 832 1.11 mrg 833 1.11 mrg mvaes 834 1.14 mrg Target Mask(ISA2_VAES) Var(ix86_isa_flags2) Save 835 1.11 mrg Support VAES built-in functions and code generation. 836 1.11 mrg 837 1.11 mrg mvpclmulqdq 838 1.14 mrg Target Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save 839 1.11 mrg Support VPCLMULQDQ built-in functions and code generation. 840 1.11 mrg 841 1.3 mrg mbmi 842 1.14 mrg Target Mask(ISA_BMI) Var(ix86_isa_flags) Save 843 1.8 mrg Support BMI built-in functions and code generation. 844 1.3 mrg 845 1.3 mrg mbmi2 846 1.14 mrg Target Mask(ISA_BMI2) Var(ix86_isa_flags) Save 847 1.8 mrg Support BMI2 built-in functions and code generation. 848 1.3 mrg 849 1.3 mrg mlzcnt 850 1.14 mrg Target Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 851 1.8 mrg Support LZCNT built-in function and code generation. 852 1.3 mrg 853 1.3 mrg mhle 854 1.14 mrg Target Mask(ISA2_HLE) Var(ix86_isa_flags2) Save 855 1.8 mrg Support Hardware Lock Elision prefixes. 856 1.3 mrg 857 1.3 mrg mrdseed 858 1.14 mrg Target Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 859 1.8 mrg Support RDSEED instruction. 860 1.3 mrg 861 1.3 mrg mprfchw 862 1.14 mrg Target Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 863 1.8 mrg Support PREFETCHW instruction. 864 1.3 mrg 865 1.3 mrg madx 866 1.14 mrg Target Mask(ISA_ADX) Var(ix86_isa_flags) Save 867 1.8 mrg Support flag-preserving add-carry instructions. 868 1.3 mrg 869 1.5 mrg mclflushopt 870 1.14 mrg Target Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save 871 1.8 mrg Support CLFLUSHOPT instructions. 872 1.5 mrg 873 1.5 mrg mclwb 874 1.14 mrg Target Mask(ISA_CLWB) Var(ix86_isa_flags) Save 875 1.8 mrg Support CLWB instruction. 876 1.5 mrg 877 1.5 mrg mpcommit 878 1.13 mrg Target WarnRemoved 879 1.5 mrg 880 1.3 mrg mfxsr 881 1.14 mrg Target Mask(ISA_FXSR) Var(ix86_isa_flags) Save 882 1.8 mrg Support FXSAVE and FXRSTOR instructions. 883 1.3 mrg 884 1.3 mrg mxsave 885 1.14 mrg Target Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 886 1.8 mrg Support XSAVE and XRSTOR instructions. 887 1.3 mrg 888 1.3 mrg mxsaveopt 889 1.14 mrg Target Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 890 1.8 mrg Support XSAVEOPT instruction. 891 1.3 mrg 892 1.5 mrg mxsavec 893 1.14 mrg Target Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save 894 1.8 mrg Support XSAVEC instructions. 895 1.5 mrg 896 1.5 mrg mxsaves 897 1.14 mrg Target Mask(ISA_XSAVES) Var(ix86_isa_flags) Save 898 1.8 mrg Support XSAVES and XRSTORS instructions. 899 1.5 mrg 900 1.3 mrg mtbm 901 1.14 mrg Target Mask(ISA_TBM) Var(ix86_isa_flags) Save 902 1.8 mrg Support TBM built-in functions and code generation. 903 1.3 mrg 904 1.1 mrg mcx16 905 1.14 mrg Target Mask(ISA2_CX16) Var(ix86_isa_flags2) Save 906 1.1 mrg Support code generation of cmpxchg16b instruction. 907 1.1 mrg 908 1.1 mrg msahf 909 1.14 mrg Target Mask(ISA_SAHF) Var(ix86_isa_flags) Save 910 1.1 mrg Support code generation of sahf instruction in 64bit x86-64 code. 911 1.1 mrg 912 1.1 mrg mmovbe 913 1.14 mrg Target Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save 914 1.1 mrg Support code generation of movbe instruction. 915 1.1 mrg 916 1.1 mrg mcrc32 917 1.14 mrg Target Mask(ISA_CRC32) Var(ix86_isa_flags) Save 918 1.1 mrg Support code generation of crc32 instruction. 919 1.1 mrg 920 1.1 mrg maes 921 1.14 mrg Target Mask(ISA_AES) Var(ix86_isa_flags) Save 922 1.8 mrg Support AES built-in functions and code generation. 923 1.1 mrg 924 1.5 mrg msha 925 1.14 mrg Target Mask(ISA_SHA) Var(ix86_isa_flags) Save 926 1.8 mrg Support SHA1 and SHA256 built-in functions and code generation. 927 1.5 mrg 928 1.1 mrg mpclmul 929 1.14 mrg Target Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 930 1.8 mrg Support PCLMUL built-in functions and code generation. 931 1.1 mrg 932 1.1 mrg msse2avx 933 1.14 mrg Target Var(ix86_sse2avx) 934 1.8 mrg Encode SSE instructions with VEX prefix. 935 1.3 mrg 936 1.3 mrg mfsgsbase 937 1.14 mrg Target Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 938 1.8 mrg Support FSGSBASE built-in functions and code generation. 939 1.3 mrg 940 1.3 mrg mrdrnd 941 1.14 mrg Target Mask(ISA_RDRND) Var(ix86_isa_flags) Save 942 1.8 mrg Support RDRND built-in functions and code generation. 943 1.3 mrg 944 1.3 mrg mf16c 945 1.14 mrg Target Mask(ISA_F16C) Var(ix86_isa_flags) Save 946 1.8 mrg Support F16C built-in functions and code generation. 947 1.3 mrg 948 1.5 mrg mprefetchwt1 949 1.14 mrg Target Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save 950 1.8 mrg Support PREFETCHWT1 built-in functions and code generation. 951 1.5 mrg 952 1.3 mrg mfentry 953 1.14 mrg Target Save Var(flag_fentry) 954 1.3 mrg Emit profiling counter call at function entry before prologue. 955 1.3 mrg 956 1.5 mrg mrecord-mcount 957 1.14 mrg Target Var(flag_record_mcount) 958 1.5 mrg Generate __mcount_loc section with all mcount or __fentry__ calls. 959 1.5 mrg 960 1.5 mrg mnop-mcount 961 1.14 mrg Target Var(flag_nop_mcount) 962 1.5 mrg Generate mcount/__fentry__ calls as nops. To activate they need to be 963 1.5 mrg patched in. 964 1.5 mrg 965 1.12 mrg mfentry-name= 966 1.12 mrg Target RejectNegative Joined Var(fentry_name) 967 1.12 mrg Set name of __fentry__ symbol called at function entry. 968 1.12 mrg 969 1.12 mrg mfentry-section= 970 1.12 mrg Target RejectNegative Joined Var(fentry_section) 971 1.12 mrg Set name of section to record mrecord-mcount calls. 972 1.12 mrg 973 1.5 mrg mskip-rax-setup 974 1.14 mrg Target Var(flag_skip_rax_setup) 975 1.5 mrg Skip setting up RAX register when passing variable arguments. 976 1.5 mrg 977 1.3 mrg m8bit-idiv 978 1.14 mrg Target Mask(USE_8BIT_IDIV) Save 979 1.8 mrg Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. 980 1.3 mrg 981 1.3 mrg mavx256-split-unaligned-load 982 1.14 mrg Target Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 983 1.8 mrg Split 32-byte AVX unaligned load. 984 1.3 mrg 985 1.3 mrg mavx256-split-unaligned-store 986 1.14 mrg Target Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 987 1.8 mrg Split 32-byte AVX unaligned store. 988 1.3 mrg 989 1.3 mrg mrtm 990 1.14 mrg Target Mask(ISA_RTM) Var(ix86_isa_flags) Save 991 1.8 mrg Support RTM built-in functions and code generation. 992 1.5 mrg 993 1.5 mrg mmpx 994 1.13 mrg Target WarnRemoved 995 1.13 mrg Removed in GCC 9. This switch has no effect. 996 1.5 mrg 997 1.5 mrg mmwaitx 998 1.14 mrg Target Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save 999 1.8 mrg Support MWAITX and MONITORX built-in functions and code generation. 1000 1.8 mrg 1001 1.8 mrg mclzero 1002 1.14 mrg Target Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save 1003 1.8 mrg Support CLZERO built-in functions and code generation. 1004 1.8 mrg 1005 1.8 mrg mpku 1006 1.14 mrg Target Mask(ISA_PKU) Var(ix86_isa_flags) Save 1007 1.8 mrg Support PKU built-in functions and code generation. 1008 1.5 mrg 1009 1.5 mrg mstack-protector-guard= 1010 1.5 mrg Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) 1011 1.8 mrg Use given stack-protector guard. 1012 1.5 mrg 1013 1.5 mrg Enum 1014 1.5 mrg Name(stack_protector_guard) Type(enum stack_protector_guard) 1015 1.5 mrg Known stack protector guard (for use with the -mstack-protector-guard= option): 1016 1.5 mrg 1017 1.5 mrg EnumValue 1018 1.5 mrg Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 1019 1.5 mrg 1020 1.5 mrg EnumValue 1021 1.5 mrg Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 1022 1.7 mrg 1023 1.11 mrg mstack-protector-guard-reg= 1024 1.14 mrg Target Save RejectNegative Joined Var(ix86_stack_protector_guard_reg_str) 1025 1.11 mrg Use the given base register for addressing the stack-protector guard. 1026 1.11 mrg 1027 1.11 mrg TargetVariable 1028 1.11 mrg addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC 1029 1.11 mrg 1030 1.11 mrg mstack-protector-guard-offset= 1031 1.14 mrg Target Save RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str) 1032 1.11 mrg Use the given offset for addressing the stack-protector guard. 1033 1.11 mrg 1034 1.11 mrg TargetVariable 1035 1.11 mrg HOST_WIDE_INT ix86_stack_protector_guard_offset = 0 1036 1.11 mrg 1037 1.11 mrg mstack-protector-guard-symbol= 1038 1.14 mrg Target Save RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str) 1039 1.11 mrg Use the given symbol for addressing the stack-protector guard. 1040 1.11 mrg 1041 1.8 mrg mmitigate-rop 1042 1.13 mrg Target WarnRemoved 1043 1.8 mrg 1044 1.10 mrg mgeneral-regs-only 1045 1.14 mrg Target RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save 1046 1.10 mrg Generate code which uses only the general registers. 1047 1.10 mrg 1048 1.11 mrg mshstk 1049 1.14 mrg Target Mask(ISA_SHSTK) Var(ix86_isa_flags) Save 1050 1.11 mrg Enable shadow stack built-in functions from Control-flow Enforcement 1051 1.11 mrg Technology (CET). 1052 1.11 mrg 1053 1.11 mrg mcet-switch 1054 1.14 mrg Target Undocumented Var(flag_cet_switch) Init(0) 1055 1.11 mrg Turn on CET instrumentation for switch statements that use a jump table and 1056 1.11 mrg an indirect jump. 1057 1.11 mrg 1058 1.12 mrg mmanual-endbr 1059 1.14 mrg Target Var(flag_manual_endbr) Init(0) 1060 1.12 mrg Insert ENDBR instruction at function entry only via cf_check attribute 1061 1.12 mrg for CET instrumentation. 1062 1.12 mrg 1063 1.11 mrg mforce-indirect-call 1064 1.14 mrg Target Var(flag_force_indirect_call) Init(0) 1065 1.11 mrg Make all function calls indirect. 1066 1.11 mrg 1067 1.7 mrg mindirect-branch= 1068 1.14 mrg Target RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) 1069 1.7 mrg Convert indirect call and jump to call and return thunks. 1070 1.7 mrg 1071 1.7 mrg mfunction-return= 1072 1.14 mrg Target RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) 1073 1.7 mrg Convert function return to call and return thunk. 1074 1.7 mrg 1075 1.7 mrg Enum 1076 1.7 mrg Name(indirect_branch) Type(enum indirect_branch) 1077 1.7 mrg Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options): 1078 1.7 mrg 1079 1.7 mrg EnumValue 1080 1.7 mrg Enum(indirect_branch) String(keep) Value(indirect_branch_keep) 1081 1.7 mrg 1082 1.7 mrg EnumValue 1083 1.7 mrg Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk) 1084 1.7 mrg 1085 1.7 mrg EnumValue 1086 1.7 mrg Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline) 1087 1.7 mrg 1088 1.7 mrg EnumValue 1089 1.7 mrg Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) 1090 1.7 mrg 1091 1.14 mrg mindirect-branch-cs-prefix 1092 1.14 mrg Target Var(ix86_indirect_branch_cs_prefix) Init(0) 1093 1.14 mrg Add CS prefix to call and jmp to indirect thunk with branch target in r8-r15 registers. 1094 1.14 mrg 1095 1.7 mrg mindirect-branch-register 1096 1.14 mrg Target Var(ix86_indirect_branch_register) Init(0) 1097 1.7 mrg Force indirect call and jump via register. 1098 1.11 mrg 1099 1.11 mrg mmovdiri 1100 1.14 mrg Target Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save 1101 1.11 mrg Support MOVDIRI built-in functions and code generation. 1102 1.11 mrg 1103 1.11 mrg mmovdir64b 1104 1.14 mrg Target Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save 1105 1.11 mrg Support MOVDIR64B built-in functions and code generation. 1106 1.12 mrg 1107 1.12 mrg mwaitpkg 1108 1.14 mrg Target Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save 1109 1.12 mrg Support WAITPKG built-in functions and code generation. 1110 1.12 mrg 1111 1.12 mrg mcldemote 1112 1.14 mrg Target Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save 1113 1.12 mrg Support CLDEMOTE built-in functions and code generation. 1114 1.12 mrg 1115 1.12 mrg minstrument-return= 1116 1.14 mrg Target RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none) 1117 1.12 mrg Instrument function exit in instrumented functions with __fentry__. 1118 1.12 mrg 1119 1.12 mrg Enum 1120 1.12 mrg Name(instrument_return) Type(enum instrument_return) 1121 1.12 mrg Known choices for return instrumentation with -minstrument-return=: 1122 1.12 mrg 1123 1.12 mrg EnumValue 1124 1.12 mrg Enum(instrument_return) String(none) Value(instrument_return_none) 1125 1.12 mrg 1126 1.12 mrg EnumValue 1127 1.12 mrg Enum(instrument_return) String(call) Value(instrument_return_call) 1128 1.12 mrg 1129 1.12 mrg EnumValue 1130 1.12 mrg Enum(instrument_return) String(nop5) Value(instrument_return_nop5) 1131 1.12 mrg 1132 1.12 mrg mrecord-return 1133 1.14 mrg Target Var(ix86_flag_record_return) Init(0) 1134 1.12 mrg Generate a __return_loc section pointing to all return instrumentation code. 1135 1.13 mrg 1136 1.14 mrg mharden-sls= 1137 1.14 mrg Target RejectNegative Joined Enum(harden_sls) Var(ix86_harden_sls) Init(harden_sls_none) 1138 1.14 mrg Generate code to mitigate against straight line speculation. 1139 1.14 mrg 1140 1.14 mrg Enum 1141 1.14 mrg Name(harden_sls) Type(enum harden_sls) 1142 1.14 mrg Known choices for mitigation against straight line speculation with -mharden-sls=: 1143 1.14 mrg 1144 1.14 mrg EnumValue 1145 1.14 mrg Enum(harden_sls) String(none) Value(harden_sls_none) 1146 1.14 mrg 1147 1.14 mrg EnumValue 1148 1.14 mrg Enum(harden_sls) String(return) Value(harden_sls_return) 1149 1.14 mrg 1150 1.14 mrg EnumValue 1151 1.14 mrg Enum(harden_sls) String(indirect-jmp) Value(harden_sls_indirect_jmp) 1152 1.14 mrg 1153 1.14 mrg EnumValue 1154 1.14 mrg Enum(harden_sls) String(all) Value(harden_sls_all) 1155 1.14 mrg 1156 1.13 mrg mavx512bf16 1157 1.14 mrg Target Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save 1158 1.13 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and 1159 1.13 mrg AVX512BF16 built-in functions and code generation. 1160 1.13 mrg 1161 1.13 mrg menqcmd 1162 1.14 mrg Target Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save 1163 1.13 mrg Support ENQCMD built-in functions and code generation. 1164 1.14 mrg 1165 1.14 mrg mserialize 1166 1.14 mrg Target Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save 1167 1.14 mrg Support SERIALIZE built-in functions and code generation. 1168 1.14 mrg 1169 1.14 mrg mtsxldtrk 1170 1.14 mrg Target Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save 1171 1.14 mrg Support TSXLDTRK built-in functions and code generation. 1172 1.14 mrg 1173 1.14 mrg mamx-tile 1174 1.14 mrg Target Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save 1175 1.14 mrg Support AMX-TILE built-in functions and code generation. 1176 1.14 mrg 1177 1.14 mrg mamx-int8 1178 1.14 mrg Target Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save 1179 1.14 mrg Support AMX-INT8 built-in functions and code generation. 1180 1.14 mrg 1181 1.14 mrg mamx-bf16 1182 1.14 mrg Target Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save 1183 1.14 mrg Support AMX-BF16 built-in functions and code generation. 1184 1.14 mrg 1185 1.14 mrg mhreset 1186 1.14 mrg Target Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save 1187 1.14 mrg Support HRESET built-in functions and code generation. 1188 1.14 mrg 1189 1.14 mrg mkl 1190 1.14 mrg Target Mask(ISA2_KL) Var(ix86_isa_flags2) Save 1191 1.14 mrg Support KL built-in functions and code generation. 1192 1.14 mrg 1193 1.14 mrg mwidekl 1194 1.14 mrg Target Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save 1195 1.14 mrg Support WIDEKL built-in functions and code generation. 1196 1.14 mrg 1197 1.14 mrg mavxvnni 1198 1.14 mrg Target Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save 1199 1.14 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and 1200 1.14 mrg AVXVNNI built-in functions and code generation. 1201 1.14 mrg 1202 1.14 mrg mneeded 1203 1.14 mrg Target Var(ix86_needed) Save 1204 1.14 mrg Emit GNU_PROPERTY_X86_ISA_1_NEEDED GNU property. 1205 1.14 mrg 1206 1.14 mrg mmwait 1207 1.14 mrg Target Mask(ISA2_MWAIT) Var(ix86_isa_flags2) Save 1208 1.14 mrg Support MWAIT and MONITOR built-in functions and code generation. 1209 1.14 mrg 1210 1.14 mrg mavx512fp16 1211 1.14 mrg Target Mask(ISA2_AVX512FP16) Var(ix86_isa_flags2) Save 1212 1.14 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512-FP16 built-in functions and code generation. 1213 1.14 mrg 1214 1.14 mrg mdirect-extern-access 1215 1.14 mrg Target Var(ix86_direct_extern_access) Init(1) 1216 1.14 mrg Do not use GOT to access external symbols. 1217 1.14 mrg 1218 1.14 mrg -param=x86-stlf-window-ninsns= 1219 1.14 mrg Target Joined UInteger Var(x86_stlf_window_ninsns) Init(64) Param 1220 1.14 mrg Instructions number above which STFL stall penalty can be compensated. 1221 1.14 mrg 1222 1.14 mrg mgather 1223 1.14 mrg Target Alias(mtune-ctrl=, use_gather, ^use_gather) 1224 1.14 mrg Enable vectorization for gather instruction. 1225 1.14 mrg 1226 1.14 mrg mscatter 1227 1.14 mrg Target Alias(mtune-ctrl=, use_scatter, ^use_scatter) 1228 1.14 mrg Enable vectorization for scatter instruction. 1229
Indexes created Wed Apr 29 00:23:26 UTC 2026