1 ; Options for the IA-32 and AMD64 ports of the compiler. 2 3 ; Copyright (C) 2005-2022 Free Software Foundation, Inc. 4 ; 5 ; This file is part of GCC. 6 ; 7 ; GCC is free software; you can redistribute it and/or modify it under 8 ; the terms of the GNU General Public License as published by the Free 9 ; Software Foundation; either version 3, or (at your option) any later 10 ; version. 11 ; 12 ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 ; for more details. 16 ; 17 ; You should have received a copy of the GNU General Public License 18 ; along with GCC; see the file COPYING3. If not see 19 ; <http://www.gnu.org/licenses/>. 20 21 HeaderInclude 22 config/i386/i386-opts.h 23 24 ; Bit flags that specify the ISA we are compiling for. 25 Variable 26 HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 28 Variable 29 HOST_WIDE_INT ix86_isa_flags2 = 0 30 31 ; A mask of ix86_isa_flags that includes bit X if X was set or cleared 32 ; on the command line. 33 Variable 34 HOST_WIDE_INT ix86_isa_flags_explicit 35 36 Variable 37 HOST_WIDE_INT ix86_isa_flags2_explicit 38 39 ; Additional target flags 40 Variable 41 int ix86_target_flags 42 43 TargetVariable 44 int recip_mask = RECIP_MASK_DEFAULT 45 46 Variable 47 int recip_mask_explicit 48 49 TargetSave 50 int x_recip_mask_explicit 51 52 ;; A copy of flag_excess_precision as a target variable that should 53 ;; force a different DECL_FUNCTION_SPECIFIC_TARGET upon 54 ;; flag_excess_precision changes. 55 TargetVariable 56 enum excess_precision ix86_excess_precision = EXCESS_PRECISION_DEFAULT 57 58 ;; Similarly for flag_unsafe_math_optimizations. 59 TargetVariable 60 bool ix86_unsafe_math_optimizations = false 61 62 ;; Definitions to add to the cl_target_option structure 63 ;; -march= processor 64 TargetSave 65 unsigned char arch 66 67 ;; -mtune= processor 68 TargetSave 69 unsigned char tune 70 71 ;; -march= processor-string 72 TargetSave 73 const char *x_ix86_arch_string 74 75 ;; -mtune= processor-string 76 TargetSave 77 const char *x_ix86_tune_string 78 79 ;; CPU schedule model 80 TargetSave 81 unsigned char schedule 82 83 ;; True if processor has SSE prefetch instruction. 84 TargetSave 85 unsigned char prefetch_sse 86 87 ;; branch cost 88 TargetSave 89 unsigned char branch_cost 90 91 ;; which flags were passed by the user 92 TargetSave 93 HOST_WIDE_INT x_ix86_isa_flags2_explicit 94 95 ;; which flags were passed by the user 96 TargetSave 97 HOST_WIDE_INT x_ix86_isa_flags_explicit 98 99 ;; whether -mtune was not specified 100 TargetSave 101 unsigned char tune_defaulted 102 103 ;; whether -march was specified 104 TargetSave 105 unsigned char arch_specified 106 107 ;; -mcmodel= model 108 TargetVariable 109 enum cmodel ix86_cmodel = CM_32 110 111 ;; -mabi= 112 TargetVariable 113 enum calling_abi ix86_abi = SYSV_ABI 114 115 ;; -masm= 116 TargetSave 117 enum asm_dialect x_ix86_asm_dialect 118 119 ;; -mbranch-cost= 120 TargetSave 121 int x_ix86_branch_cost 122 123 ;; -mdump-tune-features= 124 TargetSave 125 int x_ix86_dump_tunes 126 127 ;; -mstackrealign= 128 TargetSave 129 int x_ix86_force_align_arg_pointer 130 131 ;; -mforce-drap= 132 TargetSave 133 int x_ix86_force_drap 134 135 ;; -mincoming-stack-boundary= 136 TargetVariable 137 int ix86_incoming_stack_boundary_arg 138 139 ;; -maddress-mode= 140 TargetVariable 141 enum pmode ix86_pmode = PMODE_SI 142 143 ;; -mpreferred-stack-boundary= 144 TargetVariable 145 int ix86_preferred_stack_boundary_arg 146 147 ;; -mrecip= 148 TargetSave 149 const char *x_ix86_recip_name 150 151 ;; -mregparm= 152 TargetVariable 153 int ix86_regparm 154 155 ;; -mlarge-data-threshold= 156 TargetSave 157 int x_ix86_section_threshold 158 159 ;; -msse2avx= 160 TargetSave 161 int x_ix86_sse2avx 162 163 ;; -mstack-protector-guard= 164 TargetSave 165 enum stack_protector_guard x_ix86_stack_protector_guard 166 167 ;; -mstringop-strategy= 168 TargetSave 169 enum stringop_alg x_ix86_stringop_alg 170 171 ;; -mtls-dialect= 172 TargetSave 173 enum tls_dialect x_ix86_tls_dialect 174 175 ;; -mtune-ctrl= 176 TargetSave 177 const char *x_ix86_tune_ctrl_string 178 179 ;; -mmemcpy-strategy= 180 TargetSave 181 const char *x_ix86_tune_memcpy_strategy 182 183 ;; -mmemset-strategy= 184 TargetSave 185 const char *x_ix86_tune_memset_strategy 186 187 ;; -mno-default= 188 TargetSave 189 int x_ix86_tune_no_default 190 191 ;; -mveclibabi= 192 TargetVariable 193 enum ix86_veclibabi ix86_veclibabi_type = ix86_veclibabi_type_none 194 195 ;; x86 options 196 m128bit-long-double 197 Target RejectNegative Mask(128BIT_LONG_DOUBLE) Save 198 sizeof(long double) is 16. 199 200 m80387 201 Target Mask(80387) Save 202 Use hardware fp. 203 204 m96bit-long-double 205 Target RejectNegative InverseMask(128BIT_LONG_DOUBLE) Save 206 sizeof(long double) is 12. 207 208 mlong-double-80 209 Target RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save 210 Use 80-bit long double. 211 212 mlong-double-64 213 Target RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save 214 Use 64-bit long double. 215 216 mlong-double-128 217 Target RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save 218 Use 128-bit long double. 219 220 maccumulate-outgoing-args 221 Target Mask(ACCUMULATE_OUTGOING_ARGS) Save 222 Reserve space for outgoing arguments in the function prologue. 223 224 malign-double 225 Target Mask(ALIGN_DOUBLE) Save 226 Align some doubles on dword boundary. 227 228 malign-functions= 229 Target RejectNegative Joined UInteger 230 Function starts are aligned to this power of 2. 231 232 malign-jumps= 233 Target RejectNegative Joined UInteger 234 Jump targets are aligned to this power of 2. 235 236 malign-loops= 237 Target RejectNegative Joined UInteger 238 Loop code aligned to this power of 2. 239 240 malign-stringops 241 Target RejectNegative InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 242 Align destination of the string operations. 243 244 malign-data= 245 Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) 246 Use the given data alignment. 247 248 Enum 249 Name(ix86_align_data) Type(enum ix86_align_data) 250 Known data alignment choices (for use with the -malign-data= option): 251 252 EnumValue 253 Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat) 254 255 EnumValue 256 Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi) 257 258 EnumValue 259 Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) 260 261 march= 262 Target RejectNegative Negative(march=) Joined Var(ix86_arch_string) 263 Generate code for given CPU. 264 265 masm= 266 Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 267 Use given assembler dialect. 268 269 Enum 270 Name(asm_dialect) Type(enum asm_dialect) 271 Known assembler dialects (for use with the -masm= option): 272 273 EnumValue 274 Enum(asm_dialect) String(intel) Value(ASM_INTEL) 275 276 EnumValue 277 Enum(asm_dialect) String(att) Value(ASM_ATT) 278 279 mbranch-cost= 280 Target RejectNegative Joined UInteger Var(ix86_branch_cost) IntegerRange(0, 5) 281 Branches are this expensive (arbitrary units). 282 283 mlarge-data-threshold= 284 Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 285 -mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model. 286 287 mcmodel= 288 Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 289 Use given x86-64 code model. 290 291 Enum 292 Name(cmodel) Type(enum cmodel) 293 Known code models (for use with the -mcmodel= option): 294 295 EnumValue 296 Enum(cmodel) String(small) Value(CM_SMALL) 297 298 EnumValue 299 Enum(cmodel) String(medium) Value(CM_MEDIUM) 300 301 EnumValue 302 Enum(cmodel) String(large) Value(CM_LARGE) 303 304 EnumValue 305 Enum(cmodel) String(32) Value(CM_32) 306 307 EnumValue 308 Enum(cmodel) String(kernel) Value(CM_KERNEL) 309 310 maddress-mode= 311 Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 312 Use given address mode. 313 314 Enum 315 Name(pmode) Type(enum pmode) 316 Known address mode (for use with the -maddress-mode= option): 317 318 EnumValue 319 Enum(pmode) String(short) Value(PMODE_SI) 320 321 EnumValue 322 Enum(pmode) String(long) Value(PMODE_DI) 323 324 mcpu= 325 Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 326 327 mfancy-math-387 328 Target RejectNegative InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 329 Generate sin, cos, sqrt for FPU. 330 331 mforce-drap 332 Target Var(ix86_force_drap) 333 Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. 334 335 mfp-ret-in-387 336 Target Mask(FLOAT_RETURNS) Save 337 Return values of functions in FPU registers. 338 339 mfpmath= 340 Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 341 Generate floating point mathematics using given instruction set. 342 343 Enum 344 Name(fpmath_unit) Type(enum fpmath_unit) 345 Valid arguments to -mfpmath=: 346 347 EnumValue 348 Enum(fpmath_unit) String(387) Value(FPMATH_387) 349 350 EnumValue 351 Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 352 353 EnumValue 354 Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 355 356 EnumValue 357 Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 358 359 EnumValue 360 Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 361 362 EnumValue 363 Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 364 365 EnumValue 366 Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 367 368 mhard-float 369 Target RejectNegative Mask(80387) Save 370 Use hardware fp. 371 372 mieee-fp 373 Target Mask(IEEE_FP) Save 374 Use IEEE math for fp comparisons. 375 376 minline-all-stringops 377 Target Mask(INLINE_ALL_STRINGOPS) Save 378 Inline all known string operations. 379 380 minline-stringops-dynamically 381 Target Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 382 Inline memset/memcpy string operations, but perform inline version only for small blocks. 383 384 mintel-syntax 385 Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 386 387 mms-bitfields 388 Target Mask(MS_BITFIELD_LAYOUT) Save 389 Use native (MS) bitfield layout. 390 391 mno-align-stringops 392 Target RejectNegative Mask(NO_ALIGN_STRINGOPS) Undocumented Save 393 394 mno-fancy-math-387 395 Target RejectNegative Mask(NO_FANCY_MATH_387) Undocumented Save 396 397 mno-push-args 398 Target RejectNegative Mask(NO_PUSH_ARGS) Undocumented Save 399 400 mno-red-zone 401 Target RejectNegative Mask(NO_RED_ZONE) Undocumented Save 402 403 momit-leaf-frame-pointer 404 Target Mask(OMIT_LEAF_FRAME_POINTER) Save 405 Omit the frame pointer in leaf functions. 406 407 mrelax-cmpxchg-loop 408 Target Mask(RELAX_CMPXCHG_LOOP) Save 409 Relax cmpxchg loop for atomic_fetch_{or,xor,and,nand} by adding load and cmp before cmpxchg, execute pause and loop back to load and compare if load value is not expected. 410 411 mpc32 412 Target RejectNegative 413 Set 80387 floating-point precision to 32-bit. 414 415 mpc64 416 Target RejectNegative 417 Set 80387 floating-point precision to 64-bit. 418 419 mpc80 420 Target RejectNegative 421 Set 80387 floating-point precision to 80-bit. 422 423 mdaz-ftz 424 Target 425 Set the FTZ and DAZ Flags. 426 427 mpreferred-stack-boundary= 428 Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 429 Attempt to keep stack aligned to this power of 2. 430 431 mincoming-stack-boundary= 432 Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 433 Assume incoming stack aligned to this power of 2. 434 435 mpush-args 436 Target InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 437 Use push instructions to save outgoing arguments. 438 439 mred-zone 440 Target RejectNegative InverseMask(NO_RED_ZONE, RED_ZONE) Save 441 Use red-zone in the x86-64 code. 442 443 mregparm= 444 Target RejectNegative Joined UInteger Var(ix86_regparm) 445 Number of registers used to pass integer arguments. 446 447 mrtd 448 Target Mask(RTD) Save 449 Alternate calling convention. 450 451 msoft-float 452 Target InverseMask(80387) Save 453 Do not use hardware fp. 454 455 msseregparm 456 Target RejectNegative Mask(SSEREGPARM) Save 457 Use SSE register passing conventions for SF and DF mode. 458 459 mstackrealign 460 Target Var(ix86_force_align_arg_pointer) 461 Realign stack in prologue. 462 463 mstack-arg-probe 464 Target Mask(STACK_PROBE) Save 465 Enable stack probing. 466 467 mmemcpy-strategy= 468 Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) 469 Specify memcpy expansion strategy when expected size is known. 470 471 mmemset-strategy= 472 Target RejectNegative Joined Var(ix86_tune_memset_strategy) 473 Specify memset expansion strategy when expected size is known. 474 475 mstringop-strategy= 476 Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 477 Chose strategy to generate stringop using. 478 479 Enum 480 Name(stringop_alg) Type(enum stringop_alg) 481 Valid arguments to -mstringop-strategy=: 482 483 EnumValue 484 Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 485 486 EnumValue 487 Enum(stringop_alg) String(libcall) Value(libcall) 488 489 EnumValue 490 Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 491 492 EnumValue 493 Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 494 495 EnumValue 496 Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 497 498 EnumValue 499 Enum(stringop_alg) String(loop) Value(loop) 500 501 EnumValue 502 Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 503 504 EnumValue 505 Enum(stringop_alg) String(vector_loop) Value(vector_loop) 506 507 mtls-dialect= 508 Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 509 Use given thread-local storage dialect. 510 511 Enum 512 Name(tls_dialect) Type(enum tls_dialect) 513 Known TLS dialects (for use with the -mtls-dialect= option): 514 515 EnumValue 516 Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 517 518 EnumValue 519 Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 520 521 mtls-direct-seg-refs 522 Target Mask(TLS_DIRECT_SEG_REFS) 523 Use direct references against %gs when accessing tls data. 524 525 mtune= 526 Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string) 527 Schedule code for given CPU. 528 529 mtune-ctrl= 530 Target RejectNegative Joined Var(ix86_tune_ctrl_string) 531 Fine grain control of tune features. 532 533 mno-default 534 Target RejectNegative Var(ix86_tune_no_default) 535 Clear all tune features. 536 537 mdump-tune-features 538 Target RejectNegative Var(ix86_dump_tunes) 539 540 miamcu 541 Target Mask(IAMCU) 542 Generate code that conforms to Intel MCU psABI. 543 544 mabi= 545 Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 546 Generate code that conforms to the given ABI. 547 548 Enum 549 Name(calling_abi) Type(enum calling_abi) 550 Known ABIs (for use with the -mabi= option): 551 552 EnumValue 553 Enum(calling_abi) String(sysv) Value(SYSV_ABI) 554 555 EnumValue 556 Enum(calling_abi) String(ms) Value(MS_ABI) 557 558 mcall-ms2sysv-xlogues 559 Target Mask(CALL_MS2SYSV_XLOGUES) Save 560 Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls. 561 562 mveclibabi= 563 Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 564 Vector library ABI to use. 565 566 Enum 567 Name(ix86_veclibabi) Type(enum ix86_veclibabi) 568 Known vectorization library ABIs (for use with the -mveclibabi= option): 569 570 EnumValue 571 Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 572 573 EnumValue 574 Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 575 576 mvect8-ret-in-mem 577 Target Mask(VECT8_RETURNS) Save 578 Return 8-byte vectors in memory. 579 580 mrecip 581 Target Mask(RECIP) Save 582 Generate reciprocals instead of divss and sqrtss. 583 584 mrecip= 585 Target RejectNegative Joined Var(ix86_recip_name) 586 Control generation of reciprocal estimates. 587 588 mcld 589 Target Mask(CLD) Save 590 Generate cld instruction in the function prologue. 591 592 mvzeroupper 593 Target Mask(VZEROUPPER) Save 594 Generate vzeroupper instruction before a transfer of control flow out of 595 the function. 596 597 mstv 598 Target Mask(STV) Save 599 Disable Scalar to Vector optimization pass transforming 64-bit integer 600 computations into a vector ones. 601 602 mdispatch-scheduler 603 Target RejectNegative Var(flag_dispatch_scheduler) 604 Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4 605 or znver1 and Haifa scheduling is selected. 606 607 mprefer-avx128 608 Target Alias(mprefer-vector-width=, 128, 256) 609 Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 610 611 mprefer-vector-width= 612 Target RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save 613 Use given register vector width instructions instead of maximum register width in the auto-vectorizer. 614 615 Enum 616 Name(prefer_vector_width) Type(enum prefer_vector_width) 617 Known preferred register vector length (to use with the -mprefer-vector-width= option): 618 619 EnumValue 620 Enum(prefer_vector_width) String(none) Value(PVW_NONE) 621 622 EnumValue 623 Enum(prefer_vector_width) String(128) Value(PVW_AVX128) 624 625 EnumValue 626 Enum(prefer_vector_width) String(256) Value(PVW_AVX256) 627 628 EnumValue 629 Enum(prefer_vector_width) String(512) Value(PVW_AVX512) 630 631 mmove-max= 632 Target RejectNegative Joined Var(ix86_move_max) Enum(prefer_vector_width) Init(PVW_NONE) Save 633 Maximum number of bits that can be moved from memory to memory efficiently. 634 635 mstore-max= 636 Target RejectNegative Joined Var(ix86_store_max) Enum(prefer_vector_width) Init(PVW_NONE) Save 637 Maximum number of bits that can be stored to memory efficiently. 638 639 ;; ISA support 640 641 m32 642 Target RejectNegative Negative(m64) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 643 Generate 32bit i386 code. 644 645 m64 646 Target RejectNegative Negative(mx32) Mask(ABI_64) Var(ix86_isa_flags) Save 647 Generate 64bit x86-64 code. 648 649 mx32 650 Target RejectNegative Negative(m16) Mask(ABI_X32) Var(ix86_isa_flags) Save 651 Generate 32bit x86-64 code. 652 653 m16 654 Target RejectNegative Negative(m32) Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 655 Generate 16bit i386 code. 656 657 mmmx 658 Target Mask(ISA_MMX) Var(ix86_isa_flags) Save 659 Support MMX built-in functions. 660 661 m3dnow 662 Target Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 663 Support 3DNow! built-in functions. 664 665 m3dnowa 666 Target Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 667 Support Athlon 3Dnow! built-in functions. 668 669 msse 670 Target Mask(ISA_SSE) Var(ix86_isa_flags) Save 671 Support MMX and SSE built-in functions and code generation. 672 673 msse2 674 Target Mask(ISA_SSE2) Var(ix86_isa_flags) Save 675 Support MMX, SSE and SSE2 built-in functions and code generation. 676 677 msse3 678 Target Mask(ISA_SSE3) Var(ix86_isa_flags) Save 679 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. 680 681 mssse3 682 Target Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 683 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. 684 685 msse4.1 686 Target Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 687 Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. 688 689 msse4.2 690 Target Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 691 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 692 693 msse4 694 Target RejectNegative Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 695 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 696 697 mno-sse4 698 Target RejectNegative InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 699 Do not support SSE4.1 and SSE4.2 built-in functions and code generation. 700 701 msse5 702 Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 703 ;; Deprecated 704 705 mavx 706 Target Mask(ISA_AVX) Var(ix86_isa_flags) Save 707 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. 708 709 mavx2 710 Target Mask(ISA_AVX2) Var(ix86_isa_flags) Save 711 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. 712 713 mavx512f 714 Target Mask(ISA_AVX512F) Var(ix86_isa_flags) Save 715 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. 716 717 mavx512pf 718 Target Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save 719 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. 720 721 mavx512er 722 Target Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save 723 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. 724 725 mavx512cd 726 Target Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save 727 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. 728 729 mavx512dq 730 Target Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save 731 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. 732 733 mavx512bw 734 Target Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save 735 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. 736 737 mavx512vl 738 Target Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save 739 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. 740 741 mavx512ifma 742 Target Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save 743 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. 744 745 mavx512vbmi 746 Target Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save 747 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. 748 749 mavx5124fmaps 750 Target Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save 751 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. 752 753 mavx5124vnniw 754 Target Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save 755 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. 756 757 mavx512vpopcntdq 758 Target Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save 759 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation. 760 761 mavx512vbmi2 762 Target Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save 763 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation. 764 765 mavx512vnni 766 Target Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save 767 Support AVX512VNNI built-in functions and code generation. 768 769 mavx512bitalg 770 Target Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save 771 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation. 772 773 mavx512vp2intersect 774 Target Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save 775 Support AVX512VP2INTERSECT built-in functions and code generation. 776 777 mfma 778 Target Mask(ISA_FMA) Var(ix86_isa_flags) Save 779 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. 780 781 msse4a 782 Target Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 783 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. 784 785 mfma4 786 Target Mask(ISA_FMA4) Var(ix86_isa_flags) Save 787 Support FMA4 built-in functions and code generation. 788 789 mxop 790 Target Mask(ISA_XOP) Var(ix86_isa_flags) Save 791 Support XOP built-in functions and code generation. 792 793 mlwp 794 Target Mask(ISA_LWP) Var(ix86_isa_flags) Save 795 Support LWP built-in functions and code generation. 796 797 mabm 798 Target Mask(ISA_ABM) Var(ix86_isa_flags) Save 799 Support code generation of Advanced Bit Manipulation (ABM) instructions. 800 801 mpopcnt 802 Target Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 803 Support code generation of popcnt instruction. 804 805 mpconfig 806 Target Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save 807 Support PCONFIG built-in functions and code generation. 808 809 mwbnoinvd 810 Target Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save 811 Support WBNOINVD built-in functions and code generation. 812 813 mptwrite 814 Target Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save 815 Support PTWRITE built-in functions and code generation. 816 817 muintr 818 Target Mask(ISA2_UINTR) Var(ix86_isa_flags2) Save 819 Support UINTR built-in functions and code generation. 820 821 msgx 822 Target Mask(ISA2_SGX) Var(ix86_isa_flags2) Save 823 Support SGX built-in functions and code generation. 824 825 mrdpid 826 Target Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save 827 Support RDPID built-in functions and code generation. 828 829 mgfni 830 Target Mask(ISA_GFNI) Var(ix86_isa_flags) Save 831 Support GFNI built-in functions and code generation. 832 833 mvaes 834 Target Mask(ISA2_VAES) Var(ix86_isa_flags2) Save 835 Support VAES built-in functions and code generation. 836 837 mvpclmulqdq 838 Target Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save 839 Support VPCLMULQDQ built-in functions and code generation. 840 841 mbmi 842 Target Mask(ISA_BMI) Var(ix86_isa_flags) Save 843 Support BMI built-in functions and code generation. 844 845 mbmi2 846 Target Mask(ISA_BMI2) Var(ix86_isa_flags) Save 847 Support BMI2 built-in functions and code generation. 848 849 mlzcnt 850 Target Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 851 Support LZCNT built-in function and code generation. 852 853 mhle 854 Target Mask(ISA2_HLE) Var(ix86_isa_flags2) Save 855 Support Hardware Lock Elision prefixes. 856 857 mrdseed 858 Target Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 859 Support RDSEED instruction. 860 861 mprfchw 862 Target Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 863 Support PREFETCHW instruction. 864 865 madx 866 Target Mask(ISA_ADX) Var(ix86_isa_flags) Save 867 Support flag-preserving add-carry instructions. 868 869 mclflushopt 870 Target Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save 871 Support CLFLUSHOPT instructions. 872 873 mclwb 874 Target Mask(ISA_CLWB) Var(ix86_isa_flags) Save 875 Support CLWB instruction. 876 877 mpcommit 878 Target WarnRemoved 879 880 mfxsr 881 Target Mask(ISA_FXSR) Var(ix86_isa_flags) Save 882 Support FXSAVE and FXRSTOR instructions. 883 884 mxsave 885 Target Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 886 Support XSAVE and XRSTOR instructions. 887 888 mxsaveopt 889 Target Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 890 Support XSAVEOPT instruction. 891 892 mxsavec 893 Target Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save 894 Support XSAVEC instructions. 895 896 mxsaves 897 Target Mask(ISA_XSAVES) Var(ix86_isa_flags) Save 898 Support XSAVES and XRSTORS instructions. 899 900 mtbm 901 Target Mask(ISA_TBM) Var(ix86_isa_flags) Save 902 Support TBM built-in functions and code generation. 903 904 mcx16 905 Target Mask(ISA2_CX16) Var(ix86_isa_flags2) Save 906 Support code generation of cmpxchg16b instruction. 907 908 msahf 909 Target Mask(ISA_SAHF) Var(ix86_isa_flags) Save 910 Support code generation of sahf instruction in 64bit x86-64 code. 911 912 mmovbe 913 Target Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save 914 Support code generation of movbe instruction. 915 916 mcrc32 917 Target Mask(ISA_CRC32) Var(ix86_isa_flags) Save 918 Support code generation of crc32 instruction. 919 920 maes 921 Target Mask(ISA_AES) Var(ix86_isa_flags) Save 922 Support AES built-in functions and code generation. 923 924 msha 925 Target Mask(ISA_SHA) Var(ix86_isa_flags) Save 926 Support SHA1 and SHA256 built-in functions and code generation. 927 928 mpclmul 929 Target Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 930 Support PCLMUL built-in functions and code generation. 931 932 msse2avx 933 Target Var(ix86_sse2avx) 934 Encode SSE instructions with VEX prefix. 935 936 mfsgsbase 937 Target Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 938 Support FSGSBASE built-in functions and code generation. 939 940 mrdrnd 941 Target Mask(ISA_RDRND) Var(ix86_isa_flags) Save 942 Support RDRND built-in functions and code generation. 943 944 mf16c 945 Target Mask(ISA_F16C) Var(ix86_isa_flags) Save 946 Support F16C built-in functions and code generation. 947 948 mprefetchwt1 949 Target Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save 950 Support PREFETCHWT1 built-in functions and code generation. 951 952 mfentry 953 Target Save Var(flag_fentry) 954 Emit profiling counter call at function entry before prologue. 955 956 mrecord-mcount 957 Target Var(flag_record_mcount) 958 Generate __mcount_loc section with all mcount or __fentry__ calls. 959 960 mnop-mcount 961 Target Var(flag_nop_mcount) 962 Generate mcount/__fentry__ calls as nops. To activate they need to be 963 patched in. 964 965 mfentry-name= 966 Target RejectNegative Joined Var(fentry_name) 967 Set name of __fentry__ symbol called at function entry. 968 969 mfentry-section= 970 Target RejectNegative Joined Var(fentry_section) 971 Set name of section to record mrecord-mcount calls. 972 973 mskip-rax-setup 974 Target Var(flag_skip_rax_setup) 975 Skip setting up RAX register when passing variable arguments. 976 977 m8bit-idiv 978 Target Mask(USE_8BIT_IDIV) Save 979 Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. 980 981 mavx256-split-unaligned-load 982 Target Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 983 Split 32-byte AVX unaligned load. 984 985 mavx256-split-unaligned-store 986 Target Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 987 Split 32-byte AVX unaligned store. 988 989 mrtm 990 Target Mask(ISA_RTM) Var(ix86_isa_flags) Save 991 Support RTM built-in functions and code generation. 992 993 mmpx 994 Target WarnRemoved 995 Removed in GCC 9. This switch has no effect. 996 997 mmwaitx 998 Target Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save 999 Support MWAITX and MONITORX built-in functions and code generation. 1000 1001 mclzero 1002 Target Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save 1003 Support CLZERO built-in functions and code generation. 1004 1005 mpku 1006 Target Mask(ISA_PKU) Var(ix86_isa_flags) Save 1007 Support PKU built-in functions and code generation. 1008 1009 mstack-protector-guard= 1010 Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) 1011 Use given stack-protector guard. 1012 1013 Enum 1014 Name(stack_protector_guard) Type(enum stack_protector_guard) 1015 Known stack protector guard (for use with the -mstack-protector-guard= option): 1016 1017 EnumValue 1018 Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 1019 1020 EnumValue 1021 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 1022 1023 mstack-protector-guard-reg= 1024 Target Save RejectNegative Joined Var(ix86_stack_protector_guard_reg_str) 1025 Use the given base register for addressing the stack-protector guard. 1026 1027 TargetVariable 1028 addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC 1029 1030 mstack-protector-guard-offset= 1031 Target Save RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str) 1032 Use the given offset for addressing the stack-protector guard. 1033 1034 TargetVariable 1035 HOST_WIDE_INT ix86_stack_protector_guard_offset = 0 1036 1037 mstack-protector-guard-symbol= 1038 Target Save RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str) 1039 Use the given symbol for addressing the stack-protector guard. 1040 1041 mmitigate-rop 1042 Target WarnRemoved 1043 1044 mgeneral-regs-only 1045 Target RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save 1046 Generate code which uses only the general registers. 1047 1048 mshstk 1049 Target Mask(ISA_SHSTK) Var(ix86_isa_flags) Save 1050 Enable shadow stack built-in functions from Control-flow Enforcement 1051 Technology (CET). 1052 1053 mcet-switch 1054 Target Undocumented Var(flag_cet_switch) Init(0) 1055 Turn on CET instrumentation for switch statements that use a jump table and 1056 an indirect jump. 1057 1058 mmanual-endbr 1059 Target Var(flag_manual_endbr) Init(0) 1060 Insert ENDBR instruction at function entry only via cf_check attribute 1061 for CET instrumentation. 1062 1063 mforce-indirect-call 1064 Target Var(flag_force_indirect_call) Init(0) 1065 Make all function calls indirect. 1066 1067 mindirect-branch= 1068 Target RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) 1069 Convert indirect call and jump to call and return thunks. 1070 1071 mfunction-return= 1072 Target RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) 1073 Convert function return to call and return thunk. 1074 1075 Enum 1076 Name(indirect_branch) Type(enum indirect_branch) 1077 Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options): 1078 1079 EnumValue 1080 Enum(indirect_branch) String(keep) Value(indirect_branch_keep) 1081 1082 EnumValue 1083 Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk) 1084 1085 EnumValue 1086 Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline) 1087 1088 EnumValue 1089 Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) 1090 1091 mindirect-branch-cs-prefix 1092 Target Var(ix86_indirect_branch_cs_prefix) Init(0) 1093 Add CS prefix to call and jmp to indirect thunk with branch target in r8-r15 registers. 1094 1095 mindirect-branch-register 1096 Target Var(ix86_indirect_branch_register) Init(0) 1097 Force indirect call and jump via register. 1098 1099 mmovdiri 1100 Target Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save 1101 Support MOVDIRI built-in functions and code generation. 1102 1103 mmovdir64b 1104 Target Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save 1105 Support MOVDIR64B built-in functions and code generation. 1106 1107 mwaitpkg 1108 Target Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save 1109 Support WAITPKG built-in functions and code generation. 1110 1111 mcldemote 1112 Target Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save 1113 Support CLDEMOTE built-in functions and code generation. 1114 1115 minstrument-return= 1116 Target RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none) 1117 Instrument function exit in instrumented functions with __fentry__. 1118 1119 Enum 1120 Name(instrument_return) Type(enum instrument_return) 1121 Known choices for return instrumentation with -minstrument-return=: 1122 1123 EnumValue 1124 Enum(instrument_return) String(none) Value(instrument_return_none) 1125 1126 EnumValue 1127 Enum(instrument_return) String(call) Value(instrument_return_call) 1128 1129 EnumValue 1130 Enum(instrument_return) String(nop5) Value(instrument_return_nop5) 1131 1132 mrecord-return 1133 Target Var(ix86_flag_record_return) Init(0) 1134 Generate a __return_loc section pointing to all return instrumentation code. 1135 1136 mharden-sls= 1137 Target RejectNegative Joined Enum(harden_sls) Var(ix86_harden_sls) Init(harden_sls_none) 1138 Generate code to mitigate against straight line speculation. 1139 1140 Enum 1141 Name(harden_sls) Type(enum harden_sls) 1142 Known choices for mitigation against straight line speculation with -mharden-sls=: 1143 1144 EnumValue 1145 Enum(harden_sls) String(none) Value(harden_sls_none) 1146 1147 EnumValue 1148 Enum(harden_sls) String(return) Value(harden_sls_return) 1149 1150 EnumValue 1151 Enum(harden_sls) String(indirect-jmp) Value(harden_sls_indirect_jmp) 1152 1153 EnumValue 1154 Enum(harden_sls) String(all) Value(harden_sls_all) 1155 1156 mavx512bf16 1157 Target Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save 1158 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and 1159 AVX512BF16 built-in functions and code generation. 1160 1161 menqcmd 1162 Target Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save 1163 Support ENQCMD built-in functions and code generation. 1164 1165 mserialize 1166 Target Mask(ISA2_SERIALIZE) Var(ix86_isa_flags2) Save 1167 Support SERIALIZE built-in functions and code generation. 1168 1169 mtsxldtrk 1170 Target Mask(ISA2_TSXLDTRK) Var(ix86_isa_flags2) Save 1171 Support TSXLDTRK built-in functions and code generation. 1172 1173 mamx-tile 1174 Target Mask(ISA2_AMX_TILE) Var(ix86_isa_flags2) Save 1175 Support AMX-TILE built-in functions and code generation. 1176 1177 mamx-int8 1178 Target Mask(ISA2_AMX_INT8) Var(ix86_isa_flags2) Save 1179 Support AMX-INT8 built-in functions and code generation. 1180 1181 mamx-bf16 1182 Target Mask(ISA2_AMX_BF16) Var(ix86_isa_flags2) Save 1183 Support AMX-BF16 built-in functions and code generation. 1184 1185 mhreset 1186 Target Mask(ISA2_HRESET) Var(ix86_isa_flags2) Save 1187 Support HRESET built-in functions and code generation. 1188 1189 mkl 1190 Target Mask(ISA2_KL) Var(ix86_isa_flags2) Save 1191 Support KL built-in functions and code generation. 1192 1193 mwidekl 1194 Target Mask(ISA2_WIDEKL) Var(ix86_isa_flags2) Save 1195 Support WIDEKL built-in functions and code generation. 1196 1197 mavxvnni 1198 Target Mask(ISA2_AVXVNNI) Var(ix86_isa_flags2) Save 1199 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, and 1200 AVXVNNI built-in functions and code generation. 1201 1202 mneeded 1203 Target Var(ix86_needed) Save 1204 Emit GNU_PROPERTY_X86_ISA_1_NEEDED GNU property. 1205 1206 mmwait 1207 Target Mask(ISA2_MWAIT) Var(ix86_isa_flags2) Save 1208 Support MWAIT and MONITOR built-in functions and code generation. 1209 1210 mavx512fp16 1211 Target Mask(ISA2_AVX512FP16) Var(ix86_isa_flags2) Save 1212 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512-FP16 built-in functions and code generation. 1213 1214 mdirect-extern-access 1215 Target Var(ix86_direct_extern_access) Init(1) 1216 Do not use GOT to access external symbols. 1217 1218 -param=x86-stlf-window-ninsns= 1219 Target Joined UInteger Var(x86_stlf_window_ninsns) Init(64) Param 1220 Instructions number above which STFL stall penalty can be compensated. 1221 1222 mgather 1223 Target Alias(mtune-ctrl=, use_gather, ^use_gather) 1224 Enable vectorization for gather instruction. 1225 1226 mscatter 1227 Target Alias(mtune-ctrl=, use_scatter, ^use_scatter) 1228 Enable vectorization for scatter instruction. 1229
Indexes created Tue Apr 28 00:22:25 UTC 2026