i386.opt revision 1.1
1 1.1 mrg ; Options for the IA-32 and AMD64 ports of the compiler. 2 1.1 mrg 3 1.1 mrg ; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc. 4 1.1 mrg ; 5 1.1 mrg ; This file is part of GCC. 6 1.1 mrg ; 7 1.1 mrg ; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ; version. 11 1.1 mrg ; 12 1.1 mrg ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ; for more details. 16 1.1 mrg ; 17 1.1 mrg ; You should have received a copy of the GNU General Public License 18 1.1 mrg ; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.1 mrg ;; Definitions to add to the cl_target_option structure 22 1.1 mrg ;; -march= processor 23 1.1 mrg TargetSave 24 1.1 mrg unsigned char arch 25 1.1 mrg 26 1.1 mrg ;; -mtune= processor 27 1.1 mrg TargetSave 28 1.1 mrg unsigned char tune 29 1.1 mrg 30 1.1 mrg ;; -mfpath= 31 1.1 mrg TargetSave 32 1.1 mrg unsigned char fpmath 33 1.1 mrg 34 1.1 mrg ;; CPU schedule model 35 1.1 mrg TargetSave 36 1.1 mrg unsigned char schedule 37 1.1 mrg 38 1.1 mrg ;; branch cost 39 1.1 mrg TargetSave 40 1.1 mrg unsigned char branch_cost 41 1.1 mrg 42 1.1 mrg ;; which flags were passed by the user 43 1.1 mrg TargetSave 44 1.1 mrg int ix86_isa_flags_explicit 45 1.1 mrg 46 1.1 mrg ;; which flags were passed by the user 47 1.1 mrg TargetSave 48 1.1 mrg int target_flags_explicit 49 1.1 mrg 50 1.1 mrg ;; whether -mtune was not specified 51 1.1 mrg TargetSave 52 1.1 mrg unsigned char tune_defaulted 53 1.1 mrg 54 1.1 mrg ;; whether -march was specified 55 1.1 mrg TargetSave 56 1.1 mrg unsigned char arch_specified 57 1.1 mrg 58 1.1 mrg ;; x86 options 59 1.1 mrg m128bit-long-double 60 1.1 mrg Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save 61 1.1 mrg sizeof(long double) is 16 62 1.1 mrg 63 1.1 mrg m80387 64 1.1 mrg Target Report Mask(80387) Save 65 1.1 mrg Use hardware fp 66 1.1 mrg 67 1.1 mrg m96bit-long-double 68 1.1 mrg Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save 69 1.1 mrg sizeof(long double) is 12 70 1.1 mrg 71 1.1 mrg maccumulate-outgoing-args 72 1.1 mrg Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save 73 1.1 mrg Reserve space for outgoing arguments in the function prologue 74 1.1 mrg 75 1.1 mrg malign-double 76 1.1 mrg Target Report Mask(ALIGN_DOUBLE) Save 77 1.1 mrg Align some doubles on dword boundary 78 1.1 mrg 79 1.1 mrg malign-functions= 80 1.1 mrg Target RejectNegative Joined Var(ix86_align_funcs_string) 81 1.1 mrg Function starts are aligned to this power of 2 82 1.1 mrg 83 1.1 mrg malign-jumps= 84 1.1 mrg Target RejectNegative Joined Var(ix86_align_jumps_string) 85 1.1 mrg Jump targets are aligned to this power of 2 86 1.1 mrg 87 1.1 mrg malign-loops= 88 1.1 mrg Target RejectNegative Joined Var(ix86_align_loops_string) 89 1.1 mrg Loop code aligned to this power of 2 90 1.1 mrg 91 1.1 mrg malign-stringops 92 1.1 mrg Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 93 1.1 mrg Align destination of the string operations 94 1.1 mrg 95 1.1 mrg march= 96 1.1 mrg Target RejectNegative Joined Var(ix86_arch_string) 97 1.1 mrg Generate code for given CPU 98 1.1 mrg 99 1.1 mrg masm= 100 1.1 mrg Target RejectNegative Joined Var(ix86_asm_string) 101 1.1 mrg Use given assembler dialect 102 1.1 mrg 103 1.1 mrg mbranch-cost= 104 1.1 mrg Target RejectNegative Joined Var(ix86_branch_cost_string) 105 1.1 mrg Branches are this expensive (1-5, arbitrary units) 106 1.1 mrg 107 1.1 mrg mlarge-data-threshold= 108 1.1 mrg Target RejectNegative Joined Var(ix86_section_threshold_string) 109 1.1 mrg Data greater than given threshold will go into .ldata section in x86-64 medium model 110 1.1 mrg 111 1.1 mrg mcmodel= 112 1.1 mrg Target RejectNegative Joined Var(ix86_cmodel_string) 113 1.1 mrg Use given x86-64 code model 114 1.1 mrg 115 1.1 mrg mfancy-math-387 116 1.1 mrg Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 117 1.1 mrg Generate sin, cos, sqrt for FPU 118 1.1 mrg 119 1.1 mrg mforce-drap 120 1.1 mrg Target Report Var(ix86_force_drap) 121 1.1 mrg Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack 122 1.1 mrg 123 1.1 mrg mfp-ret-in-387 124 1.1 mrg Target Report Mask(FLOAT_RETURNS) Save 125 1.1 mrg Return values of functions in FPU registers 126 1.1 mrg 127 1.1 mrg mfpmath= 128 1.1 mrg Target RejectNegative Joined Var(ix86_fpmath_string) 129 1.1 mrg Generate floating point mathematics using given instruction set 130 1.1 mrg 131 1.1 mrg mhard-float 132 1.1 mrg Target RejectNegative Mask(80387) MaskExists Save 133 1.1 mrg Use hardware fp 134 1.1 mrg 135 1.1 mrg mieee-fp 136 1.1 mrg Target Report Mask(IEEE_FP) Save 137 1.1 mrg Use IEEE math for fp comparisons 138 1.1 mrg 139 1.1 mrg minline-all-stringops 140 1.1 mrg Target Report Mask(INLINE_ALL_STRINGOPS) Save 141 1.1 mrg Inline all known string operations 142 1.1 mrg 143 1.1 mrg minline-stringops-dynamically 144 1.1 mrg Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 145 1.1 mrg Inline memset/memcpy string operations, but perform inline version only for small blocks 146 1.1 mrg 147 1.1 mrg mintel-syntax 148 1.1 mrg Target Undocumented 149 1.1 mrg ;; Deprecated 150 1.1 mrg 151 1.1 mrg mms-bitfields 152 1.1 mrg Target Report Mask(MS_BITFIELD_LAYOUT) Save 153 1.1 mrg Use native (MS) bitfield layout 154 1.1 mrg 155 1.1 mrg mno-align-stringops 156 1.1 mrg Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save 157 1.1 mrg 158 1.1 mrg mno-fancy-math-387 159 1.1 mrg Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save 160 1.1 mrg 161 1.1 mrg mno-push-args 162 1.1 mrg Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save 163 1.1 mrg 164 1.1 mrg mno-red-zone 165 1.1 mrg Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save 166 1.1 mrg 167 1.1 mrg momit-leaf-frame-pointer 168 1.1 mrg Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save 169 1.1 mrg Omit the frame pointer in leaf functions 170 1.1 mrg 171 1.1 mrg mpc 172 1.1 mrg Target RejectNegative Report Joined Var(ix87_precision_string) 173 1.1 mrg Set 80387 floating-point precision (-mpc32, -mpc64, -mpc80) 174 1.1 mrg 175 1.1 mrg mpreferred-stack-boundary= 176 1.1 mrg Target RejectNegative Joined Var(ix86_preferred_stack_boundary_string) 177 1.1 mrg Attempt to keep stack aligned to this power of 2 178 1.1 mrg 179 1.1 mrg mincoming-stack-boundary= 180 1.1 mrg Target RejectNegative Joined Var(ix86_incoming_stack_boundary_string) 181 1.1 mrg Assume incoming stack aligned to this power of 2 182 1.1 mrg 183 1.1 mrg mpush-args 184 1.1 mrg Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 185 1.1 mrg Use push instructions to save outgoing arguments 186 1.1 mrg 187 1.1 mrg mred-zone 188 1.1 mrg Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save 189 1.1 mrg Use red-zone in the x86-64 code 190 1.1 mrg 191 1.1 mrg mregparm= 192 1.1 mrg Target RejectNegative Joined Var(ix86_regparm_string) 193 1.1 mrg Number of registers used to pass integer arguments 194 1.1 mrg 195 1.1 mrg mrtd 196 1.1 mrg Target Report Mask(RTD) Save 197 1.1 mrg Alternate calling convention 198 1.1 mrg 199 1.1 mrg msoft-float 200 1.1 mrg Target InverseMask(80387) Save 201 1.1 mrg Do not use hardware fp 202 1.1 mrg 203 1.1 mrg msseregparm 204 1.1 mrg Target RejectNegative Mask(SSEREGPARM) Save 205 1.1 mrg Use SSE register passing conventions for SF and DF mode 206 1.1 mrg 207 1.1 mrg mstackrealign 208 1.1 mrg Target Report Var(ix86_force_align_arg_pointer) Init(-1) 209 1.1 mrg Realign stack in prologue 210 1.1 mrg 211 1.1 mrg mstack-arg-probe 212 1.1 mrg Target Report Mask(STACK_PROBE) Save 213 1.1 mrg Enable stack probing 214 1.1 mrg 215 1.1 mrg mstringop-strategy= 216 1.1 mrg Target RejectNegative Joined Var(ix86_stringop_string) 217 1.1 mrg Chose strategy to generate stringop using 218 1.1 mrg 219 1.1 mrg mtls-dialect= 220 1.1 mrg Target RejectNegative Joined Var(ix86_tls_dialect_string) 221 1.1 mrg Use given thread-local storage dialect 222 1.1 mrg 223 1.1 mrg mtls-direct-seg-refs 224 1.1 mrg Target Report Mask(TLS_DIRECT_SEG_REFS) 225 1.1 mrg Use direct references against %gs when accessing tls data 226 1.1 mrg 227 1.1 mrg mtune= 228 1.1 mrg Target RejectNegative Joined Var(ix86_tune_string) 229 1.1 mrg Schedule code for given CPU 230 1.1 mrg 231 1.1 mrg mabi= 232 1.1 mrg Target RejectNegative Joined Var(ix86_abi_string) 233 1.1 mrg Generate code that conforms to the given ABI 234 1.1 mrg 235 1.1 mrg mveclibabi= 236 1.1 mrg Target RejectNegative Joined Var(ix86_veclibabi_string) 237 1.1 mrg Vector library ABI to use 238 1.1 mrg 239 1.1 mrg mrecip 240 1.1 mrg Target Report Mask(RECIP) Save 241 1.1 mrg Generate reciprocals instead of divss and sqrtss. 242 1.1 mrg 243 1.1 mrg mcld 244 1.1 mrg Target Report Mask(CLD) Save 245 1.1 mrg Generate cld instruction in the function prologue. 246 1.1 mrg 247 1.1 mrg mfused-madd 248 1.1 mrg Target Report Mask(FUSED_MADD) Save 249 1.1 mrg Enable automatic generation of fused floating point multiply-add instructions 250 1.1 mrg if the ISA supports such instructions. The -mfused-madd option is on by 251 1.1 mrg default. 252 1.1 mrg 253 1.1 mrg ;; ISA support 254 1.1 mrg 255 1.1 mrg m32 256 1.1 mrg Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save 257 1.1 mrg Generate 32bit i386 code 258 1.1 mrg 259 1.1 mrg m64 260 1.1 mrg Target RejectNegative Negative(m32) Report Mask(ISA_64BIT) Var(ix86_isa_flags) VarExists Save 261 1.1 mrg Generate 64bit x86-64 code 262 1.1 mrg 263 1.1 mrg mmmx 264 1.1 mrg Target Report Mask(ISA_MMX) Var(ix86_isa_flags) VarExists Save 265 1.1 mrg Support MMX built-in functions 266 1.1 mrg 267 1.1 mrg m3dnow 268 1.1 mrg Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) VarExists Save 269 1.1 mrg Support 3DNow! built-in functions 270 1.1 mrg 271 1.1 mrg m3dnowa 272 1.1 mrg Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) VarExists Save 273 1.1 mrg Support Athlon 3Dnow! built-in functions 274 1.1 mrg 275 1.1 mrg msse 276 1.1 mrg Target Report Mask(ISA_SSE) Var(ix86_isa_flags) VarExists Save 277 1.1 mrg Support MMX and SSE built-in functions and code generation 278 1.1 mrg 279 1.1 mrg msse2 280 1.1 mrg Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) VarExists Save 281 1.1 mrg Support MMX, SSE and SSE2 built-in functions and code generation 282 1.1 mrg 283 1.1 mrg msse3 284 1.1 mrg Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) VarExists Save 285 1.1 mrg Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation 286 1.1 mrg 287 1.1 mrg mssse3 288 1.1 mrg Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) VarExists Save 289 1.1 mrg Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation 290 1.1 mrg 291 1.1 mrg msse4.1 292 1.1 mrg Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) VarExists Save 293 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation 294 1.1 mrg 295 1.1 mrg msse4.2 296 1.1 mrg Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) VarExists Save 297 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 298 1.1 mrg 299 1.1 mrg msse4 300 1.1 mrg Target RejectNegative Report Mask(ISA_SSE4_2) MaskExists Var(ix86_isa_flags) VarExists Save 301 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 302 1.1 mrg 303 1.1 mrg mno-sse4 304 1.1 mrg Target RejectNegative Report InverseMask(ISA_SSE4_1) MaskExists Var(ix86_isa_flags) VarExists Save 305 1.1 mrg Do not support SSE4.1 and SSE4.2 built-in functions and code generation 306 1.1 mrg 307 1.1 mrg mavx 308 1.1 mrg Target Report Mask(ISA_AVX) Var(ix86_isa_flags) VarExists Save 309 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation 310 1.1 mrg 311 1.1 mrg mfma 312 1.1 mrg Target Report Mask(ISA_FMA) Var(ix86_isa_flags) VarExists Save 313 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation 314 1.1 mrg 315 1.1 mrg msse4a 316 1.1 mrg Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save 317 1.1 mrg Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation 318 1.1 mrg 319 1.1 mrg mfma4 320 1.1 mrg Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) VarExists Save 321 1.1 mrg Support FMA4 built-in functions and code generation 322 1.1 mrg 323 1.1 mrg mxop 324 1.1 mrg Target Report Mask(ISA_XOP) Var(ix86_isa_flags) VarExists Save 325 1.1 mrg Support XOP built-in functions and code generation 326 1.1 mrg 327 1.1 mrg mlwp 328 1.1 mrg Target Report Mask(ISA_LWP) Var(ix86_isa_flags) VarExists Save 329 1.1 mrg Support LWP built-in functions and code generation 330 1.1 mrg 331 1.1 mrg mabm 332 1.1 mrg Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save 333 1.1 mrg Support code generation of Advanced Bit Manipulation (ABM) instructions. 334 1.1 mrg 335 1.1 mrg mpopcnt 336 1.1 mrg Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) VarExists Save 337 1.1 mrg Support code generation of popcnt instruction. 338 1.1 mrg 339 1.1 mrg mcx16 340 1.1 mrg Target Report Mask(ISA_CX16) Var(ix86_isa_flags) VarExists Save 341 1.1 mrg Support code generation of cmpxchg16b instruction. 342 1.1 mrg 343 1.1 mrg msahf 344 1.1 mrg Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save 345 1.1 mrg Support code generation of sahf instruction in 64bit x86-64 code. 346 1.1 mrg 347 1.1 mrg mmovbe 348 1.1 mrg Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save 349 1.1 mrg Support code generation of movbe instruction. 350 1.1 mrg 351 1.1 mrg mcrc32 352 1.1 mrg Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) VarExists Save 353 1.1 mrg Support code generation of crc32 instruction. 354 1.1 mrg 355 1.1 mrg maes 356 1.1 mrg Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save 357 1.1 mrg Support AES built-in functions and code generation 358 1.1 mrg 359 1.1 mrg mpclmul 360 1.1 mrg Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) VarExists Save 361 1.1 mrg Support PCLMUL built-in functions and code generation 362 1.1 mrg 363 1.1 mrg msse2avx 364 1.1 mrg Target Report Var(ix86_sse2avx) 365 1.1 mrg Encode SSE instructions with VEX prefix 366
Indexes created Wed Apr 29 00:23:26 UTC 2026