i386.opt revision 1.10
1 1.1 mrg ; Options for the IA-32 and AMD64 ports of the compiler. 2 1.1 mrg 3 1.10 mrg ; Copyright (C) 2005-2017 Free Software Foundation, Inc. 4 1.1 mrg ; 5 1.1 mrg ; This file is part of GCC. 6 1.1 mrg ; 7 1.1 mrg ; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ; version. 11 1.1 mrg ; 12 1.1 mrg ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ; for more details. 16 1.1 mrg ; 17 1.1 mrg ; You should have received a copy of the GNU General Public License 18 1.1 mrg ; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.3 mrg HeaderInclude 22 1.3 mrg config/i386/i386-opts.h 23 1.3 mrg 24 1.3 mrg ; Bit flags that specify the ISA we are compiling for. 25 1.3 mrg Variable 26 1.3 mrg HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 1.3 mrg 28 1.10 mrg Variable 29 1.10 mrg HOST_WIDE_INT ix86_isa_flags2 = 0 30 1.10 mrg 31 1.3 mrg ; A mask of ix86_isa_flags that includes bit X if X was set or cleared 32 1.3 mrg ; on the command line. 33 1.3 mrg Variable 34 1.3 mrg HOST_WIDE_INT ix86_isa_flags_explicit 35 1.3 mrg 36 1.10 mrg Variable 37 1.10 mrg HOST_WIDE_INT ix86_isa_flags2_explicit 38 1.10 mrg 39 1.10 mrg ; Additional target flags 40 1.10 mrg Variable 41 1.10 mrg int ix86_target_flags 42 1.10 mrg 43 1.3 mrg TargetVariable 44 1.3 mrg int recip_mask = RECIP_MASK_DEFAULT 45 1.3 mrg 46 1.3 mrg Variable 47 1.3 mrg int recip_mask_explicit 48 1.3 mrg 49 1.3 mrg TargetSave 50 1.3 mrg int x_recip_mask_explicit 51 1.3 mrg 52 1.1 mrg ;; Definitions to add to the cl_target_option structure 53 1.1 mrg ;; -march= processor 54 1.1 mrg TargetSave 55 1.1 mrg unsigned char arch 56 1.1 mrg 57 1.1 mrg ;; -mtune= processor 58 1.1 mrg TargetSave 59 1.1 mrg unsigned char tune 60 1.1 mrg 61 1.5 mrg ;; -march= processor-string 62 1.5 mrg TargetSave 63 1.5 mrg const char *x_ix86_arch_string 64 1.5 mrg 65 1.5 mrg ;; -mtune= processor-string 66 1.5 mrg TargetSave 67 1.5 mrg const char *x_ix86_tune_string 68 1.5 mrg 69 1.1 mrg ;; CPU schedule model 70 1.1 mrg TargetSave 71 1.1 mrg unsigned char schedule 72 1.1 mrg 73 1.5 mrg ;; True if processor has SSE prefetch instruction. 74 1.5 mrg TargetSave 75 1.5 mrg unsigned char prefetch_sse 76 1.5 mrg 77 1.1 mrg ;; branch cost 78 1.1 mrg TargetSave 79 1.1 mrg unsigned char branch_cost 80 1.1 mrg 81 1.1 mrg ;; which flags were passed by the user 82 1.1 mrg TargetSave 83 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags2_explicit 84 1.5 mrg 85 1.5 mrg ;; which flags were passed by the user 86 1.1 mrg TargetSave 87 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags_explicit 88 1.1 mrg 89 1.1 mrg ;; whether -mtune was not specified 90 1.1 mrg TargetSave 91 1.1 mrg unsigned char tune_defaulted 92 1.1 mrg 93 1.1 mrg ;; whether -march was specified 94 1.1 mrg TargetSave 95 1.1 mrg unsigned char arch_specified 96 1.1 mrg 97 1.5 mrg ;; -mcmodel= model 98 1.5 mrg TargetSave 99 1.5 mrg enum cmodel x_ix86_cmodel 100 1.5 mrg 101 1.5 mrg ;; -mabi= 102 1.5 mrg TargetSave 103 1.5 mrg enum calling_abi x_ix86_abi 104 1.5 mrg 105 1.5 mrg ;; -masm= 106 1.5 mrg TargetSave 107 1.5 mrg enum asm_dialect x_ix86_asm_dialect 108 1.5 mrg 109 1.5 mrg ;; -mbranch-cost= 110 1.5 mrg TargetSave 111 1.5 mrg int x_ix86_branch_cost 112 1.5 mrg 113 1.8 mrg ;; -mdump-tune-features= 114 1.5 mrg TargetSave 115 1.5 mrg int x_ix86_dump_tunes 116 1.5 mrg 117 1.5 mrg ;; -mstackrealign= 118 1.5 mrg TargetSave 119 1.5 mrg int x_ix86_force_align_arg_pointer 120 1.5 mrg 121 1.8 mrg ;; -mforce-drap= 122 1.5 mrg TargetSave 123 1.5 mrg int x_ix86_force_drap 124 1.5 mrg 125 1.5 mrg ;; -mincoming-stack-boundary= 126 1.5 mrg TargetSave 127 1.5 mrg int x_ix86_incoming_stack_boundary_arg 128 1.5 mrg 129 1.5 mrg ;; -maddress-mode= 130 1.5 mrg TargetSave 131 1.5 mrg enum pmode x_ix86_pmode 132 1.5 mrg 133 1.8 mrg ;; -mpreferred-stack-boundary= 134 1.5 mrg TargetSave 135 1.5 mrg int x_ix86_preferred_stack_boundary_arg 136 1.5 mrg 137 1.5 mrg ;; -mrecip= 138 1.5 mrg TargetSave 139 1.5 mrg const char *x_ix86_recip_name 140 1.5 mrg 141 1.5 mrg ;; -mregparm= 142 1.5 mrg TargetSave 143 1.5 mrg int x_ix86_regparm 144 1.5 mrg 145 1.5 mrg ;; -mlarge-data-threshold= 146 1.5 mrg TargetSave 147 1.5 mrg int x_ix86_section_threshold 148 1.5 mrg 149 1.5 mrg ;; -msse2avx= 150 1.5 mrg TargetSave 151 1.5 mrg int x_ix86_sse2avx 152 1.5 mrg 153 1.5 mrg ;; -mstack-protector-guard= 154 1.5 mrg TargetSave 155 1.5 mrg enum stack_protector_guard x_ix86_stack_protector_guard 156 1.5 mrg 157 1.5 mrg ;; -mstringop-strategy= 158 1.5 mrg TargetSave 159 1.5 mrg enum stringop_alg x_ix86_stringop_alg 160 1.5 mrg 161 1.5 mrg ;; -mtls-dialect= 162 1.5 mrg TargetSave 163 1.5 mrg enum tls_dialect x_ix86_tls_dialect 164 1.5 mrg 165 1.5 mrg ;; -mtune-ctrl= 166 1.5 mrg TargetSave 167 1.5 mrg const char *x_ix86_tune_ctrl_string 168 1.5 mrg 169 1.5 mrg ;; -mmemcpy-strategy= 170 1.5 mrg TargetSave 171 1.5 mrg const char *x_ix86_tune_memcpy_strategy 172 1.5 mrg 173 1.5 mrg ;; -mmemset-strategy= 174 1.5 mrg TargetSave 175 1.5 mrg const char *x_ix86_tune_memset_strategy 176 1.5 mrg 177 1.5 mrg ;; -mno-default= 178 1.5 mrg TargetSave 179 1.5 mrg int x_ix86_tune_no_default 180 1.5 mrg 181 1.5 mrg ;; -mveclibabi= 182 1.5 mrg TargetSave 183 1.5 mrg enum ix86_veclibabi x_ix86_veclibabi_type 184 1.5 mrg 185 1.1 mrg ;; x86 options 186 1.1 mrg m128bit-long-double 187 1.1 mrg Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save 188 1.8 mrg sizeof(long double) is 16. 189 1.1 mrg 190 1.1 mrg m80387 191 1.1 mrg Target Report Mask(80387) Save 192 1.8 mrg Use hardware fp. 193 1.1 mrg 194 1.1 mrg m96bit-long-double 195 1.1 mrg Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save 196 1.8 mrg sizeof(long double) is 12. 197 1.1 mrg 198 1.3 mrg mlong-double-80 199 1.5 mrg Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save 200 1.8 mrg Use 80-bit long double. 201 1.3 mrg 202 1.3 mrg mlong-double-64 203 1.5 mrg Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save 204 1.8 mrg Use 64-bit long double. 205 1.3 mrg 206 1.5 mrg mlong-double-128 207 1.5 mrg Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save 208 1.8 mrg Use 128-bit long double. 209 1.5 mrg 210 1.1 mrg maccumulate-outgoing-args 211 1.1 mrg Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save 212 1.8 mrg Reserve space for outgoing arguments in the function prologue. 213 1.1 mrg 214 1.1 mrg malign-double 215 1.1 mrg Target Report Mask(ALIGN_DOUBLE) Save 216 1.8 mrg Align some doubles on dword boundary. 217 1.1 mrg 218 1.1 mrg malign-functions= 219 1.3 mrg Target RejectNegative Joined UInteger 220 1.8 mrg Function starts are aligned to this power of 2. 221 1.1 mrg 222 1.1 mrg malign-jumps= 223 1.3 mrg Target RejectNegative Joined UInteger 224 1.8 mrg Jump targets are aligned to this power of 2. 225 1.1 mrg 226 1.1 mrg malign-loops= 227 1.3 mrg Target RejectNegative Joined UInteger 228 1.8 mrg Loop code aligned to this power of 2. 229 1.1 mrg 230 1.1 mrg malign-stringops 231 1.1 mrg Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 232 1.8 mrg Align destination of the string operations. 233 1.1 mrg 234 1.5 mrg malign-data= 235 1.5 mrg Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) 236 1.8 mrg Use the given data alignment. 237 1.5 mrg 238 1.5 mrg Enum 239 1.5 mrg Name(ix86_align_data) Type(enum ix86_align_data) 240 1.5 mrg Known data alignment choices (for use with the -malign-data= option): 241 1.5 mrg 242 1.5 mrg EnumValue 243 1.5 mrg Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat) 244 1.5 mrg 245 1.5 mrg EnumValue 246 1.5 mrg Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi) 247 1.5 mrg 248 1.5 mrg EnumValue 249 1.5 mrg Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) 250 1.5 mrg 251 1.1 mrg march= 252 1.1 mrg Target RejectNegative Joined Var(ix86_arch_string) 253 1.8 mrg Generate code for given CPU. 254 1.1 mrg 255 1.1 mrg masm= 256 1.3 mrg Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 257 1.8 mrg Use given assembler dialect. 258 1.1 mrg 259 1.3 mrg Enum 260 1.3 mrg Name(asm_dialect) Type(enum asm_dialect) 261 1.10 mrg Known assembler dialects (for use with the -masm= option): 262 1.3 mrg 263 1.3 mrg EnumValue 264 1.3 mrg Enum(asm_dialect) String(intel) Value(ASM_INTEL) 265 1.3 mrg 266 1.3 mrg EnumValue 267 1.3 mrg Enum(asm_dialect) String(att) Value(ASM_ATT) 268 1.3 mrg 269 1.1 mrg mbranch-cost= 270 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_branch_cost) 271 1.8 mrg Branches are this expensive (1-5, arbitrary units). 272 1.1 mrg 273 1.1 mrg mlarge-data-threshold= 274 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 275 1.10 mrg -mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model. 276 1.1 mrg 277 1.1 mrg mcmodel= 278 1.3 mrg Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 279 1.8 mrg Use given x86-64 code model. 280 1.1 mrg 281 1.3 mrg Enum 282 1.3 mrg Name(cmodel) Type(enum cmodel) 283 1.3 mrg Known code models (for use with the -mcmodel= option): 284 1.3 mrg 285 1.3 mrg EnumValue 286 1.3 mrg Enum(cmodel) String(small) Value(CM_SMALL) 287 1.3 mrg 288 1.3 mrg EnumValue 289 1.3 mrg Enum(cmodel) String(medium) Value(CM_MEDIUM) 290 1.3 mrg 291 1.3 mrg EnumValue 292 1.3 mrg Enum(cmodel) String(large) Value(CM_LARGE) 293 1.3 mrg 294 1.3 mrg EnumValue 295 1.3 mrg Enum(cmodel) String(32) Value(CM_32) 296 1.3 mrg 297 1.3 mrg EnumValue 298 1.3 mrg Enum(cmodel) String(kernel) Value(CM_KERNEL) 299 1.3 mrg 300 1.3 mrg maddress-mode= 301 1.3 mrg Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 302 1.8 mrg Use given address mode. 303 1.3 mrg 304 1.3 mrg Enum 305 1.3 mrg Name(pmode) Type(enum pmode) 306 1.3 mrg Known address mode (for use with the -maddress-mode= option): 307 1.3 mrg 308 1.3 mrg EnumValue 309 1.3 mrg Enum(pmode) String(short) Value(PMODE_SI) 310 1.3 mrg 311 1.3 mrg EnumValue 312 1.3 mrg Enum(pmode) String(long) Value(PMODE_DI) 313 1.3 mrg 314 1.3 mrg mcpu= 315 1.3 mrg Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 316 1.3 mrg 317 1.1 mrg mfancy-math-387 318 1.1 mrg Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 319 1.8 mrg Generate sin, cos, sqrt for FPU. 320 1.1 mrg 321 1.1 mrg mforce-drap 322 1.1 mrg Target Report Var(ix86_force_drap) 323 1.8 mrg Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. 324 1.1 mrg 325 1.1 mrg mfp-ret-in-387 326 1.1 mrg Target Report Mask(FLOAT_RETURNS) Save 327 1.8 mrg Return values of functions in FPU registers. 328 1.1 mrg 329 1.1 mrg mfpmath= 330 1.3 mrg Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 331 1.8 mrg Generate floating point mathematics using given instruction set. 332 1.1 mrg 333 1.3 mrg Enum 334 1.3 mrg Name(fpmath_unit) Type(enum fpmath_unit) 335 1.3 mrg Valid arguments to -mfpmath=: 336 1.3 mrg 337 1.3 mrg EnumValue 338 1.3 mrg Enum(fpmath_unit) String(387) Value(FPMATH_387) 339 1.3 mrg 340 1.3 mrg EnumValue 341 1.3 mrg Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 342 1.3 mrg 343 1.3 mrg EnumValue 344 1.3 mrg Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 345 1.3 mrg 346 1.3 mrg EnumValue 347 1.3 mrg Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 348 1.3 mrg 349 1.3 mrg EnumValue 350 1.3 mrg Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 351 1.3 mrg 352 1.3 mrg EnumValue 353 1.3 mrg Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 354 1.3 mrg 355 1.3 mrg EnumValue 356 1.3 mrg Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 357 1.3 mrg 358 1.1 mrg mhard-float 359 1.3 mrg Target RejectNegative Mask(80387) Save 360 1.8 mrg Use hardware fp. 361 1.1 mrg 362 1.1 mrg mieee-fp 363 1.1 mrg Target Report Mask(IEEE_FP) Save 364 1.8 mrg Use IEEE math for fp comparisons. 365 1.1 mrg 366 1.1 mrg minline-all-stringops 367 1.1 mrg Target Report Mask(INLINE_ALL_STRINGOPS) Save 368 1.8 mrg Inline all known string operations. 369 1.1 mrg 370 1.1 mrg minline-stringops-dynamically 371 1.1 mrg Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 372 1.8 mrg Inline memset/memcpy string operations, but perform inline version only for small blocks. 373 1.1 mrg 374 1.1 mrg mintel-syntax 375 1.3 mrg Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 376 1.1 mrg ;; Deprecated 377 1.1 mrg 378 1.1 mrg mms-bitfields 379 1.1 mrg Target Report Mask(MS_BITFIELD_LAYOUT) Save 380 1.8 mrg Use native (MS) bitfield layout. 381 1.1 mrg 382 1.1 mrg mno-align-stringops 383 1.1 mrg Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save 384 1.1 mrg 385 1.1 mrg mno-fancy-math-387 386 1.1 mrg Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save 387 1.1 mrg 388 1.1 mrg mno-push-args 389 1.1 mrg Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save 390 1.1 mrg 391 1.1 mrg mno-red-zone 392 1.1 mrg Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save 393 1.1 mrg 394 1.1 mrg momit-leaf-frame-pointer 395 1.1 mrg Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save 396 1.8 mrg Omit the frame pointer in leaf functions. 397 1.1 mrg 398 1.3 mrg mpc32 399 1.3 mrg Target RejectNegative Report 400 1.8 mrg Set 80387 floating-point precision to 32-bit. 401 1.3 mrg 402 1.3 mrg mpc64 403 1.3 mrg Target RejectNegative Report 404 1.8 mrg Set 80387 floating-point precision to 64-bit. 405 1.3 mrg 406 1.3 mrg mpc80 407 1.3 mrg Target RejectNegative Report 408 1.8 mrg Set 80387 floating-point precision to 80-bit. 409 1.1 mrg 410 1.1 mrg mpreferred-stack-boundary= 411 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 412 1.8 mrg Attempt to keep stack aligned to this power of 2. 413 1.1 mrg 414 1.1 mrg mincoming-stack-boundary= 415 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 416 1.8 mrg Assume incoming stack aligned to this power of 2. 417 1.1 mrg 418 1.1 mrg mpush-args 419 1.1 mrg Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 420 1.8 mrg Use push instructions to save outgoing arguments. 421 1.1 mrg 422 1.1 mrg mred-zone 423 1.1 mrg Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save 424 1.8 mrg Use red-zone in the x86-64 code. 425 1.1 mrg 426 1.1 mrg mregparm= 427 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_regparm) 428 1.8 mrg Number of registers used to pass integer arguments. 429 1.1 mrg 430 1.1 mrg mrtd 431 1.1 mrg Target Report Mask(RTD) Save 432 1.8 mrg Alternate calling convention. 433 1.1 mrg 434 1.1 mrg msoft-float 435 1.1 mrg Target InverseMask(80387) Save 436 1.8 mrg Do not use hardware fp. 437 1.1 mrg 438 1.1 mrg msseregparm 439 1.1 mrg Target RejectNegative Mask(SSEREGPARM) Save 440 1.8 mrg Use SSE register passing conventions for SF and DF mode. 441 1.1 mrg 442 1.1 mrg mstackrealign 443 1.1 mrg Target Report Var(ix86_force_align_arg_pointer) Init(-1) 444 1.8 mrg Realign stack in prologue. 445 1.1 mrg 446 1.1 mrg mstack-arg-probe 447 1.1 mrg Target Report Mask(STACK_PROBE) Save 448 1.8 mrg Enable stack probing. 449 1.1 mrg 450 1.5 mrg mmemcpy-strategy= 451 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) 452 1.8 mrg Specify memcpy expansion strategy when expected size is known. 453 1.5 mrg 454 1.5 mrg mmemset-strategy= 455 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memset_strategy) 456 1.8 mrg Specify memset expansion strategy when expected size is known. 457 1.5 mrg 458 1.1 mrg mstringop-strategy= 459 1.3 mrg Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 460 1.8 mrg Chose strategy to generate stringop using. 461 1.1 mrg 462 1.3 mrg Enum 463 1.3 mrg Name(stringop_alg) Type(enum stringop_alg) 464 1.3 mrg Valid arguments to -mstringop-strategy=: 465 1.3 mrg 466 1.3 mrg EnumValue 467 1.3 mrg Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 468 1.3 mrg 469 1.3 mrg EnumValue 470 1.3 mrg Enum(stringop_alg) String(libcall) Value(libcall) 471 1.3 mrg 472 1.3 mrg EnumValue 473 1.3 mrg Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 474 1.3 mrg 475 1.3 mrg EnumValue 476 1.3 mrg Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 477 1.3 mrg 478 1.3 mrg EnumValue 479 1.3 mrg Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 480 1.3 mrg 481 1.3 mrg EnumValue 482 1.3 mrg Enum(stringop_alg) String(loop) Value(loop) 483 1.3 mrg 484 1.3 mrg EnumValue 485 1.3 mrg Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 486 1.3 mrg 487 1.5 mrg EnumValue 488 1.5 mrg Enum(stringop_alg) String(vector_loop) Value(vector_loop) 489 1.5 mrg 490 1.1 mrg mtls-dialect= 491 1.3 mrg Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 492 1.8 mrg Use given thread-local storage dialect. 493 1.1 mrg 494 1.3 mrg Enum 495 1.3 mrg Name(tls_dialect) Type(enum tls_dialect) 496 1.3 mrg Known TLS dialects (for use with the -mtls-dialect= option): 497 1.3 mrg 498 1.3 mrg EnumValue 499 1.3 mrg Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 500 1.3 mrg 501 1.3 mrg EnumValue 502 1.3 mrg Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 503 1.3 mrg 504 1.1 mrg mtls-direct-seg-refs 505 1.1 mrg Target Report Mask(TLS_DIRECT_SEG_REFS) 506 1.8 mrg Use direct references against %gs when accessing tls data. 507 1.1 mrg 508 1.1 mrg mtune= 509 1.1 mrg Target RejectNegative Joined Var(ix86_tune_string) 510 1.8 mrg Schedule code for given CPU. 511 1.1 mrg 512 1.5 mrg mtune-ctrl= 513 1.5 mrg Target RejectNegative Joined Var(ix86_tune_ctrl_string) 514 1.8 mrg Fine grain control of tune features. 515 1.5 mrg 516 1.5 mrg mno-default 517 1.5 mrg Target RejectNegative Var(ix86_tune_no_default) Init(0) 518 1.8 mrg Clear all tune features. 519 1.5 mrg 520 1.5 mrg mdump-tune-features 521 1.5 mrg Target RejectNegative Var(ix86_dump_tunes) Init(0) 522 1.5 mrg 523 1.8 mrg miamcu 524 1.8 mrg Target Report Mask(IAMCU) 525 1.8 mrg Generate code that conforms to Intel MCU psABI. 526 1.8 mrg 527 1.1 mrg mabi= 528 1.3 mrg Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 529 1.8 mrg Generate code that conforms to the given ABI. 530 1.1 mrg 531 1.3 mrg Enum 532 1.3 mrg Name(calling_abi) Type(enum calling_abi) 533 1.3 mrg Known ABIs (for use with the -mabi= option): 534 1.3 mrg 535 1.3 mrg EnumValue 536 1.3 mrg Enum(calling_abi) String(sysv) Value(SYSV_ABI) 537 1.3 mrg 538 1.3 mrg EnumValue 539 1.3 mrg Enum(calling_abi) String(ms) Value(MS_ABI) 540 1.3 mrg 541 1.1 mrg mveclibabi= 542 1.3 mrg Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 543 1.8 mrg Vector library ABI to use. 544 1.1 mrg 545 1.3 mrg Enum 546 1.3 mrg Name(ix86_veclibabi) Type(enum ix86_veclibabi) 547 1.3 mrg Known vectorization library ABIs (for use with the -mveclibabi= option): 548 1.3 mrg 549 1.3 mrg EnumValue 550 1.3 mrg Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 551 1.3 mrg 552 1.3 mrg EnumValue 553 1.3 mrg Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 554 1.3 mrg 555 1.3 mrg mvect8-ret-in-mem 556 1.3 mrg Target Report Mask(VECT8_RETURNS) Save 557 1.8 mrg Return 8-byte vectors in memory. 558 1.3 mrg 559 1.1 mrg mrecip 560 1.1 mrg Target Report Mask(RECIP) Save 561 1.1 mrg Generate reciprocals instead of divss and sqrtss. 562 1.1 mrg 563 1.3 mrg mrecip= 564 1.3 mrg Target Report RejectNegative Joined Var(ix86_recip_name) 565 1.3 mrg Control generation of reciprocal estimates. 566 1.3 mrg 567 1.1 mrg mcld 568 1.1 mrg Target Report Mask(CLD) Save 569 1.1 mrg Generate cld instruction in the function prologue. 570 1.1 mrg 571 1.3 mrg mvzeroupper 572 1.3 mrg Target Report Mask(VZEROUPPER) Save 573 1.3 mrg Generate vzeroupper instruction before a transfer of control flow out of 574 1.3 mrg the function. 575 1.3 mrg 576 1.8 mrg mstv 577 1.8 mrg Target Report Mask(STV) Save 578 1.8 mrg Disable Scalar to Vector optimization pass transforming 64-bit integer 579 1.8 mrg computations into a vector ones. 580 1.8 mrg 581 1.3 mrg mdispatch-scheduler 582 1.3 mrg Target RejectNegative Var(flag_dispatch_scheduler) 583 1.8 mrg Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4 584 1.8 mrg or znver1 and Haifa scheduling is selected. 585 1.3 mrg 586 1.3 mrg mprefer-avx128 587 1.3 mrg Target Report Mask(PREFER_AVX128) SAVE 588 1.3 mrg Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 589 1.1 mrg 590 1.1 mrg ;; ISA support 591 1.1 mrg 592 1.1 mrg m32 593 1.3 mrg Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 594 1.8 mrg Generate 32bit i386 code. 595 1.1 mrg 596 1.1 mrg m64 597 1.3 mrg Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save 598 1.8 mrg Generate 64bit x86-64 code. 599 1.1 mrg 600 1.3 mrg mx32 601 1.5 mrg Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save 602 1.8 mrg Generate 32bit x86-64 code. 603 1.3 mrg 604 1.5 mrg m16 605 1.5 mrg Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 606 1.8 mrg Generate 16bit i386 code. 607 1.5 mrg 608 1.1 mrg mmmx 609 1.3 mrg Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save 610 1.8 mrg Support MMX built-in functions. 611 1.1 mrg 612 1.1 mrg m3dnow 613 1.3 mrg Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 614 1.8 mrg Support 3DNow! built-in functions. 615 1.1 mrg 616 1.1 mrg m3dnowa 617 1.10 mrg Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 618 1.8 mrg Support Athlon 3Dnow! built-in functions. 619 1.1 mrg 620 1.1 mrg msse 621 1.3 mrg Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save 622 1.8 mrg Support MMX and SSE built-in functions and code generation. 623 1.1 mrg 624 1.1 mrg msse2 625 1.3 mrg Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save 626 1.8 mrg Support MMX, SSE and SSE2 built-in functions and code generation. 627 1.1 mrg 628 1.1 mrg msse3 629 1.3 mrg Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save 630 1.8 mrg Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. 631 1.1 mrg 632 1.1 mrg mssse3 633 1.3 mrg Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 634 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. 635 1.1 mrg 636 1.1 mrg msse4.1 637 1.3 mrg Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 638 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. 639 1.1 mrg 640 1.1 mrg msse4.2 641 1.3 mrg Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 642 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 643 1.1 mrg 644 1.1 mrg msse4 645 1.3 mrg Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 646 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 647 1.1 mrg 648 1.1 mrg mno-sse4 649 1.3 mrg Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 650 1.8 mrg Do not support SSE4.1 and SSE4.2 built-in functions and code generation. 651 1.1 mrg 652 1.3 mrg msse5 653 1.3 mrg Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 654 1.3 mrg ;; Deprecated 655 1.3 mrg 656 1.1 mrg mavx 657 1.3 mrg Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save 658 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. 659 1.1 mrg 660 1.3 mrg mavx2 661 1.3 mrg Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save 662 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. 663 1.3 mrg 664 1.5 mrg mavx512f 665 1.5 mrg Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save 666 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. 667 1.5 mrg 668 1.5 mrg mavx512pf 669 1.5 mrg Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save 670 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. 671 1.5 mrg 672 1.5 mrg mavx512er 673 1.5 mrg Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save 674 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. 675 1.5 mrg 676 1.5 mrg mavx512cd 677 1.5 mrg Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save 678 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. 679 1.5 mrg 680 1.5 mrg mavx512dq 681 1.5 mrg Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save 682 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. 683 1.5 mrg 684 1.5 mrg mavx512bw 685 1.5 mrg Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save 686 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. 687 1.5 mrg 688 1.5 mrg mavx512vl 689 1.5 mrg Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save 690 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. 691 1.5 mrg 692 1.5 mrg mavx512ifma 693 1.5 mrg Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save 694 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. 695 1.5 mrg 696 1.5 mrg mavx512vbmi 697 1.5 mrg Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save 698 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. 699 1.5 mrg 700 1.10 mrg mavx5124fmaps 701 1.10 mrg Target Report Mask(ISA_AVX5124FMAPS) Var(ix86_isa_flags2) Save 702 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. 703 1.10 mrg 704 1.10 mrg mavx5124vnniw 705 1.10 mrg Target Report Mask(ISA_AVX5124VNNIW) Var(ix86_isa_flags2) Save 706 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. 707 1.10 mrg 708 1.10 mrg mavx512vpopcntdq 709 1.10 mrg Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags2) Save 710 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation. 711 1.10 mrg 712 1.1 mrg mfma 713 1.3 mrg Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save 714 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. 715 1.1 mrg 716 1.1 mrg msse4a 717 1.3 mrg Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 718 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. 719 1.1 mrg 720 1.1 mrg mfma4 721 1.3 mrg Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save 722 1.8 mrg Support FMA4 built-in functions and code generation. 723 1.1 mrg 724 1.1 mrg mxop 725 1.3 mrg Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save 726 1.8 mrg Support XOP built-in functions and code generation. 727 1.1 mrg 728 1.1 mrg mlwp 729 1.3 mrg Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save 730 1.8 mrg Support LWP built-in functions and code generation. 731 1.1 mrg 732 1.1 mrg mabm 733 1.3 mrg Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save 734 1.1 mrg Support code generation of Advanced Bit Manipulation (ABM) instructions. 735 1.1 mrg 736 1.1 mrg mpopcnt 737 1.3 mrg Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 738 1.1 mrg Support code generation of popcnt instruction. 739 1.1 mrg 740 1.10 mrg msgx 741 1.10 mrg Target Report Mask(ISA_SGX) Var(ix86_isa_flags2) Save 742 1.10 mrg Support SGX built-in functions and code generation. 743 1.10 mrg 744 1.10 mrg mrdpid 745 1.10 mrg Target Report Mask(ISA_RDPID) Var(ix86_isa_flags2) Save 746 1.10 mrg Support RDPID built-in functions and code generation. 747 1.10 mrg 748 1.3 mrg mbmi 749 1.3 mrg Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save 750 1.8 mrg Support BMI built-in functions and code generation. 751 1.3 mrg 752 1.3 mrg mbmi2 753 1.3 mrg Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save 754 1.8 mrg Support BMI2 built-in functions and code generation. 755 1.3 mrg 756 1.3 mrg mlzcnt 757 1.3 mrg Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 758 1.8 mrg Support LZCNT built-in function and code generation. 759 1.3 mrg 760 1.3 mrg mhle 761 1.3 mrg Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save 762 1.8 mrg Support Hardware Lock Elision prefixes. 763 1.3 mrg 764 1.3 mrg mrdseed 765 1.3 mrg Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 766 1.8 mrg Support RDSEED instruction. 767 1.3 mrg 768 1.3 mrg mprfchw 769 1.3 mrg Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 770 1.8 mrg Support PREFETCHW instruction. 771 1.3 mrg 772 1.3 mrg madx 773 1.3 mrg Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save 774 1.8 mrg Support flag-preserving add-carry instructions. 775 1.3 mrg 776 1.5 mrg mclflushopt 777 1.5 mrg Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save 778 1.8 mrg Support CLFLUSHOPT instructions. 779 1.5 mrg 780 1.5 mrg mclwb 781 1.5 mrg Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save 782 1.8 mrg Support CLWB instruction. 783 1.5 mrg 784 1.5 mrg mpcommit 785 1.6 mrg Target Undocumented Warn(%<-mpcommit%> was deprecated) 786 1.6 mrg ;; Deprecated 787 1.5 mrg 788 1.3 mrg mfxsr 789 1.3 mrg Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save 790 1.8 mrg Support FXSAVE and FXRSTOR instructions. 791 1.3 mrg 792 1.3 mrg mxsave 793 1.3 mrg Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 794 1.8 mrg Support XSAVE and XRSTOR instructions. 795 1.3 mrg 796 1.3 mrg mxsaveopt 797 1.3 mrg Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 798 1.8 mrg Support XSAVEOPT instruction. 799 1.3 mrg 800 1.5 mrg mxsavec 801 1.5 mrg Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save 802 1.8 mrg Support XSAVEC instructions. 803 1.5 mrg 804 1.5 mrg mxsaves 805 1.5 mrg Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save 806 1.8 mrg Support XSAVES and XRSTORS instructions. 807 1.5 mrg 808 1.3 mrg mtbm 809 1.3 mrg Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save 810 1.8 mrg Support TBM built-in functions and code generation. 811 1.3 mrg 812 1.1 mrg mcx16 813 1.3 mrg Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save 814 1.1 mrg Support code generation of cmpxchg16b instruction. 815 1.1 mrg 816 1.1 mrg msahf 817 1.3 mrg Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save 818 1.1 mrg Support code generation of sahf instruction in 64bit x86-64 code. 819 1.1 mrg 820 1.1 mrg mmovbe 821 1.3 mrg Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save 822 1.1 mrg Support code generation of movbe instruction. 823 1.1 mrg 824 1.1 mrg mcrc32 825 1.3 mrg Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save 826 1.1 mrg Support code generation of crc32 instruction. 827 1.1 mrg 828 1.1 mrg maes 829 1.3 mrg Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save 830 1.8 mrg Support AES built-in functions and code generation. 831 1.1 mrg 832 1.5 mrg msha 833 1.5 mrg Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save 834 1.8 mrg Support SHA1 and SHA256 built-in functions and code generation. 835 1.5 mrg 836 1.1 mrg mpclmul 837 1.3 mrg Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 838 1.8 mrg Support PCLMUL built-in functions and code generation. 839 1.1 mrg 840 1.1 mrg msse2avx 841 1.1 mrg Target Report Var(ix86_sse2avx) 842 1.8 mrg Encode SSE instructions with VEX prefix. 843 1.3 mrg 844 1.3 mrg mfsgsbase 845 1.3 mrg Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 846 1.8 mrg Support FSGSBASE built-in functions and code generation. 847 1.3 mrg 848 1.3 mrg mrdrnd 849 1.3 mrg Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save 850 1.8 mrg Support RDRND built-in functions and code generation. 851 1.3 mrg 852 1.3 mrg mf16c 853 1.3 mrg Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save 854 1.8 mrg Support F16C built-in functions and code generation. 855 1.3 mrg 856 1.5 mrg mprefetchwt1 857 1.5 mrg Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save 858 1.8 mrg Support PREFETCHWT1 built-in functions and code generation. 859 1.5 mrg 860 1.3 mrg mfentry 861 1.3 mrg Target Report Var(flag_fentry) Init(-1) 862 1.3 mrg Emit profiling counter call at function entry before prologue. 863 1.3 mrg 864 1.5 mrg mrecord-mcount 865 1.5 mrg Target Report Var(flag_record_mcount) Init(0) 866 1.5 mrg Generate __mcount_loc section with all mcount or __fentry__ calls. 867 1.5 mrg 868 1.5 mrg mnop-mcount 869 1.5 mrg Target Report Var(flag_nop_mcount) Init(0) 870 1.5 mrg Generate mcount/__fentry__ calls as nops. To activate they need to be 871 1.5 mrg patched in. 872 1.5 mrg 873 1.5 mrg mskip-rax-setup 874 1.5 mrg Target Report Var(flag_skip_rax_setup) Init(0) 875 1.5 mrg Skip setting up RAX register when passing variable arguments. 876 1.5 mrg 877 1.3 mrg m8bit-idiv 878 1.3 mrg Target Report Mask(USE_8BIT_IDIV) Save 879 1.8 mrg Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. 880 1.3 mrg 881 1.3 mrg mavx256-split-unaligned-load 882 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 883 1.8 mrg Split 32-byte AVX unaligned load. 884 1.3 mrg 885 1.3 mrg mavx256-split-unaligned-store 886 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 887 1.8 mrg Split 32-byte AVX unaligned store. 888 1.3 mrg 889 1.3 mrg mrtm 890 1.3 mrg Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save 891 1.8 mrg Support RTM built-in functions and code generation. 892 1.5 mrg 893 1.5 mrg mmpx 894 1.5 mrg Target Report Mask(ISA_MPX) Var(ix86_isa_flags) Save 895 1.8 mrg Support MPX code generation. 896 1.5 mrg 897 1.5 mrg mmwaitx 898 1.5 mrg Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags) Save 899 1.8 mrg Support MWAITX and MONITORX built-in functions and code generation. 900 1.8 mrg 901 1.8 mrg mclzero 902 1.8 mrg Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags) Save 903 1.8 mrg Support CLZERO built-in functions and code generation. 904 1.8 mrg 905 1.8 mrg mpku 906 1.8 mrg Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save 907 1.8 mrg Support PKU built-in functions and code generation. 908 1.5 mrg 909 1.5 mrg mstack-protector-guard= 910 1.5 mrg Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) 911 1.8 mrg Use given stack-protector guard. 912 1.5 mrg 913 1.5 mrg Enum 914 1.5 mrg Name(stack_protector_guard) Type(enum stack_protector_guard) 915 1.5 mrg Known stack protector guard (for use with the -mstack-protector-guard= option): 916 1.5 mrg 917 1.5 mrg EnumValue 918 1.5 mrg Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 919 1.5 mrg 920 1.5 mrg EnumValue 921 1.5 mrg Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 922 1.7 mrg 923 1.8 mrg mmitigate-rop 924 1.8 mrg Target Var(flag_mitigate_rop) Init(0) 925 1.8 mrg Attempt to avoid generating instruction sequences containing ret bytes. 926 1.8 mrg 927 1.10 mrg mgeneral-regs-only 928 1.10 mrg Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save 929 1.10 mrg Generate code which uses only the general registers. 930 1.10 mrg 931 1.7 mrg mindirect-branch= 932 1.7 mrg Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) 933 1.7 mrg Convert indirect call and jump to call and return thunks. 934 1.7 mrg 935 1.7 mrg mfunction-return= 936 1.7 mrg Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) 937 1.7 mrg Convert function return to call and return thunk. 938 1.7 mrg 939 1.7 mrg Enum 940 1.7 mrg Name(indirect_branch) Type(enum indirect_branch) 941 1.7 mrg Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options): 942 1.7 mrg 943 1.7 mrg EnumValue 944 1.7 mrg Enum(indirect_branch) String(keep) Value(indirect_branch_keep) 945 1.7 mrg 946 1.7 mrg EnumValue 947 1.7 mrg Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk) 948 1.7 mrg 949 1.7 mrg EnumValue 950 1.7 mrg Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline) 951 1.7 mrg 952 1.7 mrg EnumValue 953 1.7 mrg Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) 954 1.7 mrg 955 1.7 mrg mindirect-branch-register 956 1.7 mrg Target Report Var(ix86_indirect_branch_register) Init(0) 957 1.7 mrg Force indirect call and jump via register. 958
Indexes created Wed Apr 29 00:23:26 UTC 2026