i386.opt revision 1.12
1 1.1 mrg ; Options for the IA-32 and AMD64 ports of the compiler. 2 1.1 mrg 3 1.12 mrg ; Copyright (C) 2005-2019 Free Software Foundation, Inc. 4 1.1 mrg ; 5 1.1 mrg ; This file is part of GCC. 6 1.1 mrg ; 7 1.1 mrg ; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ; version. 11 1.1 mrg ; 12 1.1 mrg ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ; for more details. 16 1.1 mrg ; 17 1.1 mrg ; You should have received a copy of the GNU General Public License 18 1.1 mrg ; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.3 mrg HeaderInclude 22 1.3 mrg config/i386/i386-opts.h 23 1.3 mrg 24 1.3 mrg ; Bit flags that specify the ISA we are compiling for. 25 1.3 mrg Variable 26 1.3 mrg HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 1.3 mrg 28 1.10 mrg Variable 29 1.10 mrg HOST_WIDE_INT ix86_isa_flags2 = 0 30 1.10 mrg 31 1.3 mrg ; A mask of ix86_isa_flags that includes bit X if X was set or cleared 32 1.3 mrg ; on the command line. 33 1.3 mrg Variable 34 1.3 mrg HOST_WIDE_INT ix86_isa_flags_explicit 35 1.3 mrg 36 1.10 mrg Variable 37 1.10 mrg HOST_WIDE_INT ix86_isa_flags2_explicit 38 1.10 mrg 39 1.10 mrg ; Additional target flags 40 1.10 mrg Variable 41 1.10 mrg int ix86_target_flags 42 1.10 mrg 43 1.3 mrg TargetVariable 44 1.3 mrg int recip_mask = RECIP_MASK_DEFAULT 45 1.3 mrg 46 1.3 mrg Variable 47 1.3 mrg int recip_mask_explicit 48 1.3 mrg 49 1.3 mrg TargetSave 50 1.3 mrg int x_recip_mask_explicit 51 1.3 mrg 52 1.1 mrg ;; Definitions to add to the cl_target_option structure 53 1.1 mrg ;; -march= processor 54 1.1 mrg TargetSave 55 1.1 mrg unsigned char arch 56 1.1 mrg 57 1.1 mrg ;; -mtune= processor 58 1.1 mrg TargetSave 59 1.1 mrg unsigned char tune 60 1.1 mrg 61 1.5 mrg ;; -march= processor-string 62 1.5 mrg TargetSave 63 1.5 mrg const char *x_ix86_arch_string 64 1.5 mrg 65 1.5 mrg ;; -mtune= processor-string 66 1.5 mrg TargetSave 67 1.5 mrg const char *x_ix86_tune_string 68 1.5 mrg 69 1.1 mrg ;; CPU schedule model 70 1.1 mrg TargetSave 71 1.1 mrg unsigned char schedule 72 1.1 mrg 73 1.5 mrg ;; True if processor has SSE prefetch instruction. 74 1.5 mrg TargetSave 75 1.5 mrg unsigned char prefetch_sse 76 1.5 mrg 77 1.1 mrg ;; branch cost 78 1.1 mrg TargetSave 79 1.1 mrg unsigned char branch_cost 80 1.1 mrg 81 1.1 mrg ;; which flags were passed by the user 82 1.1 mrg TargetSave 83 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags2_explicit 84 1.5 mrg 85 1.5 mrg ;; which flags were passed by the user 86 1.1 mrg TargetSave 87 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags_explicit 88 1.1 mrg 89 1.1 mrg ;; whether -mtune was not specified 90 1.1 mrg TargetSave 91 1.1 mrg unsigned char tune_defaulted 92 1.1 mrg 93 1.1 mrg ;; whether -march was specified 94 1.1 mrg TargetSave 95 1.1 mrg unsigned char arch_specified 96 1.1 mrg 97 1.5 mrg ;; -mcmodel= model 98 1.5 mrg TargetSave 99 1.5 mrg enum cmodel x_ix86_cmodel 100 1.5 mrg 101 1.5 mrg ;; -mabi= 102 1.5 mrg TargetSave 103 1.5 mrg enum calling_abi x_ix86_abi 104 1.5 mrg 105 1.5 mrg ;; -masm= 106 1.5 mrg TargetSave 107 1.5 mrg enum asm_dialect x_ix86_asm_dialect 108 1.5 mrg 109 1.5 mrg ;; -mbranch-cost= 110 1.5 mrg TargetSave 111 1.5 mrg int x_ix86_branch_cost 112 1.5 mrg 113 1.8 mrg ;; -mdump-tune-features= 114 1.5 mrg TargetSave 115 1.5 mrg int x_ix86_dump_tunes 116 1.5 mrg 117 1.5 mrg ;; -mstackrealign= 118 1.5 mrg TargetSave 119 1.5 mrg int x_ix86_force_align_arg_pointer 120 1.5 mrg 121 1.8 mrg ;; -mforce-drap= 122 1.5 mrg TargetSave 123 1.5 mrg int x_ix86_force_drap 124 1.5 mrg 125 1.5 mrg ;; -mincoming-stack-boundary= 126 1.5 mrg TargetSave 127 1.5 mrg int x_ix86_incoming_stack_boundary_arg 128 1.5 mrg 129 1.5 mrg ;; -maddress-mode= 130 1.5 mrg TargetSave 131 1.5 mrg enum pmode x_ix86_pmode 132 1.5 mrg 133 1.8 mrg ;; -mpreferred-stack-boundary= 134 1.5 mrg TargetSave 135 1.5 mrg int x_ix86_preferred_stack_boundary_arg 136 1.5 mrg 137 1.5 mrg ;; -mrecip= 138 1.5 mrg TargetSave 139 1.5 mrg const char *x_ix86_recip_name 140 1.5 mrg 141 1.5 mrg ;; -mregparm= 142 1.5 mrg TargetSave 143 1.5 mrg int x_ix86_regparm 144 1.5 mrg 145 1.5 mrg ;; -mlarge-data-threshold= 146 1.5 mrg TargetSave 147 1.5 mrg int x_ix86_section_threshold 148 1.5 mrg 149 1.5 mrg ;; -msse2avx= 150 1.5 mrg TargetSave 151 1.5 mrg int x_ix86_sse2avx 152 1.5 mrg 153 1.5 mrg ;; -mstack-protector-guard= 154 1.5 mrg TargetSave 155 1.5 mrg enum stack_protector_guard x_ix86_stack_protector_guard 156 1.5 mrg 157 1.5 mrg ;; -mstringop-strategy= 158 1.5 mrg TargetSave 159 1.5 mrg enum stringop_alg x_ix86_stringop_alg 160 1.5 mrg 161 1.5 mrg ;; -mtls-dialect= 162 1.5 mrg TargetSave 163 1.5 mrg enum tls_dialect x_ix86_tls_dialect 164 1.5 mrg 165 1.5 mrg ;; -mtune-ctrl= 166 1.5 mrg TargetSave 167 1.5 mrg const char *x_ix86_tune_ctrl_string 168 1.5 mrg 169 1.5 mrg ;; -mmemcpy-strategy= 170 1.5 mrg TargetSave 171 1.5 mrg const char *x_ix86_tune_memcpy_strategy 172 1.5 mrg 173 1.5 mrg ;; -mmemset-strategy= 174 1.5 mrg TargetSave 175 1.5 mrg const char *x_ix86_tune_memset_strategy 176 1.5 mrg 177 1.5 mrg ;; -mno-default= 178 1.5 mrg TargetSave 179 1.5 mrg int x_ix86_tune_no_default 180 1.5 mrg 181 1.5 mrg ;; -mveclibabi= 182 1.5 mrg TargetSave 183 1.5 mrg enum ix86_veclibabi x_ix86_veclibabi_type 184 1.5 mrg 185 1.11 mrg ;; -mprefer-vector-width= 186 1.11 mrg TargetSave 187 1.11 mrg enum prefer_vector_width x_prefer_vector_width_type 188 1.11 mrg 189 1.1 mrg ;; x86 options 190 1.1 mrg m128bit-long-double 191 1.1 mrg Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save 192 1.8 mrg sizeof(long double) is 16. 193 1.1 mrg 194 1.1 mrg m80387 195 1.1 mrg Target Report Mask(80387) Save 196 1.8 mrg Use hardware fp. 197 1.1 mrg 198 1.1 mrg m96bit-long-double 199 1.1 mrg Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save 200 1.8 mrg sizeof(long double) is 12. 201 1.1 mrg 202 1.3 mrg mlong-double-80 203 1.5 mrg Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save 204 1.8 mrg Use 80-bit long double. 205 1.3 mrg 206 1.3 mrg mlong-double-64 207 1.5 mrg Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save 208 1.8 mrg Use 64-bit long double. 209 1.3 mrg 210 1.5 mrg mlong-double-128 211 1.5 mrg Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save 212 1.8 mrg Use 128-bit long double. 213 1.5 mrg 214 1.1 mrg maccumulate-outgoing-args 215 1.1 mrg Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save 216 1.8 mrg Reserve space for outgoing arguments in the function prologue. 217 1.1 mrg 218 1.1 mrg malign-double 219 1.1 mrg Target Report Mask(ALIGN_DOUBLE) Save 220 1.8 mrg Align some doubles on dword boundary. 221 1.1 mrg 222 1.1 mrg malign-functions= 223 1.3 mrg Target RejectNegative Joined UInteger 224 1.8 mrg Function starts are aligned to this power of 2. 225 1.1 mrg 226 1.1 mrg malign-jumps= 227 1.3 mrg Target RejectNegative Joined UInteger 228 1.8 mrg Jump targets are aligned to this power of 2. 229 1.1 mrg 230 1.1 mrg malign-loops= 231 1.3 mrg Target RejectNegative Joined UInteger 232 1.8 mrg Loop code aligned to this power of 2. 233 1.1 mrg 234 1.1 mrg malign-stringops 235 1.1 mrg Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 236 1.8 mrg Align destination of the string operations. 237 1.1 mrg 238 1.5 mrg malign-data= 239 1.5 mrg Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) 240 1.8 mrg Use the given data alignment. 241 1.5 mrg 242 1.5 mrg Enum 243 1.5 mrg Name(ix86_align_data) Type(enum ix86_align_data) 244 1.5 mrg Known data alignment choices (for use with the -malign-data= option): 245 1.5 mrg 246 1.5 mrg EnumValue 247 1.5 mrg Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat) 248 1.5 mrg 249 1.5 mrg EnumValue 250 1.5 mrg Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi) 251 1.5 mrg 252 1.5 mrg EnumValue 253 1.5 mrg Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) 254 1.5 mrg 255 1.1 mrg march= 256 1.12 mrg Target RejectNegative Negative(march=) Joined Var(ix86_arch_string) 257 1.8 mrg Generate code for given CPU. 258 1.1 mrg 259 1.1 mrg masm= 260 1.3 mrg Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 261 1.8 mrg Use given assembler dialect. 262 1.1 mrg 263 1.3 mrg Enum 264 1.3 mrg Name(asm_dialect) Type(enum asm_dialect) 265 1.10 mrg Known assembler dialects (for use with the -masm= option): 266 1.3 mrg 267 1.3 mrg EnumValue 268 1.3 mrg Enum(asm_dialect) String(intel) Value(ASM_INTEL) 269 1.3 mrg 270 1.3 mrg EnumValue 271 1.3 mrg Enum(asm_dialect) String(att) Value(ASM_ATT) 272 1.3 mrg 273 1.1 mrg mbranch-cost= 274 1.11 mrg Target RejectNegative Joined UInteger Var(ix86_branch_cost) IntegerRange(0, 5) 275 1.11 mrg Branches are this expensive (arbitrary units). 276 1.1 mrg 277 1.1 mrg mlarge-data-threshold= 278 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 279 1.10 mrg -mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model. 280 1.1 mrg 281 1.1 mrg mcmodel= 282 1.3 mrg Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 283 1.8 mrg Use given x86-64 code model. 284 1.1 mrg 285 1.3 mrg Enum 286 1.3 mrg Name(cmodel) Type(enum cmodel) 287 1.3 mrg Known code models (for use with the -mcmodel= option): 288 1.3 mrg 289 1.3 mrg EnumValue 290 1.3 mrg Enum(cmodel) String(small) Value(CM_SMALL) 291 1.3 mrg 292 1.3 mrg EnumValue 293 1.3 mrg Enum(cmodel) String(medium) Value(CM_MEDIUM) 294 1.3 mrg 295 1.3 mrg EnumValue 296 1.3 mrg Enum(cmodel) String(large) Value(CM_LARGE) 297 1.3 mrg 298 1.3 mrg EnumValue 299 1.3 mrg Enum(cmodel) String(32) Value(CM_32) 300 1.3 mrg 301 1.3 mrg EnumValue 302 1.3 mrg Enum(cmodel) String(kernel) Value(CM_KERNEL) 303 1.3 mrg 304 1.3 mrg maddress-mode= 305 1.3 mrg Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 306 1.8 mrg Use given address mode. 307 1.3 mrg 308 1.3 mrg Enum 309 1.3 mrg Name(pmode) Type(enum pmode) 310 1.3 mrg Known address mode (for use with the -maddress-mode= option): 311 1.3 mrg 312 1.3 mrg EnumValue 313 1.3 mrg Enum(pmode) String(short) Value(PMODE_SI) 314 1.3 mrg 315 1.3 mrg EnumValue 316 1.3 mrg Enum(pmode) String(long) Value(PMODE_DI) 317 1.3 mrg 318 1.3 mrg mcpu= 319 1.3 mrg Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 320 1.3 mrg 321 1.1 mrg mfancy-math-387 322 1.1 mrg Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 323 1.8 mrg Generate sin, cos, sqrt for FPU. 324 1.1 mrg 325 1.1 mrg mforce-drap 326 1.1 mrg Target Report Var(ix86_force_drap) 327 1.8 mrg Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. 328 1.1 mrg 329 1.1 mrg mfp-ret-in-387 330 1.1 mrg Target Report Mask(FLOAT_RETURNS) Save 331 1.8 mrg Return values of functions in FPU registers. 332 1.1 mrg 333 1.1 mrg mfpmath= 334 1.3 mrg Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 335 1.8 mrg Generate floating point mathematics using given instruction set. 336 1.1 mrg 337 1.3 mrg Enum 338 1.3 mrg Name(fpmath_unit) Type(enum fpmath_unit) 339 1.3 mrg Valid arguments to -mfpmath=: 340 1.3 mrg 341 1.3 mrg EnumValue 342 1.3 mrg Enum(fpmath_unit) String(387) Value(FPMATH_387) 343 1.3 mrg 344 1.3 mrg EnumValue 345 1.3 mrg Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 346 1.3 mrg 347 1.3 mrg EnumValue 348 1.3 mrg Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 349 1.3 mrg 350 1.3 mrg EnumValue 351 1.3 mrg Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 352 1.3 mrg 353 1.3 mrg EnumValue 354 1.3 mrg Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 355 1.3 mrg 356 1.3 mrg EnumValue 357 1.3 mrg Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 358 1.3 mrg 359 1.3 mrg EnumValue 360 1.3 mrg Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 361 1.3 mrg 362 1.1 mrg mhard-float 363 1.3 mrg Target RejectNegative Mask(80387) Save 364 1.8 mrg Use hardware fp. 365 1.1 mrg 366 1.1 mrg mieee-fp 367 1.1 mrg Target Report Mask(IEEE_FP) Save 368 1.8 mrg Use IEEE math for fp comparisons. 369 1.1 mrg 370 1.1 mrg minline-all-stringops 371 1.1 mrg Target Report Mask(INLINE_ALL_STRINGOPS) Save 372 1.8 mrg Inline all known string operations. 373 1.1 mrg 374 1.1 mrg minline-stringops-dynamically 375 1.1 mrg Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 376 1.8 mrg Inline memset/memcpy string operations, but perform inline version only for small blocks. 377 1.1 mrg 378 1.1 mrg mintel-syntax 379 1.3 mrg Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 380 1.1 mrg ;; Deprecated 381 1.1 mrg 382 1.1 mrg mms-bitfields 383 1.1 mrg Target Report Mask(MS_BITFIELD_LAYOUT) Save 384 1.8 mrg Use native (MS) bitfield layout. 385 1.1 mrg 386 1.1 mrg mno-align-stringops 387 1.1 mrg Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save 388 1.1 mrg 389 1.1 mrg mno-fancy-math-387 390 1.1 mrg Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save 391 1.1 mrg 392 1.1 mrg mno-push-args 393 1.1 mrg Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save 394 1.1 mrg 395 1.1 mrg mno-red-zone 396 1.1 mrg Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save 397 1.1 mrg 398 1.1 mrg momit-leaf-frame-pointer 399 1.1 mrg Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save 400 1.8 mrg Omit the frame pointer in leaf functions. 401 1.1 mrg 402 1.3 mrg mpc32 403 1.3 mrg Target RejectNegative Report 404 1.8 mrg Set 80387 floating-point precision to 32-bit. 405 1.3 mrg 406 1.3 mrg mpc64 407 1.3 mrg Target RejectNegative Report 408 1.8 mrg Set 80387 floating-point precision to 64-bit. 409 1.3 mrg 410 1.3 mrg mpc80 411 1.3 mrg Target RejectNegative Report 412 1.8 mrg Set 80387 floating-point precision to 80-bit. 413 1.1 mrg 414 1.1 mrg mpreferred-stack-boundary= 415 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 416 1.8 mrg Attempt to keep stack aligned to this power of 2. 417 1.1 mrg 418 1.1 mrg mincoming-stack-boundary= 419 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 420 1.8 mrg Assume incoming stack aligned to this power of 2. 421 1.1 mrg 422 1.1 mrg mpush-args 423 1.1 mrg Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 424 1.8 mrg Use push instructions to save outgoing arguments. 425 1.1 mrg 426 1.1 mrg mred-zone 427 1.1 mrg Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save 428 1.8 mrg Use red-zone in the x86-64 code. 429 1.1 mrg 430 1.1 mrg mregparm= 431 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_regparm) 432 1.8 mrg Number of registers used to pass integer arguments. 433 1.1 mrg 434 1.1 mrg mrtd 435 1.1 mrg Target Report Mask(RTD) Save 436 1.8 mrg Alternate calling convention. 437 1.1 mrg 438 1.1 mrg msoft-float 439 1.1 mrg Target InverseMask(80387) Save 440 1.8 mrg Do not use hardware fp. 441 1.1 mrg 442 1.1 mrg msseregparm 443 1.1 mrg Target RejectNegative Mask(SSEREGPARM) Save 444 1.8 mrg Use SSE register passing conventions for SF and DF mode. 445 1.1 mrg 446 1.1 mrg mstackrealign 447 1.11 mrg Target Report Var(ix86_force_align_arg_pointer) 448 1.8 mrg Realign stack in prologue. 449 1.1 mrg 450 1.1 mrg mstack-arg-probe 451 1.1 mrg Target Report Mask(STACK_PROBE) Save 452 1.8 mrg Enable stack probing. 453 1.1 mrg 454 1.5 mrg mmemcpy-strategy= 455 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) 456 1.8 mrg Specify memcpy expansion strategy when expected size is known. 457 1.5 mrg 458 1.5 mrg mmemset-strategy= 459 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memset_strategy) 460 1.8 mrg Specify memset expansion strategy when expected size is known. 461 1.5 mrg 462 1.1 mrg mstringop-strategy= 463 1.3 mrg Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 464 1.8 mrg Chose strategy to generate stringop using. 465 1.1 mrg 466 1.3 mrg Enum 467 1.3 mrg Name(stringop_alg) Type(enum stringop_alg) 468 1.3 mrg Valid arguments to -mstringop-strategy=: 469 1.3 mrg 470 1.3 mrg EnumValue 471 1.3 mrg Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 472 1.3 mrg 473 1.3 mrg EnumValue 474 1.3 mrg Enum(stringop_alg) String(libcall) Value(libcall) 475 1.3 mrg 476 1.3 mrg EnumValue 477 1.3 mrg Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 478 1.3 mrg 479 1.3 mrg EnumValue 480 1.3 mrg Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 481 1.3 mrg 482 1.3 mrg EnumValue 483 1.3 mrg Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 484 1.3 mrg 485 1.3 mrg EnumValue 486 1.3 mrg Enum(stringop_alg) String(loop) Value(loop) 487 1.3 mrg 488 1.3 mrg EnumValue 489 1.3 mrg Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 490 1.3 mrg 491 1.5 mrg EnumValue 492 1.5 mrg Enum(stringop_alg) String(vector_loop) Value(vector_loop) 493 1.5 mrg 494 1.1 mrg mtls-dialect= 495 1.3 mrg Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 496 1.8 mrg Use given thread-local storage dialect. 497 1.1 mrg 498 1.3 mrg Enum 499 1.3 mrg Name(tls_dialect) Type(enum tls_dialect) 500 1.3 mrg Known TLS dialects (for use with the -mtls-dialect= option): 501 1.3 mrg 502 1.3 mrg EnumValue 503 1.3 mrg Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 504 1.3 mrg 505 1.3 mrg EnumValue 506 1.3 mrg Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 507 1.3 mrg 508 1.1 mrg mtls-direct-seg-refs 509 1.1 mrg Target Report Mask(TLS_DIRECT_SEG_REFS) 510 1.8 mrg Use direct references against %gs when accessing tls data. 511 1.1 mrg 512 1.1 mrg mtune= 513 1.12 mrg Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string) 514 1.8 mrg Schedule code for given CPU. 515 1.1 mrg 516 1.5 mrg mtune-ctrl= 517 1.5 mrg Target RejectNegative Joined Var(ix86_tune_ctrl_string) 518 1.8 mrg Fine grain control of tune features. 519 1.5 mrg 520 1.5 mrg mno-default 521 1.11 mrg Target RejectNegative Var(ix86_tune_no_default) 522 1.8 mrg Clear all tune features. 523 1.5 mrg 524 1.5 mrg mdump-tune-features 525 1.11 mrg Target RejectNegative Var(ix86_dump_tunes) 526 1.5 mrg 527 1.8 mrg miamcu 528 1.8 mrg Target Report Mask(IAMCU) 529 1.8 mrg Generate code that conforms to Intel MCU psABI. 530 1.8 mrg 531 1.1 mrg mabi= 532 1.3 mrg Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 533 1.8 mrg Generate code that conforms to the given ABI. 534 1.1 mrg 535 1.3 mrg Enum 536 1.3 mrg Name(calling_abi) Type(enum calling_abi) 537 1.3 mrg Known ABIs (for use with the -mabi= option): 538 1.3 mrg 539 1.3 mrg EnumValue 540 1.3 mrg Enum(calling_abi) String(sysv) Value(SYSV_ABI) 541 1.3 mrg 542 1.3 mrg EnumValue 543 1.3 mrg Enum(calling_abi) String(ms) Value(MS_ABI) 544 1.3 mrg 545 1.11 mrg mcall-ms2sysv-xlogues 546 1.11 mrg Target Report Mask(CALL_MS2SYSV_XLOGUES) Save 547 1.11 mrg Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls. 548 1.11 mrg 549 1.1 mrg mveclibabi= 550 1.3 mrg Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 551 1.8 mrg Vector library ABI to use. 552 1.1 mrg 553 1.3 mrg Enum 554 1.3 mrg Name(ix86_veclibabi) Type(enum ix86_veclibabi) 555 1.3 mrg Known vectorization library ABIs (for use with the -mveclibabi= option): 556 1.3 mrg 557 1.3 mrg EnumValue 558 1.3 mrg Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 559 1.3 mrg 560 1.3 mrg EnumValue 561 1.3 mrg Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 562 1.3 mrg 563 1.3 mrg mvect8-ret-in-mem 564 1.3 mrg Target Report Mask(VECT8_RETURNS) Save 565 1.8 mrg Return 8-byte vectors in memory. 566 1.3 mrg 567 1.1 mrg mrecip 568 1.1 mrg Target Report Mask(RECIP) Save 569 1.1 mrg Generate reciprocals instead of divss and sqrtss. 570 1.1 mrg 571 1.3 mrg mrecip= 572 1.3 mrg Target Report RejectNegative Joined Var(ix86_recip_name) 573 1.3 mrg Control generation of reciprocal estimates. 574 1.3 mrg 575 1.1 mrg mcld 576 1.1 mrg Target Report Mask(CLD) Save 577 1.1 mrg Generate cld instruction in the function prologue. 578 1.1 mrg 579 1.3 mrg mvzeroupper 580 1.3 mrg Target Report Mask(VZEROUPPER) Save 581 1.3 mrg Generate vzeroupper instruction before a transfer of control flow out of 582 1.3 mrg the function. 583 1.3 mrg 584 1.8 mrg mstv 585 1.8 mrg Target Report Mask(STV) Save 586 1.8 mrg Disable Scalar to Vector optimization pass transforming 64-bit integer 587 1.8 mrg computations into a vector ones. 588 1.8 mrg 589 1.3 mrg mdispatch-scheduler 590 1.3 mrg Target RejectNegative Var(flag_dispatch_scheduler) 591 1.8 mrg Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4 592 1.8 mrg or znver1 and Haifa scheduling is selected. 593 1.3 mrg 594 1.3 mrg mprefer-avx128 595 1.11 mrg Target Alias(mprefer-vector-width=, 128, 256) 596 1.3 mrg Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 597 1.1 mrg 598 1.11 mrg mprefer-vector-width= 599 1.11 mrg Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) 600 1.11 mrg Use given register vector width instructions instead of maximum register width in the auto-vectorizer. 601 1.11 mrg 602 1.11 mrg Enum 603 1.11 mrg Name(prefer_vector_width) Type(enum prefer_vector_width) 604 1.12 mrg Known preferred register vector length (to use with the -mprefer-vector-width= option): 605 1.11 mrg 606 1.11 mrg EnumValue 607 1.11 mrg Enum(prefer_vector_width) String(none) Value(PVW_NONE) 608 1.11 mrg 609 1.11 mrg EnumValue 610 1.11 mrg Enum(prefer_vector_width) String(128) Value(PVW_AVX128) 611 1.11 mrg 612 1.11 mrg EnumValue 613 1.11 mrg Enum(prefer_vector_width) String(256) Value(PVW_AVX256) 614 1.11 mrg 615 1.11 mrg EnumValue 616 1.11 mrg Enum(prefer_vector_width) String(512) Value(PVW_AVX512) 617 1.11 mrg 618 1.1 mrg ;; ISA support 619 1.1 mrg 620 1.1 mrg m32 621 1.3 mrg Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 622 1.8 mrg Generate 32bit i386 code. 623 1.1 mrg 624 1.1 mrg m64 625 1.3 mrg Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save 626 1.8 mrg Generate 64bit x86-64 code. 627 1.1 mrg 628 1.3 mrg mx32 629 1.5 mrg Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save 630 1.8 mrg Generate 32bit x86-64 code. 631 1.3 mrg 632 1.5 mrg m16 633 1.5 mrg Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 634 1.8 mrg Generate 16bit i386 code. 635 1.5 mrg 636 1.1 mrg mmmx 637 1.3 mrg Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save 638 1.8 mrg Support MMX built-in functions. 639 1.1 mrg 640 1.1 mrg m3dnow 641 1.3 mrg Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 642 1.8 mrg Support 3DNow! built-in functions. 643 1.1 mrg 644 1.1 mrg m3dnowa 645 1.10 mrg Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 646 1.8 mrg Support Athlon 3Dnow! built-in functions. 647 1.1 mrg 648 1.1 mrg msse 649 1.3 mrg Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save 650 1.8 mrg Support MMX and SSE built-in functions and code generation. 651 1.1 mrg 652 1.1 mrg msse2 653 1.3 mrg Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save 654 1.8 mrg Support MMX, SSE and SSE2 built-in functions and code generation. 655 1.1 mrg 656 1.1 mrg msse3 657 1.3 mrg Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save 658 1.8 mrg Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. 659 1.1 mrg 660 1.1 mrg mssse3 661 1.3 mrg Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 662 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. 663 1.1 mrg 664 1.1 mrg msse4.1 665 1.3 mrg Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 666 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. 667 1.1 mrg 668 1.1 mrg msse4.2 669 1.3 mrg Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 670 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 671 1.1 mrg 672 1.1 mrg msse4 673 1.3 mrg Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 674 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 675 1.1 mrg 676 1.1 mrg mno-sse4 677 1.3 mrg Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 678 1.8 mrg Do not support SSE4.1 and SSE4.2 built-in functions and code generation. 679 1.1 mrg 680 1.3 mrg msse5 681 1.3 mrg Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 682 1.3 mrg ;; Deprecated 683 1.3 mrg 684 1.1 mrg mavx 685 1.3 mrg Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save 686 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. 687 1.1 mrg 688 1.3 mrg mavx2 689 1.3 mrg Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save 690 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. 691 1.3 mrg 692 1.5 mrg mavx512f 693 1.5 mrg Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save 694 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. 695 1.5 mrg 696 1.5 mrg mavx512pf 697 1.5 mrg Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save 698 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. 699 1.5 mrg 700 1.5 mrg mavx512er 701 1.5 mrg Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save 702 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. 703 1.5 mrg 704 1.5 mrg mavx512cd 705 1.5 mrg Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save 706 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. 707 1.5 mrg 708 1.5 mrg mavx512dq 709 1.5 mrg Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save 710 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. 711 1.5 mrg 712 1.5 mrg mavx512bw 713 1.5 mrg Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save 714 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. 715 1.5 mrg 716 1.5 mrg mavx512vl 717 1.5 mrg Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save 718 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. 719 1.5 mrg 720 1.5 mrg mavx512ifma 721 1.5 mrg Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save 722 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. 723 1.5 mrg 724 1.5 mrg mavx512vbmi 725 1.5 mrg Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save 726 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. 727 1.5 mrg 728 1.10 mrg mavx5124fmaps 729 1.10 mrg Target Report Mask(ISA_AVX5124FMAPS) Var(ix86_isa_flags2) Save 730 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. 731 1.10 mrg 732 1.10 mrg mavx5124vnniw 733 1.10 mrg Target Report Mask(ISA_AVX5124VNNIW) Var(ix86_isa_flags2) Save 734 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. 735 1.10 mrg 736 1.10 mrg mavx512vpopcntdq 737 1.11 mrg Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save 738 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation. 739 1.10 mrg 740 1.11 mrg mavx512vbmi2 741 1.11 mrg Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save 742 1.11 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation. 743 1.11 mrg 744 1.11 mrg mavx512vnni 745 1.11 mrg Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save 746 1.11 mrg Support AVX512VNNI built-in functions and code generation. 747 1.11 mrg 748 1.11 mrg mavx512bitalg 749 1.11 mrg Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save 750 1.11 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation. 751 1.11 mrg 752 1.1 mrg mfma 753 1.3 mrg Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save 754 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. 755 1.1 mrg 756 1.1 mrg msse4a 757 1.3 mrg Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 758 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. 759 1.1 mrg 760 1.1 mrg mfma4 761 1.3 mrg Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save 762 1.8 mrg Support FMA4 built-in functions and code generation. 763 1.1 mrg 764 1.1 mrg mxop 765 1.3 mrg Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save 766 1.8 mrg Support XOP built-in functions and code generation. 767 1.1 mrg 768 1.1 mrg mlwp 769 1.3 mrg Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save 770 1.8 mrg Support LWP built-in functions and code generation. 771 1.1 mrg 772 1.1 mrg mabm 773 1.3 mrg Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save 774 1.1 mrg Support code generation of Advanced Bit Manipulation (ABM) instructions. 775 1.1 mrg 776 1.1 mrg mpopcnt 777 1.3 mrg Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 778 1.1 mrg Support code generation of popcnt instruction. 779 1.1 mrg 780 1.11 mrg mpconfig 781 1.11 mrg Target Report Mask(ISA_PCONFIG) Var(ix86_isa_flags2) Save 782 1.11 mrg Support PCONFIG built-in functions and code generation. 783 1.11 mrg 784 1.11 mrg mwbnoinvd 785 1.11 mrg Target Report Mask(ISA_WBNOINVD) Var(ix86_isa_flags2) Save 786 1.11 mrg Support WBNOINVD built-in functions and code generation. 787 1.11 mrg 788 1.12 mrg mptwrite 789 1.12 mrg Target Report Mask(ISA_PTWRITE) Var(ix86_isa_flags2) Save 790 1.12 mrg Support PTWRITE built-in functions and code generation. 791 1.12 mrg 792 1.10 mrg msgx 793 1.10 mrg Target Report Mask(ISA_SGX) Var(ix86_isa_flags2) Save 794 1.10 mrg Support SGX built-in functions and code generation. 795 1.10 mrg 796 1.10 mrg mrdpid 797 1.10 mrg Target Report Mask(ISA_RDPID) Var(ix86_isa_flags2) Save 798 1.10 mrg Support RDPID built-in functions and code generation. 799 1.10 mrg 800 1.11 mrg mgfni 801 1.11 mrg Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save 802 1.11 mrg Support GFNI built-in functions and code generation. 803 1.11 mrg 804 1.11 mrg mvaes 805 1.11 mrg Target Report Mask(ISA_VAES) Var(ix86_isa_flags2) Save 806 1.11 mrg Support VAES built-in functions and code generation. 807 1.11 mrg 808 1.11 mrg mvpclmulqdq 809 1.11 mrg Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save 810 1.11 mrg Support VPCLMULQDQ built-in functions and code generation. 811 1.11 mrg 812 1.3 mrg mbmi 813 1.3 mrg Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save 814 1.8 mrg Support BMI built-in functions and code generation. 815 1.3 mrg 816 1.3 mrg mbmi2 817 1.3 mrg Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save 818 1.8 mrg Support BMI2 built-in functions and code generation. 819 1.3 mrg 820 1.3 mrg mlzcnt 821 1.3 mrg Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 822 1.8 mrg Support LZCNT built-in function and code generation. 823 1.3 mrg 824 1.3 mrg mhle 825 1.11 mrg Target Report Mask(ISA_HLE) Var(ix86_isa_flags2) Save 826 1.8 mrg Support Hardware Lock Elision prefixes. 827 1.3 mrg 828 1.3 mrg mrdseed 829 1.3 mrg Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 830 1.8 mrg Support RDSEED instruction. 831 1.3 mrg 832 1.3 mrg mprfchw 833 1.3 mrg Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 834 1.8 mrg Support PREFETCHW instruction. 835 1.3 mrg 836 1.3 mrg madx 837 1.3 mrg Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save 838 1.8 mrg Support flag-preserving add-carry instructions. 839 1.3 mrg 840 1.5 mrg mclflushopt 841 1.5 mrg Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save 842 1.8 mrg Support CLFLUSHOPT instructions. 843 1.5 mrg 844 1.5 mrg mclwb 845 1.5 mrg Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save 846 1.8 mrg Support CLWB instruction. 847 1.5 mrg 848 1.5 mrg mpcommit 849 1.12 mrg Target Deprecated 850 1.6 mrg ;; Deprecated 851 1.5 mrg 852 1.3 mrg mfxsr 853 1.3 mrg Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save 854 1.8 mrg Support FXSAVE and FXRSTOR instructions. 855 1.3 mrg 856 1.3 mrg mxsave 857 1.3 mrg Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 858 1.8 mrg Support XSAVE and XRSTOR instructions. 859 1.3 mrg 860 1.3 mrg mxsaveopt 861 1.3 mrg Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 862 1.8 mrg Support XSAVEOPT instruction. 863 1.3 mrg 864 1.5 mrg mxsavec 865 1.5 mrg Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save 866 1.8 mrg Support XSAVEC instructions. 867 1.5 mrg 868 1.5 mrg mxsaves 869 1.5 mrg Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save 870 1.8 mrg Support XSAVES and XRSTORS instructions. 871 1.5 mrg 872 1.3 mrg mtbm 873 1.3 mrg Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save 874 1.8 mrg Support TBM built-in functions and code generation. 875 1.3 mrg 876 1.1 mrg mcx16 877 1.11 mrg Target Report Mask(ISA_CX16) Var(ix86_isa_flags2) Save 878 1.1 mrg Support code generation of cmpxchg16b instruction. 879 1.1 mrg 880 1.1 mrg msahf 881 1.3 mrg Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save 882 1.1 mrg Support code generation of sahf instruction in 64bit x86-64 code. 883 1.1 mrg 884 1.1 mrg mmovbe 885 1.11 mrg Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags2) Save 886 1.1 mrg Support code generation of movbe instruction. 887 1.1 mrg 888 1.1 mrg mcrc32 889 1.3 mrg Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save 890 1.1 mrg Support code generation of crc32 instruction. 891 1.1 mrg 892 1.1 mrg maes 893 1.3 mrg Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save 894 1.8 mrg Support AES built-in functions and code generation. 895 1.1 mrg 896 1.5 mrg msha 897 1.5 mrg Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save 898 1.8 mrg Support SHA1 and SHA256 built-in functions and code generation. 899 1.5 mrg 900 1.1 mrg mpclmul 901 1.3 mrg Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 902 1.8 mrg Support PCLMUL built-in functions and code generation. 903 1.1 mrg 904 1.1 mrg msse2avx 905 1.1 mrg Target Report Var(ix86_sse2avx) 906 1.8 mrg Encode SSE instructions with VEX prefix. 907 1.3 mrg 908 1.3 mrg mfsgsbase 909 1.3 mrg Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 910 1.8 mrg Support FSGSBASE built-in functions and code generation. 911 1.3 mrg 912 1.3 mrg mrdrnd 913 1.3 mrg Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save 914 1.8 mrg Support RDRND built-in functions and code generation. 915 1.3 mrg 916 1.3 mrg mf16c 917 1.3 mrg Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save 918 1.8 mrg Support F16C built-in functions and code generation. 919 1.3 mrg 920 1.5 mrg mprefetchwt1 921 1.5 mrg Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save 922 1.8 mrg Support PREFETCHWT1 built-in functions and code generation. 923 1.5 mrg 924 1.3 mrg mfentry 925 1.11 mrg Target Report Var(flag_fentry) 926 1.3 mrg Emit profiling counter call at function entry before prologue. 927 1.3 mrg 928 1.5 mrg mrecord-mcount 929 1.11 mrg Target Report Var(flag_record_mcount) 930 1.5 mrg Generate __mcount_loc section with all mcount or __fentry__ calls. 931 1.5 mrg 932 1.5 mrg mnop-mcount 933 1.11 mrg Target Report Var(flag_nop_mcount) 934 1.5 mrg Generate mcount/__fentry__ calls as nops. To activate they need to be 935 1.5 mrg patched in. 936 1.5 mrg 937 1.12 mrg mfentry-name= 938 1.12 mrg Target RejectNegative Joined Var(fentry_name) 939 1.12 mrg Set name of __fentry__ symbol called at function entry. 940 1.12 mrg 941 1.12 mrg mfentry-section= 942 1.12 mrg Target RejectNegative Joined Var(fentry_section) 943 1.12 mrg Set name of section to record mrecord-mcount calls. 944 1.12 mrg 945 1.5 mrg mskip-rax-setup 946 1.11 mrg Target Report Var(flag_skip_rax_setup) 947 1.5 mrg Skip setting up RAX register when passing variable arguments. 948 1.5 mrg 949 1.3 mrg m8bit-idiv 950 1.3 mrg Target Report Mask(USE_8BIT_IDIV) Save 951 1.8 mrg Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. 952 1.3 mrg 953 1.3 mrg mavx256-split-unaligned-load 954 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 955 1.8 mrg Split 32-byte AVX unaligned load. 956 1.3 mrg 957 1.3 mrg mavx256-split-unaligned-store 958 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 959 1.8 mrg Split 32-byte AVX unaligned store. 960 1.3 mrg 961 1.3 mrg mrtm 962 1.3 mrg Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save 963 1.8 mrg Support RTM built-in functions and code generation. 964 1.5 mrg 965 1.5 mrg mmpx 966 1.12 mrg Target Deprecated 967 1.12 mrg Deprecated in GCC 9. This switch has no effect. 968 1.5 mrg 969 1.5 mrg mmwaitx 970 1.11 mrg Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags2) Save 971 1.8 mrg Support MWAITX and MONITORX built-in functions and code generation. 972 1.8 mrg 973 1.8 mrg mclzero 974 1.11 mrg Target Report Mask(ISA_CLZERO) Var(ix86_isa_flags2) Save 975 1.8 mrg Support CLZERO built-in functions and code generation. 976 1.8 mrg 977 1.8 mrg mpku 978 1.8 mrg Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save 979 1.8 mrg Support PKU built-in functions and code generation. 980 1.5 mrg 981 1.5 mrg mstack-protector-guard= 982 1.5 mrg Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) 983 1.8 mrg Use given stack-protector guard. 984 1.5 mrg 985 1.5 mrg Enum 986 1.5 mrg Name(stack_protector_guard) Type(enum stack_protector_guard) 987 1.5 mrg Known stack protector guard (for use with the -mstack-protector-guard= option): 988 1.5 mrg 989 1.5 mrg EnumValue 990 1.5 mrg Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 991 1.5 mrg 992 1.5 mrg EnumValue 993 1.5 mrg Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 994 1.7 mrg 995 1.11 mrg mstack-protector-guard-reg= 996 1.11 mrg Target RejectNegative Joined Var(ix86_stack_protector_guard_reg_str) 997 1.11 mrg Use the given base register for addressing the stack-protector guard. 998 1.11 mrg 999 1.11 mrg TargetVariable 1000 1.11 mrg addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC 1001 1.11 mrg 1002 1.11 mrg mstack-protector-guard-offset= 1003 1.11 mrg Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str) 1004 1.11 mrg Use the given offset for addressing the stack-protector guard. 1005 1.11 mrg 1006 1.11 mrg TargetVariable 1007 1.11 mrg HOST_WIDE_INT ix86_stack_protector_guard_offset = 0 1008 1.11 mrg 1009 1.11 mrg mstack-protector-guard-symbol= 1010 1.11 mrg Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str) 1011 1.11 mrg Use the given symbol for addressing the stack-protector guard. 1012 1.11 mrg 1013 1.8 mrg mmitigate-rop 1014 1.12 mrg Target Deprecated 1015 1.12 mrg ;; Deprecated 1016 1.8 mrg 1017 1.10 mrg mgeneral-regs-only 1018 1.10 mrg Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save 1019 1.10 mrg Generate code which uses only the general registers. 1020 1.10 mrg 1021 1.11 mrg mshstk 1022 1.11 mrg Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save 1023 1.11 mrg Enable shadow stack built-in functions from Control-flow Enforcement 1024 1.11 mrg Technology (CET). 1025 1.11 mrg 1026 1.11 mrg mcet-switch 1027 1.11 mrg Target Report Undocumented Var(flag_cet_switch) Init(0) 1028 1.11 mrg Turn on CET instrumentation for switch statements that use a jump table and 1029 1.11 mrg an indirect jump. 1030 1.11 mrg 1031 1.12 mrg mmanual-endbr 1032 1.12 mrg Target Report Var(flag_manual_endbr) Init(0) 1033 1.12 mrg Insert ENDBR instruction at function entry only via cf_check attribute 1034 1.12 mrg for CET instrumentation. 1035 1.12 mrg 1036 1.11 mrg mforce-indirect-call 1037 1.11 mrg Target Report Var(flag_force_indirect_call) Init(0) 1038 1.11 mrg Make all function calls indirect. 1039 1.11 mrg 1040 1.7 mrg mindirect-branch= 1041 1.7 mrg Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) 1042 1.7 mrg Convert indirect call and jump to call and return thunks. 1043 1.7 mrg 1044 1.7 mrg mfunction-return= 1045 1.7 mrg Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) 1046 1.7 mrg Convert function return to call and return thunk. 1047 1.7 mrg 1048 1.7 mrg Enum 1049 1.7 mrg Name(indirect_branch) Type(enum indirect_branch) 1050 1.7 mrg Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options): 1051 1.7 mrg 1052 1.7 mrg EnumValue 1053 1.7 mrg Enum(indirect_branch) String(keep) Value(indirect_branch_keep) 1054 1.7 mrg 1055 1.7 mrg EnumValue 1056 1.7 mrg Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk) 1057 1.7 mrg 1058 1.7 mrg EnumValue 1059 1.7 mrg Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline) 1060 1.7 mrg 1061 1.7 mrg EnumValue 1062 1.7 mrg Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) 1063 1.7 mrg 1064 1.7 mrg mindirect-branch-register 1065 1.7 mrg Target Report Var(ix86_indirect_branch_register) Init(0) 1066 1.7 mrg Force indirect call and jump via register. 1067 1.11 mrg 1068 1.11 mrg mmovdiri 1069 1.11 mrg Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save 1070 1.11 mrg Support MOVDIRI built-in functions and code generation. 1071 1.11 mrg 1072 1.11 mrg mmovdir64b 1073 1.11 mrg Target Report Mask(ISA_MOVDIR64B) Var(ix86_isa_flags2) Save 1074 1.11 mrg Support MOVDIR64B built-in functions and code generation. 1075 1.12 mrg 1076 1.12 mrg mwaitpkg 1077 1.12 mrg Target Report Mask(ISA_WAITPKG) Var(ix86_isa_flags2) Save 1078 1.12 mrg Support WAITPKG built-in functions and code generation. 1079 1.12 mrg 1080 1.12 mrg mcldemote 1081 1.12 mrg Target Report Mask(ISA_CLDEMOTE) Var(ix86_isa_flags2) Save 1082 1.12 mrg Support CLDEMOTE built-in functions and code generation. 1083 1.12 mrg 1084 1.12 mrg minstrument-return= 1085 1.12 mrg Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none) 1086 1.12 mrg Instrument function exit in instrumented functions with __fentry__. 1087 1.12 mrg 1088 1.12 mrg Enum 1089 1.12 mrg Name(instrument_return) Type(enum instrument_return) 1090 1.12 mrg Known choices for return instrumentation with -minstrument-return=: 1091 1.12 mrg 1092 1.12 mrg EnumValue 1093 1.12 mrg Enum(instrument_return) String(none) Value(instrument_return_none) 1094 1.12 mrg 1095 1.12 mrg EnumValue 1096 1.12 mrg Enum(instrument_return) String(call) Value(instrument_return_call) 1097 1.12 mrg 1098 1.12 mrg EnumValue 1099 1.12 mrg Enum(instrument_return) String(nop5) Value(instrument_return_nop5) 1100 1.12 mrg 1101 1.12 mrg mrecord-return 1102 1.12 mrg Target Report Var(ix86_flag_record_return) Init(0) 1103 1.12 mrg Generate a __return_loc section pointing to all return instrumentation code. 1104
Indexes created Wed Apr 29 00:23:26 UTC 2026