i386.opt revision 1.13
1 1.1 mrg ; Options for the IA-32 and AMD64 ports of the compiler. 2 1.1 mrg 3 1.13 mrg ; Copyright (C) 2005-2020 Free Software Foundation, Inc. 4 1.1 mrg ; 5 1.1 mrg ; This file is part of GCC. 6 1.1 mrg ; 7 1.1 mrg ; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ; version. 11 1.1 mrg ; 12 1.1 mrg ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ; for more details. 16 1.1 mrg ; 17 1.1 mrg ; You should have received a copy of the GNU General Public License 18 1.1 mrg ; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.3 mrg HeaderInclude 22 1.3 mrg config/i386/i386-opts.h 23 1.3 mrg 24 1.3 mrg ; Bit flags that specify the ISA we are compiling for. 25 1.3 mrg Variable 26 1.3 mrg HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 1.3 mrg 28 1.10 mrg Variable 29 1.10 mrg HOST_WIDE_INT ix86_isa_flags2 = 0 30 1.10 mrg 31 1.3 mrg ; A mask of ix86_isa_flags that includes bit X if X was set or cleared 32 1.3 mrg ; on the command line. 33 1.3 mrg Variable 34 1.3 mrg HOST_WIDE_INT ix86_isa_flags_explicit 35 1.3 mrg 36 1.10 mrg Variable 37 1.10 mrg HOST_WIDE_INT ix86_isa_flags2_explicit 38 1.10 mrg 39 1.10 mrg ; Additional target flags 40 1.10 mrg Variable 41 1.10 mrg int ix86_target_flags 42 1.10 mrg 43 1.3 mrg TargetVariable 44 1.3 mrg int recip_mask = RECIP_MASK_DEFAULT 45 1.3 mrg 46 1.3 mrg Variable 47 1.3 mrg int recip_mask_explicit 48 1.3 mrg 49 1.3 mrg TargetSave 50 1.3 mrg int x_recip_mask_explicit 51 1.3 mrg 52 1.13 mrg ;; A copy of flag_excess_precision as a target variable that should 53 1.13 mrg ;; force a different DECL_FUNCTION_SPECIFIC_TARGET upon 54 1.13 mrg ;; flag_excess_precision changes. 55 1.13 mrg TargetVariable 56 1.13 mrg enum excess_precision ix86_excess_precision = EXCESS_PRECISION_DEFAULT 57 1.13 mrg 58 1.13 mrg ;; Similarly for flag_unsafe_math_optimizations. 59 1.13 mrg TargetVariable 60 1.13 mrg bool ix86_unsafe_math_optimizations = false 61 1.13 mrg 62 1.1 mrg ;; Definitions to add to the cl_target_option structure 63 1.1 mrg ;; -march= processor 64 1.1 mrg TargetSave 65 1.1 mrg unsigned char arch 66 1.1 mrg 67 1.1 mrg ;; -mtune= processor 68 1.1 mrg TargetSave 69 1.1 mrg unsigned char tune 70 1.1 mrg 71 1.5 mrg ;; -march= processor-string 72 1.5 mrg TargetSave 73 1.5 mrg const char *x_ix86_arch_string 74 1.5 mrg 75 1.5 mrg ;; -mtune= processor-string 76 1.5 mrg TargetSave 77 1.5 mrg const char *x_ix86_tune_string 78 1.5 mrg 79 1.1 mrg ;; CPU schedule model 80 1.1 mrg TargetSave 81 1.1 mrg unsigned char schedule 82 1.1 mrg 83 1.5 mrg ;; True if processor has SSE prefetch instruction. 84 1.5 mrg TargetSave 85 1.5 mrg unsigned char prefetch_sse 86 1.5 mrg 87 1.1 mrg ;; branch cost 88 1.1 mrg TargetSave 89 1.1 mrg unsigned char branch_cost 90 1.1 mrg 91 1.1 mrg ;; which flags were passed by the user 92 1.1 mrg TargetSave 93 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags2_explicit 94 1.5 mrg 95 1.5 mrg ;; which flags were passed by the user 96 1.1 mrg TargetSave 97 1.10 mrg HOST_WIDE_INT x_ix86_isa_flags_explicit 98 1.1 mrg 99 1.1 mrg ;; whether -mtune was not specified 100 1.1 mrg TargetSave 101 1.1 mrg unsigned char tune_defaulted 102 1.1 mrg 103 1.1 mrg ;; whether -march was specified 104 1.1 mrg TargetSave 105 1.1 mrg unsigned char arch_specified 106 1.1 mrg 107 1.5 mrg ;; -mcmodel= model 108 1.5 mrg TargetSave 109 1.5 mrg enum cmodel x_ix86_cmodel 110 1.5 mrg 111 1.5 mrg ;; -mabi= 112 1.5 mrg TargetSave 113 1.5 mrg enum calling_abi x_ix86_abi 114 1.5 mrg 115 1.5 mrg ;; -masm= 116 1.5 mrg TargetSave 117 1.5 mrg enum asm_dialect x_ix86_asm_dialect 118 1.5 mrg 119 1.5 mrg ;; -mbranch-cost= 120 1.5 mrg TargetSave 121 1.5 mrg int x_ix86_branch_cost 122 1.5 mrg 123 1.8 mrg ;; -mdump-tune-features= 124 1.5 mrg TargetSave 125 1.5 mrg int x_ix86_dump_tunes 126 1.5 mrg 127 1.5 mrg ;; -mstackrealign= 128 1.5 mrg TargetSave 129 1.5 mrg int x_ix86_force_align_arg_pointer 130 1.5 mrg 131 1.8 mrg ;; -mforce-drap= 132 1.5 mrg TargetSave 133 1.5 mrg int x_ix86_force_drap 134 1.5 mrg 135 1.5 mrg ;; -mincoming-stack-boundary= 136 1.5 mrg TargetSave 137 1.5 mrg int x_ix86_incoming_stack_boundary_arg 138 1.5 mrg 139 1.5 mrg ;; -maddress-mode= 140 1.5 mrg TargetSave 141 1.5 mrg enum pmode x_ix86_pmode 142 1.5 mrg 143 1.8 mrg ;; -mpreferred-stack-boundary= 144 1.5 mrg TargetSave 145 1.5 mrg int x_ix86_preferred_stack_boundary_arg 146 1.5 mrg 147 1.5 mrg ;; -mrecip= 148 1.5 mrg TargetSave 149 1.5 mrg const char *x_ix86_recip_name 150 1.5 mrg 151 1.5 mrg ;; -mregparm= 152 1.5 mrg TargetSave 153 1.5 mrg int x_ix86_regparm 154 1.5 mrg 155 1.5 mrg ;; -mlarge-data-threshold= 156 1.5 mrg TargetSave 157 1.5 mrg int x_ix86_section_threshold 158 1.5 mrg 159 1.5 mrg ;; -msse2avx= 160 1.5 mrg TargetSave 161 1.5 mrg int x_ix86_sse2avx 162 1.5 mrg 163 1.5 mrg ;; -mstack-protector-guard= 164 1.5 mrg TargetSave 165 1.5 mrg enum stack_protector_guard x_ix86_stack_protector_guard 166 1.5 mrg 167 1.5 mrg ;; -mstringop-strategy= 168 1.5 mrg TargetSave 169 1.5 mrg enum stringop_alg x_ix86_stringop_alg 170 1.5 mrg 171 1.5 mrg ;; -mtls-dialect= 172 1.5 mrg TargetSave 173 1.5 mrg enum tls_dialect x_ix86_tls_dialect 174 1.5 mrg 175 1.5 mrg ;; -mtune-ctrl= 176 1.5 mrg TargetSave 177 1.5 mrg const char *x_ix86_tune_ctrl_string 178 1.5 mrg 179 1.5 mrg ;; -mmemcpy-strategy= 180 1.5 mrg TargetSave 181 1.5 mrg const char *x_ix86_tune_memcpy_strategy 182 1.5 mrg 183 1.5 mrg ;; -mmemset-strategy= 184 1.5 mrg TargetSave 185 1.5 mrg const char *x_ix86_tune_memset_strategy 186 1.5 mrg 187 1.5 mrg ;; -mno-default= 188 1.5 mrg TargetSave 189 1.5 mrg int x_ix86_tune_no_default 190 1.5 mrg 191 1.5 mrg ;; -mveclibabi= 192 1.5 mrg TargetSave 193 1.5 mrg enum ix86_veclibabi x_ix86_veclibabi_type 194 1.5 mrg 195 1.1 mrg ;; x86 options 196 1.1 mrg m128bit-long-double 197 1.1 mrg Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save 198 1.8 mrg sizeof(long double) is 16. 199 1.1 mrg 200 1.1 mrg m80387 201 1.1 mrg Target Report Mask(80387) Save 202 1.8 mrg Use hardware fp. 203 1.1 mrg 204 1.1 mrg m96bit-long-double 205 1.1 mrg Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save 206 1.8 mrg sizeof(long double) is 12. 207 1.1 mrg 208 1.3 mrg mlong-double-80 209 1.5 mrg Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save 210 1.8 mrg Use 80-bit long double. 211 1.3 mrg 212 1.3 mrg mlong-double-64 213 1.5 mrg Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save 214 1.8 mrg Use 64-bit long double. 215 1.3 mrg 216 1.5 mrg mlong-double-128 217 1.5 mrg Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save 218 1.8 mrg Use 128-bit long double. 219 1.5 mrg 220 1.1 mrg maccumulate-outgoing-args 221 1.1 mrg Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save 222 1.8 mrg Reserve space for outgoing arguments in the function prologue. 223 1.1 mrg 224 1.1 mrg malign-double 225 1.1 mrg Target Report Mask(ALIGN_DOUBLE) Save 226 1.8 mrg Align some doubles on dword boundary. 227 1.1 mrg 228 1.1 mrg malign-functions= 229 1.3 mrg Target RejectNegative Joined UInteger 230 1.8 mrg Function starts are aligned to this power of 2. 231 1.1 mrg 232 1.1 mrg malign-jumps= 233 1.3 mrg Target RejectNegative Joined UInteger 234 1.8 mrg Jump targets are aligned to this power of 2. 235 1.1 mrg 236 1.1 mrg malign-loops= 237 1.3 mrg Target RejectNegative Joined UInteger 238 1.8 mrg Loop code aligned to this power of 2. 239 1.1 mrg 240 1.1 mrg malign-stringops 241 1.1 mrg Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 242 1.8 mrg Align destination of the string operations. 243 1.1 mrg 244 1.5 mrg malign-data= 245 1.5 mrg Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) 246 1.8 mrg Use the given data alignment. 247 1.5 mrg 248 1.5 mrg Enum 249 1.5 mrg Name(ix86_align_data) Type(enum ix86_align_data) 250 1.5 mrg Known data alignment choices (for use with the -malign-data= option): 251 1.5 mrg 252 1.5 mrg EnumValue 253 1.5 mrg Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat) 254 1.5 mrg 255 1.5 mrg EnumValue 256 1.5 mrg Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi) 257 1.5 mrg 258 1.5 mrg EnumValue 259 1.5 mrg Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) 260 1.5 mrg 261 1.1 mrg march= 262 1.12 mrg Target RejectNegative Negative(march=) Joined Var(ix86_arch_string) 263 1.8 mrg Generate code for given CPU. 264 1.1 mrg 265 1.1 mrg masm= 266 1.3 mrg Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 267 1.8 mrg Use given assembler dialect. 268 1.1 mrg 269 1.3 mrg Enum 270 1.3 mrg Name(asm_dialect) Type(enum asm_dialect) 271 1.10 mrg Known assembler dialects (for use with the -masm= option): 272 1.3 mrg 273 1.3 mrg EnumValue 274 1.3 mrg Enum(asm_dialect) String(intel) Value(ASM_INTEL) 275 1.3 mrg 276 1.3 mrg EnumValue 277 1.3 mrg Enum(asm_dialect) String(att) Value(ASM_ATT) 278 1.3 mrg 279 1.1 mrg mbranch-cost= 280 1.11 mrg Target RejectNegative Joined UInteger Var(ix86_branch_cost) IntegerRange(0, 5) 281 1.11 mrg Branches are this expensive (arbitrary units). 282 1.1 mrg 283 1.1 mrg mlarge-data-threshold= 284 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 285 1.10 mrg -mlarge-data-threshold=<number> Data greater than given threshold will go into .ldata section in x86-64 medium model. 286 1.1 mrg 287 1.1 mrg mcmodel= 288 1.3 mrg Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 289 1.8 mrg Use given x86-64 code model. 290 1.1 mrg 291 1.3 mrg Enum 292 1.3 mrg Name(cmodel) Type(enum cmodel) 293 1.3 mrg Known code models (for use with the -mcmodel= option): 294 1.3 mrg 295 1.3 mrg EnumValue 296 1.3 mrg Enum(cmodel) String(small) Value(CM_SMALL) 297 1.3 mrg 298 1.3 mrg EnumValue 299 1.3 mrg Enum(cmodel) String(medium) Value(CM_MEDIUM) 300 1.3 mrg 301 1.3 mrg EnumValue 302 1.3 mrg Enum(cmodel) String(large) Value(CM_LARGE) 303 1.3 mrg 304 1.3 mrg EnumValue 305 1.3 mrg Enum(cmodel) String(32) Value(CM_32) 306 1.3 mrg 307 1.3 mrg EnumValue 308 1.3 mrg Enum(cmodel) String(kernel) Value(CM_KERNEL) 309 1.3 mrg 310 1.3 mrg maddress-mode= 311 1.3 mrg Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 312 1.8 mrg Use given address mode. 313 1.3 mrg 314 1.3 mrg Enum 315 1.3 mrg Name(pmode) Type(enum pmode) 316 1.3 mrg Known address mode (for use with the -maddress-mode= option): 317 1.3 mrg 318 1.3 mrg EnumValue 319 1.3 mrg Enum(pmode) String(short) Value(PMODE_SI) 320 1.3 mrg 321 1.3 mrg EnumValue 322 1.3 mrg Enum(pmode) String(long) Value(PMODE_DI) 323 1.3 mrg 324 1.3 mrg mcpu= 325 1.3 mrg Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 326 1.3 mrg 327 1.1 mrg mfancy-math-387 328 1.1 mrg Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 329 1.8 mrg Generate sin, cos, sqrt for FPU. 330 1.1 mrg 331 1.1 mrg mforce-drap 332 1.1 mrg Target Report Var(ix86_force_drap) 333 1.8 mrg Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack. 334 1.1 mrg 335 1.1 mrg mfp-ret-in-387 336 1.1 mrg Target Report Mask(FLOAT_RETURNS) Save 337 1.8 mrg Return values of functions in FPU registers. 338 1.1 mrg 339 1.1 mrg mfpmath= 340 1.3 mrg Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 341 1.8 mrg Generate floating point mathematics using given instruction set. 342 1.1 mrg 343 1.3 mrg Enum 344 1.3 mrg Name(fpmath_unit) Type(enum fpmath_unit) 345 1.3 mrg Valid arguments to -mfpmath=: 346 1.3 mrg 347 1.3 mrg EnumValue 348 1.3 mrg Enum(fpmath_unit) String(387) Value(FPMATH_387) 349 1.3 mrg 350 1.3 mrg EnumValue 351 1.3 mrg Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 352 1.3 mrg 353 1.3 mrg EnumValue 354 1.3 mrg Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 355 1.3 mrg 356 1.3 mrg EnumValue 357 1.3 mrg Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 358 1.3 mrg 359 1.3 mrg EnumValue 360 1.3 mrg Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 361 1.3 mrg 362 1.3 mrg EnumValue 363 1.3 mrg Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 364 1.3 mrg 365 1.3 mrg EnumValue 366 1.3 mrg Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 367 1.3 mrg 368 1.1 mrg mhard-float 369 1.3 mrg Target RejectNegative Mask(80387) Save 370 1.8 mrg Use hardware fp. 371 1.1 mrg 372 1.1 mrg mieee-fp 373 1.1 mrg Target Report Mask(IEEE_FP) Save 374 1.8 mrg Use IEEE math for fp comparisons. 375 1.1 mrg 376 1.1 mrg minline-all-stringops 377 1.1 mrg Target Report Mask(INLINE_ALL_STRINGOPS) Save 378 1.8 mrg Inline all known string operations. 379 1.1 mrg 380 1.1 mrg minline-stringops-dynamically 381 1.1 mrg Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 382 1.8 mrg Inline memset/memcpy string operations, but perform inline version only for small blocks. 383 1.1 mrg 384 1.1 mrg mintel-syntax 385 1.3 mrg Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 386 1.1 mrg 387 1.1 mrg mms-bitfields 388 1.1 mrg Target Report Mask(MS_BITFIELD_LAYOUT) Save 389 1.8 mrg Use native (MS) bitfield layout. 390 1.1 mrg 391 1.1 mrg mno-align-stringops 392 1.1 mrg Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save 393 1.1 mrg 394 1.1 mrg mno-fancy-math-387 395 1.1 mrg Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save 396 1.1 mrg 397 1.1 mrg mno-push-args 398 1.1 mrg Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save 399 1.1 mrg 400 1.1 mrg mno-red-zone 401 1.1 mrg Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save 402 1.1 mrg 403 1.1 mrg momit-leaf-frame-pointer 404 1.1 mrg Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save 405 1.8 mrg Omit the frame pointer in leaf functions. 406 1.1 mrg 407 1.3 mrg mpc32 408 1.3 mrg Target RejectNegative Report 409 1.8 mrg Set 80387 floating-point precision to 32-bit. 410 1.3 mrg 411 1.3 mrg mpc64 412 1.3 mrg Target RejectNegative Report 413 1.8 mrg Set 80387 floating-point precision to 64-bit. 414 1.3 mrg 415 1.3 mrg mpc80 416 1.3 mrg Target RejectNegative Report 417 1.8 mrg Set 80387 floating-point precision to 80-bit. 418 1.1 mrg 419 1.1 mrg mpreferred-stack-boundary= 420 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 421 1.8 mrg Attempt to keep stack aligned to this power of 2. 422 1.1 mrg 423 1.1 mrg mincoming-stack-boundary= 424 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 425 1.8 mrg Assume incoming stack aligned to this power of 2. 426 1.1 mrg 427 1.1 mrg mpush-args 428 1.1 mrg Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 429 1.8 mrg Use push instructions to save outgoing arguments. 430 1.1 mrg 431 1.1 mrg mred-zone 432 1.1 mrg Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save 433 1.8 mrg Use red-zone in the x86-64 code. 434 1.1 mrg 435 1.1 mrg mregparm= 436 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_regparm) 437 1.8 mrg Number of registers used to pass integer arguments. 438 1.1 mrg 439 1.1 mrg mrtd 440 1.1 mrg Target Report Mask(RTD) Save 441 1.8 mrg Alternate calling convention. 442 1.1 mrg 443 1.1 mrg msoft-float 444 1.1 mrg Target InverseMask(80387) Save 445 1.8 mrg Do not use hardware fp. 446 1.1 mrg 447 1.1 mrg msseregparm 448 1.1 mrg Target RejectNegative Mask(SSEREGPARM) Save 449 1.8 mrg Use SSE register passing conventions for SF and DF mode. 450 1.1 mrg 451 1.1 mrg mstackrealign 452 1.11 mrg Target Report Var(ix86_force_align_arg_pointer) 453 1.8 mrg Realign stack in prologue. 454 1.1 mrg 455 1.1 mrg mstack-arg-probe 456 1.1 mrg Target Report Mask(STACK_PROBE) Save 457 1.8 mrg Enable stack probing. 458 1.1 mrg 459 1.5 mrg mmemcpy-strategy= 460 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) 461 1.8 mrg Specify memcpy expansion strategy when expected size is known. 462 1.5 mrg 463 1.5 mrg mmemset-strategy= 464 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memset_strategy) 465 1.8 mrg Specify memset expansion strategy when expected size is known. 466 1.5 mrg 467 1.1 mrg mstringop-strategy= 468 1.3 mrg Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 469 1.8 mrg Chose strategy to generate stringop using. 470 1.1 mrg 471 1.3 mrg Enum 472 1.3 mrg Name(stringop_alg) Type(enum stringop_alg) 473 1.3 mrg Valid arguments to -mstringop-strategy=: 474 1.3 mrg 475 1.3 mrg EnumValue 476 1.3 mrg Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 477 1.3 mrg 478 1.3 mrg EnumValue 479 1.3 mrg Enum(stringop_alg) String(libcall) Value(libcall) 480 1.3 mrg 481 1.3 mrg EnumValue 482 1.3 mrg Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 483 1.3 mrg 484 1.3 mrg EnumValue 485 1.3 mrg Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 486 1.3 mrg 487 1.3 mrg EnumValue 488 1.3 mrg Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 489 1.3 mrg 490 1.3 mrg EnumValue 491 1.3 mrg Enum(stringop_alg) String(loop) Value(loop) 492 1.3 mrg 493 1.3 mrg EnumValue 494 1.3 mrg Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 495 1.3 mrg 496 1.5 mrg EnumValue 497 1.5 mrg Enum(stringop_alg) String(vector_loop) Value(vector_loop) 498 1.5 mrg 499 1.1 mrg mtls-dialect= 500 1.3 mrg Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 501 1.8 mrg Use given thread-local storage dialect. 502 1.1 mrg 503 1.3 mrg Enum 504 1.3 mrg Name(tls_dialect) Type(enum tls_dialect) 505 1.3 mrg Known TLS dialects (for use with the -mtls-dialect= option): 506 1.3 mrg 507 1.3 mrg EnumValue 508 1.3 mrg Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 509 1.3 mrg 510 1.3 mrg EnumValue 511 1.3 mrg Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 512 1.3 mrg 513 1.1 mrg mtls-direct-seg-refs 514 1.1 mrg Target Report Mask(TLS_DIRECT_SEG_REFS) 515 1.8 mrg Use direct references against %gs when accessing tls data. 516 1.1 mrg 517 1.1 mrg mtune= 518 1.12 mrg Target RejectNegative Negative(mtune=) Joined Var(ix86_tune_string) 519 1.8 mrg Schedule code for given CPU. 520 1.1 mrg 521 1.5 mrg mtune-ctrl= 522 1.5 mrg Target RejectNegative Joined Var(ix86_tune_ctrl_string) 523 1.8 mrg Fine grain control of tune features. 524 1.5 mrg 525 1.5 mrg mno-default 526 1.11 mrg Target RejectNegative Var(ix86_tune_no_default) 527 1.8 mrg Clear all tune features. 528 1.5 mrg 529 1.5 mrg mdump-tune-features 530 1.11 mrg Target RejectNegative Var(ix86_dump_tunes) 531 1.5 mrg 532 1.8 mrg miamcu 533 1.8 mrg Target Report Mask(IAMCU) 534 1.8 mrg Generate code that conforms to Intel MCU psABI. 535 1.8 mrg 536 1.1 mrg mabi= 537 1.3 mrg Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 538 1.8 mrg Generate code that conforms to the given ABI. 539 1.1 mrg 540 1.3 mrg Enum 541 1.3 mrg Name(calling_abi) Type(enum calling_abi) 542 1.3 mrg Known ABIs (for use with the -mabi= option): 543 1.3 mrg 544 1.3 mrg EnumValue 545 1.3 mrg Enum(calling_abi) String(sysv) Value(SYSV_ABI) 546 1.3 mrg 547 1.3 mrg EnumValue 548 1.3 mrg Enum(calling_abi) String(ms) Value(MS_ABI) 549 1.3 mrg 550 1.11 mrg mcall-ms2sysv-xlogues 551 1.11 mrg Target Report Mask(CALL_MS2SYSV_XLOGUES) Save 552 1.11 mrg Use libgcc stubs to save and restore registers clobbered by 64-bit Microsoft to System V ABI calls. 553 1.11 mrg 554 1.1 mrg mveclibabi= 555 1.3 mrg Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 556 1.8 mrg Vector library ABI to use. 557 1.1 mrg 558 1.3 mrg Enum 559 1.3 mrg Name(ix86_veclibabi) Type(enum ix86_veclibabi) 560 1.3 mrg Known vectorization library ABIs (for use with the -mveclibabi= option): 561 1.3 mrg 562 1.3 mrg EnumValue 563 1.3 mrg Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 564 1.3 mrg 565 1.3 mrg EnumValue 566 1.3 mrg Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 567 1.3 mrg 568 1.3 mrg mvect8-ret-in-mem 569 1.3 mrg Target Report Mask(VECT8_RETURNS) Save 570 1.8 mrg Return 8-byte vectors in memory. 571 1.3 mrg 572 1.1 mrg mrecip 573 1.1 mrg Target Report Mask(RECIP) Save 574 1.1 mrg Generate reciprocals instead of divss and sqrtss. 575 1.1 mrg 576 1.3 mrg mrecip= 577 1.3 mrg Target Report RejectNegative Joined Var(ix86_recip_name) 578 1.3 mrg Control generation of reciprocal estimates. 579 1.3 mrg 580 1.1 mrg mcld 581 1.1 mrg Target Report Mask(CLD) Save 582 1.1 mrg Generate cld instruction in the function prologue. 583 1.1 mrg 584 1.3 mrg mvzeroupper 585 1.3 mrg Target Report Mask(VZEROUPPER) Save 586 1.3 mrg Generate vzeroupper instruction before a transfer of control flow out of 587 1.3 mrg the function. 588 1.3 mrg 589 1.8 mrg mstv 590 1.8 mrg Target Report Mask(STV) Save 591 1.8 mrg Disable Scalar to Vector optimization pass transforming 64-bit integer 592 1.8 mrg computations into a vector ones. 593 1.8 mrg 594 1.3 mrg mdispatch-scheduler 595 1.3 mrg Target RejectNegative Var(flag_dispatch_scheduler) 596 1.8 mrg Do dispatch scheduling if processor is bdver1, bdver2, bdver3, bdver4 597 1.8 mrg or znver1 and Haifa scheduling is selected. 598 1.3 mrg 599 1.3 mrg mprefer-avx128 600 1.11 mrg Target Alias(mprefer-vector-width=, 128, 256) 601 1.3 mrg Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 602 1.1 mrg 603 1.11 mrg mprefer-vector-width= 604 1.13 mrg Target Report RejectNegative Joined Var(prefer_vector_width_type) Enum(prefer_vector_width) Init(PVW_NONE) Save 605 1.11 mrg Use given register vector width instructions instead of maximum register width in the auto-vectorizer. 606 1.11 mrg 607 1.11 mrg Enum 608 1.11 mrg Name(prefer_vector_width) Type(enum prefer_vector_width) 609 1.12 mrg Known preferred register vector length (to use with the -mprefer-vector-width= option): 610 1.11 mrg 611 1.11 mrg EnumValue 612 1.11 mrg Enum(prefer_vector_width) String(none) Value(PVW_NONE) 613 1.11 mrg 614 1.11 mrg EnumValue 615 1.11 mrg Enum(prefer_vector_width) String(128) Value(PVW_AVX128) 616 1.11 mrg 617 1.11 mrg EnumValue 618 1.11 mrg Enum(prefer_vector_width) String(256) Value(PVW_AVX256) 619 1.11 mrg 620 1.11 mrg EnumValue 621 1.11 mrg Enum(prefer_vector_width) String(512) Value(PVW_AVX512) 622 1.11 mrg 623 1.1 mrg ;; ISA support 624 1.1 mrg 625 1.1 mrg m32 626 1.3 mrg Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 627 1.8 mrg Generate 32bit i386 code. 628 1.1 mrg 629 1.1 mrg m64 630 1.3 mrg Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save 631 1.8 mrg Generate 64bit x86-64 code. 632 1.1 mrg 633 1.3 mrg mx32 634 1.5 mrg Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save 635 1.8 mrg Generate 32bit x86-64 code. 636 1.3 mrg 637 1.5 mrg m16 638 1.5 mrg Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 639 1.8 mrg Generate 16bit i386 code. 640 1.5 mrg 641 1.1 mrg mmmx 642 1.3 mrg Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save 643 1.8 mrg Support MMX built-in functions. 644 1.1 mrg 645 1.1 mrg m3dnow 646 1.3 mrg Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 647 1.8 mrg Support 3DNow! built-in functions. 648 1.1 mrg 649 1.1 mrg m3dnowa 650 1.10 mrg Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 651 1.8 mrg Support Athlon 3Dnow! built-in functions. 652 1.1 mrg 653 1.1 mrg msse 654 1.3 mrg Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save 655 1.8 mrg Support MMX and SSE built-in functions and code generation. 656 1.1 mrg 657 1.1 mrg msse2 658 1.3 mrg Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save 659 1.8 mrg Support MMX, SSE and SSE2 built-in functions and code generation. 660 1.1 mrg 661 1.1 mrg msse3 662 1.3 mrg Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save 663 1.8 mrg Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation. 664 1.1 mrg 665 1.1 mrg mssse3 666 1.3 mrg Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 667 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation. 668 1.1 mrg 669 1.1 mrg msse4.1 670 1.3 mrg Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 671 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation. 672 1.1 mrg 673 1.1 mrg msse4.2 674 1.3 mrg Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 675 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 676 1.1 mrg 677 1.1 mrg msse4 678 1.3 mrg Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 679 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation. 680 1.1 mrg 681 1.1 mrg mno-sse4 682 1.3 mrg Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 683 1.8 mrg Do not support SSE4.1 and SSE4.2 built-in functions and code generation. 684 1.1 mrg 685 1.3 mrg msse5 686 1.3 mrg Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 687 1.3 mrg ;; Deprecated 688 1.3 mrg 689 1.1 mrg mavx 690 1.3 mrg Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save 691 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation. 692 1.1 mrg 693 1.3 mrg mavx2 694 1.3 mrg Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save 695 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation. 696 1.3 mrg 697 1.5 mrg mavx512f 698 1.5 mrg Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save 699 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation. 700 1.5 mrg 701 1.5 mrg mavx512pf 702 1.5 mrg Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save 703 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation. 704 1.5 mrg 705 1.5 mrg mavx512er 706 1.5 mrg Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save 707 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation. 708 1.5 mrg 709 1.5 mrg mavx512cd 710 1.5 mrg Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save 711 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation. 712 1.5 mrg 713 1.5 mrg mavx512dq 714 1.5 mrg Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save 715 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation. 716 1.5 mrg 717 1.5 mrg mavx512bw 718 1.5 mrg Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save 719 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation. 720 1.5 mrg 721 1.5 mrg mavx512vl 722 1.5 mrg Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save 723 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation. 724 1.5 mrg 725 1.5 mrg mavx512ifma 726 1.5 mrg Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save 727 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation. 728 1.5 mrg 729 1.5 mrg mavx512vbmi 730 1.5 mrg Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save 731 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation. 732 1.5 mrg 733 1.10 mrg mavx5124fmaps 734 1.13 mrg Target Report Mask(ISA2_AVX5124FMAPS) Var(ix86_isa_flags2) Save 735 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124FMAPS built-in functions and code generation. 736 1.10 mrg 737 1.10 mrg mavx5124vnniw 738 1.13 mrg Target Report Mask(ISA2_AVX5124VNNIW) Var(ix86_isa_flags2) Save 739 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX5124VNNIW built-in functions and code generation. 740 1.10 mrg 741 1.10 mrg mavx512vpopcntdq 742 1.11 mrg Target Report Mask(ISA_AVX512VPOPCNTDQ) Var(ix86_isa_flags) Save 743 1.10 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VPOPCNTDQ built-in functions and code generation. 744 1.10 mrg 745 1.11 mrg mavx512vbmi2 746 1.11 mrg Target Report Mask(ISA_AVX512VBMI2) Var(ix86_isa_flags) Save 747 1.11 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512VBMI2 built-in functions and code generation. 748 1.11 mrg 749 1.11 mrg mavx512vnni 750 1.11 mrg Target Report Mask(ISA_AVX512VNNI) Var(ix86_isa_flags) Save 751 1.11 mrg Support AVX512VNNI built-in functions and code generation. 752 1.11 mrg 753 1.11 mrg mavx512bitalg 754 1.11 mrg Target Report Mask(ISA_AVX512BITALG) Var(ix86_isa_flags) Save 755 1.11 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512BITALG built-in functions and code generation. 756 1.11 mrg 757 1.13 mrg mavx512vp2intersect 758 1.13 mrg Target Report Mask(ISA2_AVX512VP2INTERSECT) Var(ix86_isa_flags2) Save 759 1.13 mrg Support AVX512VP2INTERSECT built-in functions and code generation. 760 1.13 mrg 761 1.1 mrg mfma 762 1.3 mrg Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save 763 1.8 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation. 764 1.1 mrg 765 1.1 mrg msse4a 766 1.3 mrg Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 767 1.8 mrg Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation. 768 1.1 mrg 769 1.1 mrg mfma4 770 1.3 mrg Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save 771 1.8 mrg Support FMA4 built-in functions and code generation. 772 1.1 mrg 773 1.1 mrg mxop 774 1.3 mrg Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save 775 1.8 mrg Support XOP built-in functions and code generation. 776 1.1 mrg 777 1.1 mrg mlwp 778 1.3 mrg Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save 779 1.8 mrg Support LWP built-in functions and code generation. 780 1.1 mrg 781 1.1 mrg mabm 782 1.3 mrg Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save 783 1.1 mrg Support code generation of Advanced Bit Manipulation (ABM) instructions. 784 1.1 mrg 785 1.1 mrg mpopcnt 786 1.3 mrg Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 787 1.1 mrg Support code generation of popcnt instruction. 788 1.1 mrg 789 1.11 mrg mpconfig 790 1.13 mrg Target Report Mask(ISA2_PCONFIG) Var(ix86_isa_flags2) Save 791 1.11 mrg Support PCONFIG built-in functions and code generation. 792 1.11 mrg 793 1.11 mrg mwbnoinvd 794 1.13 mrg Target Report Mask(ISA2_WBNOINVD) Var(ix86_isa_flags2) Save 795 1.11 mrg Support WBNOINVD built-in functions and code generation. 796 1.11 mrg 797 1.12 mrg mptwrite 798 1.13 mrg Target Report Mask(ISA2_PTWRITE) Var(ix86_isa_flags2) Save 799 1.12 mrg Support PTWRITE built-in functions and code generation. 800 1.12 mrg 801 1.10 mrg msgx 802 1.13 mrg Target Report Mask(ISA2_SGX) Var(ix86_isa_flags2) Save 803 1.10 mrg Support SGX built-in functions and code generation. 804 1.10 mrg 805 1.10 mrg mrdpid 806 1.13 mrg Target Report Mask(ISA2_RDPID) Var(ix86_isa_flags2) Save 807 1.10 mrg Support RDPID built-in functions and code generation. 808 1.10 mrg 809 1.11 mrg mgfni 810 1.11 mrg Target Report Mask(ISA_GFNI) Var(ix86_isa_flags) Save 811 1.11 mrg Support GFNI built-in functions and code generation. 812 1.11 mrg 813 1.11 mrg mvaes 814 1.13 mrg Target Report Mask(ISA2_VAES) Var(ix86_isa_flags2) Save 815 1.11 mrg Support VAES built-in functions and code generation. 816 1.11 mrg 817 1.11 mrg mvpclmulqdq 818 1.11 mrg Target Report Mask(ISA_VPCLMULQDQ) Var(ix86_isa_flags) Save 819 1.11 mrg Support VPCLMULQDQ built-in functions and code generation. 820 1.11 mrg 821 1.3 mrg mbmi 822 1.3 mrg Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save 823 1.8 mrg Support BMI built-in functions and code generation. 824 1.3 mrg 825 1.3 mrg mbmi2 826 1.3 mrg Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save 827 1.8 mrg Support BMI2 built-in functions and code generation. 828 1.3 mrg 829 1.3 mrg mlzcnt 830 1.3 mrg Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 831 1.8 mrg Support LZCNT built-in function and code generation. 832 1.3 mrg 833 1.3 mrg mhle 834 1.13 mrg Target Report Mask(ISA2_HLE) Var(ix86_isa_flags2) Save 835 1.8 mrg Support Hardware Lock Elision prefixes. 836 1.3 mrg 837 1.3 mrg mrdseed 838 1.3 mrg Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 839 1.8 mrg Support RDSEED instruction. 840 1.3 mrg 841 1.3 mrg mprfchw 842 1.3 mrg Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 843 1.8 mrg Support PREFETCHW instruction. 844 1.3 mrg 845 1.3 mrg madx 846 1.3 mrg Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save 847 1.8 mrg Support flag-preserving add-carry instructions. 848 1.3 mrg 849 1.5 mrg mclflushopt 850 1.5 mrg Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save 851 1.8 mrg Support CLFLUSHOPT instructions. 852 1.5 mrg 853 1.5 mrg mclwb 854 1.5 mrg Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save 855 1.8 mrg Support CLWB instruction. 856 1.5 mrg 857 1.5 mrg mpcommit 858 1.13 mrg Target WarnRemoved 859 1.5 mrg 860 1.3 mrg mfxsr 861 1.3 mrg Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save 862 1.8 mrg Support FXSAVE and FXRSTOR instructions. 863 1.3 mrg 864 1.3 mrg mxsave 865 1.3 mrg Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 866 1.8 mrg Support XSAVE and XRSTOR instructions. 867 1.3 mrg 868 1.3 mrg mxsaveopt 869 1.3 mrg Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 870 1.8 mrg Support XSAVEOPT instruction. 871 1.3 mrg 872 1.5 mrg mxsavec 873 1.5 mrg Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save 874 1.8 mrg Support XSAVEC instructions. 875 1.5 mrg 876 1.5 mrg mxsaves 877 1.5 mrg Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save 878 1.8 mrg Support XSAVES and XRSTORS instructions. 879 1.5 mrg 880 1.3 mrg mtbm 881 1.3 mrg Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save 882 1.8 mrg Support TBM built-in functions and code generation. 883 1.3 mrg 884 1.1 mrg mcx16 885 1.13 mrg Target Report Mask(ISA2_CX16) Var(ix86_isa_flags2) Save 886 1.1 mrg Support code generation of cmpxchg16b instruction. 887 1.1 mrg 888 1.1 mrg msahf 889 1.3 mrg Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save 890 1.1 mrg Support code generation of sahf instruction in 64bit x86-64 code. 891 1.1 mrg 892 1.1 mrg mmovbe 893 1.13 mrg Target Report Mask(ISA2_MOVBE) Var(ix86_isa_flags2) Save 894 1.1 mrg Support code generation of movbe instruction. 895 1.1 mrg 896 1.1 mrg mcrc32 897 1.3 mrg Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save 898 1.1 mrg Support code generation of crc32 instruction. 899 1.1 mrg 900 1.1 mrg maes 901 1.3 mrg Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save 902 1.8 mrg Support AES built-in functions and code generation. 903 1.1 mrg 904 1.5 mrg msha 905 1.5 mrg Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save 906 1.8 mrg Support SHA1 and SHA256 built-in functions and code generation. 907 1.5 mrg 908 1.1 mrg mpclmul 909 1.3 mrg Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 910 1.8 mrg Support PCLMUL built-in functions and code generation. 911 1.1 mrg 912 1.1 mrg msse2avx 913 1.1 mrg Target Report Var(ix86_sse2avx) 914 1.8 mrg Encode SSE instructions with VEX prefix. 915 1.3 mrg 916 1.3 mrg mfsgsbase 917 1.3 mrg Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 918 1.8 mrg Support FSGSBASE built-in functions and code generation. 919 1.3 mrg 920 1.3 mrg mrdrnd 921 1.3 mrg Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save 922 1.8 mrg Support RDRND built-in functions and code generation. 923 1.3 mrg 924 1.3 mrg mf16c 925 1.3 mrg Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save 926 1.8 mrg Support F16C built-in functions and code generation. 927 1.3 mrg 928 1.5 mrg mprefetchwt1 929 1.5 mrg Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save 930 1.8 mrg Support PREFETCHWT1 built-in functions and code generation. 931 1.5 mrg 932 1.3 mrg mfentry 933 1.11 mrg Target Report Var(flag_fentry) 934 1.3 mrg Emit profiling counter call at function entry before prologue. 935 1.3 mrg 936 1.5 mrg mrecord-mcount 937 1.11 mrg Target Report Var(flag_record_mcount) 938 1.5 mrg Generate __mcount_loc section with all mcount or __fentry__ calls. 939 1.5 mrg 940 1.5 mrg mnop-mcount 941 1.11 mrg Target Report Var(flag_nop_mcount) 942 1.5 mrg Generate mcount/__fentry__ calls as nops. To activate they need to be 943 1.5 mrg patched in. 944 1.5 mrg 945 1.12 mrg mfentry-name= 946 1.12 mrg Target RejectNegative Joined Var(fentry_name) 947 1.12 mrg Set name of __fentry__ symbol called at function entry. 948 1.12 mrg 949 1.12 mrg mfentry-section= 950 1.12 mrg Target RejectNegative Joined Var(fentry_section) 951 1.12 mrg Set name of section to record mrecord-mcount calls. 952 1.12 mrg 953 1.5 mrg mskip-rax-setup 954 1.11 mrg Target Report Var(flag_skip_rax_setup) 955 1.5 mrg Skip setting up RAX register when passing variable arguments. 956 1.5 mrg 957 1.3 mrg m8bit-idiv 958 1.3 mrg Target Report Mask(USE_8BIT_IDIV) Save 959 1.8 mrg Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check. 960 1.3 mrg 961 1.3 mrg mavx256-split-unaligned-load 962 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 963 1.8 mrg Split 32-byte AVX unaligned load. 964 1.3 mrg 965 1.3 mrg mavx256-split-unaligned-store 966 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 967 1.8 mrg Split 32-byte AVX unaligned store. 968 1.3 mrg 969 1.3 mrg mrtm 970 1.3 mrg Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save 971 1.8 mrg Support RTM built-in functions and code generation. 972 1.5 mrg 973 1.5 mrg mmpx 974 1.13 mrg Target WarnRemoved 975 1.13 mrg Removed in GCC 9. This switch has no effect. 976 1.5 mrg 977 1.5 mrg mmwaitx 978 1.13 mrg Target Report Mask(ISA2_MWAITX) Var(ix86_isa_flags2) Save 979 1.8 mrg Support MWAITX and MONITORX built-in functions and code generation. 980 1.8 mrg 981 1.8 mrg mclzero 982 1.13 mrg Target Report Mask(ISA2_CLZERO) Var(ix86_isa_flags2) Save 983 1.8 mrg Support CLZERO built-in functions and code generation. 984 1.8 mrg 985 1.8 mrg mpku 986 1.8 mrg Target Report Mask(ISA_PKU) Var(ix86_isa_flags) Save 987 1.8 mrg Support PKU built-in functions and code generation. 988 1.5 mrg 989 1.5 mrg mstack-protector-guard= 990 1.5 mrg Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) 991 1.8 mrg Use given stack-protector guard. 992 1.5 mrg 993 1.5 mrg Enum 994 1.5 mrg Name(stack_protector_guard) Type(enum stack_protector_guard) 995 1.5 mrg Known stack protector guard (for use with the -mstack-protector-guard= option): 996 1.5 mrg 997 1.5 mrg EnumValue 998 1.5 mrg Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 999 1.5 mrg 1000 1.5 mrg EnumValue 1001 1.5 mrg Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 1002 1.7 mrg 1003 1.11 mrg mstack-protector-guard-reg= 1004 1.11 mrg Target RejectNegative Joined Var(ix86_stack_protector_guard_reg_str) 1005 1.11 mrg Use the given base register for addressing the stack-protector guard. 1006 1.11 mrg 1007 1.11 mrg TargetVariable 1008 1.11 mrg addr_space_t ix86_stack_protector_guard_reg = ADDR_SPACE_GENERIC 1009 1.11 mrg 1010 1.11 mrg mstack-protector-guard-offset= 1011 1.11 mrg Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_offset_str) 1012 1.11 mrg Use the given offset for addressing the stack-protector guard. 1013 1.11 mrg 1014 1.11 mrg TargetVariable 1015 1.11 mrg HOST_WIDE_INT ix86_stack_protector_guard_offset = 0 1016 1.11 mrg 1017 1.11 mrg mstack-protector-guard-symbol= 1018 1.11 mrg Target RejectNegative Joined Integer Var(ix86_stack_protector_guard_symbol_str) 1019 1.11 mrg Use the given symbol for addressing the stack-protector guard. 1020 1.11 mrg 1021 1.8 mrg mmitigate-rop 1022 1.13 mrg Target WarnRemoved 1023 1.8 mrg 1024 1.10 mrg mgeneral-regs-only 1025 1.10 mrg Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save 1026 1.10 mrg Generate code which uses only the general registers. 1027 1.10 mrg 1028 1.11 mrg mshstk 1029 1.11 mrg Target Report Mask(ISA_SHSTK) Var(ix86_isa_flags) Save 1030 1.11 mrg Enable shadow stack built-in functions from Control-flow Enforcement 1031 1.11 mrg Technology (CET). 1032 1.11 mrg 1033 1.11 mrg mcet-switch 1034 1.11 mrg Target Report Undocumented Var(flag_cet_switch) Init(0) 1035 1.11 mrg Turn on CET instrumentation for switch statements that use a jump table and 1036 1.11 mrg an indirect jump. 1037 1.11 mrg 1038 1.12 mrg mmanual-endbr 1039 1.12 mrg Target Report Var(flag_manual_endbr) Init(0) 1040 1.12 mrg Insert ENDBR instruction at function entry only via cf_check attribute 1041 1.12 mrg for CET instrumentation. 1042 1.12 mrg 1043 1.11 mrg mforce-indirect-call 1044 1.11 mrg Target Report Var(flag_force_indirect_call) Init(0) 1045 1.11 mrg Make all function calls indirect. 1046 1.11 mrg 1047 1.7 mrg mindirect-branch= 1048 1.7 mrg Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_indirect_branch) Init(indirect_branch_keep) 1049 1.7 mrg Convert indirect call and jump to call and return thunks. 1050 1.7 mrg 1051 1.7 mrg mfunction-return= 1052 1.7 mrg Target Report RejectNegative Joined Enum(indirect_branch) Var(ix86_function_return) Init(indirect_branch_keep) 1053 1.7 mrg Convert function return to call and return thunk. 1054 1.7 mrg 1055 1.7 mrg Enum 1056 1.7 mrg Name(indirect_branch) Type(enum indirect_branch) 1057 1.7 mrg Known indirect branch choices (for use with the -mindirect-branch=/-mfunction-return= options): 1058 1.7 mrg 1059 1.7 mrg EnumValue 1060 1.7 mrg Enum(indirect_branch) String(keep) Value(indirect_branch_keep) 1061 1.7 mrg 1062 1.7 mrg EnumValue 1063 1.7 mrg Enum(indirect_branch) String(thunk) Value(indirect_branch_thunk) 1064 1.7 mrg 1065 1.7 mrg EnumValue 1066 1.7 mrg Enum(indirect_branch) String(thunk-inline) Value(indirect_branch_thunk_inline) 1067 1.7 mrg 1068 1.7 mrg EnumValue 1069 1.7 mrg Enum(indirect_branch) String(thunk-extern) Value(indirect_branch_thunk_extern) 1070 1.7 mrg 1071 1.7 mrg mindirect-branch-register 1072 1.7 mrg Target Report Var(ix86_indirect_branch_register) Init(0) 1073 1.7 mrg Force indirect call and jump via register. 1074 1.11 mrg 1075 1.11 mrg mmovdiri 1076 1.11 mrg Target Report Mask(ISA_MOVDIRI) Var(ix86_isa_flags) Save 1077 1.11 mrg Support MOVDIRI built-in functions and code generation. 1078 1.11 mrg 1079 1.11 mrg mmovdir64b 1080 1.13 mrg Target Report Mask(ISA2_MOVDIR64B) Var(ix86_isa_flags2) Save 1081 1.11 mrg Support MOVDIR64B built-in functions and code generation. 1082 1.12 mrg 1083 1.12 mrg mwaitpkg 1084 1.13 mrg Target Report Mask(ISA2_WAITPKG) Var(ix86_isa_flags2) Save 1085 1.12 mrg Support WAITPKG built-in functions and code generation. 1086 1.12 mrg 1087 1.12 mrg mcldemote 1088 1.13 mrg Target Report Mask(ISA2_CLDEMOTE) Var(ix86_isa_flags2) Save 1089 1.12 mrg Support CLDEMOTE built-in functions and code generation. 1090 1.12 mrg 1091 1.12 mrg minstrument-return= 1092 1.12 mrg Target Report RejectNegative Joined Enum(instrument_return) Var(ix86_instrument_return) Init(instrument_return_none) 1093 1.12 mrg Instrument function exit in instrumented functions with __fentry__. 1094 1.12 mrg 1095 1.12 mrg Enum 1096 1.12 mrg Name(instrument_return) Type(enum instrument_return) 1097 1.12 mrg Known choices for return instrumentation with -minstrument-return=: 1098 1.12 mrg 1099 1.12 mrg EnumValue 1100 1.12 mrg Enum(instrument_return) String(none) Value(instrument_return_none) 1101 1.12 mrg 1102 1.12 mrg EnumValue 1103 1.12 mrg Enum(instrument_return) String(call) Value(instrument_return_call) 1104 1.12 mrg 1105 1.12 mrg EnumValue 1106 1.12 mrg Enum(instrument_return) String(nop5) Value(instrument_return_nop5) 1107 1.12 mrg 1108 1.12 mrg mrecord-return 1109 1.12 mrg Target Report Var(ix86_flag_record_return) Init(0) 1110 1.12 mrg Generate a __return_loc section pointing to all return instrumentation code. 1111 1.13 mrg 1112 1.13 mrg mavx512bf16 1113 1.13 mrg Target Report Mask(ISA2_AVX512BF16) Var(ix86_isa_flags2) Save 1114 1.13 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and 1115 1.13 mrg AVX512BF16 built-in functions and code generation. 1116 1.13 mrg 1117 1.13 mrg menqcmd 1118 1.13 mrg Target Report Mask(ISA2_ENQCMD) Var(ix86_isa_flags2) Save 1119 1.13 mrg Support ENQCMD built-in functions and code generation. 1120
Indexes created Wed Apr 29 00:23:26 UTC 2026