i386.opt revision 1.3
1 1.1 mrg ; Options for the IA-32 and AMD64 ports of the compiler. 2 1.1 mrg 3 1.3 mrg ; Copyright (C) 2005-2013 Free Software Foundation, Inc. 4 1.1 mrg ; 5 1.1 mrg ; This file is part of GCC. 6 1.1 mrg ; 7 1.1 mrg ; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ; version. 11 1.1 mrg ; 12 1.1 mrg ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ; for more details. 16 1.1 mrg ; 17 1.1 mrg ; You should have received a copy of the GNU General Public License 18 1.1 mrg ; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.3 mrg HeaderInclude 22 1.3 mrg config/i386/i386-opts.h 23 1.3 mrg 24 1.3 mrg ; Bit flags that specify the ISA we are compiling for. 25 1.3 mrg Variable 26 1.3 mrg HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 1.3 mrg 28 1.3 mrg ; A mask of ix86_isa_flags that includes bit X if X was set or cleared 29 1.3 mrg ; on the command line. 30 1.3 mrg Variable 31 1.3 mrg HOST_WIDE_INT ix86_isa_flags_explicit 32 1.3 mrg 33 1.3 mrg TargetVariable 34 1.3 mrg int recip_mask = RECIP_MASK_DEFAULT 35 1.3 mrg 36 1.3 mrg Variable 37 1.3 mrg int recip_mask_explicit 38 1.3 mrg 39 1.3 mrg TargetSave 40 1.3 mrg int x_recip_mask_explicit 41 1.3 mrg 42 1.1 mrg ;; Definitions to add to the cl_target_option structure 43 1.1 mrg ;; -march= processor 44 1.1 mrg TargetSave 45 1.1 mrg unsigned char arch 46 1.1 mrg 47 1.1 mrg ;; -mtune= processor 48 1.1 mrg TargetSave 49 1.1 mrg unsigned char tune 50 1.1 mrg 51 1.1 mrg ;; CPU schedule model 52 1.1 mrg TargetSave 53 1.1 mrg unsigned char schedule 54 1.1 mrg 55 1.1 mrg ;; branch cost 56 1.1 mrg TargetSave 57 1.1 mrg unsigned char branch_cost 58 1.1 mrg 59 1.1 mrg ;; which flags were passed by the user 60 1.1 mrg TargetSave 61 1.3 mrg HOST_WIDE_INT x_ix86_isa_flags_explicit 62 1.1 mrg 63 1.1 mrg ;; which flags were passed by the user 64 1.1 mrg TargetSave 65 1.3 mrg int ix86_target_flags_explicit 66 1.1 mrg 67 1.1 mrg ;; whether -mtune was not specified 68 1.1 mrg TargetSave 69 1.1 mrg unsigned char tune_defaulted 70 1.1 mrg 71 1.1 mrg ;; whether -march was specified 72 1.1 mrg TargetSave 73 1.1 mrg unsigned char arch_specified 74 1.1 mrg 75 1.1 mrg ;; x86 options 76 1.1 mrg m128bit-long-double 77 1.1 mrg Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save 78 1.1 mrg sizeof(long double) is 16 79 1.1 mrg 80 1.1 mrg m80387 81 1.1 mrg Target Report Mask(80387) Save 82 1.1 mrg Use hardware fp 83 1.1 mrg 84 1.1 mrg m96bit-long-double 85 1.1 mrg Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save 86 1.1 mrg sizeof(long double) is 12 87 1.1 mrg 88 1.3 mrg mlong-double-80 89 1.3 mrg Target Report RejectNegative InverseMask(LONG_DOUBLE_64) Save 90 1.3 mrg Use 80-bit long double 91 1.3 mrg 92 1.3 mrg mlong-double-64 93 1.3 mrg Target Report RejectNegative Mask(LONG_DOUBLE_64) Save 94 1.3 mrg Use 64-bit long double 95 1.3 mrg 96 1.1 mrg maccumulate-outgoing-args 97 1.1 mrg Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save 98 1.1 mrg Reserve space for outgoing arguments in the function prologue 99 1.1 mrg 100 1.1 mrg malign-double 101 1.1 mrg Target Report Mask(ALIGN_DOUBLE) Save 102 1.1 mrg Align some doubles on dword boundary 103 1.1 mrg 104 1.1 mrg malign-functions= 105 1.3 mrg Target RejectNegative Joined UInteger 106 1.1 mrg Function starts are aligned to this power of 2 107 1.1 mrg 108 1.1 mrg malign-jumps= 109 1.3 mrg Target RejectNegative Joined UInteger 110 1.1 mrg Jump targets are aligned to this power of 2 111 1.1 mrg 112 1.1 mrg malign-loops= 113 1.3 mrg Target RejectNegative Joined UInteger 114 1.1 mrg Loop code aligned to this power of 2 115 1.1 mrg 116 1.1 mrg malign-stringops 117 1.1 mrg Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 118 1.1 mrg Align destination of the string operations 119 1.1 mrg 120 1.1 mrg march= 121 1.1 mrg Target RejectNegative Joined Var(ix86_arch_string) 122 1.1 mrg Generate code for given CPU 123 1.1 mrg 124 1.1 mrg masm= 125 1.3 mrg Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 126 1.1 mrg Use given assembler dialect 127 1.1 mrg 128 1.3 mrg Enum 129 1.3 mrg Name(asm_dialect) Type(enum asm_dialect) 130 1.3 mrg Known assembler dialects (for use with the -masm-dialect= option): 131 1.3 mrg 132 1.3 mrg EnumValue 133 1.3 mrg Enum(asm_dialect) String(intel) Value(ASM_INTEL) 134 1.3 mrg 135 1.3 mrg EnumValue 136 1.3 mrg Enum(asm_dialect) String(att) Value(ASM_ATT) 137 1.3 mrg 138 1.1 mrg mbranch-cost= 139 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_branch_cost) 140 1.1 mrg Branches are this expensive (1-5, arbitrary units) 141 1.1 mrg 142 1.1 mrg mlarge-data-threshold= 143 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 144 1.1 mrg Data greater than given threshold will go into .ldata section in x86-64 medium model 145 1.1 mrg 146 1.1 mrg mcmodel= 147 1.3 mrg Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 148 1.1 mrg Use given x86-64 code model 149 1.1 mrg 150 1.3 mrg Enum 151 1.3 mrg Name(cmodel) Type(enum cmodel) 152 1.3 mrg Known code models (for use with the -mcmodel= option): 153 1.3 mrg 154 1.3 mrg EnumValue 155 1.3 mrg Enum(cmodel) String(small) Value(CM_SMALL) 156 1.3 mrg 157 1.3 mrg EnumValue 158 1.3 mrg Enum(cmodel) String(medium) Value(CM_MEDIUM) 159 1.3 mrg 160 1.3 mrg EnumValue 161 1.3 mrg Enum(cmodel) String(large) Value(CM_LARGE) 162 1.3 mrg 163 1.3 mrg EnumValue 164 1.3 mrg Enum(cmodel) String(32) Value(CM_32) 165 1.3 mrg 166 1.3 mrg EnumValue 167 1.3 mrg Enum(cmodel) String(kernel) Value(CM_KERNEL) 168 1.3 mrg 169 1.3 mrg maddress-mode= 170 1.3 mrg Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 171 1.3 mrg Use given address mode 172 1.3 mrg 173 1.3 mrg Enum 174 1.3 mrg Name(pmode) Type(enum pmode) 175 1.3 mrg Known address mode (for use with the -maddress-mode= option): 176 1.3 mrg 177 1.3 mrg EnumValue 178 1.3 mrg Enum(pmode) String(short) Value(PMODE_SI) 179 1.3 mrg 180 1.3 mrg EnumValue 181 1.3 mrg Enum(pmode) String(long) Value(PMODE_DI) 182 1.3 mrg 183 1.3 mrg mcpu= 184 1.3 mrg Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 185 1.3 mrg 186 1.1 mrg mfancy-math-387 187 1.1 mrg Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 188 1.1 mrg Generate sin, cos, sqrt for FPU 189 1.1 mrg 190 1.1 mrg mforce-drap 191 1.1 mrg Target Report Var(ix86_force_drap) 192 1.1 mrg Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack 193 1.1 mrg 194 1.1 mrg mfp-ret-in-387 195 1.1 mrg Target Report Mask(FLOAT_RETURNS) Save 196 1.1 mrg Return values of functions in FPU registers 197 1.1 mrg 198 1.1 mrg mfpmath= 199 1.3 mrg Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 200 1.1 mrg Generate floating point mathematics using given instruction set 201 1.1 mrg 202 1.3 mrg Enum 203 1.3 mrg Name(fpmath_unit) Type(enum fpmath_unit) 204 1.3 mrg Valid arguments to -mfpmath=: 205 1.3 mrg 206 1.3 mrg EnumValue 207 1.3 mrg Enum(fpmath_unit) String(387) Value(FPMATH_387) 208 1.3 mrg 209 1.3 mrg EnumValue 210 1.3 mrg Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 211 1.3 mrg 212 1.3 mrg EnumValue 213 1.3 mrg Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 214 1.3 mrg 215 1.3 mrg EnumValue 216 1.3 mrg Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 217 1.3 mrg 218 1.3 mrg EnumValue 219 1.3 mrg Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 220 1.3 mrg 221 1.3 mrg EnumValue 222 1.3 mrg Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 223 1.3 mrg 224 1.3 mrg EnumValue 225 1.3 mrg Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 226 1.3 mrg 227 1.1 mrg mhard-float 228 1.3 mrg Target RejectNegative Mask(80387) Save 229 1.1 mrg Use hardware fp 230 1.1 mrg 231 1.1 mrg mieee-fp 232 1.1 mrg Target Report Mask(IEEE_FP) Save 233 1.1 mrg Use IEEE math for fp comparisons 234 1.1 mrg 235 1.1 mrg minline-all-stringops 236 1.1 mrg Target Report Mask(INLINE_ALL_STRINGOPS) Save 237 1.1 mrg Inline all known string operations 238 1.1 mrg 239 1.1 mrg minline-stringops-dynamically 240 1.1 mrg Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 241 1.1 mrg Inline memset/memcpy string operations, but perform inline version only for small blocks 242 1.1 mrg 243 1.1 mrg mintel-syntax 244 1.3 mrg Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 245 1.1 mrg ;; Deprecated 246 1.1 mrg 247 1.1 mrg mms-bitfields 248 1.1 mrg Target Report Mask(MS_BITFIELD_LAYOUT) Save 249 1.1 mrg Use native (MS) bitfield layout 250 1.1 mrg 251 1.1 mrg mno-align-stringops 252 1.1 mrg Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save 253 1.1 mrg 254 1.1 mrg mno-fancy-math-387 255 1.1 mrg Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save 256 1.1 mrg 257 1.1 mrg mno-push-args 258 1.1 mrg Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save 259 1.1 mrg 260 1.1 mrg mno-red-zone 261 1.1 mrg Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save 262 1.1 mrg 263 1.1 mrg momit-leaf-frame-pointer 264 1.1 mrg Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save 265 1.1 mrg Omit the frame pointer in leaf functions 266 1.1 mrg 267 1.3 mrg mpc32 268 1.3 mrg Target RejectNegative Report 269 1.3 mrg Set 80387 floating-point precision to 32-bit 270 1.3 mrg 271 1.3 mrg mpc64 272 1.3 mrg Target RejectNegative Report 273 1.3 mrg Set 80387 floating-point precision to 64-bit 274 1.3 mrg 275 1.3 mrg mpc80 276 1.3 mrg Target RejectNegative Report 277 1.3 mrg Set 80387 floating-point precision to 80-bit 278 1.1 mrg 279 1.1 mrg mpreferred-stack-boundary= 280 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 281 1.1 mrg Attempt to keep stack aligned to this power of 2 282 1.1 mrg 283 1.1 mrg mincoming-stack-boundary= 284 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 285 1.1 mrg Assume incoming stack aligned to this power of 2 286 1.1 mrg 287 1.1 mrg mpush-args 288 1.1 mrg Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 289 1.1 mrg Use push instructions to save outgoing arguments 290 1.1 mrg 291 1.1 mrg mred-zone 292 1.1 mrg Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save 293 1.1 mrg Use red-zone in the x86-64 code 294 1.1 mrg 295 1.1 mrg mregparm= 296 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_regparm) 297 1.1 mrg Number of registers used to pass integer arguments 298 1.1 mrg 299 1.1 mrg mrtd 300 1.1 mrg Target Report Mask(RTD) Save 301 1.1 mrg Alternate calling convention 302 1.1 mrg 303 1.1 mrg msoft-float 304 1.1 mrg Target InverseMask(80387) Save 305 1.1 mrg Do not use hardware fp 306 1.1 mrg 307 1.1 mrg msseregparm 308 1.1 mrg Target RejectNegative Mask(SSEREGPARM) Save 309 1.1 mrg Use SSE register passing conventions for SF and DF mode 310 1.1 mrg 311 1.1 mrg mstackrealign 312 1.1 mrg Target Report Var(ix86_force_align_arg_pointer) Init(-1) 313 1.1 mrg Realign stack in prologue 314 1.1 mrg 315 1.1 mrg mstack-arg-probe 316 1.1 mrg Target Report Mask(STACK_PROBE) Save 317 1.1 mrg Enable stack probing 318 1.1 mrg 319 1.1 mrg mstringop-strategy= 320 1.3 mrg Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 321 1.1 mrg Chose strategy to generate stringop using 322 1.1 mrg 323 1.3 mrg Enum 324 1.3 mrg Name(stringop_alg) Type(enum stringop_alg) 325 1.3 mrg Valid arguments to -mstringop-strategy=: 326 1.3 mrg 327 1.3 mrg EnumValue 328 1.3 mrg Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 329 1.3 mrg 330 1.3 mrg EnumValue 331 1.3 mrg Enum(stringop_alg) String(libcall) Value(libcall) 332 1.3 mrg 333 1.3 mrg EnumValue 334 1.3 mrg Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 335 1.3 mrg 336 1.3 mrg EnumValue 337 1.3 mrg Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 338 1.3 mrg 339 1.3 mrg EnumValue 340 1.3 mrg Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 341 1.3 mrg 342 1.3 mrg EnumValue 343 1.3 mrg Enum(stringop_alg) String(loop) Value(loop) 344 1.3 mrg 345 1.3 mrg EnumValue 346 1.3 mrg Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 347 1.3 mrg 348 1.1 mrg mtls-dialect= 349 1.3 mrg Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 350 1.1 mrg Use given thread-local storage dialect 351 1.1 mrg 352 1.3 mrg Enum 353 1.3 mrg Name(tls_dialect) Type(enum tls_dialect) 354 1.3 mrg Known TLS dialects (for use with the -mtls-dialect= option): 355 1.3 mrg 356 1.3 mrg EnumValue 357 1.3 mrg Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 358 1.3 mrg 359 1.3 mrg EnumValue 360 1.3 mrg Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 361 1.3 mrg 362 1.1 mrg mtls-direct-seg-refs 363 1.1 mrg Target Report Mask(TLS_DIRECT_SEG_REFS) 364 1.1 mrg Use direct references against %gs when accessing tls data 365 1.1 mrg 366 1.1 mrg mtune= 367 1.1 mrg Target RejectNegative Joined Var(ix86_tune_string) 368 1.1 mrg Schedule code for given CPU 369 1.1 mrg 370 1.1 mrg mabi= 371 1.3 mrg Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 372 1.1 mrg Generate code that conforms to the given ABI 373 1.1 mrg 374 1.3 mrg Enum 375 1.3 mrg Name(calling_abi) Type(enum calling_abi) 376 1.3 mrg Known ABIs (for use with the -mabi= option): 377 1.3 mrg 378 1.3 mrg EnumValue 379 1.3 mrg Enum(calling_abi) String(sysv) Value(SYSV_ABI) 380 1.3 mrg 381 1.3 mrg EnumValue 382 1.3 mrg Enum(calling_abi) String(ms) Value(MS_ABI) 383 1.3 mrg 384 1.1 mrg mveclibabi= 385 1.3 mrg Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 386 1.1 mrg Vector library ABI to use 387 1.1 mrg 388 1.3 mrg Enum 389 1.3 mrg Name(ix86_veclibabi) Type(enum ix86_veclibabi) 390 1.3 mrg Known vectorization library ABIs (for use with the -mveclibabi= option): 391 1.3 mrg 392 1.3 mrg EnumValue 393 1.3 mrg Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 394 1.3 mrg 395 1.3 mrg EnumValue 396 1.3 mrg Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 397 1.3 mrg 398 1.3 mrg mvect8-ret-in-mem 399 1.3 mrg Target Report Mask(VECT8_RETURNS) Save 400 1.3 mrg Return 8-byte vectors in memory 401 1.3 mrg 402 1.1 mrg mrecip 403 1.1 mrg Target Report Mask(RECIP) Save 404 1.1 mrg Generate reciprocals instead of divss and sqrtss. 405 1.1 mrg 406 1.3 mrg mrecip= 407 1.3 mrg Target Report RejectNegative Joined Var(ix86_recip_name) 408 1.3 mrg Control generation of reciprocal estimates. 409 1.3 mrg 410 1.1 mrg mcld 411 1.1 mrg Target Report Mask(CLD) Save 412 1.1 mrg Generate cld instruction in the function prologue. 413 1.1 mrg 414 1.3 mrg mvzeroupper 415 1.3 mrg Target Report Mask(VZEROUPPER) Save 416 1.3 mrg Generate vzeroupper instruction before a transfer of control flow out of 417 1.3 mrg the function. 418 1.3 mrg 419 1.3 mrg mdispatch-scheduler 420 1.3 mrg Target RejectNegative Var(flag_dispatch_scheduler) 421 1.3 mrg Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 and Haifa scheduling 422 1.3 mrg is selected. 423 1.3 mrg 424 1.3 mrg mprefer-avx128 425 1.3 mrg Target Report Mask(PREFER_AVX128) SAVE 426 1.3 mrg Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 427 1.1 mrg 428 1.1 mrg ;; ISA support 429 1.1 mrg 430 1.1 mrg m32 431 1.3 mrg Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 432 1.1 mrg Generate 32bit i386 code 433 1.1 mrg 434 1.1 mrg m64 435 1.3 mrg Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save 436 1.1 mrg Generate 64bit x86-64 code 437 1.1 mrg 438 1.3 mrg mx32 439 1.3 mrg Target RejectNegative Negative(m32) Report Mask(ABI_X32) Var(ix86_isa_flags) Save 440 1.3 mrg Generate 32bit x86-64 code 441 1.3 mrg 442 1.1 mrg mmmx 443 1.3 mrg Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save 444 1.1 mrg Support MMX built-in functions 445 1.1 mrg 446 1.1 mrg m3dnow 447 1.3 mrg Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 448 1.1 mrg Support 3DNow! built-in functions 449 1.1 mrg 450 1.1 mrg m3dnowa 451 1.3 mrg Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 452 1.1 mrg Support Athlon 3Dnow! built-in functions 453 1.1 mrg 454 1.1 mrg msse 455 1.3 mrg Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save 456 1.1 mrg Support MMX and SSE built-in functions and code generation 457 1.1 mrg 458 1.1 mrg msse2 459 1.3 mrg Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save 460 1.1 mrg Support MMX, SSE and SSE2 built-in functions and code generation 461 1.1 mrg 462 1.1 mrg msse3 463 1.3 mrg Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save 464 1.1 mrg Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation 465 1.1 mrg 466 1.1 mrg mssse3 467 1.3 mrg Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 468 1.1 mrg Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation 469 1.1 mrg 470 1.1 mrg msse4.1 471 1.3 mrg Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 472 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation 473 1.1 mrg 474 1.1 mrg msse4.2 475 1.3 mrg Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 476 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 477 1.1 mrg 478 1.1 mrg msse4 479 1.3 mrg Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 480 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 481 1.1 mrg 482 1.1 mrg mno-sse4 483 1.3 mrg Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 484 1.1 mrg Do not support SSE4.1 and SSE4.2 built-in functions and code generation 485 1.1 mrg 486 1.3 mrg msse5 487 1.3 mrg Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 488 1.3 mrg ;; Deprecated 489 1.3 mrg 490 1.1 mrg mavx 491 1.3 mrg Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save 492 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation 493 1.1 mrg 494 1.3 mrg mavx2 495 1.3 mrg Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save 496 1.3 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation 497 1.3 mrg 498 1.1 mrg mfma 499 1.3 mrg Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save 500 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation 501 1.1 mrg 502 1.1 mrg msse4a 503 1.3 mrg Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 504 1.1 mrg Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation 505 1.1 mrg 506 1.1 mrg mfma4 507 1.3 mrg Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save 508 1.1 mrg Support FMA4 built-in functions and code generation 509 1.1 mrg 510 1.1 mrg mxop 511 1.3 mrg Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save 512 1.1 mrg Support XOP built-in functions and code generation 513 1.1 mrg 514 1.1 mrg mlwp 515 1.3 mrg Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save 516 1.1 mrg Support LWP built-in functions and code generation 517 1.1 mrg 518 1.1 mrg mabm 519 1.3 mrg Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save 520 1.1 mrg Support code generation of Advanced Bit Manipulation (ABM) instructions. 521 1.1 mrg 522 1.1 mrg mpopcnt 523 1.3 mrg Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 524 1.1 mrg Support code generation of popcnt instruction. 525 1.1 mrg 526 1.3 mrg mbmi 527 1.3 mrg Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save 528 1.3 mrg Support BMI built-in functions and code generation 529 1.3 mrg 530 1.3 mrg mbmi2 531 1.3 mrg Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save 532 1.3 mrg Support BMI2 built-in functions and code generation 533 1.3 mrg 534 1.3 mrg mlzcnt 535 1.3 mrg Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 536 1.3 mrg Support LZCNT built-in function and code generation 537 1.3 mrg 538 1.3 mrg mhle 539 1.3 mrg Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save 540 1.3 mrg Support Hardware Lock Elision prefixes 541 1.3 mrg 542 1.3 mrg mrdseed 543 1.3 mrg Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 544 1.3 mrg Support RDSEED instruction 545 1.3 mrg 546 1.3 mrg mprfchw 547 1.3 mrg Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 548 1.3 mrg Support PREFETCHW instruction 549 1.3 mrg 550 1.3 mrg madx 551 1.3 mrg Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save 552 1.3 mrg Support flag-preserving add-carry instructions 553 1.3 mrg 554 1.3 mrg mfxsr 555 1.3 mrg Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save 556 1.3 mrg Support FXSAVE and FXRSTOR instructions 557 1.3 mrg 558 1.3 mrg mxsave 559 1.3 mrg Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 560 1.3 mrg Support XSAVE and XRSTOR instructions 561 1.3 mrg 562 1.3 mrg mxsaveopt 563 1.3 mrg Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 564 1.3 mrg Support XSAVEOPT instruction 565 1.3 mrg 566 1.3 mrg mtbm 567 1.3 mrg Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save 568 1.3 mrg Support TBM built-in functions and code generation 569 1.3 mrg 570 1.1 mrg mcx16 571 1.3 mrg Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save 572 1.1 mrg Support code generation of cmpxchg16b instruction. 573 1.1 mrg 574 1.1 mrg msahf 575 1.3 mrg Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save 576 1.1 mrg Support code generation of sahf instruction in 64bit x86-64 code. 577 1.1 mrg 578 1.1 mrg mmovbe 579 1.3 mrg Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save 580 1.1 mrg Support code generation of movbe instruction. 581 1.1 mrg 582 1.1 mrg mcrc32 583 1.3 mrg Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save 584 1.1 mrg Support code generation of crc32 instruction. 585 1.1 mrg 586 1.1 mrg maes 587 1.3 mrg Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save 588 1.1 mrg Support AES built-in functions and code generation 589 1.1 mrg 590 1.1 mrg mpclmul 591 1.3 mrg Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 592 1.1 mrg Support PCLMUL built-in functions and code generation 593 1.1 mrg 594 1.1 mrg msse2avx 595 1.1 mrg Target Report Var(ix86_sse2avx) 596 1.1 mrg Encode SSE instructions with VEX prefix 597 1.3 mrg 598 1.3 mrg mfsgsbase 599 1.3 mrg Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 600 1.3 mrg Support FSGSBASE built-in functions and code generation 601 1.3 mrg 602 1.3 mrg mrdrnd 603 1.3 mrg Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save 604 1.3 mrg Support RDRND built-in functions and code generation 605 1.3 mrg 606 1.3 mrg mf16c 607 1.3 mrg Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save 608 1.3 mrg Support F16C built-in functions and code generation 609 1.3 mrg 610 1.3 mrg mfentry 611 1.3 mrg Target Report Var(flag_fentry) Init(-1) 612 1.3 mrg Emit profiling counter call at function entry before prologue. 613 1.3 mrg 614 1.3 mrg m8bit-idiv 615 1.3 mrg Target Report Mask(USE_8BIT_IDIV) Save 616 1.3 mrg Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check 617 1.3 mrg 618 1.3 mrg mavx256-split-unaligned-load 619 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 620 1.3 mrg Split 32-byte AVX unaligned load 621 1.3 mrg 622 1.3 mrg mavx256-split-unaligned-store 623 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 624 1.3 mrg Split 32-byte AVX unaligned store 625 1.3 mrg 626 1.3 mrg mrtm 627 1.3 mrg Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save 628 1.3 mrg Support RTM built-in functions and code generation 629
Indexes created Wed Apr 29 00:23:26 UTC 2026