i386.opt revision 1.5
1 1.1 mrg ; Options for the IA-32 and AMD64 ports of the compiler. 2 1.1 mrg 3 1.5 mrg ; Copyright (C) 2005-2015 Free Software Foundation, Inc. 4 1.1 mrg ; 5 1.1 mrg ; This file is part of GCC. 6 1.1 mrg ; 7 1.1 mrg ; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ; version. 11 1.1 mrg ; 12 1.1 mrg ; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ; for more details. 16 1.1 mrg ; 17 1.1 mrg ; You should have received a copy of the GNU General Public License 18 1.1 mrg ; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.3 mrg HeaderInclude 22 1.3 mrg config/i386/i386-opts.h 23 1.3 mrg 24 1.3 mrg ; Bit flags that specify the ISA we are compiling for. 25 1.3 mrg Variable 26 1.3 mrg HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAULT 27 1.3 mrg 28 1.3 mrg ; A mask of ix86_isa_flags that includes bit X if X was set or cleared 29 1.3 mrg ; on the command line. 30 1.3 mrg Variable 31 1.3 mrg HOST_WIDE_INT ix86_isa_flags_explicit 32 1.3 mrg 33 1.3 mrg TargetVariable 34 1.3 mrg int recip_mask = RECIP_MASK_DEFAULT 35 1.3 mrg 36 1.3 mrg Variable 37 1.3 mrg int recip_mask_explicit 38 1.3 mrg 39 1.3 mrg TargetSave 40 1.3 mrg int x_recip_mask_explicit 41 1.3 mrg 42 1.1 mrg ;; Definitions to add to the cl_target_option structure 43 1.1 mrg ;; -march= processor 44 1.1 mrg TargetSave 45 1.1 mrg unsigned char arch 46 1.1 mrg 47 1.1 mrg ;; -mtune= processor 48 1.1 mrg TargetSave 49 1.1 mrg unsigned char tune 50 1.1 mrg 51 1.5 mrg ;; -march= processor-string 52 1.5 mrg TargetSave 53 1.5 mrg const char *x_ix86_arch_string 54 1.5 mrg 55 1.5 mrg ;; -mtune= processor-string 56 1.5 mrg TargetSave 57 1.5 mrg const char *x_ix86_tune_string 58 1.5 mrg 59 1.1 mrg ;; CPU schedule model 60 1.1 mrg TargetSave 61 1.1 mrg unsigned char schedule 62 1.1 mrg 63 1.5 mrg ;; True if processor has SSE prefetch instruction. 64 1.5 mrg TargetSave 65 1.5 mrg unsigned char prefetch_sse 66 1.5 mrg 67 1.1 mrg ;; branch cost 68 1.1 mrg TargetSave 69 1.1 mrg unsigned char branch_cost 70 1.1 mrg 71 1.1 mrg ;; which flags were passed by the user 72 1.1 mrg TargetSave 73 1.3 mrg HOST_WIDE_INT x_ix86_isa_flags_explicit 74 1.1 mrg 75 1.1 mrg ;; which flags were passed by the user 76 1.5 mrg Variable 77 1.5 mrg int ix86_target_flags_explicit 78 1.5 mrg 79 1.5 mrg ;; which flags were passed by the user 80 1.1 mrg TargetSave 81 1.5 mrg HOST_WIDE_INT x_ix86_target_flags_explicit 82 1.1 mrg 83 1.1 mrg ;; whether -mtune was not specified 84 1.1 mrg TargetSave 85 1.1 mrg unsigned char tune_defaulted 86 1.1 mrg 87 1.1 mrg ;; whether -march was specified 88 1.1 mrg TargetSave 89 1.1 mrg unsigned char arch_specified 90 1.1 mrg 91 1.5 mrg ;; -mcmodel= model 92 1.5 mrg TargetSave 93 1.5 mrg enum cmodel x_ix86_cmodel 94 1.5 mrg 95 1.5 mrg ;; -mabi= 96 1.5 mrg TargetSave 97 1.5 mrg enum calling_abi x_ix86_abi 98 1.5 mrg 99 1.5 mrg ;; -masm= 100 1.5 mrg TargetSave 101 1.5 mrg enum asm_dialect x_ix86_asm_dialect 102 1.5 mrg 103 1.5 mrg ;; -mbranch-cost= 104 1.5 mrg TargetSave 105 1.5 mrg int x_ix86_branch_cost 106 1.5 mrg 107 1.5 mrg ;; -mdump-tune-features= 108 1.5 mrg TargetSave 109 1.5 mrg int x_ix86_dump_tunes 110 1.5 mrg 111 1.5 mrg ;; -mstackrealign= 112 1.5 mrg TargetSave 113 1.5 mrg int x_ix86_force_align_arg_pointer 114 1.5 mrg 115 1.5 mrg ;; -mforce-drap= 116 1.5 mrg TargetSave 117 1.5 mrg int x_ix86_force_drap 118 1.5 mrg 119 1.5 mrg ;; -mincoming-stack-boundary= 120 1.5 mrg TargetSave 121 1.5 mrg int x_ix86_incoming_stack_boundary_arg 122 1.5 mrg 123 1.5 mrg ;; -maddress-mode= 124 1.5 mrg TargetSave 125 1.5 mrg enum pmode x_ix86_pmode 126 1.5 mrg 127 1.5 mrg ;; -mpreferred-stack-boundary= 128 1.5 mrg TargetSave 129 1.5 mrg int x_ix86_preferred_stack_boundary_arg 130 1.5 mrg 131 1.5 mrg ;; -mrecip= 132 1.5 mrg TargetSave 133 1.5 mrg const char *x_ix86_recip_name 134 1.5 mrg 135 1.5 mrg ;; -mregparm= 136 1.5 mrg TargetSave 137 1.5 mrg int x_ix86_regparm 138 1.5 mrg 139 1.5 mrg ;; -mlarge-data-threshold= 140 1.5 mrg TargetSave 141 1.5 mrg int x_ix86_section_threshold 142 1.5 mrg 143 1.5 mrg ;; -msse2avx= 144 1.5 mrg TargetSave 145 1.5 mrg int x_ix86_sse2avx 146 1.5 mrg 147 1.5 mrg ;; -mstack-protector-guard= 148 1.5 mrg TargetSave 149 1.5 mrg enum stack_protector_guard x_ix86_stack_protector_guard 150 1.5 mrg 151 1.5 mrg ;; -mstringop-strategy= 152 1.5 mrg TargetSave 153 1.5 mrg enum stringop_alg x_ix86_stringop_alg 154 1.5 mrg 155 1.5 mrg ;; -mtls-dialect= 156 1.5 mrg TargetSave 157 1.5 mrg enum tls_dialect x_ix86_tls_dialect 158 1.5 mrg 159 1.5 mrg ;; -mtune-ctrl= 160 1.5 mrg TargetSave 161 1.5 mrg const char *x_ix86_tune_ctrl_string 162 1.5 mrg 163 1.5 mrg ;; -mmemcpy-strategy= 164 1.5 mrg TargetSave 165 1.5 mrg const char *x_ix86_tune_memcpy_strategy 166 1.5 mrg 167 1.5 mrg ;; -mmemset-strategy= 168 1.5 mrg TargetSave 169 1.5 mrg const char *x_ix86_tune_memset_strategy 170 1.5 mrg 171 1.5 mrg ;; -mno-default= 172 1.5 mrg TargetSave 173 1.5 mrg int x_ix86_tune_no_default 174 1.5 mrg 175 1.5 mrg ;; -mveclibabi= 176 1.5 mrg TargetSave 177 1.5 mrg enum ix86_veclibabi x_ix86_veclibabi_type 178 1.5 mrg 179 1.1 mrg ;; x86 options 180 1.1 mrg m128bit-long-double 181 1.1 mrg Target RejectNegative Report Mask(128BIT_LONG_DOUBLE) Save 182 1.1 mrg sizeof(long double) is 16 183 1.1 mrg 184 1.1 mrg m80387 185 1.1 mrg Target Report Mask(80387) Save 186 1.1 mrg Use hardware fp 187 1.1 mrg 188 1.1 mrg m96bit-long-double 189 1.1 mrg Target RejectNegative Report InverseMask(128BIT_LONG_DOUBLE) Save 190 1.1 mrg sizeof(long double) is 12 191 1.1 mrg 192 1.3 mrg mlong-double-80 193 1.5 mrg Target Report RejectNegative Negative(mlong-double-64) InverseMask(LONG_DOUBLE_64) Save 194 1.3 mrg Use 80-bit long double 195 1.3 mrg 196 1.3 mrg mlong-double-64 197 1.5 mrg Target Report RejectNegative Negative(mlong-double-128) Mask(LONG_DOUBLE_64) InverseMask(LONG_DOUBLE_128) Save 198 1.3 mrg Use 64-bit long double 199 1.3 mrg 200 1.5 mrg mlong-double-128 201 1.5 mrg Target Report RejectNegative Negative(mlong-double-80) Mask(LONG_DOUBLE_128) InverseMask(LONG_DOUBLE_64) Save 202 1.5 mrg Use 128-bit long double 203 1.5 mrg 204 1.1 mrg maccumulate-outgoing-args 205 1.1 mrg Target Report Mask(ACCUMULATE_OUTGOING_ARGS) Save 206 1.1 mrg Reserve space for outgoing arguments in the function prologue 207 1.1 mrg 208 1.1 mrg malign-double 209 1.1 mrg Target Report Mask(ALIGN_DOUBLE) Save 210 1.1 mrg Align some doubles on dword boundary 211 1.1 mrg 212 1.1 mrg malign-functions= 213 1.3 mrg Target RejectNegative Joined UInteger 214 1.1 mrg Function starts are aligned to this power of 2 215 1.1 mrg 216 1.1 mrg malign-jumps= 217 1.3 mrg Target RejectNegative Joined UInteger 218 1.1 mrg Jump targets are aligned to this power of 2 219 1.1 mrg 220 1.1 mrg malign-loops= 221 1.3 mrg Target RejectNegative Joined UInteger 222 1.1 mrg Loop code aligned to this power of 2 223 1.1 mrg 224 1.1 mrg malign-stringops 225 1.1 mrg Target RejectNegative Report InverseMask(NO_ALIGN_STRINGOPS, ALIGN_STRINGOPS) Save 226 1.1 mrg Align destination of the string operations 227 1.1 mrg 228 1.5 mrg malign-data= 229 1.5 mrg Target RejectNegative Joined Var(ix86_align_data_type) Enum(ix86_align_data) Init(ix86_align_data_type_compat) 230 1.5 mrg Use the given data alignment 231 1.5 mrg 232 1.5 mrg Enum 233 1.5 mrg Name(ix86_align_data) Type(enum ix86_align_data) 234 1.5 mrg Known data alignment choices (for use with the -malign-data= option): 235 1.5 mrg 236 1.5 mrg EnumValue 237 1.5 mrg Enum(ix86_align_data) String(compat) Value(ix86_align_data_type_compat) 238 1.5 mrg 239 1.5 mrg EnumValue 240 1.5 mrg Enum(ix86_align_data) String(abi) Value(ix86_align_data_type_abi) 241 1.5 mrg 242 1.5 mrg EnumValue 243 1.5 mrg Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline) 244 1.5 mrg 245 1.1 mrg march= 246 1.1 mrg Target RejectNegative Joined Var(ix86_arch_string) 247 1.1 mrg Generate code for given CPU 248 1.1 mrg 249 1.1 mrg masm= 250 1.3 mrg Target RejectNegative Joined Enum(asm_dialect) Var(ix86_asm_dialect) Init(ASM_ATT) 251 1.1 mrg Use given assembler dialect 252 1.1 mrg 253 1.3 mrg Enum 254 1.3 mrg Name(asm_dialect) Type(enum asm_dialect) 255 1.3 mrg Known assembler dialects (for use with the -masm-dialect= option): 256 1.3 mrg 257 1.3 mrg EnumValue 258 1.3 mrg Enum(asm_dialect) String(intel) Value(ASM_INTEL) 259 1.3 mrg 260 1.3 mrg EnumValue 261 1.3 mrg Enum(asm_dialect) String(att) Value(ASM_ATT) 262 1.3 mrg 263 1.1 mrg mbranch-cost= 264 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_branch_cost) 265 1.1 mrg Branches are this expensive (1-5, arbitrary units) 266 1.1 mrg 267 1.1 mrg mlarge-data-threshold= 268 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_section_threshold) Init(DEFAULT_LARGE_SECTION_THRESHOLD) 269 1.1 mrg Data greater than given threshold will go into .ldata section in x86-64 medium model 270 1.1 mrg 271 1.1 mrg mcmodel= 272 1.3 mrg Target RejectNegative Joined Enum(cmodel) Var(ix86_cmodel) Init(CM_32) 273 1.1 mrg Use given x86-64 code model 274 1.1 mrg 275 1.3 mrg Enum 276 1.3 mrg Name(cmodel) Type(enum cmodel) 277 1.3 mrg Known code models (for use with the -mcmodel= option): 278 1.3 mrg 279 1.3 mrg EnumValue 280 1.3 mrg Enum(cmodel) String(small) Value(CM_SMALL) 281 1.3 mrg 282 1.3 mrg EnumValue 283 1.3 mrg Enum(cmodel) String(medium) Value(CM_MEDIUM) 284 1.3 mrg 285 1.3 mrg EnumValue 286 1.3 mrg Enum(cmodel) String(large) Value(CM_LARGE) 287 1.3 mrg 288 1.3 mrg EnumValue 289 1.3 mrg Enum(cmodel) String(32) Value(CM_32) 290 1.3 mrg 291 1.3 mrg EnumValue 292 1.3 mrg Enum(cmodel) String(kernel) Value(CM_KERNEL) 293 1.3 mrg 294 1.3 mrg maddress-mode= 295 1.3 mrg Target RejectNegative Joined Enum(pmode) Var(ix86_pmode) Init(PMODE_SI) 296 1.3 mrg Use given address mode 297 1.3 mrg 298 1.3 mrg Enum 299 1.3 mrg Name(pmode) Type(enum pmode) 300 1.3 mrg Known address mode (for use with the -maddress-mode= option): 301 1.3 mrg 302 1.3 mrg EnumValue 303 1.3 mrg Enum(pmode) String(short) Value(PMODE_SI) 304 1.3 mrg 305 1.3 mrg EnumValue 306 1.3 mrg Enum(pmode) String(long) Value(PMODE_DI) 307 1.3 mrg 308 1.3 mrg mcpu= 309 1.3 mrg Target RejectNegative Joined Undocumented Alias(mtune=) Warn(%<-mcpu=%> is deprecated; use %<-mtune=%> or %<-march=%> instead) 310 1.3 mrg 311 1.1 mrg mfancy-math-387 312 1.1 mrg Target RejectNegative Report InverseMask(NO_FANCY_MATH_387, USE_FANCY_MATH_387) Save 313 1.1 mrg Generate sin, cos, sqrt for FPU 314 1.1 mrg 315 1.1 mrg mforce-drap 316 1.1 mrg Target Report Var(ix86_force_drap) 317 1.1 mrg Always use Dynamic Realigned Argument Pointer (DRAP) to realign stack 318 1.1 mrg 319 1.1 mrg mfp-ret-in-387 320 1.1 mrg Target Report Mask(FLOAT_RETURNS) Save 321 1.1 mrg Return values of functions in FPU registers 322 1.1 mrg 323 1.1 mrg mfpmath= 324 1.3 mrg Target RejectNegative Joined Var(ix86_fpmath) Enum(fpmath_unit) Init(FPMATH_387) Save 325 1.1 mrg Generate floating point mathematics using given instruction set 326 1.1 mrg 327 1.3 mrg Enum 328 1.3 mrg Name(fpmath_unit) Type(enum fpmath_unit) 329 1.3 mrg Valid arguments to -mfpmath=: 330 1.3 mrg 331 1.3 mrg EnumValue 332 1.3 mrg Enum(fpmath_unit) String(387) Value(FPMATH_387) 333 1.3 mrg 334 1.3 mrg EnumValue 335 1.3 mrg Enum(fpmath_unit) String(sse) Value(FPMATH_SSE) 336 1.3 mrg 337 1.3 mrg EnumValue 338 1.3 mrg Enum(fpmath_unit) String(387,sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 339 1.3 mrg 340 1.3 mrg EnumValue 341 1.3 mrg Enum(fpmath_unit) String(387+sse) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 342 1.3 mrg 343 1.3 mrg EnumValue 344 1.3 mrg Enum(fpmath_unit) String(sse,387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 345 1.3 mrg 346 1.3 mrg EnumValue 347 1.3 mrg Enum(fpmath_unit) String(sse+387) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 348 1.3 mrg 349 1.3 mrg EnumValue 350 1.3 mrg Enum(fpmath_unit) String(both) Value({(enum fpmath_unit) (FPMATH_SSE | FPMATH_387)}) 351 1.3 mrg 352 1.1 mrg mhard-float 353 1.3 mrg Target RejectNegative Mask(80387) Save 354 1.1 mrg Use hardware fp 355 1.1 mrg 356 1.1 mrg mieee-fp 357 1.1 mrg Target Report Mask(IEEE_FP) Save 358 1.1 mrg Use IEEE math for fp comparisons 359 1.1 mrg 360 1.1 mrg minline-all-stringops 361 1.1 mrg Target Report Mask(INLINE_ALL_STRINGOPS) Save 362 1.1 mrg Inline all known string operations 363 1.1 mrg 364 1.1 mrg minline-stringops-dynamically 365 1.1 mrg Target Report Mask(INLINE_STRINGOPS_DYNAMICALLY) Save 366 1.1 mrg Inline memset/memcpy string operations, but perform inline version only for small blocks 367 1.1 mrg 368 1.1 mrg mintel-syntax 369 1.3 mrg Target Undocumented Alias(masm=, intel, att) Warn(%<-mintel-syntax%> and %<-mno-intel-syntax%> are deprecated; use %<-masm=intel%> and %<-masm=att%> instead) 370 1.1 mrg ;; Deprecated 371 1.1 mrg 372 1.1 mrg mms-bitfields 373 1.1 mrg Target Report Mask(MS_BITFIELD_LAYOUT) Save 374 1.1 mrg Use native (MS) bitfield layout 375 1.1 mrg 376 1.1 mrg mno-align-stringops 377 1.1 mrg Target RejectNegative Report Mask(NO_ALIGN_STRINGOPS) Undocumented Save 378 1.1 mrg 379 1.1 mrg mno-fancy-math-387 380 1.1 mrg Target RejectNegative Report Mask(NO_FANCY_MATH_387) Undocumented Save 381 1.1 mrg 382 1.1 mrg mno-push-args 383 1.1 mrg Target RejectNegative Report Mask(NO_PUSH_ARGS) Undocumented Save 384 1.1 mrg 385 1.1 mrg mno-red-zone 386 1.1 mrg Target RejectNegative Report Mask(NO_RED_ZONE) Undocumented Save 387 1.1 mrg 388 1.1 mrg momit-leaf-frame-pointer 389 1.1 mrg Target Report Mask(OMIT_LEAF_FRAME_POINTER) Save 390 1.1 mrg Omit the frame pointer in leaf functions 391 1.1 mrg 392 1.3 mrg mpc32 393 1.3 mrg Target RejectNegative Report 394 1.3 mrg Set 80387 floating-point precision to 32-bit 395 1.3 mrg 396 1.3 mrg mpc64 397 1.3 mrg Target RejectNegative Report 398 1.3 mrg Set 80387 floating-point precision to 64-bit 399 1.3 mrg 400 1.3 mrg mpc80 401 1.3 mrg Target RejectNegative Report 402 1.3 mrg Set 80387 floating-point precision to 80-bit 403 1.1 mrg 404 1.1 mrg mpreferred-stack-boundary= 405 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_preferred_stack_boundary_arg) 406 1.1 mrg Attempt to keep stack aligned to this power of 2 407 1.1 mrg 408 1.1 mrg mincoming-stack-boundary= 409 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_incoming_stack_boundary_arg) 410 1.1 mrg Assume incoming stack aligned to this power of 2 411 1.1 mrg 412 1.1 mrg mpush-args 413 1.1 mrg Target Report InverseMask(NO_PUSH_ARGS, PUSH_ARGS) Save 414 1.1 mrg Use push instructions to save outgoing arguments 415 1.1 mrg 416 1.1 mrg mred-zone 417 1.1 mrg Target RejectNegative Report InverseMask(NO_RED_ZONE, RED_ZONE) Save 418 1.1 mrg Use red-zone in the x86-64 code 419 1.1 mrg 420 1.1 mrg mregparm= 421 1.3 mrg Target RejectNegative Joined UInteger Var(ix86_regparm) 422 1.1 mrg Number of registers used to pass integer arguments 423 1.1 mrg 424 1.1 mrg mrtd 425 1.1 mrg Target Report Mask(RTD) Save 426 1.1 mrg Alternate calling convention 427 1.1 mrg 428 1.1 mrg msoft-float 429 1.1 mrg Target InverseMask(80387) Save 430 1.1 mrg Do not use hardware fp 431 1.1 mrg 432 1.1 mrg msseregparm 433 1.1 mrg Target RejectNegative Mask(SSEREGPARM) Save 434 1.1 mrg Use SSE register passing conventions for SF and DF mode 435 1.1 mrg 436 1.1 mrg mstackrealign 437 1.1 mrg Target Report Var(ix86_force_align_arg_pointer) Init(-1) 438 1.1 mrg Realign stack in prologue 439 1.1 mrg 440 1.1 mrg mstack-arg-probe 441 1.1 mrg Target Report Mask(STACK_PROBE) Save 442 1.1 mrg Enable stack probing 443 1.1 mrg 444 1.5 mrg mmemcpy-strategy= 445 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memcpy_strategy) 446 1.5 mrg Specify memcpy expansion strategy when expected size is known 447 1.5 mrg 448 1.5 mrg mmemset-strategy= 449 1.5 mrg Target RejectNegative Joined Var(ix86_tune_memset_strategy) 450 1.5 mrg Specify memset expansion strategy when expected size is known 451 1.5 mrg 452 1.1 mrg mstringop-strategy= 453 1.3 mrg Target RejectNegative Joined Enum(stringop_alg) Var(ix86_stringop_alg) Init(no_stringop) 454 1.1 mrg Chose strategy to generate stringop using 455 1.1 mrg 456 1.3 mrg Enum 457 1.3 mrg Name(stringop_alg) Type(enum stringop_alg) 458 1.3 mrg Valid arguments to -mstringop-strategy=: 459 1.3 mrg 460 1.3 mrg EnumValue 461 1.3 mrg Enum(stringop_alg) String(rep_byte) Value(rep_prefix_1_byte) 462 1.3 mrg 463 1.3 mrg EnumValue 464 1.3 mrg Enum(stringop_alg) String(libcall) Value(libcall) 465 1.3 mrg 466 1.3 mrg EnumValue 467 1.3 mrg Enum(stringop_alg) String(rep_4byte) Value(rep_prefix_4_byte) 468 1.3 mrg 469 1.3 mrg EnumValue 470 1.3 mrg Enum(stringop_alg) String(rep_8byte) Value(rep_prefix_8_byte) 471 1.3 mrg 472 1.3 mrg EnumValue 473 1.3 mrg Enum(stringop_alg) String(byte_loop) Value(loop_1_byte) 474 1.3 mrg 475 1.3 mrg EnumValue 476 1.3 mrg Enum(stringop_alg) String(loop) Value(loop) 477 1.3 mrg 478 1.3 mrg EnumValue 479 1.3 mrg Enum(stringop_alg) String(unrolled_loop) Value(unrolled_loop) 480 1.3 mrg 481 1.5 mrg EnumValue 482 1.5 mrg Enum(stringop_alg) String(vector_loop) Value(vector_loop) 483 1.5 mrg 484 1.1 mrg mtls-dialect= 485 1.3 mrg Target RejectNegative Joined Var(ix86_tls_dialect) Enum(tls_dialect) Init(TLS_DIALECT_GNU) 486 1.1 mrg Use given thread-local storage dialect 487 1.1 mrg 488 1.3 mrg Enum 489 1.3 mrg Name(tls_dialect) Type(enum tls_dialect) 490 1.3 mrg Known TLS dialects (for use with the -mtls-dialect= option): 491 1.3 mrg 492 1.3 mrg EnumValue 493 1.3 mrg Enum(tls_dialect) String(gnu) Value(TLS_DIALECT_GNU) 494 1.3 mrg 495 1.3 mrg EnumValue 496 1.3 mrg Enum(tls_dialect) String(gnu2) Value(TLS_DIALECT_GNU2) 497 1.3 mrg 498 1.1 mrg mtls-direct-seg-refs 499 1.1 mrg Target Report Mask(TLS_DIRECT_SEG_REFS) 500 1.1 mrg Use direct references against %gs when accessing tls data 501 1.1 mrg 502 1.1 mrg mtune= 503 1.1 mrg Target RejectNegative Joined Var(ix86_tune_string) 504 1.1 mrg Schedule code for given CPU 505 1.1 mrg 506 1.5 mrg mtune-ctrl= 507 1.5 mrg Target RejectNegative Joined Var(ix86_tune_ctrl_string) 508 1.5 mrg Fine grain control of tune features 509 1.5 mrg 510 1.5 mrg mno-default 511 1.5 mrg Target RejectNegative Var(ix86_tune_no_default) Init(0) 512 1.5 mrg Clear all tune features 513 1.5 mrg 514 1.5 mrg mdump-tune-features 515 1.5 mrg Target RejectNegative Var(ix86_dump_tunes) Init(0) 516 1.5 mrg 517 1.1 mrg mabi= 518 1.3 mrg Target RejectNegative Joined Var(ix86_abi) Enum(calling_abi) Init(SYSV_ABI) 519 1.1 mrg Generate code that conforms to the given ABI 520 1.1 mrg 521 1.3 mrg Enum 522 1.3 mrg Name(calling_abi) Type(enum calling_abi) 523 1.3 mrg Known ABIs (for use with the -mabi= option): 524 1.3 mrg 525 1.3 mrg EnumValue 526 1.3 mrg Enum(calling_abi) String(sysv) Value(SYSV_ABI) 527 1.3 mrg 528 1.3 mrg EnumValue 529 1.3 mrg Enum(calling_abi) String(ms) Value(MS_ABI) 530 1.3 mrg 531 1.1 mrg mveclibabi= 532 1.3 mrg Target RejectNegative Joined Var(ix86_veclibabi_type) Enum(ix86_veclibabi) Init(ix86_veclibabi_type_none) 533 1.1 mrg Vector library ABI to use 534 1.1 mrg 535 1.3 mrg Enum 536 1.3 mrg Name(ix86_veclibabi) Type(enum ix86_veclibabi) 537 1.3 mrg Known vectorization library ABIs (for use with the -mveclibabi= option): 538 1.3 mrg 539 1.3 mrg EnumValue 540 1.3 mrg Enum(ix86_veclibabi) String(svml) Value(ix86_veclibabi_type_svml) 541 1.3 mrg 542 1.3 mrg EnumValue 543 1.3 mrg Enum(ix86_veclibabi) String(acml) Value(ix86_veclibabi_type_acml) 544 1.3 mrg 545 1.3 mrg mvect8-ret-in-mem 546 1.3 mrg Target Report Mask(VECT8_RETURNS) Save 547 1.3 mrg Return 8-byte vectors in memory 548 1.3 mrg 549 1.1 mrg mrecip 550 1.1 mrg Target Report Mask(RECIP) Save 551 1.1 mrg Generate reciprocals instead of divss and sqrtss. 552 1.1 mrg 553 1.3 mrg mrecip= 554 1.3 mrg Target Report RejectNegative Joined Var(ix86_recip_name) 555 1.3 mrg Control generation of reciprocal estimates. 556 1.3 mrg 557 1.1 mrg mcld 558 1.1 mrg Target Report Mask(CLD) Save 559 1.1 mrg Generate cld instruction in the function prologue. 560 1.1 mrg 561 1.3 mrg mvzeroupper 562 1.3 mrg Target Report Mask(VZEROUPPER) Save 563 1.3 mrg Generate vzeroupper instruction before a transfer of control flow out of 564 1.3 mrg the function. 565 1.3 mrg 566 1.3 mrg mdispatch-scheduler 567 1.3 mrg Target RejectNegative Var(flag_dispatch_scheduler) 568 1.5 mrg Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 or bdver4 and Haifa scheduling 569 1.3 mrg is selected. 570 1.3 mrg 571 1.3 mrg mprefer-avx128 572 1.3 mrg Target Report Mask(PREFER_AVX128) SAVE 573 1.3 mrg Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer. 574 1.1 mrg 575 1.1 mrg ;; ISA support 576 1.1 mrg 577 1.1 mrg m32 578 1.3 mrg Target RejectNegative Negative(m64) Report InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 579 1.1 mrg Generate 32bit i386 code 580 1.1 mrg 581 1.1 mrg m64 582 1.3 mrg Target RejectNegative Negative(mx32) Report Mask(ABI_64) Var(ix86_isa_flags) Save 583 1.1 mrg Generate 64bit x86-64 code 584 1.1 mrg 585 1.3 mrg mx32 586 1.5 mrg Target RejectNegative Negative(m16) Report Mask(ABI_X32) Var(ix86_isa_flags) Save 587 1.3 mrg Generate 32bit x86-64 code 588 1.3 mrg 589 1.5 mrg m16 590 1.5 mrg Target RejectNegative Negative(m32) Report Mask(CODE16) InverseMask(ISA_64BIT) Var(ix86_isa_flags) Save 591 1.5 mrg Generate 16bit i386 code 592 1.5 mrg 593 1.1 mrg mmmx 594 1.3 mrg Target Report Mask(ISA_MMX) Var(ix86_isa_flags) Save 595 1.1 mrg Support MMX built-in functions 596 1.1 mrg 597 1.1 mrg m3dnow 598 1.3 mrg Target Report Mask(ISA_3DNOW) Var(ix86_isa_flags) Save 599 1.1 mrg Support 3DNow! built-in functions 600 1.1 mrg 601 1.1 mrg m3dnowa 602 1.3 mrg Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save 603 1.1 mrg Support Athlon 3Dnow! built-in functions 604 1.1 mrg 605 1.1 mrg msse 606 1.3 mrg Target Report Mask(ISA_SSE) Var(ix86_isa_flags) Save 607 1.1 mrg Support MMX and SSE built-in functions and code generation 608 1.1 mrg 609 1.1 mrg msse2 610 1.3 mrg Target Report Mask(ISA_SSE2) Var(ix86_isa_flags) Save 611 1.1 mrg Support MMX, SSE and SSE2 built-in functions and code generation 612 1.1 mrg 613 1.1 mrg msse3 614 1.3 mrg Target Report Mask(ISA_SSE3) Var(ix86_isa_flags) Save 615 1.1 mrg Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation 616 1.1 mrg 617 1.1 mrg mssse3 618 1.3 mrg Target Report Mask(ISA_SSSE3) Var(ix86_isa_flags) Save 619 1.1 mrg Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation 620 1.1 mrg 621 1.1 mrg msse4.1 622 1.3 mrg Target Report Mask(ISA_SSE4_1) Var(ix86_isa_flags) Save 623 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation 624 1.1 mrg 625 1.1 mrg msse4.2 626 1.3 mrg Target Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 627 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 628 1.1 mrg 629 1.1 mrg msse4 630 1.3 mrg Target RejectNegative Report Mask(ISA_SSE4_2) Var(ix86_isa_flags) Save 631 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 and SSE4.2 built-in functions and code generation 632 1.1 mrg 633 1.1 mrg mno-sse4 634 1.3 mrg Target RejectNegative Report InverseMask(ISA_SSE4_1) Var(ix86_isa_flags) Save 635 1.1 mrg Do not support SSE4.1 and SSE4.2 built-in functions and code generation 636 1.1 mrg 637 1.3 mrg msse5 638 1.3 mrg Target Undocumented Alias(mavx) Warn(%<-msse5%> was removed) 639 1.3 mrg ;; Deprecated 640 1.3 mrg 641 1.1 mrg mavx 642 1.3 mrg Target Report Mask(ISA_AVX) Var(ix86_isa_flags) Save 643 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2 and AVX built-in functions and code generation 644 1.1 mrg 645 1.3 mrg mavx2 646 1.3 mrg Target Report Mask(ISA_AVX2) Var(ix86_isa_flags) Save 647 1.3 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and AVX2 built-in functions and code generation 648 1.3 mrg 649 1.5 mrg mavx512f 650 1.5 mrg Target Report Mask(ISA_AVX512F) Var(ix86_isa_flags) Save 651 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F built-in functions and code generation 652 1.5 mrg 653 1.5 mrg mavx512pf 654 1.5 mrg Target Report Mask(ISA_AVX512PF) Var(ix86_isa_flags) Save 655 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512PF built-in functions and code generation 656 1.5 mrg 657 1.5 mrg mavx512er 658 1.5 mrg Target Report Mask(ISA_AVX512ER) Var(ix86_isa_flags) Save 659 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512ER built-in functions and code generation 660 1.5 mrg 661 1.5 mrg mavx512cd 662 1.5 mrg Target Report Mask(ISA_AVX512CD) Var(ix86_isa_flags) Save 663 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512CD built-in functions and code generation 664 1.5 mrg 665 1.5 mrg mavx512dq 666 1.5 mrg Target Report Mask(ISA_AVX512DQ) Var(ix86_isa_flags) Save 667 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512DQ built-in functions and code generation 668 1.5 mrg 669 1.5 mrg mavx512bw 670 1.5 mrg Target Report Mask(ISA_AVX512BW) Var(ix86_isa_flags) Save 671 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512BW built-in functions and code generation 672 1.5 mrg 673 1.5 mrg mavx512vl 674 1.5 mrg Target Report Mask(ISA_AVX512VL) Var(ix86_isa_flags) Save 675 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VL built-in functions and code generation 676 1.5 mrg 677 1.5 mrg mavx512ifma 678 1.5 mrg Target Report Mask(ISA_AVX512IFMA) Var(ix86_isa_flags) Save 679 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512IFMA built-in functions and code generation 680 1.5 mrg 681 1.5 mrg mavx512vbmi 682 1.5 mrg Target Report Mask(ISA_AVX512VBMI) Var(ix86_isa_flags) Save 683 1.5 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX512F and AVX512VBMI built-in functions and code generation 684 1.5 mrg 685 1.1 mrg mfma 686 1.3 mrg Target Report Mask(ISA_FMA) Var(ix86_isa_flags) Save 687 1.1 mrg Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and FMA built-in functions and code generation 688 1.1 mrg 689 1.1 mrg msse4a 690 1.3 mrg Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) Save 691 1.1 mrg Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation 692 1.1 mrg 693 1.1 mrg mfma4 694 1.3 mrg Target Report Mask(ISA_FMA4) Var(ix86_isa_flags) Save 695 1.1 mrg Support FMA4 built-in functions and code generation 696 1.1 mrg 697 1.1 mrg mxop 698 1.3 mrg Target Report Mask(ISA_XOP) Var(ix86_isa_flags) Save 699 1.1 mrg Support XOP built-in functions and code generation 700 1.1 mrg 701 1.1 mrg mlwp 702 1.3 mrg Target Report Mask(ISA_LWP) Var(ix86_isa_flags) Save 703 1.1 mrg Support LWP built-in functions and code generation 704 1.1 mrg 705 1.1 mrg mabm 706 1.3 mrg Target Report Mask(ISA_ABM) Var(ix86_isa_flags) Save 707 1.1 mrg Support code generation of Advanced Bit Manipulation (ABM) instructions. 708 1.1 mrg 709 1.1 mrg mpopcnt 710 1.3 mrg Target Report Mask(ISA_POPCNT) Var(ix86_isa_flags) Save 711 1.1 mrg Support code generation of popcnt instruction. 712 1.1 mrg 713 1.3 mrg mbmi 714 1.3 mrg Target Report Mask(ISA_BMI) Var(ix86_isa_flags) Save 715 1.3 mrg Support BMI built-in functions and code generation 716 1.3 mrg 717 1.3 mrg mbmi2 718 1.3 mrg Target Report Mask(ISA_BMI2) Var(ix86_isa_flags) Save 719 1.3 mrg Support BMI2 built-in functions and code generation 720 1.3 mrg 721 1.3 mrg mlzcnt 722 1.3 mrg Target Report Mask(ISA_LZCNT) Var(ix86_isa_flags) Save 723 1.3 mrg Support LZCNT built-in function and code generation 724 1.3 mrg 725 1.3 mrg mhle 726 1.3 mrg Target Report Mask(ISA_HLE) Var(ix86_isa_flags) Save 727 1.3 mrg Support Hardware Lock Elision prefixes 728 1.3 mrg 729 1.3 mrg mrdseed 730 1.3 mrg Target Report Mask(ISA_RDSEED) Var(ix86_isa_flags) Save 731 1.3 mrg Support RDSEED instruction 732 1.3 mrg 733 1.3 mrg mprfchw 734 1.3 mrg Target Report Mask(ISA_PRFCHW) Var(ix86_isa_flags) Save 735 1.3 mrg Support PREFETCHW instruction 736 1.3 mrg 737 1.3 mrg madx 738 1.3 mrg Target Report Mask(ISA_ADX) Var(ix86_isa_flags) Save 739 1.3 mrg Support flag-preserving add-carry instructions 740 1.3 mrg 741 1.5 mrg mclflushopt 742 1.5 mrg Target Report Mask(ISA_CLFLUSHOPT) Var(ix86_isa_flags) Save 743 1.5 mrg Support CLFLUSHOPT instructions 744 1.5 mrg 745 1.5 mrg mclwb 746 1.5 mrg Target Report Mask(ISA_CLWB) Var(ix86_isa_flags) Save 747 1.5 mrg Support CLWB instruction 748 1.5 mrg 749 1.5 mrg mpcommit 750 1.5 mrg Target Report Mask(ISA_PCOMMIT) Var(ix86_isa_flags) Save 751 1.5 mrg Support PCOMMIT instruction 752 1.5 mrg 753 1.3 mrg mfxsr 754 1.3 mrg Target Report Mask(ISA_FXSR) Var(ix86_isa_flags) Save 755 1.3 mrg Support FXSAVE and FXRSTOR instructions 756 1.3 mrg 757 1.3 mrg mxsave 758 1.3 mrg Target Report Mask(ISA_XSAVE) Var(ix86_isa_flags) Save 759 1.3 mrg Support XSAVE and XRSTOR instructions 760 1.3 mrg 761 1.3 mrg mxsaveopt 762 1.3 mrg Target Report Mask(ISA_XSAVEOPT) Var(ix86_isa_flags) Save 763 1.3 mrg Support XSAVEOPT instruction 764 1.3 mrg 765 1.5 mrg mxsavec 766 1.5 mrg Target Report Mask(ISA_XSAVEC) Var(ix86_isa_flags) Save 767 1.5 mrg Support XSAVEC instructions 768 1.5 mrg 769 1.5 mrg mxsaves 770 1.5 mrg Target Report Mask(ISA_XSAVES) Var(ix86_isa_flags) Save 771 1.5 mrg Support XSAVES and XRSTORS instructions 772 1.5 mrg 773 1.3 mrg mtbm 774 1.3 mrg Target Report Mask(ISA_TBM) Var(ix86_isa_flags) Save 775 1.3 mrg Support TBM built-in functions and code generation 776 1.3 mrg 777 1.1 mrg mcx16 778 1.3 mrg Target Report Mask(ISA_CX16) Var(ix86_isa_flags) Save 779 1.1 mrg Support code generation of cmpxchg16b instruction. 780 1.1 mrg 781 1.1 mrg msahf 782 1.3 mrg Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) Save 783 1.1 mrg Support code generation of sahf instruction in 64bit x86-64 code. 784 1.1 mrg 785 1.1 mrg mmovbe 786 1.3 mrg Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) Save 787 1.1 mrg Support code generation of movbe instruction. 788 1.1 mrg 789 1.1 mrg mcrc32 790 1.3 mrg Target Report Mask(ISA_CRC32) Var(ix86_isa_flags) Save 791 1.1 mrg Support code generation of crc32 instruction. 792 1.1 mrg 793 1.1 mrg maes 794 1.3 mrg Target Report Mask(ISA_AES) Var(ix86_isa_flags) Save 795 1.1 mrg Support AES built-in functions and code generation 796 1.1 mrg 797 1.5 mrg msha 798 1.5 mrg Target Report Mask(ISA_SHA) Var(ix86_isa_flags) Save 799 1.5 mrg Support SHA1 and SHA256 built-in functions and code generation 800 1.5 mrg 801 1.1 mrg mpclmul 802 1.3 mrg Target Report Mask(ISA_PCLMUL) Var(ix86_isa_flags) Save 803 1.1 mrg Support PCLMUL built-in functions and code generation 804 1.1 mrg 805 1.1 mrg msse2avx 806 1.1 mrg Target Report Var(ix86_sse2avx) 807 1.1 mrg Encode SSE instructions with VEX prefix 808 1.3 mrg 809 1.3 mrg mfsgsbase 810 1.3 mrg Target Report Mask(ISA_FSGSBASE) Var(ix86_isa_flags) Save 811 1.3 mrg Support FSGSBASE built-in functions and code generation 812 1.3 mrg 813 1.3 mrg mrdrnd 814 1.3 mrg Target Report Mask(ISA_RDRND) Var(ix86_isa_flags) Save 815 1.3 mrg Support RDRND built-in functions and code generation 816 1.3 mrg 817 1.3 mrg mf16c 818 1.3 mrg Target Report Mask(ISA_F16C) Var(ix86_isa_flags) Save 819 1.3 mrg Support F16C built-in functions and code generation 820 1.3 mrg 821 1.5 mrg mprefetchwt1 822 1.5 mrg Target Report Mask(ISA_PREFETCHWT1) Var(ix86_isa_flags) Save 823 1.5 mrg Support PREFETCHWT1 built-in functions and code generation 824 1.5 mrg 825 1.3 mrg mfentry 826 1.3 mrg Target Report Var(flag_fentry) Init(-1) 827 1.3 mrg Emit profiling counter call at function entry before prologue. 828 1.3 mrg 829 1.5 mrg mrecord-mcount 830 1.5 mrg Target Report Var(flag_record_mcount) Init(0) 831 1.5 mrg Generate __mcount_loc section with all mcount or __fentry__ calls. 832 1.5 mrg 833 1.5 mrg mnop-mcount 834 1.5 mrg Target Report Var(flag_nop_mcount) Init(0) 835 1.5 mrg Generate mcount/__fentry__ calls as nops. To activate they need to be 836 1.5 mrg patched in. 837 1.5 mrg 838 1.5 mrg mskip-rax-setup 839 1.5 mrg Target Report Var(flag_skip_rax_setup) Init(0) 840 1.5 mrg Skip setting up RAX register when passing variable arguments. 841 1.5 mrg 842 1.3 mrg m8bit-idiv 843 1.3 mrg Target Report Mask(USE_8BIT_IDIV) Save 844 1.3 mrg Expand 32bit/64bit integer divide into 8bit unsigned integer divide with run-time check 845 1.3 mrg 846 1.3 mrg mavx256-split-unaligned-load 847 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_LOAD) Save 848 1.3 mrg Split 32-byte AVX unaligned load 849 1.3 mrg 850 1.3 mrg mavx256-split-unaligned-store 851 1.3 mrg Target Report Mask(AVX256_SPLIT_UNALIGNED_STORE) Save 852 1.3 mrg Split 32-byte AVX unaligned store 853 1.3 mrg 854 1.3 mrg mrtm 855 1.3 mrg Target Report Mask(ISA_RTM) Var(ix86_isa_flags) Save 856 1.3 mrg Support RTM built-in functions and code generation 857 1.5 mrg 858 1.5 mrg mmpx 859 1.5 mrg Target Report Mask(ISA_MPX) Var(ix86_isa_flags) Save 860 1.5 mrg Support MPX code generation 861 1.5 mrg 862 1.5 mrg mmwaitx 863 1.5 mrg Target Report Mask(ISA_MWAITX) Var(ix86_isa_flags) Save 864 1.5 mrg Support MWAITX and MONITORX built-in functions and code generation 865 1.5 mrg 866 1.5 mrg mstack-protector-guard= 867 1.5 mrg Target RejectNegative Joined Enum(stack_protector_guard) Var(ix86_stack_protector_guard) Init(SSP_TLS) 868 1.5 mrg Use given stack-protector guard 869 1.5 mrg 870 1.5 mrg Enum 871 1.5 mrg Name(stack_protector_guard) Type(enum stack_protector_guard) 872 1.5 mrg Known stack protector guard (for use with the -mstack-protector-guard= option): 873 1.5 mrg 874 1.5 mrg EnumValue 875 1.5 mrg Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 876 1.5 mrg 877 1.5 mrg EnumValue 878 1.5 mrg Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 879
Indexes created Wed Apr 29 00:23:26 UTC 2026