1 ;; GCC machine description for AVX512F instructions 2 ;; Copyright (C) 2013-2022 Free Software Foundation, Inc. 3 ;; 4 ;; This file is part of GCC. 5 ;; 6 ;; GCC is free software; you can redistribute it and/or modify 7 ;; it under the terms of the GNU General Public License as published by 8 ;; the Free Software Foundation; either version 3, or (at your option) 9 ;; any later version. 10 ;; 11 ;; GCC is distributed in the hope that it will be useful, 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 ;; GNU General Public License for more details. 15 ;; 16 ;; You should have received a copy of the GNU General Public License 17 ;; along with GCC; see the file COPYING3. If not see 18 ;; <http://www.gnu.org/licenses/>. 19 20 ;; Some iterators for extending subst as much as possible 21 ;; All vectors (Use it for destination) 22 (define_mode_iterator SUBST_V 23 [V64QI V32QI V16QI 24 V32HI V16HI V8HI 25 V16SI V8SI V4SI 26 V8DI V4DI V2DI 27 V32HF V16HF V8HF 28 V16SF V8SF V4SF 29 V8DF V4DF V2DF]) 30 31 (define_mode_iterator SUBST_CV 32 [V32HF V16HF V8HF]) 33 34 (define_mode_iterator SUBST_S 35 [QI HI SI DI]) 36 37 (define_mode_iterator SUBST_A 38 [V64QI V32QI V16QI 39 V32HI V16HI V8HI 40 V16SI V8SI V4SI 41 V8DI V4DI V2DI 42 V32HF V16HF V8HF 43 V16SF V8SF V4SF 44 V8DF V4DF V2DF 45 QI HI SI DI SF DF]) 46 47 (define_subst_attr "mask_name" "mask" "" "_mask") 48 (define_subst_attr "maskc_name" "maskc" "" "_mask") 49 (define_subst_attr "mask_applied" "mask" "false" "true") 50 (define_subst_attr "mask_operand2" "mask" "" "%{%3%}%N2") 51 (define_subst_attr "mask_operand3" "mask" "" "%{%4%}%N3") 52 (define_subst_attr "maskc_operand3" "maskc" "" "%{%4%}%N3") 53 (define_subst_attr "mask_operand3_1" "mask" "" "%%{%%4%%}%%N3") ;; for sprintf 54 (define_subst_attr "mask_operand4" "mask" "" "%{%5%}%N4") 55 (define_subst_attr "mask_operand6" "mask" "" "%{%7%}%N6") 56 (define_subst_attr "mask_operand7" "mask" "" "%{%8%}%N7") 57 (define_subst_attr "mask_operand10" "mask" "" "%{%11%}%N10") 58 (define_subst_attr "mask_operand11" "mask" "" "%{%12%}%N11") 59 (define_subst_attr "mask_operand18" "mask" "" "%{%19%}%N18") 60 (define_subst_attr "mask_operand19" "mask" "" "%{%20%}%N19") 61 (define_subst_attr "mask_codefor" "mask" "*" "") 62 (define_subst_attr "mask_operand_arg34" "mask" "" ", operands[3], operands[4]") 63 (define_subst_attr "mask_mode512bit_condition" "mask" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)") 64 (define_subst_attr "mask_avx512vl_condition" "mask" "1" "TARGET_AVX512VL") 65 (define_subst_attr "mask_avx512bw_condition" "mask" "1" "TARGET_AVX512BW") 66 (define_subst_attr "mask_avx512dq_condition" "mask" "1" "TARGET_AVX512DQ") 67 (define_subst_attr "mask_prefix" "mask" "vex" "evex") 68 (define_subst_attr "mask_prefix2" "mask" "maybe_vex" "evex") 69 (define_subst_attr "mask_prefix3" "mask" "orig,vex" "evex,evex") 70 (define_subst_attr "bcst_mask_prefix3" "mask" "orig,maybe_evex" "evex,evex") 71 (define_subst_attr "mask_prefix4" "mask" "orig,orig,vex" "evex,evex,evex") 72 (define_subst_attr "bcst_mask_prefix4" "mask" "orig,orig,maybe_evex" "evex,evex,evex") 73 (define_subst_attr "mask_expand_op3" "mask" "3" "5") 74 (define_subst_attr "mask3_dest_false_dep_for_glc_cond" "mask" "1" "operands[3] == CONST0_RTX(<MODE>mode)") 75 (define_subst_attr "mask4_dest_false_dep_for_glc_cond" "mask" "1" "operands[4] == CONST0_RTX(<MODE>mode)") 76 (define_subst_attr "mask6_dest_false_dep_for_glc_cond" "mask" "1" "operands[6] == CONST0_RTX(<MODE>mode)") 77 (define_subst_attr "mask10_dest_false_dep_for_glc_cond" "mask" "1" "operands[10] == CONST0_RTX(<MODE>mode)") 78 (define_subst_attr "maskc_dest_false_dep_for_glc_cond" "maskc" "1" "operands[3] == CONST0_RTX(<MODE>mode)") 79 80 (define_subst "mask" 81 [(set (match_operand:SUBST_V 0) 82 (match_operand:SUBST_V 1))] 83 "TARGET_AVX512F" 84 [(set (match_dup 0) 85 (vec_merge:SUBST_V 86 (match_dup 1) 87 (match_operand:SUBST_V 2 "nonimm_or_0_operand" "0C") 88 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))]) 89 90 (define_subst_attr "merge_mask_name" "merge_mask" "" "_merge_mask") 91 (define_subst_attr "merge_mask_operand3" "merge_mask" "" "%{%3%}") 92 (define_subst "merge_mask" 93 [(set (match_operand:SUBST_V 0) 94 (match_operand:SUBST_V 1))] 95 "TARGET_AVX512F" 96 [(set (match_dup 0) 97 (vec_merge:SUBST_V 98 (match_dup 1) 99 (match_dup 0) 100 (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")))]) 101 102 (define_subst "maskc" 103 [(set (match_operand:SUBST_CV 0) 104 (match_operand:SUBST_CV 1))] 105 "TARGET_AVX512F" 106 [(set (match_dup 0) 107 (vec_merge:SUBST_CV 108 (match_dup 1) 109 (match_operand:SUBST_CV 2 "nonimm_or_0_operand" "0C") 110 (unspec:<avx512fmaskmode> 111 [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")] 112 UNSPEC_COMPLEX_MASK)))]) 113 114 (define_subst_attr "mask_scalar_merge_name" "mask_scalar_merge" "" "_mask") 115 (define_subst_attr "mask_scalar_merge_operand3" "mask_scalar_merge" "" "%{%3%}") 116 (define_subst_attr "mask_scalar_merge_operand4" "mask_scalar_merge" "" "%{%4%}") 117 118 (define_subst "mask_scalar_merge" 119 [(set (match_operand:SUBST_S 0) 120 (match_operand:SUBST_S 1))] 121 "TARGET_AVX512F" 122 [(set (match_dup 0) 123 (and:SUBST_S 124 (match_dup 1) 125 (match_operand:SUBST_S 3 "register_operand" "Yk")))]) 126 127 (define_subst_attr "sd_maskz_name" "sd" "" "_maskz_1") 128 (define_subst_attr "sd_mask_op4" "sd" "" "%{%5%}%N4") 129 (define_subst_attr "sd_mask_op5" "sd" "" "%{%6%}%N5") 130 (define_subst_attr "sd_mask_codefor" "sd" "*" "") 131 (define_subst_attr "sd_mask_mode512bit_condition" "sd" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)") 132 133 (define_subst "sd" 134 [(set (match_operand:SUBST_V 0) 135 (match_operand:SUBST_V 1))] 136 "" 137 [(set (match_dup 0) 138 (vec_merge:SUBST_V 139 (match_dup 1) 140 (match_operand:SUBST_V 2 "const0_operand" "C") 141 (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk"))) 142 ]) 143 144 (define_subst_attr "maskz_scalar_name" "maskz_scalar" "" "_maskz_1") 145 (define_subst_attr "maskz_scalar_op5" "maskz_scalar" "" "%{%6%}%N5") 146 147 (define_subst "maskz_scalar" 148 [(set (match_operand:SUBST_V 0) 149 (vec_merge:SUBST_V 150 (match_operand:SUBST_V 1) 151 (match_operand:SUBST_V 2) 152 (const_int 1)))] 153 "TARGET_AVX512F" 154 [(set (match_dup 0) 155 (vec_merge:SUBST_V 156 (vec_merge:SUBST_V 157 (match_dup 1) 158 (match_operand:SUBST_V 3 "const0_operand" "C") 159 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")) 160 (match_dup 2) 161 (const_int 1)))]) 162 (define_subst_attr "sdc_maskz_name" "sdc" "" "_maskz_1") 163 (define_subst_attr "sdc_mask_op4" "sdc" "" "%{%5%}%N4") 164 (define_subst_attr "sdc_mask_op5" "sdc" "" "%{%6%}%N5") 165 (define_subst_attr "sdc_mask_mode512bit_condition" "sdc" "1" "(<MODE_SIZE> == 64 || TARGET_AVX512VL)") 166 167 (define_subst "sdc" 168 [(set (match_operand:SUBST_CV 0) 169 (match_operand:SUBST_CV 1))] 170 "" 171 [(set (match_dup 0) 172 (vec_merge:SUBST_CV 173 (match_dup 1) 174 (match_operand:SUBST_CV 2 "const0_operand" "C") 175 (unspec:<avx512fmaskmode> 176 [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")] 177 UNSPEC_COMPLEX_MASK))) 178 ]) 179 180 (define_subst_attr "round_name" "round" "" "_round") 181 (define_subst_attr "round_mask_operand2" "mask" "%R2" "%R4") 182 (define_subst_attr "round_mask_operand3" "mask" "%R3" "%R5") 183 (define_subst_attr "round_maskc_operand3" "maskc" "%R3" "%R5") 184 (define_subst_attr "round_mask_operand4" "mask" "%R4" "%R6") 185 (define_subst_attr "round_sd_mask_operand4" "sd" "%R4" "%R6") 186 (define_subst_attr "round_sdc_mask_operand4" "sdc" "%R4" "%R6") 187 (define_subst_attr "round_op2" "round" "" "%R2") 188 (define_subst_attr "round_op3" "round" "" "%R3") 189 (define_subst_attr "round_op4" "round" "" "%R4") 190 (define_subst_attr "round_op5" "round" "" "%R5") 191 (define_subst_attr "round_op6" "round" "" "%R6") 192 (define_subst_attr "round_mask_op2" "round" "" "<round_mask_operand2>") 193 (define_subst_attr "round_mask_op3" "round" "" "<round_mask_operand3>") 194 (define_subst_attr "round_maskc_op3" "round" "" "<round_maskc_operand3>") 195 (define_subst_attr "round_mask_op4" "round" "" "<round_mask_operand4>") 196 (define_subst_attr "round_sd_mask_op4" "round" "" "<round_sd_mask_operand4>") 197 (define_subst_attr "round_sdc_mask_op4" "round" "" "<round_sdc_mask_operand4>") 198 (define_subst_attr "round_constraint" "round" "vm" "v") 199 (define_subst_attr "round_qq2phsuff" "round" "<qq2phsuff>" "") 200 (define_subst_attr "bcst_round_constraint" "round" "vmBr" "v") 201 (define_subst_attr "round_constraint2" "round" "m" "v") 202 (define_subst_attr "round_constraint3" "round" "rm" "r") 203 (define_subst_attr "round_nimm_predicate" "round" "vector_operand" "register_operand") 204 (define_subst_attr "bcst_round_nimm_predicate" "round" "bcst_vector_operand" "register_operand") 205 (define_subst_attr "round_nimm_scalar_predicate" "round" "nonimmediate_operand" "register_operand") 206 (define_subst_attr "round_prefix" "round" "vex" "evex") 207 (define_subst_attr "round_mode512bit_condition" "round" "1" "(<MODE>mode == V16SFmode 208 || <MODE>mode == V8DFmode 209 || <MODE>mode == V8DImode 210 || <MODE>mode == V16SImode 211 || <MODE>mode == V32HFmode)") 212 213 (define_subst_attr "round_modev8sf_condition" "round" "1" "(<MODE>mode == V8SFmode)") 214 (define_subst_attr "round_modev4sf_condition" "round" "1" "(<MODE>mode == V4SFmode)") 215 (define_subst_attr "round_codefor" "round" "*" "") 216 (define_subst_attr "round_opnum" "round" "5" "6") 217 218 (define_subst "round" 219 [(set (match_operand:SUBST_A 0) 220 (match_operand:SUBST_A 1))] 221 "TARGET_AVX512F" 222 [(set (match_dup 0) 223 (unspec:SUBST_A [(match_dup 1) 224 (match_operand:SI 2 "const_4_or_8_to_11_operand")] 225 UNSPEC_EMBEDDED_ROUNDING)) 226 ]) 227 228 (define_subst_attr "round_saeonly_name" "round_saeonly" "" "_round") 229 (define_subst_attr "round_saeonly_mask_operand2" "mask" "%r2" "%r4") 230 (define_subst_attr "round_saeonly_mask_operand3" "mask" "%r3" "%r5") 231 (define_subst_attr "round_saeonly_mask_operand4" "mask" "%r4" "%r6") 232 (define_subst_attr "round_saeonly_mask_scalar_merge_operand4" "mask_scalar_merge" "%r4" "%r5") 233 (define_subst_attr "round_saeonly_maskz_scalar_operand5" "maskz_scalar" "%r5" "%r7") 234 (define_subst_attr "round_saeonly_sd_mask_operand5" "sd" "%r5" "%r7") 235 (define_subst_attr "round_saeonly_sdc_mask_operand5" "sdc" "%r5" "%r7") 236 (define_subst_attr "round_saeonly_op2" "round_saeonly" "" "%r2") 237 (define_subst_attr "round_saeonly_op3" "round_saeonly" "" "%r3") 238 (define_subst_attr "round_saeonly_op4" "round_saeonly" "" "%r4") 239 (define_subst_attr "round_saeonly_op5" "round_saeonly" "" "%r5") 240 (define_subst_attr "round_saeonly_op6" "round_saeonly" "" "%r6") 241 (define_subst_attr "round_saeonly_prefix" "round_saeonly" "vex" "evex") 242 (define_subst_attr "round_saeonly_mask_op2" "round_saeonly" "" "<round_saeonly_mask_operand2>") 243 (define_subst_attr "round_saeonly_mask_op3" "round_saeonly" "" "<round_saeonly_mask_operand3>") 244 (define_subst_attr "round_saeonly_mask_op4" "round_saeonly" "" "<round_saeonly_mask_operand4>") 245 (define_subst_attr "round_saeonly_mask_scalar_merge_op4" "round_saeonly" "" "<round_saeonly_mask_scalar_merge_operand4>") 246 (define_subst_attr "round_saeonly_sd_mask_op5" "round_saeonly" "" "<round_saeonly_sd_mask_operand5>") 247 (define_subst_attr "round_saeonly_maskz_scalar_op5" "round_saeonly" "" "<round_saeonly_maskz_scalar_operand5>") 248 (define_subst_attr "round_saeonly_mask_arg3" "round_saeonly" "" ", operands[<mask_expand_op3>]") 249 (define_subst_attr "round_saeonly_constraint" "round_saeonly" "vm" "v") 250 (define_subst_attr "round_saeonly_constraint2" "round_saeonly" "m" "v") 251 (define_subst_attr "round_saeonly_nimm_predicate" "round_saeonly" "vector_operand" "register_operand") 252 (define_subst_attr "round_saeonly_nimm_scalar_predicate" "round_saeonly" "nonimmediate_operand" "register_operand") 253 (define_subst_attr "round_saeonly_mode512bit_condition" "round_saeonly" "1" "(<MODE>mode == V16SFmode 254 || <MODE>mode == V8DFmode 255 || <MODE>mode == V8DImode 256 || <MODE>mode == V16SImode 257 || <MODE>mode == V32HFmode)") 258 259 (define_subst_attr "round_saeonly_modev8sf_condition" "round_saeonly" "1" "(<MODE>mode == V8SFmode)") 260 261 (define_subst "round_saeonly" 262 [(set (match_operand:SUBST_A 0) 263 (match_operand:SUBST_A 1))] 264 "TARGET_AVX512F" 265 [(set (match_dup 0) 266 (unspec:SUBST_A [(match_dup 1) 267 (match_operand:SI 2 "const48_operand")] 268 UNSPEC_EMBEDDED_ROUNDING)) 269 ]) 270 271 (define_subst "round_saeonly" 272 [(set (match_operand:CCFP 0) 273 (match_operand:CCFP 1))] 274 "TARGET_AVX512F" 275 [(set (match_dup 0) 276 (unspec:CCFP [(match_dup 1) 277 (match_operand:SI 2 "const48_operand")] 278 UNSPEC_EMBEDDED_ROUNDING)) 279 ]) 280 281 (define_subst_attr "round_expand_name" "round_expand" "" "_round") 282 (define_subst_attr "round_expand_nimm_predicate" "round_expand" "nonimmediate_operand" "register_operand") 283 (define_subst_attr "round_expand_operand" "round_expand" "" ", operands[5]") 284 (define_subst_attr "round_embedded_complex" "round_expand" "0" "!(CONST_INT_P (operands[5]) 285 && (INTVAL (operands[5]) 286 == NO_ROUND))") 287 288 (define_subst "round_expand" 289 [(match_operand:SUBST_V 0) 290 (match_operand:SUBST_V 1) 291 (match_operand:SUBST_V 2) 292 (match_operand:SUBST_V 3) 293 (match_operand:SUBST_S 4)] 294 "TARGET_AVX512F" 295 [(match_dup 0) 296 (match_dup 1) 297 (match_dup 2) 298 (match_dup 3) 299 (match_dup 4) 300 (unspec [(match_operand:SI 5 "const_4_or_8_to_11_operand")] UNSPEC_EMBEDDED_ROUNDING)]) 301 302 (define_subst_attr "round_saeonly_expand_name" "round_saeonly_expand" "" "_round") 303 (define_subst_attr "round_saeonly_expand_nimm_predicate" "round_saeonly_expand" "nonimmediate_operand" "register_operand") 304 (define_subst_attr "round_saeonly_expand_operand6" "round_saeonly_expand" "" ", operands[6]") 305 306 (define_subst "round_saeonly_expand" 307 [(match_operand:SUBST_V 0) 308 (match_operand:SUBST_V 1) 309 (match_operand:SUBST_V 2) 310 (match_operand:SUBST_A 3) 311 (match_operand:SI 4) 312 (match_operand:SUBST_S 5)] 313 "TARGET_AVX512F" 314 [(match_dup 0) 315 (match_dup 1) 316 (match_dup 2) 317 (match_dup 3) 318 (match_dup 4) 319 (match_dup 5) 320 (unspec [(match_operand:SI 6 "const48_operand")] UNSPEC_EMBEDDED_ROUNDING)]) 321 322 (define_subst_attr "mask_expand4_name" "mask_expand4" "" "_mask") 323 (define_subst_attr "mask_expand4_args" "mask_expand4" "" ", operands[4], operands[5]") 324 325 (define_subst "mask_expand4" 326 [(match_operand:SUBST_V 0) 327 (match_operand:SUBST_V 1) 328 (match_operand:SUBST_V 2) 329 (match_operand:SI 3)] 330 "TARGET_AVX512VL" 331 [(match_dup 0) 332 (match_dup 1) 333 (match_dup 2) 334 (match_dup 3) 335 (match_operand:SUBST_V 4 "nonimm_or_0_operand") 336 (match_operand:<avx512fmaskmode> 5 "register_operand")]) 337 338 (define_subst_attr "mask_scalar_name" "mask_scalar" "" "_mask") 339 (define_subst_attr "mask_scalarcz_name" "mask_scalarcz" "" "_maskz") 340 (define_subst_attr "mask_scalarc_name" "mask_scalarc" "" "_mask") 341 (define_subst_attr "mask_scalarc_operand3" "mask_scalarc" "" "%{%4%}%N3") 342 (define_subst_attr "mask_scalar_operand3" "mask_scalar" "" "%{%4%}%N3") 343 (define_subst_attr "mask_scalar_operand4" "mask_scalar" "" "%{%5%}%N4") 344 (define_subst_attr "mask_scalarcz_operand4" "mask_scalarcz" "" "%{%5%}%N4") 345 (define_subst_attr "mask_scalar4_dest_false_dep_for_glc_cond" "mask_scalar" "1" "operands[4] == CONST0_RTX(<MODE>mode)") 346 (define_subst_attr "mask_scalarc_dest_false_dep_for_glc_cond" "mask_scalarc" "1" "operands[3] == CONST0_RTX(V8HFmode)") 347 (define_subst_attr "mask_scalar_operand_arg34" "mask_scalar" "" ", operands[3], operands[4]") 348 (define_subst_attr "mask_scalar_expand_op3" "mask_scalar" "3" "5") 349 350 (define_subst "mask_scalar" 351 [(set (match_operand:SUBST_V 0) 352 (vec_merge:SUBST_V 353 (match_operand:SUBST_V 1) 354 (match_operand:SUBST_V 2) 355 (const_int 1)))] 356 "TARGET_AVX512F" 357 [(set (match_dup 0) 358 (vec_merge:SUBST_V 359 (vec_merge:SUBST_V 360 (match_dup 1) 361 (match_operand:SUBST_V 3 "nonimm_or_0_operand" "0C") 362 (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")) 363 (match_dup 2) 364 (const_int 1)))]) 365 366 (define_subst "mask_scalarcz" 367 [(set (match_operand:SUBST_CV 0) 368 (vec_merge:SUBST_CV 369 (match_operand:SUBST_CV 1) 370 (match_operand:SUBST_CV 2) 371 (const_int 3)))] 372 "TARGET_AVX512F" 373 [(set (match_dup 0) 374 (vec_merge:SUBST_CV 375 (vec_merge:SUBST_CV 376 (match_dup 1) 377 (match_operand:SUBST_CV 3 "const0_operand" "C") 378 (unspec:<avx512fmaskmode> 379 [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")] 380 UNSPEC_COMPLEX_MASK)) 381 (match_dup 2) 382 (const_int 3)))]) 383 384 (define_subst "mask_scalarc" 385 [(set (match_operand:SUBST_CV 0) 386 (vec_merge:SUBST_CV 387 (match_operand:SUBST_CV 1) 388 (match_operand:SUBST_CV 2) 389 (const_int 3)))] 390 "TARGET_AVX512F" 391 [(set (match_dup 0) 392 (vec_merge:SUBST_CV 393 (vec_merge:SUBST_CV 394 (match_dup 1) 395 (match_operand:SUBST_CV 3 "nonimm_or_0_operand" "0C") 396 (unspec:<avx512fmaskmode> 397 [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")] 398 UNSPEC_COMPLEX_MASK)) 399 (match_dup 2) 400 (const_int 3)))]) 401 402 (define_subst_attr "round_scalar_name" "round_scalar" "" "_round") 403 (define_subst_attr "round_scalarcz_name" "round_scalarcz" "" "_round") 404 (define_subst_attr "round_scalar_mask_operand3" "mask_scalar" "%R3" "%R5") 405 (define_subst_attr "round_scalarc_mask_operand3" "mask_scalarc" "%R3" "%R5") 406 (define_subst_attr "round_scalarcz_mask_operand4" "mask_scalarcz" "%R4" "%R6") 407 (define_subst_attr "round_scalar_mask_op3" "round_scalar" "" "<round_scalar_mask_operand3>") 408 (define_subst_attr "round_scalarc_mask_op3" "round_scalarcz" "" "<round_scalarc_mask_operand3>") 409 (define_subst_attr "round_scalarcz_mask_op4" "round_scalarcz" "" "<round_scalarcz_mask_operand4>") 410 (define_subst_attr "round_scalar_constraint" "round_scalar" "vm" "v") 411 (define_subst_attr "round_scalarcz_constraint" "round_scalarcz" "vm" "v") 412 (define_subst_attr "round_scalar_prefix" "round_scalar" "vex" "evex") 413 (define_subst_attr "round_scalar_nimm_predicate" "round_scalar" "nonimmediate_operand" "register_operand") 414 (define_subst_attr "round_scalarcz_nimm_predicate" "round_scalarcz" "vector_operand" "register_operand") 415 416 (define_subst "round_scalar" 417 [(set (match_operand:SUBST_V 0) 418 (vec_merge:SUBST_V 419 (match_operand:SUBST_V 1) 420 (match_operand:SUBST_V 2) 421 (const_int 1)))] 422 "TARGET_AVX512F" 423 [(set (match_dup 0) 424 (unspec:SUBST_V [ 425 (vec_merge:SUBST_V 426 (match_dup 1) 427 (match_dup 2) 428 (const_int 1)) 429 (match_operand:SI 3 "const_4_or_8_to_11_operand")] 430 UNSPEC_EMBEDDED_ROUNDING))]) 431 432 (define_subst "round_scalarcz" 433 [(set (match_operand:SUBST_V 0) 434 (vec_merge:SUBST_V 435 (match_operand:SUBST_V 1) 436 (match_operand:SUBST_V 2) 437 (const_int 3)))] 438 "TARGET_AVX512F" 439 [(set (match_dup 0) 440 (unspec:SUBST_V [ 441 (vec_merge:SUBST_V 442 (match_dup 1) 443 (match_dup 2) 444 (const_int 3)) 445 (match_operand:SI 3 "const_4_or_8_to_11_operand")] 446 UNSPEC_EMBEDDED_ROUNDING))]) 447 448 (define_subst_attr "round_saeonly_scalar_name" "round_saeonly_scalar" "" "_round") 449 (define_subst_attr "round_saeonly_scalar_mask_operand3" "mask_scalar" "%r3" "%r5") 450 (define_subst_attr "round_saeonly_scalar_mask_operand4" "mask_scalar" "%r4" "%r6") 451 (define_subst_attr "round_saeonly_scalar_mask_op3" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand3>") 452 (define_subst_attr "round_saeonly_scalar_mask_op4" "round_saeonly_scalar" "" "<round_saeonly_scalar_mask_operand4>") 453 (define_subst_attr "round_saeonly_scalar_constraint" "round_saeonly_scalar" "vm" "v") 454 (define_subst_attr "round_saeonly_scalar_prefix" "round_saeonly_scalar" "vex" "evex") 455 (define_subst_attr "round_saeonly_scalar_nimm_predicate" "round_saeonly_scalar" "nonimmediate_operand" "register_operand") 456 (define_subst_attr "round_saeonly_scalar_mask_arg3" "round_saeonly_scalar" "" ", operands[<mask_scalar_expand_op3>]") 457 458 (define_subst "round_saeonly_scalar" 459 [(set (match_operand:SUBST_V 0) 460 (vec_merge:SUBST_V 461 (match_operand:SUBST_V 1) 462 (match_operand:SUBST_V 2) 463 (const_int 1)))] 464 "TARGET_AVX512F" 465 [(set (match_dup 0) 466 (unspec:SUBST_V [ 467 (vec_merge:SUBST_V 468 (match_dup 1) 469 (match_dup 2) 470 (const_int 1)) 471 (match_operand:SI 3 "const48_operand")] 472 UNSPEC_EMBEDDED_ROUNDING))]) 473 474 (define_subst_attr "maskz_half_name" "maskz_half" "" "_maskz_1") 475 (define_subst_attr "maskz_half_operand4" "maskz_half" "" "%{%5%}%N4") 476 477 (define_subst "maskz_half" 478 [(set (match_operand:SUBST_V 0) 479 (match_operand:SUBST_V 1))] 480 "" 481 [(set (match_dup 0) 482 (vec_merge:SUBST_V 483 (match_dup 1) 484 (match_operand:SUBST_V 2 "const0_operand" "C") 485 (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))]) 486
Indexes created Sun Jun 28 00:24:58 UTC 2026