1 ;; Machine Description for Renesas RL78 processors 2 ;; Copyright (C) 2011-2022 Free Software Foundation, Inc. 3 ;; Contributed by Red Hat. 4 5 ;; This file is part of GCC. 6 7 ;; GCC is free software; you can redistribute it and/or modify 8 ;; it under the terms of the GNU General Public License as published by 9 ;; the Free Software Foundation; either version 3, or (at your option) 10 ;; any later version. 11 12 ;; GCC is distributed in the hope that it will be useful, 13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 ;; GNU General Public License for more details. 16 17 ;; You should have received a copy of the GNU General Public License 18 ;; along with GCC; see the file COPYING3. If not see 19 ;; <http://www.gnu.org/licenses/>. 20 22 ;; In this MD file, we define those insn patterns that involve 23 ;; registers, where such registers are virtual until allocated to a 24 ;; physical register. All of these insns need to be conditional on 25 ;; rl78_virt_insns_ok () being true. 26 27 ;; This tells the physical register allocator what method to use to 28 ;; allocate registers. Basically, this defines the template of the 29 ;; instruction - op1 is of the form "a = op(b)", op2 is "a = b op c" 30 ;; etc. 31 32 (define_attr "valloc" "op1,op2,ro1,cmp,umul,macax,divhi,divsi" 33 (const_string "op2")) 34 35 ;;---------- Moving ------------------------ 36 37 (define_insn "*movqi_virt_mm" 38 [(set (match_operand:QI 0 "rl78_near_mem_operand" "=Y") 39 (match_operand 1 "rl78_near_mem_operand" "Y"))] 40 "rl78_virt_insns_ok ()" 41 "v.mov %0, %1" 42 [(set_attr "valloc" "op1")] 43 ) 44 45 (define_insn "*movqi_virt" 46 [(set (match_operand:QI 0 "nonimmediate_operand" "=vY,v,*Wfr,Y,*Wfr,*Wfr") 47 (match_operand 1 "general_operand" "vInt8JY,*Wfr,vInt8J,*Wfr,Y,*Wfr"))] 48 "rl78_virt_insns_ok ()" 49 "v.mov %0, %1" 50 [(set_attr "valloc" "op1")] 51 ) 52 53 (define_insn "*movhi_virt_mm" 54 [(set (match_operand:HI 0 "rl78_near_mem_operand" "=Y") 55 (match_operand:HI 1 "rl78_near_mem_operand" "Y"))] 56 "rl78_virt_insns_ok ()" 57 "v.movw %0, %1" 58 [(set_attr "valloc" "op1")] 59 ) 60 61 (define_insn "*movhi_virt" 62 [(set (match_operand:HI 0 "nonimmediate_operand" "=vS, Y, v, *Wfr") 63 (match_operand:HI 1 "general_operand" "viYS, viS, *Wfr, vi"))] 64 "rl78_virt_insns_ok ()" 65 "v.movw %0, %1" 66 [(set_attr "valloc" "op1")] 67 ) 68 69 (define_insn "*bswaphi2_virt" 70 [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" "=vm") 71 (bswap:HI (match_operand:HI 1 "general_operand" "vim")))] 72 "rl78_virt_insns_ok ()" 73 "v.bswaphi\t%0, %1" 74 [(set_attr "valloc" "op1")] 75 ) 76 77 ;;---------- Conversions ------------------------ 78 79 (define_insn "*zero_extendqihi2_virt" 80 [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" "=vY,*Wfr") 81 (zero_extend:HI (match_operand:QI 1 "general_operand" "vim,viY")))] 82 "rl78_virt_insns_ok () && rl78_one_far_p (operands, 2)" 83 "v.zero_extend\t%0, %1" 84 [(set_attr "valloc" "op1")] 85 ) 86 87 (define_insn "*extendqihi2_virt" 88 [(set (match_operand:HI 0 "rl78_nonfar_nonimm_operand" "=vY,*Wfr") 89 (sign_extend:HI (match_operand:QI 1 "general_operand" "vim,viY")))] 90 "rl78_virt_insns_ok () && rl78_one_far_p (operands, 2)" 91 "v.sign_extend\t%0, %1" 92 [(set_attr "valloc" "op1")] 93 ) 94 95 ;;---------- Arithmetic ------------------------ 96 97 (define_insn "*inc<mode>3_virt" 98 [(set (match_operand:QHI 0 "rl78_incdec_memory_operand" "=vm") 99 (plus:QHI (match_operand:QHI 1 "rl78_incdec_memory_operand" "0") 100 (match_operand:QHI 2 "rl78_1_2_operand" "KLNO"))) 101 ] 102 "rl78_virt_insns_ok ()" 103 "v.inc\t%0, %1, %2" 104 ) 105 106 (define_insn "*add<mode>3_virt" 107 [(set (match_operand:QHI 0 "rl78_nonimmediate_operand" "=vY, S, *Wfr, vY") 108 (plus:QHI (match_operand:QHI 1 "rl78_general_operand" "%viY, 0, 0viY, *Wfr") 109 (match_operand:QHI 2 "rl78_general_operand" "vim, i, viY, viY"))) 110 ] 111 "rl78_virt_insns_ok () && rl78_one_far_p (operands, 3)" 112 "v.add\t%0, %1, %2" 113 ) 114 115 (define_insn "*sub<mode>3_virt" 116 [(set (match_operand:QHI 0 "rl78_nonimmediate_operand" "=vY, S, *Wfr, vY") 117 (minus:QHI (match_operand:QHI 1 "rl78_general_operand" "viY, 0, 0viY, *Wfr") 118 (match_operand:QHI 2 "rl78_general_operand" "vim, i, viY, viY"))) 119 ] 120 "rl78_virt_insns_ok () && rl78_one_far_p (operands, 3)" 121 "v.sub\t%0, %1, %2" 122 ) 123 124 (define_insn "*umulhi3_shift_virt" 125 [(set (match_operand:HI 0 "register_operand" "=v") 126 (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "%vim") 127 (match_operand:HI 2 "rl78_24_operand" "Ni")))] 128 "rl78_virt_insns_ok ()" 129 "v.mulu\t%0, %1, %2" 130 [(set_attr "valloc" "umul")] 131 ) 132 133 (define_insn "*umulqihi3_virt" 134 [(set (match_operand:HI 0 "register_operand" "=v") 135 (mult:HI (zero_extend:HI (match_operand:QI 1 "rl78_nonfar_operand" "%vim")) 136 (zero_extend:HI (match_operand:QI 2 "general_operand" "vim"))))] 137 "rl78_virt_insns_ok ()" 138 "v.mulu\t%0, %2" 139 [(set_attr "valloc" "umul")] 140 ) 141 142 (define_insn "*andqi3_virt" 143 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=vm, *Wfr, vY") 144 (and:QI (match_operand:QI 1 "rl78_general_operand" "%vim, 0viY, *Wfr") 145 (match_operand:QI 2 "rl78_general_operand" "vim, viY, viY"))) 146 ] 147 "rl78_virt_insns_ok () && rl78_one_far_p (operands, 3)" 148 "v.and\t%0, %1, %2" 149 ) 150 151 (define_insn "*iorqi3_virt" 152 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=vm, *Wfr, vY") 153 (ior:QI (match_operand:QI 1 "rl78_general_operand" "%vim, 0viY, *Wfr") 154 (match_operand:QI 2 "rl78_general_operand" "vim, viY, viY"))) 155 ] 156 "rl78_virt_insns_ok () && rl78_one_far_p (operands, 3)" 157 "v.or\t%0, %1, %2" 158 ) 159 160 (define_insn "*xorqi3_virt" 161 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=vm, *Wfr, vY") 162 (xor:QI (match_operand:QI 1 "rl78_general_operand" "%vim, 0viY, *Wfr") 163 (match_operand 2 "rl78_general_operand" "vim, viY, viY"))) 164 ] 165 "rl78_virt_insns_ok () && rl78_one_far_p (operands, 3)" 166 "v.xor\t%0, %1, %2" 167 ) 168 169 ;;---------- Shifts ------------------------ 170 171 (define_insn "*ashl<mode>3_virt" 172 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vm") 173 (ashift:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim") 174 (match_operand:QI 2 "general_operand" "vim"))) 175 ] 176 "rl78_virt_insns_ok ()" 177 "v.shl\t%0, %1, %2" 178 ) 179 180 (define_insn "*ashr<mode>3_virt" 181 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vm") 182 (ashiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim") 183 (match_operand:QI 2 "general_operand" "vim"))) 184 ] 185 "rl78_virt_insns_ok ()" 186 "v.sar\t%0, %1, %2" 187 ) 188 189 (define_insn "*lshr<mode>3_virt" 190 [(set (match_operand:QHI 0 "rl78_nonfar_nonimm_operand" "=vm") 191 (lshiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim") 192 (match_operand:QI 2 "general_operand" "vim"))) 193 ] 194 "rl78_virt_insns_ok ()" 195 "v.shr\t%0, %1, %2" 196 ) 197 198 ;; This is complex mostly because the RL78 has no SImode operations, 199 ;; and very limited HImode operations, and no variable shifts. This 200 ;; pattern is optimized for each constant shift count and operand 201 ;; types, so as to use a hand-optimized pattern. For readability, the 202 ;; usual \t\; syntax is not used here. Also, there's no easy way to 203 ;; constrain to avoid partial overlaps, hence the duplication. 204 (define_insn "ashrsi3_virt" ;; 0 1 2-7 8 9-15 16 17-23 24 25-31 var 205 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,vU,&vU,v, &vU, &vU, v, &vU, v, &vU, &vU, vU, v,&vU, vU, vU, vU") 206 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0, 0, vU,0, vWab, U, 0, vU, 0, vWab,U, vU, 0, vU, vU, vU, 0") 207 (match_operand:SI 2 "nonmemory_operand" "M, K, K, Int3,Int3,Int3,Iv08,Iv08,Is09,Is09,Is09,Iv16,Is17,Is17,Iv24,Is25, iv"))) 208 (clobber (reg:HI X_REG)) 209 ] 210 "" 211 "@ 212 ; ashrsi %0, 0 213 214 movw ax,%H1 \; sarw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a 215 movw ax,%H1 \; sarw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a 216 217 movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax 218 movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax 219 movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax 220 221 mov x,%Q1 \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; sarw ax,8 \; movw %H0,ax 222 mov a,%Q1 \; mov x, a \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; sarw ax,8 \; movw %H0,ax 223 224 mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax 225 mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax 226 mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax 227 228 movw ax,%H1 \; movw %0,ax \; sarw ax,15 \; movw %H0,ax 229 230 movw ax,%H1 \; sarw ax,%S2 \; movw %0,ax \; sarw ax,15 \; movw %H0,ax 231 movw ax,%H1 \; sarw ax,%S2 \; movw %0,ax \; sarw ax,15 \; movw %H0,ax 232 233 movw ax,%H1 \; mov %0,a \; sarw ax,15 \; movw %H0,ax \; mov %Q0,a 234 235 movw ax,%H1 \; sar a,%s2 \; mov %0,a \; sarw ax,15 \; movw %H0,ax \; mov %Q0,a 236 237 mov b,%2 \; cmp0 b \; bz $2f \; 1: \; movw ax,%H1 \; sarw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a \; dec b \; bnz $1b \; 2:" 238 [(set_attr "valloc" "macax")] 239 ) 240 241 ;; Likewise. 242 (define_insn "lshrsi3_virt" ;; 0 1 2-7 8 9-15 16 17-23 24 25-31 var 243 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,vU,&vU,v, &vU, &vU, v, &vU, v, &vU, &vU, vU, v,&vU, vU, vU, vU") 244 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0, 0, vU,0, vWab, U, 0, vU, 0, vWab,U, vU, 0, vU, vU, vU, 0") 245 (match_operand:SI 2 "nonmemory_operand" "M, K, K, Int3,Int3,Int3,Iv08,Iv08,Is09,Is09,Is09,Iv16,Is17,Is17,Iv24,Is25, iv"))) 246 (clobber (reg:HI X_REG)) 247 ] 248 "" 249 "@ 250 ; lshrsi %0, 0 251 252 movw ax,%H1 \; shrw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a 253 movw ax,%H1 \; shrw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a 254 255 movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax 256 movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax 257 movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax 258 259 mov x,%Q1 \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; shrw ax,8 \; movw %H0,ax 260 mov a,%Q1 \; mov x, a \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; shrw ax,8 \; movw %H0,ax 261 262 mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax 263 mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax 264 mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax 265 266 movw ax,%H1 \; movw %0,ax \; movw ax,#0 \; movw %H0,ax 267 268 movw ax,%H1 \; shrw ax,%S2 \; movw %0,ax \; movw ax,#0 \; movw %H0,ax 269 movw ax,%H1 \; shrw ax,%S2 \; movw %0,ax \; movw ax,#0 \; movw %H0,ax 270 271 movw ax,%H1 \; mov %0,a \; movw ax,#0 \; movw %H0,ax \; mov %Q0,a 272 273 movw ax,%H1 \; shr a,%s2 \; mov %0,a \; movw ax,#0 \; movw %H0,ax \; mov %Q0,a 274 275 mov b,%2 \; cmp0 b \; bz $2f \; 1: \; movw ax,%H1 \; shrw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a \; dec b \; bnz $1b \; 2:" 276 [(set_attr "valloc" "macax")] 277 ) 278 279 ;; Likewise. 280 (define_insn "ashlsi3_virt" ;; 0 1 2-7 8 9-15 16 17-23 24 25-31 var 281 [(set (match_operand:SI 0 "nonimmediate_operand" "=v,vU,&vU,v, &vU, &vU, v, &vU, v, &vU, &vU, v, U, v,&vU, v, U, v, U, vWab,vU, vU") 282 (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0, 0, vU,0, vWab, U, 0, vU, 0, vWab,U, vU, vU, 0, vU, vU, vU, vU, vU, 0, vWab,U") 283 (match_operand:SI 2 "nonmemory_operand" "M, K, K, Int3,Int3,Int3,Iv08,Iv08,Is09,Is09,Is09,Iv16,Iv16,Is17,Is17,Iv24,Iv24,Is25,Is25,iv, iv, iv"))) 284 (clobber (reg:HI X_REG)) 285 ] 286 "" 287 "@ 288 ; lshrsi %0, 0 289 290 movw ax,%1 \; shlw ax,1 \; movw %0,ax \; movw ax,%H1 \; rolwc ax,1 \; movw %H0,ax 291 movw ax,%1 \; shlw ax,1 \; movw %0,ax \; movw ax,%H1 \; rolwc ax,1 \; movw %H0,ax 292 293 movw ax,%H1 \; shlw ax,%u2 \; mov %E0,a \; mov x,%Q1 \; mov a, %H1 \; shlw ax,%S2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax 294 movw ax,%H1 \; shlw ax,%u2 \; mov %E0,a \; mov x,%Q1 \; mov a, %H1 \; shlw ax,%S2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax 295 movw ax,%H1 \; shlw ax,%u2 \; mov %E0,a \; mov a,%Q1 \; mov x,a \; mov a, %H1 \; shlw ax,%S2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax 296 297 mov x,%Q1 \; mov a,%H1 \; movw %H0,ax \; movw ax,%1 \; shlw ax,8 \; movw %0,ax 298 mov a,%Q1 \; mov x,a \; mov a,%H1 \; movw %H0,ax \; movw ax,%1 \; shlw ax,8 \; movw %0,ax 299 300 mov x,%Q1 \; mov a,%H1 \; shlw ax,%s2 \; movw %H0,ax \; movw ax,%1 \; shlw ax,%s2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax 301 mov x,%Q1 \; mov a,%H1 \; shlw ax,%s2 \; movw %H0,ax \; movw ax,%1 \; shlw ax,%s2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax 302 mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%s2 \; movw %H0,ax \; movw ax,%1 \; shlw ax,%s2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax 303 304 movw ax,%1 \; movw %H0,ax \; movw %0,#0 305 movw ax,%1 \; movw %H0,ax \; movw ax,#0 \; movw %0,ax 306 307 movw ax,%1 \; shlw ax,%S2 \; movw %H0,ax \; movw %0,#0 308 movw ax,%1 \; shlw ax,%S2 \; movw %H0,ax \; movw ax,#0 \; movw %0,ax 309 310 mov a,%1 \; movw %H0,ax \; mov %H0,#0 \; movw %0,#0 311 mov a,%1 \; movw %H0,ax \; movw ax,#0 \; mov %H0,a \; movW %0,ax 312 313 mov a,%1 \; shl a,%s2 \; movw %H0,ax \; mov %H0,#0 \; movw %0,#0 314 mov a,%1 \; shl a,%s2 \; movw %H0,ax \; movw ax,#0 \; mov %H0,a \; movW %0,ax 315 316 mov a,%2 \; cmp0 a \; bz $2f \; mov d,a \; movw ax,%H1 \; movw bc,%1 \; 1: \; shlw bc,1 \; rolwc ax,1 \; dec d \; bnz $1b \; movw %H0,ax \; movw ax,bc \; movw %0,ax \; 2: 317 mov a,%2 \; mov d,a \; movw ax,%H1 \; movw bc,%1 \; cmp0 0xFFEFD \; bz $2f \; 1: \; shlw bc,1 \; rolwc ax,1 \; dec d \; bnz $1b \; 2: \; movw %H0,ax \; movw ax,bc \; movw %0,ax 318 mov a,%2 \; mov d,a \; movw ax,%1 \; movw bc,ax \; movw ax,%H1 \; cmp0 0xFFEFD \; bz $2f \; 1: \; shlw bc,1 \; rolwc ax,1 \; dec d \; bnz $1b \; 2: \; movw %H0,ax \; movw ax,bc \; movw %0,ax" 319 [(set_attr "valloc" "macax")] 320 ) 321 322 ;;---------- Branching ------------------------ 323 324 (define_insn "*indirect_jump_virt" 325 [(set (pc) 326 (match_operand:HI 0 "nonimmediate_operand" "vm"))] 327 "rl78_virt_insns_ok ()" 328 "v.br\t%0" 329 [(set_attr "valloc" "ro1")] 330 ) 331 332 (define_insn "*call_virt" 333 [(call (match_operand:HI 0 "memory_operand" "Wab,Wcv") 334 (match_operand 1 "" ""))] 335 "rl78_virt_insns_ok ()" 336 "v.call\t%0" 337 [(set_attr "valloc" "ro1")] 338 ) 339 340 (define_insn "*call_value_virt" 341 [(set (match_operand 0 "register_operand" "=v,v") 342 (call (match_operand:HI 1 "memory_operand" "Wab,Wcv") 343 (match_operand 2 "" "")))] 344 "rl78_virt_insns_ok ()" 345 "v.call\t%1" 346 [(set_attr "valloc" "op1")] 347 ) 348 349 (define_insn "*cbranchqi4_virt_signed" 350 [(set (pc) (if_then_else 351 (match_operator 0 "rl78_cmp_operator_signed" 352 [(match_operand:QI 1 "general_operand" "vim") 353 (match_operand:QI 2 "nonmemory_operand" "vi")]) 354 (label_ref (match_operand 3 "" "")) 355 (pc)))] 356 "rl78_virt_insns_ok ()" 357 "v.cmp\t%1, %2\\n\tv.b%C0\t%3" 358 [(set_attr "valloc" "cmp")] 359 ) 360 361 (define_insn "*cbranchqi4_virt" 362 [(set (pc) (if_then_else 363 (match_operator 0 "rl78_cmp_operator_real" 364 [(match_operand:QI 1 "rl78_general_operand" "vim") 365 (match_operand:QI 2 "rl78_general_operand" "vim")]) 366 (label_ref (match_operand 3 "" "")) 367 (pc)))] 368 "rl78_virt_insns_ok ()" 369 "v.cmp\t%1, %2\\n\tv.b%C0\t%3" 370 [(set_attr "valloc" "cmp")] 371 ) 372 373 (define_insn "*cbranchhi4_virt_signed" 374 [(set (pc) (if_then_else 375 (match_operator 0 "rl78_cmp_operator_signed" 376 [(match_operand:HI 1 "general_operand" "vim") 377 (match_operand:HI 2 "nonmemory_operand" "vi")]) 378 (label_ref (match_operand 3 "" "")) 379 (pc)))] 380 "rl78_virt_insns_ok ()" 381 "v.cmpw\t%1, %2\\n\tv.b%C0\t%3" 382 [(set_attr "valloc" "cmp")] 383 ) 384 385 (define_insn "*cbranchhi4_virt" 386 [(set (pc) (if_then_else 387 (match_operator 0 "rl78_cmp_operator_real" 388 [(match_operand:HI 1 "rl78_general_operand" "vim") 389 (match_operand:HI 2 "rl78_general_operand" "vim")]) 390 (label_ref (match_operand 3 "" "")) 391 (pc)))] 392 "rl78_virt_insns_ok ()" 393 "v.cmpw\t%1, %2\\n\tv.b%C0\t%3" 394 [(set_attr "valloc" "cmp")] 395 ) 396 397 (define_insn "*cbranchsi4_virt" 398 [(set (pc) (if_then_else 399 (match_operator 0 "rl78_cmp_operator" 400 [(match_operand:SI 1 "general_operand" "vim") 401 (match_operand:SI 2 "nonmemory_operand" "vi")]) 402 (label_ref (match_operand 3 "" "")) 403 (pc))) 404 (clobber (reg:HI AX_REG)) 405 ] 406 "rl78_virt_insns_ok ()" 407 "v.cmpd\t%1, %2\\n\tv.b%C0\t%3" 408 [(set_attr "valloc" "macax")] 409 ) 410 411 ;;---------- Peepholes ------------------------ 412 413 (define_peephole2 414 [(set (match_operand:QI 0 "" "") 415 (match_operand:QI 1 "" "")) 416 (set (match_operand:QI 2 "" "") 417 (match_operand:QI 3 "" ""))] 418 "rl78_peep_movhi_p (operands)" 419 [(set (match_dup 4) 420 (match_dup 5))] 421 "rl78_setup_peep_movhi (operands);" 422 ) 423 424 (define_peephole2 425 [(set (reg:QI A_REG) 426 (match_operand:QI 1 "" "")) 427 (set (match_operand:QI 0 "" "") 428 (reg:QI A_REG)) 429 (set (reg:QI A_REG) 430 (match_operand:QI 3 "" "")) 431 (set (match_operand:QI 2 "" "") 432 (reg:QI A_REG)) 433 ] 434 "rl78_peep_movhi_p (operands)" 435 [(set (reg:HI AX_REG) 436 (match_dup 5)) 437 (set (match_dup 4) 438 (reg:HI AX_REG)) 439 ] 440 "rl78_setup_peep_movhi (operands);" 441 ) 442 443 (define_insn "*negandhi3_virt" 444 [(set (match_operand:HI 0 "register_operand" "=v") 445 (and:HI (neg:HI (match_operand:HI 1 "register_operand" "0")) 446 (match_operand:HI 2 "immediate_operand" "n"))) 447 ] 448 "rl78_virt_insns_ok ()" 449 "v.nand\t%0, %1, %2" 450 ) 451
Indexes created Wed Sep 09 00:24:13 UTC 2026