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rl78-virt.md revision 1.4 
      1 ;;  Machine Description for Renesas RL78 processors
      2 ;;  Copyright (C) 2011-2015 Free Software Foundation, Inc.
      3 ;;  Contributed by Red Hat.
      4 
      5 ;; This file is part of GCC.
      6 
      7 ;; GCC is free software; you can redistribute it and/or modify
      8 ;; it under the terms of the GNU General Public License as published by
      9 ;; the Free Software Foundation; either version 3, or (at your option)
     10 ;; any later version.
     11 
     12 ;; GCC is distributed in the hope that it will be useful,
     13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15 ;; GNU General Public License for more details.
     16 
     17 ;; You should have received a copy of the GNU General Public License
     18 ;; along with GCC; see the file COPYING3.  If not see
     19 ;; <http://www.gnu.org/licenses/>.
     20 
     22 ;; In this MD file, we define those insn patterns that involve
     23 ;; registers, where such registers are virtual until allocated to a
     24 ;; physical register.  All of these insns need to be conditional on
     25 ;; rl78_virt_insns_ok () being true.
     26 
     27 ;; This tells the physical register allocator what method to use to
     28 ;; allocate registers.  Basically, this defines the template of the
     29 ;; instruction - op1 is of the form "a = op(b)", op2 is "a = b op c"
     30 ;; etc.
     31 
     32 (define_attr "valloc" "op1,op2,ro1,cmp,umul,macax"
     33   (const_string "op2"))
     34 
     35 ;;---------- Moving ------------------------
     36 
     37 (define_insn "*movqi_virt_mm"
     38   [(set (match_operand:QI 0 "rl78_near_mem_operand" "=Y")
     39 	(match_operand    1 "rl78_near_mem_operand" "Y"))]
     40   "rl78_virt_insns_ok ()"
     41   "v.mov %0, %1"
     42   [(set_attr "valloc" "op1")]
     43 )
     44 
     45 (define_insn "*movqi_virt"
     46   [(set (match_operand:QI 0 "nonimmediate_operand" "=vY,v,Wfr")
     47 	(match_operand    1 "general_operand" "vInt8J,YWfr,vInt8J"))]
     48   "rl78_virt_insns_ok ()"
     49   "v.mov %0, %1"
     50   [(set_attr "valloc" "op1")]
     51 )
     52 
     53 (define_insn "*movhi_virt_mm"
     54   [(set (match_operand:HI 0 "rl78_near_mem_operand" "=Y")
     55 	(match_operand:HI 1 "rl78_near_mem_operand" "Y"))]
     56   "rl78_virt_insns_ok ()"
     57   "v.movw %0, %1"
     58   [(set_attr "valloc" "op1")]
     59 )
     60 
     61 (define_insn "*movhi_virt"
     62   [(set (match_operand:HI 0 "nonimmediate_operand" "=vS,  Y,   v,   Wfr")
     63 	(match_operand:HI 1 "general_operand"      "viYS, viS, Wfr, vi"))]
     64   "rl78_virt_insns_ok ()"
     65   "v.movw %0, %1"
     66   [(set_attr "valloc" "op1")]
     67 )
     68 
     69 ;;---------- Conversions ------------------------
     70 
     71 (define_insn "*zero_extendqihi2_virt"
     72   [(set (match_operand:HI                 0 "rl78_nonfar_nonimm_operand" "=vm")
     73 	(zero_extend:HI (match_operand:QI 1 "general_operand" "vim")))]
     74   "rl78_virt_insns_ok ()"
     75   "v.zero_extend\t%0, %1"
     76   [(set_attr "valloc" "op1")]
     77   )
     78 
     79 (define_insn "*extendqihi2_virt"
     80   [(set (match_operand:HI                 0 "rl78_nonfar_nonimm_operand" "=vm")
     81 	(sign_extend:HI (match_operand:QI 1 "general_operand" "vim")))]
     82   "rl78_virt_insns_ok ()"
     83   "v.sign_extend\t%0, %1"
     84   [(set_attr "valloc" "op1")]
     85   )
     86 
     87 ;;---------- Arithmetic ------------------------
     88 
     89 (define_insn "*inc<mode>3_virt"
     90   [(set (match_operand:QHI           0 "rl78_incdec_memory_operand" "=vm")
     91 	(plus:QHI (match_operand:QHI 1 "rl78_incdec_memory_operand" "0")
     92 		  (match_operand:QHI 2 "rl78_1_2_operand" "KLNO")))
     93    ]
     94   "rl78_virt_insns_ok ()"
     95   "v.inc\t%0, %1, %2"
     96 )
     97 
     98 (define_insn "*add<mode>3_virt"
     99   [(set (match_operand:QHI           0 "rl78_nonfar_nonimm_operand" "=vY,S")
    100 	(plus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "viY,0")
    101 		  (match_operand:QHI 2 "rl78_general_operand" "vim,i")))
    102    ]
    103   "rl78_virt_insns_ok ()"
    104   "v.add\t%0, %1, %2"
    105 )
    106 
    107 (define_insn "*sub<mode>3_virt"
    108   [(set (match_operand:QHI            0 "rl78_nonfar_nonimm_operand" "=vm,S")
    109 	(minus:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim,0")
    110 		   (match_operand:QHI 2 "rl78_general_operand" "vim,i")))
    111    ]
    112   "rl78_virt_insns_ok ()"
    113   "v.sub\t%0, %1, %2"
    114 )
    115 
    116 (define_insn "*umulhi3_shift_virt"
    117   [(set (match_operand:HI 0 "register_operand" "=vm")
    118         (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "%vim")
    119                  (match_operand:HI 2 "rl78_24_operand" "Ni")))]
    120   "rl78_virt_insns_ok ()"
    121   "v.mulu\t%0, %1, %2"
    122   [(set_attr "valloc" "umul")]
    123 )
    124 
    125 (define_insn "*umulqihi3_virt"
    126   [(set (match_operand:HI 0 "register_operand" "=vm")
    127         (mult:HI (zero_extend:HI (match_operand:QI 1 "rl78_nonfar_operand" "%vim"))
    128                  (zero_extend:HI (match_operand:QI 2 "general_operand" "vim"))))]
    129   "rl78_virt_insns_ok ()"
    130   "v.mulu\t%0, %2"
    131   [(set_attr "valloc" "umul")]
    132 )
    133 
    134 (define_insn "*andqi3_virt"
    135   [(set (match_operand:QI         0 "rl78_nonimmediate_operand" "=vm")
    136 	(and:QI (match_operand:QI 1 "rl78_general_operand" "vim")
    137 		(match_operand:QI 2 "rl78_general_operand" "vim")))
    138    ]
    139   "rl78_virt_insns_ok ()"
    140   "v.and\t%0, %1, %2"
    141 )
    142 
    143 (define_insn "*iorqi3_virt"
    144   [(set (match_operand:QI         0 "rl78_nonimmediate_operand" "=vm")
    145 	(ior:QI (match_operand:QI 1 "rl78_general_operand" "vim")
    146 		(match_operand:QI 2 "rl78_general_operand" "vim")))
    147    ]
    148   "rl78_virt_insns_ok ()"
    149   "v.or\t%0, %1, %2"
    150 )
    151 
    152 (define_insn "*xorqi3_virt"
    153   [(set (match_operand:QI         0 "rl78_nonfar_nonimm_operand" "=v,vm,m")
    154 	(xor:QI (match_operand:QI 1 "rl78_nonfar_operand" "%0,vm,vm")
    155 		(match_operand    2 "rl78_general_operand" "i,vm,vim")))
    156    ]
    157   "rl78_virt_insns_ok ()"
    158   "v.xor\t%0, %1, %2"
    159 )
    160 
    161 ;;---------- Shifts ------------------------
    162 
    163 (define_insn "*ashl<mode>3_virt"
    164   [(set (match_operand:QHI             0 "rl78_nonfar_nonimm_operand" "=vm")
    165 	(ashift:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
    166 		    (match_operand:QI  2 "general_operand" "vim")))
    167    ]
    168   "rl78_virt_insns_ok ()"
    169   "v.shl\t%0, %1, %2"
    170 )
    171 
    172 (define_insn "*ashr<mode>3_virt"
    173   [(set (match_operand:QHI               0 "rl78_nonfar_nonimm_operand" "=vm")
    174 	(ashiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
    175 		      (match_operand:QI  2 "general_operand" "vim")))
    176    ]
    177   "rl78_virt_insns_ok ()"
    178   "v.sar\t%0, %1, %2"
    179 )
    180 
    181 (define_insn "*lshr<mode>3_virt"
    182   [(set (match_operand:QHI               0 "rl78_nonfar_nonimm_operand" "=vm")
    183 	(lshiftrt:QHI (match_operand:QHI 1 "rl78_nonfar_operand" "vim")
    184 		      (match_operand:QI  2 "general_operand" "vim")))
    185    ]
    186   "rl78_virt_insns_ok ()"
    187   "v.shr\t%0, %1, %2"
    188 )
    189 
    190 ;; This is complex mostly because the RL78 has no SImode operations,
    191 ;; and very limited HImode operations, and no variable shifts.  This
    192 ;; pattern is optimized for each constant shift count and operand
    193 ;; types, so as to use a hand-optimized pattern.  For readability, the
    194 ;; usual \t\; syntax is not used here.  Also, there's no easy way to 
    195 ;; constrain to avoid partial overlaps, hence the duplication.
    196 (define_insn "ashrsi3_virt"                                  ;;   0  1      2-7            8         9-15           16   17-23     24   25-31 var
    197   [(set (match_operand:SI               0 "nonimmediate_operand" "=v,vU,&vU,v,  &vU,  &vU, v,  &vU,  v,  &vU, &vU,  vU,  v,&vU,    vU,  vU,   vU")
    198 	(ashiftrt:SI (match_operand:SI  1 "nonimmediate_operand" "0, 0,  vU,0,   vWab, U,  0,   vU,  0,   vWab,U,   vU,  0, vU,    vU,  vU,   0")
    199 		      (match_operand:SI 2 "nonmemory_operand"    "M, K,  K, Int3,Int3,Int3,Iv08,Iv08,Is09,Is09,Is09,Iv16,Is17,Is17,Iv24,Is25, iv")))
    200    (clobber (reg:HI X_REG))
    201     ]
    202    ""
    203    "@
    204     ; ashrsi %0, 0
    205 
    206    movw ax,%H1 \; sarw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a
    207    movw ax,%H1 \; sarw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a
    208 
    209    movw ax,%1 \; shlw ax,%r2 \; mov %0,a             \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax
    210    movw ax,%1 \; shlw ax,%r2 \; mov %0,a             \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax
    211    movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov a,%Q1 \; mov x,a   \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax
    212 
    213    mov x,%Q1            \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; sarw ax,8 \; movw %H0,ax
    214    mov a,%Q1 \; mov x, a \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; sarw ax,8 \; movw %H0,ax
    215 
    216    mov x,%Q1           \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax
    217    mov x,%Q1           \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax
    218    mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; sarw ax,%u2 \; movw %H0,ax
    219 
    220    movw ax,%H1 \; movw %0,ax \; sarw ax,15 \; movw %H0,ax
    221 
    222    movw ax,%H1 \; sarw ax,%S2 \; movw %0,ax \; sarw ax,15 \; movw %H0,ax
    223    movw ax,%H1 \; sarw ax,%S2 \; movw %0,ax \; sarw ax,15 \; movw %H0,ax
    224 
    225    movw ax,%H1 \; mov %0,a \; sarw ax,15 \; movw %H0,ax \; mov %Q0,a
    226 
    227    movw ax,%H1 \; sar a,%s2 \; mov %0,a \; sarw ax,15 \; movw %H0,ax \; mov %Q0,a
    228 
    229    mov b,%2 \; cmp0 b \; bz $2f \; 1: \; movw ax,%H1 \; sarw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a \; dec b \; bnz $1b \; 2:"
    230   [(set_attr "valloc" "macax")]
    231 )
    232 
    233 ;; Likewise.
    234 (define_insn "lshrsi3_virt"                                  ;;   0  1      2-7            8         9-15           16   17-23     24   25-31 var
    235   [(set (match_operand:SI               0 "nonimmediate_operand" "=v,vU,&vU,v,  &vU,  &vU, v,  &vU,  v,  &vU, &vU,  vU,  v,&vU,    vU,  vU,   vU")
    236 	(lshiftrt:SI (match_operand:SI  1 "nonimmediate_operand" "0, 0,  vU,0,   vWab, U,  0,   vU,  0,   vWab,U,   vU,  0, vU,    vU,  vU,   0")
    237 		      (match_operand:SI 2 "nonmemory_operand"    "M, K,  K, Int3,Int3,Int3,Iv08,Iv08,Is09,Is09,Is09,Iv16,Is17,Is17,Iv24,Is25, iv")))
    238    (clobber (reg:HI X_REG))
    239    ]
    240   ""
    241   "@
    242    ; lshrsi %0, 0
    243 
    244    movw ax,%H1 \; shrw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a
    245    movw ax,%H1 \; shrw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a
    246 
    247    movw ax,%1 \; shlw ax,%r2 \; mov %0,a             \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax
    248    movw ax,%1 \; shlw ax,%r2 \; mov %0,a             \; mov x,%Q1 \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax
    249    movw ax,%1 \; shlw ax,%r2 \; mov %0,a \; mov a,%Q1 \; mov x,a   \; mov a,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax
    250 
    251    mov x,%Q1            \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; shrw ax,8 \; movw %H0,ax
    252    mov a,%Q1 \; mov x, a \; mov a,%H1 \; movw %0,ax \; movw ax,%H1 \; shrw ax,8 \; movw %H0,ax
    253 
    254    mov x,%Q1           \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax
    255    mov x,%Q1           \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax
    256    mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%r2 \; mov %0,a \; movw ax,%H1 \; shlw ax,%r2 \; mov %Q0,a \; movw ax,%H1 \; shrw ax,%u2 \; movw %H0,ax
    257 
    258    movw ax,%H1 \; movw %0,ax \; movw ax,#0 \; movw %H0,ax
    259 
    260    movw ax,%H1 \; shrw ax,%S2 \; movw %0,ax \; movw ax,#0 \; movw %H0,ax
    261    movw ax,%H1 \; shrw ax,%S2 \; movw %0,ax \; movw ax,#0 \; movw %H0,ax
    262 
    263    movw ax,%H1 \; mov %0,a \; movw ax,#0 \; movw %H0,ax \; mov %Q0,a
    264 
    265    movw ax,%H1 \; shr a,%s2 \; mov %0,a \; movw ax,#0 \; movw %H0,ax \; mov %Q0,a
    266 
    267    mov b,%2 \; cmp0 b \; bz $2f \; 1: \; movw ax,%H1 \; shrw ax,1 \; movw %H0,ax \; mov a,%Q1 \; rorc a,1 \; mov %Q0,a \; mov a,%q1 \; rorc a,1 \; mov %q0,a \; dec b \; bnz $1b \; 2:"
    268   [(set_attr "valloc" "macax")]
    269 )
    270 
    271 ;; Likewise.
    272 (define_insn "ashlsi3_virt"                                ;;   0  1      2-7            8         9-15           16        17-23     24        25-31     var
    273   [(set (match_operand:SI             0 "nonimmediate_operand" "=v,vU,&vU,v,  &vU,  &vU, v,  &vU,  v,  &vU, &vU,  v,   U,   v,&vU,    v,   U,   v,   U,   vWab,vU,  vU")
    274 	(ashift:SI (match_operand:SI  1 "nonimmediate_operand" "0, 0,  vU,0,   vWab, U,  0,   vU,  0,   vWab,U,   vU,  vU,  0, vU,    vU,  vU,  vU,  vU,  0,   vWab,U")
    275 		    (match_operand:SI 2 "nonmemory_operand"    "M, K,  K, Int3,Int3,Int3,Iv08,Iv08,Is09,Is09,Is09,Iv16,Iv16,Is17,Is17,Iv24,Iv24,Is25,Is25,iv,  iv,  iv")))
    276    (clobber (reg:HI X_REG))
    277    ]
    278   ""
    279   "@
    280    ; lshrsi %0, 0
    281 
    282    movw ax,%1 \; shlw ax,1 \; movw %0,ax \; movw ax,%H1 \; rolwc ax,1 \; movw %H0,ax
    283    movw ax,%1 \; shlw ax,1 \; movw %0,ax \; movw ax,%H1 \; rolwc ax,1 \; movw %H0,ax
    284 
    285    movw ax,%H1 \; shlw ax,%u2 \; mov %E0,a \; mov x,%Q1           \; mov a, %H1 \; shlw ax,%S2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax
    286    movw ax,%H1 \; shlw ax,%u2 \; mov %E0,a \; mov x,%Q1           \; mov a, %H1 \; shlw ax,%S2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax
    287    movw ax,%H1 \; shlw ax,%u2 \; mov %E0,a \; mov a,%Q1 \; mov x,a \; mov a, %H1 \; shlw ax,%S2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax
    288 
    289    mov x,%Q1           \; mov a,%H1 \; movw %H0,ax \; movw ax,%1 \; shlw ax,8 \; movw %0,ax
    290    mov a,%Q1 \; mov x,a \; mov a,%H1 \; movw %H0,ax \; movw ax,%1 \; shlw ax,8 \; movw %0,ax
    291 
    292    mov x,%Q1           \; mov a,%H1 \; shlw ax,%s2 \; movw %H0,ax \; movw ax,%1 \; shlw ax,%s2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax
    293    mov x,%Q1           \; mov a,%H1 \; shlw ax,%s2 \; movw %H0,ax \; movw ax,%1 \; shlw ax,%s2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax
    294    mov a,%Q1 \; mov x,a \; mov a,%H1 \; shlw ax,%s2 \; movw %H0,ax \; movw ax,%1 \; shlw ax,%s2 \; mov %H0,a \; movw ax,%1 \; shlw ax,%u2 \; movw %0,ax
    295 
    296    movw ax,%1 \; movw %H0,ax \; movw %0,#0
    297    movw ax,%1 \; movw %H0,ax \; movw ax,#0 \; movw %0,ax
    298 
    299    movw ax,%1 \; shlw ax,%S2 \; movw %H0,ax \; movw %0,#0
    300    movw ax,%1 \; shlw ax,%S2 \; movw %H0,ax \; movw ax,#0 \; movw %0,ax
    301 
    302    mov a,%1 \; movw %H0,ax \; mov %H0,#0 \; movw %0,#0
    303    mov a,%1 \; movw %H0,ax \; movw ax,#0 \; mov %H0,a \; movW %0,ax
    304 
    305    mov a,%1 \; shl a,%s2 \; movw %H0,ax \; mov %H0,#0 \; movw %0,#0
    306    mov a,%1 \; shl a,%s2 \; movw %H0,ax \; movw ax,#0 \; mov %H0,a \; movW %0,ax
    307 
    308    mov a,%2 \; cmp0 a \; bz $2f \; mov d,a \; movw ax,%H1 \; movw bc,%1 \; 1: \; shlw bc,1 \; rolwc ax,1 \; dec d \; bnz $1b \; movw %H0,ax \; movw ax,bc \; movw %0,ax \; 2:
    309    mov a,%2 \; mov d,a \; movw ax,%H1 \; movw bc,%1 \; cmp0 0xFFEFD \; bz $2f \; 1: \; shlw bc,1 \; rolwc ax,1 \; dec d \; bnz $1b \; 2: \; movw %H0,ax \; movw ax,bc \; movw %0,ax
    310    mov a,%2 \; mov d,a \; movw ax,%1 \; movw bc,ax \; movw ax,%H1 \; cmp0 0xFFEFD \; bz $2f \; 1: \; shlw bc,1 \; rolwc ax,1 \; dec d \; bnz $1b \; 2: \; movw %H0,ax \; movw ax,bc \; movw %0,ax"
    311    [(set_attr "valloc" "macax")]
    312  )
    313 
    314 ;;---------- Branching ------------------------
    315 
    316 (define_insn "*indirect_jump_virt"
    317   [(set (pc)
    318 	(match_operand:HI 0 "nonimmediate_operand" "vm"))]
    319   "rl78_virt_insns_ok ()"
    320   "v.br\t%0"
    321   [(set_attr "valloc" "ro1")]
    322 )
    323 
    324 (define_insn "*call_virt"
    325   [(call (match_operand:HI 0 "memory_operand" "Wab,Wcv")
    326 	 (match_operand 1 "" ""))]
    327   "rl78_virt_insns_ok ()"
    328   "v.call\t%0"
    329   [(set_attr "valloc" "ro1")]
    330   )
    331 
    332 (define_insn "*call_value_virt"
    333   [(set (match_operand 0 "register_operand" "=v,v")
    334 	(call (match_operand:HI 1 "memory_operand" "Wab,Wcv")
    335 	      (match_operand 2 "" "")))]
    336   "rl78_virt_insns_ok ()"
    337   "v.call\t%1"
    338   [(set_attr "valloc" "op1")]
    339   )
    340 
    341 (define_insn "*cbranchqi4_virt_signed"
    342   [(set (pc) (if_then_else
    343 	      (match_operator 0 "rl78_cmp_operator_signed"
    344 			      [(match_operand:QI 1 "general_operand" "vim")
    345 			       (match_operand:QI 2 "nonmemory_operand" "vi")])
    346               (label_ref (match_operand 3 "" ""))
    347 	      (pc)))]
    348   "rl78_virt_insns_ok ()"
    349   "v.cmp\t%1, %2\\n\tv.b%C0\t%3"
    350   [(set_attr "valloc" "cmp")]
    351   )
    352 
    353 (define_insn "*cbranchqi4_virt"
    354   [(set (pc) (if_then_else
    355 	      (match_operator 0 "rl78_cmp_operator_real"
    356 			      [(match_operand:QI 1 "rl78_general_operand" "vim")
    357 			       (match_operand:QI 2 "rl78_general_operand" "vim")])
    358               (label_ref (match_operand 3 "" ""))
    359 	      (pc)))]
    360   "rl78_virt_insns_ok ()"
    361   "v.cmp\t%1, %2\\n\tv.b%C0\t%3"
    362   [(set_attr "valloc" "cmp")]
    363   )
    364 
    365 (define_insn "*cbranchhi4_virt_signed"
    366   [(set (pc) (if_then_else
    367 	      (match_operator 0 "rl78_cmp_operator_signed"
    368 			      [(match_operand:HI 1 "general_operand" "vim")
    369 			       (match_operand:HI 2 "nonmemory_operand" "vi")])
    370               (label_ref (match_operand 3 "" ""))
    371 	      (pc)))]
    372   "rl78_virt_insns_ok ()"
    373   "v.cmpw\t%1, %2\\n\tv.b%C0\t%3"
    374   [(set_attr "valloc" "cmp")]
    375   )
    376 
    377 (define_insn "*cbranchhi4_virt"
    378   [(set (pc) (if_then_else
    379 	      (match_operator 0 "rl78_cmp_operator_real"
    380 			      [(match_operand:HI 1 "rl78_general_operand" "vim")
    381 			       (match_operand:HI 2 "rl78_general_operand" "vim")])
    382               (label_ref (match_operand 3 "" ""))
    383 	      (pc)))]
    384   "rl78_virt_insns_ok ()"
    385   "v.cmpw\t%1, %2\\n\tv.b%C0\t%3"
    386   [(set_attr "valloc" "cmp")]
    387   )
    388 
    389 (define_insn "*cbranchsi4_virt"
    390   [(set (pc) (if_then_else
    391 	      (match_operator 0 "rl78_cmp_operator"
    392 			      [(match_operand:SI 1 "general_operand" "vim")
    393 			       (match_operand:SI 2 "nonmemory_operand" "vi")])
    394               (label_ref (match_operand 3 "" ""))
    395 	      (pc)))
    396    (clobber (reg:HI AX_REG))
    397    ]
    398   "rl78_virt_insns_ok ()"
    399   "v.cmpd\t%1, %2\\n\tv.b%C0\t%3"
    400   [(set_attr "valloc" "macax")]
    401   )
    402 
    403 ;;---------- Peepholes ------------------------
    404 
    405 (define_peephole2
    406   [(set (match_operand:QI 0 "" "")
    407 	(match_operand:QI 1 "" ""))
    408    (set (match_operand:QI 2 "" "")
    409 	(match_operand:QI 3 "" ""))]
    410   "rl78_peep_movhi_p (operands)"
    411   [(set (match_dup 4)
    412 	(match_dup 5))]
    413   "rl78_setup_peep_movhi (operands);"
    414   )
    415 
    416 (define_peephole2
    417   [(set (reg:QI A_REG)
    418 	(match_operand:QI 1 "" ""))
    419    (set (match_operand:QI 0 "" "")
    420 	(reg:QI A_REG))
    421    (set (reg:QI A_REG)
    422 	(match_operand:QI 3 "" ""))
    423    (set (match_operand:QI 2 "" "")
    424 	(reg:QI A_REG))
    425    ]
    426   "rl78_peep_movhi_p (operands)"
    427   [(set (reg:HI AX_REG)
    428 	(match_dup 5))
    429    (set (match_dup 4)
    430 	(reg:HI AX_REG))
    431    ]
    432   "rl78_setup_peep_movhi (operands);"
    433   )
    434 
    435 (define_insn "*negandhi3_virt"
    436   [(set (match_operand:HI                 0 "register_operand" "=v")
    437 	(and:HI (neg:HI (match_operand:HI 1 "register_operand"  "0"))
    438  		(match_operand:HI         2 "immediate_operand" "n")))
    439    ]
    440   "rl78_virt_insns_ok ()"
    441   "v.nand\t%0, %1, %2"
    442 )
    443