1 1.1 mrg ;; Generated automatically by genfusion.pl 2 1.1 mrg 3 1.1 mrg ;; Copyright (C) 2020-2022 Free Software Foundation, Inc. 4 1.1 mrg ;; 5 1.1 mrg ;; This file is part of GCC. 6 1.1 mrg ;; 7 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ;; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ;; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ;; version. 11 1.1 mrg ;; 12 1.1 mrg ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ;; for more details. 16 1.1 mrg ;; 17 1.1 mrg ;; You should have received a copy of the GNU General Public License 18 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ;; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 22 1.1 mrg ;; load mode is DI result mode is clobber compare mode is CC extend is none 23 1.1 mrg (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" 24 1.1 mrg [(set (match_operand:CC 2 "cc_reg_operand" "=x") 25 1.1 mrg (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") 26 1.1 mrg (match_operand:DI 3 "const_m1_to_1_operand" "n"))) 27 1.1 mrg (clobber (match_scratch:DI 0 "=r"))] 28 1.1 mrg "(TARGET_P10_FUSION)" 29 1.1 mrg "ld%X1 %0,%1\;cmpdi %2,%0,%3" 30 1.1 mrg "&& reload_completed 31 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 32 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 33 1.1 mrg DImode, NON_PREFIXED_DS))" 34 1.1 mrg [(set (match_dup 0) (match_dup 1)) 35 1.1 mrg (set (match_dup 2) 36 1.1 mrg (compare:CC (match_dup 0) (match_dup 3)))] 37 1.1 mrg "" 38 1.1 mrg [(set_attr "type" "fused_load_cmpi") 39 1.1 mrg (set_attr "cost" "8") 40 1.1 mrg (set_attr "length" "8")]) 41 1.1 mrg 42 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 43 1.1 mrg ;; load mode is DI result mode is clobber compare mode is CCUNS extend is none 44 1.1 mrg (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" 45 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 46 1.1 mrg (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") 47 1.1 mrg (match_operand:DI 3 "const_0_to_1_operand" "n"))) 48 1.1 mrg (clobber (match_scratch:DI 0 "=r"))] 49 1.1 mrg "(TARGET_P10_FUSION)" 50 1.1 mrg "ld%X1 %0,%1\;cmpldi %2,%0,%3" 51 1.1 mrg "&& reload_completed 52 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 53 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 54 1.1 mrg DImode, NON_PREFIXED_DS))" 55 1.1 mrg [(set (match_dup 0) (match_dup 1)) 56 1.1 mrg (set (match_dup 2) 57 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 58 1.1 mrg "" 59 1.1 mrg [(set_attr "type" "fused_load_cmpi") 60 1.1 mrg (set_attr "cost" "8") 61 1.1 mrg (set_attr "length" "8")]) 62 1.1 mrg 63 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 64 1.1 mrg ;; load mode is DI result mode is DI compare mode is CC extend is none 65 1.1 mrg (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" 66 1.1 mrg [(set (match_operand:CC 2 "cc_reg_operand" "=x") 67 1.1 mrg (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") 68 1.1 mrg (match_operand:DI 3 "const_m1_to_1_operand" "n"))) 69 1.1 mrg (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] 70 1.1 mrg "(TARGET_P10_FUSION)" 71 1.1 mrg "ld%X1 %0,%1\;cmpdi %2,%0,%3" 72 1.1 mrg "&& reload_completed 73 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 74 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 75 1.1 mrg DImode, NON_PREFIXED_DS))" 76 1.1 mrg [(set (match_dup 0) (match_dup 1)) 77 1.1 mrg (set (match_dup 2) 78 1.1 mrg (compare:CC (match_dup 0) (match_dup 3)))] 79 1.1 mrg "" 80 1.1 mrg [(set_attr "type" "fused_load_cmpi") 81 1.1 mrg (set_attr "cost" "8") 82 1.1 mrg (set_attr "length" "8")]) 83 1.1 mrg 84 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 85 1.1 mrg ;; load mode is DI result mode is DI compare mode is CCUNS extend is none 86 1.1 mrg (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" 87 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 88 1.1 mrg (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") 89 1.1 mrg (match_operand:DI 3 "const_0_to_1_operand" "n"))) 90 1.1 mrg (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] 91 1.1 mrg "(TARGET_P10_FUSION)" 92 1.1 mrg "ld%X1 %0,%1\;cmpldi %2,%0,%3" 93 1.1 mrg "&& reload_completed 94 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 95 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 96 1.1 mrg DImode, NON_PREFIXED_DS))" 97 1.1 mrg [(set (match_dup 0) (match_dup 1)) 98 1.1 mrg (set (match_dup 2) 99 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 100 1.1 mrg "" 101 1.1 mrg [(set_attr "type" "fused_load_cmpi") 102 1.1 mrg (set_attr "cost" "8") 103 1.1 mrg (set_attr "length" "8")]) 104 1.1 mrg 105 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 106 1.1 mrg ;; load mode is SI result mode is clobber compare mode is CC extend is none 107 1.1 mrg (define_insn_and_split "*lwz_cmpwi_cr0_SI_clobber_CC_none" 108 1.1 mrg [(set (match_operand:CC 2 "cc_reg_operand" "=x") 109 1.1 mrg (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") 110 1.1 mrg (match_operand:SI 3 "const_m1_to_1_operand" "n"))) 111 1.1 mrg (clobber (match_scratch:SI 0 "=r"))] 112 1.1 mrg "(TARGET_P10_FUSION)" 113 1.1 mrg "lwz%X1 %0,%1\;cmpwi %2,%0,%3" 114 1.1 mrg "&& reload_completed 115 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 116 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 117 1.1 mrg SImode, NON_PREFIXED_D))" 118 1.1 mrg [(set (match_dup 0) (match_dup 1)) 119 1.1 mrg (set (match_dup 2) 120 1.1 mrg (compare:CC (match_dup 0) (match_dup 3)))] 121 1.1 mrg "" 122 1.1 mrg [(set_attr "type" "fused_load_cmpi") 123 1.1 mrg (set_attr "cost" "8") 124 1.1 mrg (set_attr "length" "8")]) 125 1.1 mrg 126 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 127 1.1 mrg ;; load mode is SI result mode is clobber compare mode is CCUNS extend is none 128 1.1 mrg (define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 129 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 130 1.1 mrg (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") 131 1.1 mrg (match_operand:SI 3 "const_0_to_1_operand" "n"))) 132 1.1 mrg (clobber (match_scratch:SI 0 "=r"))] 133 1.1 mrg "(TARGET_P10_FUSION)" 134 1.1 mrg "lwz%X1 %0,%1\;cmpldi %2,%0,%3" 135 1.1 mrg "&& reload_completed 136 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 137 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 138 1.1 mrg SImode, NON_PREFIXED_D))" 139 1.1 mrg [(set (match_dup 0) (match_dup 1)) 140 1.1 mrg (set (match_dup 2) 141 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 142 1.1 mrg "" 143 1.1 mrg [(set_attr "type" "fused_load_cmpi") 144 1.1 mrg (set_attr "cost" "8") 145 1.1 mrg (set_attr "length" "8")]) 146 1.1 mrg 147 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 148 1.1 mrg ;; load mode is SI result mode is SI compare mode is CC extend is none 149 1.1 mrg (define_insn_and_split "*lwz_cmpwi_cr0_SI_SI_CC_none" 150 1.1 mrg [(set (match_operand:CC 2 "cc_reg_operand" "=x") 151 1.1 mrg (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") 152 1.1 mrg (match_operand:SI 3 "const_m1_to_1_operand" "n"))) 153 1.1 mrg (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] 154 1.1 mrg "(TARGET_P10_FUSION)" 155 1.1 mrg "lwz%X1 %0,%1\;cmpwi %2,%0,%3" 156 1.1 mrg "&& reload_completed 157 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 158 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 159 1.1 mrg SImode, NON_PREFIXED_D))" 160 1.1 mrg [(set (match_dup 0) (match_dup 1)) 161 1.1 mrg (set (match_dup 2) 162 1.1 mrg (compare:CC (match_dup 0) (match_dup 3)))] 163 1.1 mrg "" 164 1.1 mrg [(set_attr "type" "fused_load_cmpi") 165 1.1 mrg (set_attr "cost" "8") 166 1.1 mrg (set_attr "length" "8")]) 167 1.1 mrg 168 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 169 1.1 mrg ;; load mode is SI result mode is SI compare mode is CCUNS extend is none 170 1.1 mrg (define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none" 171 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 172 1.1 mrg (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") 173 1.1 mrg (match_operand:SI 3 "const_0_to_1_operand" "n"))) 174 1.1 mrg (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] 175 1.1 mrg "(TARGET_P10_FUSION)" 176 1.1 mrg "lwz%X1 %0,%1\;cmpldi %2,%0,%3" 177 1.1 mrg "&& reload_completed 178 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 179 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 180 1.1 mrg SImode, NON_PREFIXED_D))" 181 1.1 mrg [(set (match_dup 0) (match_dup 1)) 182 1.1 mrg (set (match_dup 2) 183 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 184 1.1 mrg "" 185 1.1 mrg [(set_attr "type" "fused_load_cmpi") 186 1.1 mrg (set_attr "cost" "8") 187 1.1 mrg (set_attr "length" "8")]) 188 1.1 mrg 189 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 190 1.1 mrg ;; load mode is SI result mode is EXTSI compare mode is CC extend is sign 191 1.1 mrg (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 192 1.1 mrg [(set (match_operand:CC 2 "cc_reg_operand" "=x") 193 1.1 mrg (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ") 194 1.1 mrg (match_operand:SI 3 "const_m1_to_1_operand" "n"))) 195 1.1 mrg (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))] 196 1.1 mrg "(TARGET_P10_FUSION)" 197 1.1 mrg "lwa%X1 %0,%1\;cmpdi %2,%0,%3" 198 1.1 mrg "&& reload_completed 199 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 200 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 201 1.1 mrg SImode, NON_PREFIXED_DS))" 202 1.1 mrg [(set (match_dup 0) (sign_extend:EXTSI (match_dup 1))) 203 1.1 mrg (set (match_dup 2) 204 1.1 mrg (compare:CC (match_dup 0) (match_dup 3)))] 205 1.1 mrg "" 206 1.1 mrg [(set_attr "type" "fused_load_cmpi") 207 1.1 mrg (set_attr "cost" "8") 208 1.1 mrg (set_attr "sign_extend" "yes") 209 1.1 mrg (set_attr "length" "8")]) 210 1.1 mrg 211 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 212 1.1 mrg ;; load mode is SI result mode is EXTSI compare mode is CCUNS extend is zero 213 1.1 mrg (define_insn_and_split "*lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 214 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 215 1.1 mrg (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") 216 1.1 mrg (match_operand:SI 3 "const_0_to_1_operand" "n"))) 217 1.1 mrg (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (zero_extend:EXTSI (match_dup 1)))] 218 1.1 mrg "(TARGET_P10_FUSION)" 219 1.1 mrg "lwz%X1 %0,%1\;cmpldi %2,%0,%3" 220 1.1 mrg "&& reload_completed 221 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 222 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 223 1.1 mrg SImode, NON_PREFIXED_D))" 224 1.1 mrg [(set (match_dup 0) (zero_extend:EXTSI (match_dup 1))) 225 1.1 mrg (set (match_dup 2) 226 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 227 1.1 mrg "" 228 1.1 mrg [(set_attr "type" "fused_load_cmpi") 229 1.1 mrg (set_attr "cost" "8") 230 1.1 mrg (set_attr "length" "8")]) 231 1.1 mrg 232 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 233 1.1 mrg ;; load mode is HI result mode is clobber compare mode is CC extend is sign 234 1.1 mrg (define_insn_and_split "*lha_cmpdi_cr0_HI_clobber_CC_sign" 235 1.1 mrg [(set (match_operand:CC 2 "cc_reg_operand" "=x") 236 1.1 mrg (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") 237 1.1 mrg (match_operand:HI 3 "const_m1_to_1_operand" "n"))) 238 1.1 mrg (clobber (match_scratch:GPR 0 "=r"))] 239 1.1 mrg "(TARGET_P10_FUSION)" 240 1.1 mrg "lha%X1 %0,%1\;cmpdi %2,%0,%3" 241 1.1 mrg "&& reload_completed 242 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 243 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 244 1.1 mrg HImode, NON_PREFIXED_D))" 245 1.1 mrg [(set (match_dup 0) (sign_extend:GPR (match_dup 1))) 246 1.1 mrg (set (match_dup 2) 247 1.1 mrg (compare:CC (match_dup 0) (match_dup 3)))] 248 1.1 mrg "" 249 1.1 mrg [(set_attr "type" "fused_load_cmpi") 250 1.1 mrg (set_attr "cost" "8") 251 1.1 mrg (set_attr "length" "8")]) 252 1.1 mrg 253 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 254 1.1 mrg ;; load mode is HI result mode is clobber compare mode is CCUNS extend is zero 255 1.1 mrg (define_insn_and_split "*lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 256 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 257 1.1 mrg (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") 258 1.1 mrg (match_operand:HI 3 "const_0_to_1_operand" "n"))) 259 1.1 mrg (clobber (match_scratch:GPR 0 "=r"))] 260 1.1 mrg "(TARGET_P10_FUSION)" 261 1.1 mrg "lhz%X1 %0,%1\;cmpldi %2,%0,%3" 262 1.1 mrg "&& reload_completed 263 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 264 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 265 1.1 mrg HImode, NON_PREFIXED_D))" 266 1.1 mrg [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) 267 1.1 mrg (set (match_dup 2) 268 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 269 1.1 mrg "" 270 1.1 mrg [(set_attr "type" "fused_load_cmpi") 271 1.1 mrg (set_attr "cost" "8") 272 1.1 mrg (set_attr "length" "8")]) 273 1.1 mrg 274 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 275 1.1 mrg ;; load mode is HI result mode is EXTHI compare mode is CC extend is sign 276 1.1 mrg (define_insn_and_split "*lha_cmpdi_cr0_HI_EXTHI_CC_sign" 277 1.1 mrg [(set (match_operand:CC 2 "cc_reg_operand" "=x") 278 1.1 mrg (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") 279 1.1 mrg (match_operand:HI 3 "const_m1_to_1_operand" "n"))) 280 1.1 mrg (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (sign_extend:EXTHI (match_dup 1)))] 281 1.1 mrg "(TARGET_P10_FUSION)" 282 1.1 mrg "lha%X1 %0,%1\;cmpdi %2,%0,%3" 283 1.1 mrg "&& reload_completed 284 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 285 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 286 1.1 mrg HImode, NON_PREFIXED_D))" 287 1.1 mrg [(set (match_dup 0) (sign_extend:EXTHI (match_dup 1))) 288 1.1 mrg (set (match_dup 2) 289 1.1 mrg (compare:CC (match_dup 0) (match_dup 3)))] 290 1.1 mrg "" 291 1.1 mrg [(set_attr "type" "fused_load_cmpi") 292 1.1 mrg (set_attr "cost" "8") 293 1.1 mrg (set_attr "length" "8")]) 294 1.1 mrg 295 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 296 1.1 mrg ;; load mode is HI result mode is EXTHI compare mode is CCUNS extend is zero 297 1.1 mrg (define_insn_and_split "*lhz_cmpldi_cr0_HI_EXTHI_CCUNS_zero" 298 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 299 1.1 mrg (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") 300 1.1 mrg (match_operand:HI 3 "const_0_to_1_operand" "n"))) 301 1.1 mrg (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (zero_extend:EXTHI (match_dup 1)))] 302 1.1 mrg "(TARGET_P10_FUSION)" 303 1.1 mrg "lhz%X1 %0,%1\;cmpldi %2,%0,%3" 304 1.1 mrg "&& reload_completed 305 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 306 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 307 1.1 mrg HImode, NON_PREFIXED_D))" 308 1.1 mrg [(set (match_dup 0) (zero_extend:EXTHI (match_dup 1))) 309 1.1 mrg (set (match_dup 2) 310 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 311 1.1 mrg "" 312 1.1 mrg [(set_attr "type" "fused_load_cmpi") 313 1.1 mrg (set_attr "cost" "8") 314 1.1 mrg (set_attr "length" "8")]) 315 1.1 mrg 316 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 317 1.1 mrg ;; load mode is QI result mode is clobber compare mode is CCUNS extend is zero 318 1.1 mrg (define_insn_and_split "*lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" 319 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 320 1.1 mrg (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") 321 1.1 mrg (match_operand:QI 3 "const_0_to_1_operand" "n"))) 322 1.1 mrg (clobber (match_scratch:GPR 0 "=r"))] 323 1.1 mrg "(TARGET_P10_FUSION)" 324 1.1 mrg "lbz%X1 %0,%1\;cmpldi %2,%0,%3" 325 1.1 mrg "&& reload_completed 326 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 327 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 328 1.1 mrg QImode, NON_PREFIXED_D))" 329 1.1 mrg [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) 330 1.1 mrg (set (match_dup 2) 331 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 332 1.1 mrg "" 333 1.1 mrg [(set_attr "type" "fused_load_cmpi") 334 1.1 mrg (set_attr "cost" "8") 335 1.1 mrg (set_attr "length" "8")]) 336 1.1 mrg 337 1.1 mrg ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 338 1.1 mrg ;; load mode is QI result mode is GPR compare mode is CCUNS extend is zero 339 1.1 mrg (define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero" 340 1.1 mrg [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 341 1.1 mrg (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") 342 1.1 mrg (match_operand:QI 3 "const_0_to_1_operand" "n"))) 343 1.1 mrg (set (match_operand:GPR 0 "gpc_reg_operand" "=r") (zero_extend:GPR (match_dup 1)))] 344 1.1 mrg "(TARGET_P10_FUSION)" 345 1.1 mrg "lbz%X1 %0,%1\;cmpldi %2,%0,%3" 346 1.1 mrg "&& reload_completed 347 1.1 mrg && (cc_reg_not_cr0_operand (operands[2], CCmode) 348 1.1 mrg || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 349 1.1 mrg QImode, NON_PREFIXED_D))" 350 1.1 mrg [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) 351 1.1 mrg (set (match_dup 2) 352 1.1 mrg (compare:CCUNS (match_dup 0) (match_dup 3)))] 353 1.1 mrg "" 354 1.1 mrg [(set_attr "type" "fused_load_cmpi") 355 1.1 mrg (set_attr "cost" "8") 356 1.1 mrg (set_attr "length" "8")]) 357 1.1 mrg 358 1.1 mrg 359 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 360 1.1 mrg ;; scalar and -> and 361 1.1 mrg (define_insn "*fuse_and_and" 362 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 363 1.1 mrg (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 364 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 365 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 366 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 367 1.1 mrg "(TARGET_P10_FUSION)" 368 1.1 mrg "@ 369 1.1 mrg and %3,%1,%0\;and %3,%3,%2 370 1.1 mrg and %3,%1,%0\;and %3,%3,%2 371 1.1 mrg and %3,%1,%0\;and %3,%3,%2 372 1.1 mrg and %4,%1,%0\;and %3,%4,%2" 373 1.1 mrg [(set_attr "type" "fused_arith_logical") 374 1.1 mrg (set_attr "cost" "6") 375 1.1 mrg (set_attr "length" "8")]) 376 1.1 mrg 377 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 378 1.1 mrg ;; scalar andc -> and 379 1.1 mrg (define_insn "*fuse_andc_and" 380 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 381 1.1 mrg (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 382 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 383 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 384 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 385 1.1 mrg "(TARGET_P10_FUSION)" 386 1.1 mrg "@ 387 1.1 mrg andc %3,%1,%0\;and %3,%3,%2 388 1.1 mrg andc %3,%1,%0\;and %3,%3,%2 389 1.1 mrg andc %3,%1,%0\;and %3,%3,%2 390 1.1 mrg andc %4,%1,%0\;and %3,%4,%2" 391 1.1 mrg [(set_attr "type" "fused_arith_logical") 392 1.1 mrg (set_attr "cost" "6") 393 1.1 mrg (set_attr "length" "8")]) 394 1.1 mrg 395 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 396 1.1 mrg ;; scalar eqv -> and 397 1.1 mrg (define_insn "*fuse_eqv_and" 398 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 399 1.1 mrg (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 400 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 401 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 402 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 403 1.1 mrg "(TARGET_P10_FUSION)" 404 1.1 mrg "@ 405 1.1 mrg eqv %3,%1,%0\;and %3,%3,%2 406 1.1 mrg eqv %3,%1,%0\;and %3,%3,%2 407 1.1 mrg eqv %3,%1,%0\;and %3,%3,%2 408 1.1 mrg eqv %4,%1,%0\;and %3,%4,%2" 409 1.1 mrg [(set_attr "type" "fused_arith_logical") 410 1.1 mrg (set_attr "cost" "6") 411 1.1 mrg (set_attr "length" "8")]) 412 1.1 mrg 413 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 414 1.1 mrg ;; scalar nand -> and 415 1.1 mrg (define_insn "*fuse_nand_and" 416 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 417 1.1 mrg (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 418 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 419 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 420 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 421 1.1 mrg "(TARGET_P10_FUSION)" 422 1.1 mrg "@ 423 1.1 mrg nand %3,%1,%0\;and %3,%3,%2 424 1.1 mrg nand %3,%1,%0\;and %3,%3,%2 425 1.1 mrg nand %3,%1,%0\;and %3,%3,%2 426 1.1 mrg nand %4,%1,%0\;and %3,%4,%2" 427 1.1 mrg [(set_attr "type" "fused_arith_logical") 428 1.1 mrg (set_attr "cost" "6") 429 1.1 mrg (set_attr "length" "8")]) 430 1.1 mrg 431 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 432 1.1 mrg ;; scalar nor -> and 433 1.1 mrg (define_insn "*fuse_nor_and" 434 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 435 1.1 mrg (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 436 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 437 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 438 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 439 1.1 mrg "(TARGET_P10_FUSION)" 440 1.1 mrg "@ 441 1.1 mrg nor %3,%1,%0\;and %3,%3,%2 442 1.1 mrg nor %3,%1,%0\;and %3,%3,%2 443 1.1 mrg nor %3,%1,%0\;and %3,%3,%2 444 1.1 mrg nor %4,%1,%0\;and %3,%4,%2" 445 1.1 mrg [(set_attr "type" "fused_arith_logical") 446 1.1 mrg (set_attr "cost" "6") 447 1.1 mrg (set_attr "length" "8")]) 448 1.1 mrg 449 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 450 1.1 mrg ;; scalar or -> and 451 1.1 mrg (define_insn "*fuse_or_and" 452 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 453 1.1 mrg (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 454 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 455 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 456 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 457 1.1 mrg "(TARGET_P10_FUSION)" 458 1.1 mrg "@ 459 1.1 mrg or %3,%1,%0\;and %3,%3,%2 460 1.1 mrg or %3,%1,%0\;and %3,%3,%2 461 1.1 mrg or %3,%1,%0\;and %3,%3,%2 462 1.1 mrg or %4,%1,%0\;and %3,%4,%2" 463 1.1 mrg [(set_attr "type" "fused_arith_logical") 464 1.1 mrg (set_attr "cost" "6") 465 1.1 mrg (set_attr "length" "8")]) 466 1.1 mrg 467 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 468 1.1 mrg ;; scalar orc -> and 469 1.1 mrg (define_insn "*fuse_orc_and" 470 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 471 1.1 mrg (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 472 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 473 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 474 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 475 1.1 mrg "(TARGET_P10_FUSION)" 476 1.1 mrg "@ 477 1.1 mrg orc %3,%1,%0\;and %3,%3,%2 478 1.1 mrg orc %3,%1,%0\;and %3,%3,%2 479 1.1 mrg orc %3,%1,%0\;and %3,%3,%2 480 1.1 mrg orc %4,%1,%0\;and %3,%4,%2" 481 1.1 mrg [(set_attr "type" "fused_arith_logical") 482 1.1 mrg (set_attr "cost" "6") 483 1.1 mrg (set_attr "length" "8")]) 484 1.1 mrg 485 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 486 1.1 mrg ;; scalar xor -> and 487 1.1 mrg (define_insn "*fuse_xor_and" 488 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 489 1.1 mrg (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 490 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 491 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 492 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 493 1.1 mrg "(TARGET_P10_FUSION)" 494 1.1 mrg "@ 495 1.1 mrg xor %3,%1,%0\;and %3,%3,%2 496 1.1 mrg xor %3,%1,%0\;and %3,%3,%2 497 1.1 mrg xor %3,%1,%0\;and %3,%3,%2 498 1.1 mrg xor %4,%1,%0\;and %3,%4,%2" 499 1.1 mrg [(set_attr "type" "fused_arith_logical") 500 1.1 mrg (set_attr "cost" "6") 501 1.1 mrg (set_attr "length" "8")]) 502 1.1 mrg 503 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 504 1.1 mrg ;; scalar add -> and 505 1.1 mrg (define_insn "*fuse_add_and" 506 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 507 1.1 mrg (and:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 508 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 509 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 510 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 511 1.1 mrg "(TARGET_P10_FUSION)" 512 1.1 mrg "@ 513 1.1 mrg add %3,%1,%0\;and %3,%3,%2 514 1.1 mrg add %3,%1,%0\;and %3,%3,%2 515 1.1 mrg add %3,%1,%0\;and %3,%3,%2 516 1.1 mrg add %4,%1,%0\;and %3,%4,%2" 517 1.1 mrg [(set_attr "type" "fused_arith_logical") 518 1.1 mrg (set_attr "cost" "6") 519 1.1 mrg (set_attr "length" "8")]) 520 1.1 mrg 521 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 522 1.1 mrg ;; scalar subf -> and 523 1.1 mrg (define_insn "*fuse_subf_and" 524 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 525 1.1 mrg (and:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 526 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 527 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 528 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 529 1.1 mrg "(TARGET_P10_FUSION)" 530 1.1 mrg "@ 531 1.1 mrg subf %3,%1,%0\;and %3,%3,%2 532 1.1 mrg subf %3,%1,%0\;and %3,%3,%2 533 1.1 mrg subf %3,%1,%0\;and %3,%3,%2 534 1.1 mrg subf %4,%1,%0\;and %3,%4,%2" 535 1.1 mrg [(set_attr "type" "fused_arith_logical") 536 1.1 mrg (set_attr "cost" "6") 537 1.1 mrg (set_attr "length" "8")]) 538 1.1 mrg 539 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 540 1.1 mrg ;; scalar and -> andc 541 1.1 mrg (define_insn "*fuse_and_andc" 542 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 543 1.1 mrg (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 544 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 545 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 546 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 547 1.1 mrg "(TARGET_P10_FUSION)" 548 1.1 mrg "@ 549 1.1 mrg and %3,%1,%0\;andc %3,%3,%2 550 1.1 mrg and %3,%1,%0\;andc %3,%3,%2 551 1.1 mrg and %3,%1,%0\;andc %3,%3,%2 552 1.1 mrg and %4,%1,%0\;andc %3,%4,%2" 553 1.1 mrg [(set_attr "type" "fused_arith_logical") 554 1.1 mrg (set_attr "cost" "6") 555 1.1 mrg (set_attr "length" "8")]) 556 1.1 mrg 557 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 558 1.1 mrg ;; scalar andc -> andc 559 1.1 mrg (define_insn "*fuse_andc_andc" 560 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 561 1.1 mrg (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 562 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 563 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 564 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 565 1.1 mrg "(TARGET_P10_FUSION)" 566 1.1 mrg "@ 567 1.1 mrg andc %3,%1,%0\;andc %3,%3,%2 568 1.1 mrg andc %3,%1,%0\;andc %3,%3,%2 569 1.1 mrg andc %3,%1,%0\;andc %3,%3,%2 570 1.1 mrg andc %4,%1,%0\;andc %3,%4,%2" 571 1.1 mrg [(set_attr "type" "fused_arith_logical") 572 1.1 mrg (set_attr "cost" "6") 573 1.1 mrg (set_attr "length" "8")]) 574 1.1 mrg 575 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 576 1.1 mrg ;; scalar eqv -> andc 577 1.1 mrg (define_insn "*fuse_eqv_andc" 578 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 579 1.1 mrg (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 580 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 581 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 582 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 583 1.1 mrg "(TARGET_P10_FUSION)" 584 1.1 mrg "@ 585 1.1 mrg eqv %3,%1,%0\;andc %3,%3,%2 586 1.1 mrg eqv %3,%1,%0\;andc %3,%3,%2 587 1.1 mrg eqv %3,%1,%0\;andc %3,%3,%2 588 1.1 mrg eqv %4,%1,%0\;andc %3,%4,%2" 589 1.1 mrg [(set_attr "type" "fused_arith_logical") 590 1.1 mrg (set_attr "cost" "6") 591 1.1 mrg (set_attr "length" "8")]) 592 1.1 mrg 593 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 594 1.1 mrg ;; scalar nand -> andc 595 1.1 mrg (define_insn "*fuse_nand_andc" 596 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 597 1.1 mrg (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 598 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 599 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 600 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 601 1.1 mrg "(TARGET_P10_FUSION)" 602 1.1 mrg "@ 603 1.1 mrg nand %3,%1,%0\;andc %3,%3,%2 604 1.1 mrg nand %3,%1,%0\;andc %3,%3,%2 605 1.1 mrg nand %3,%1,%0\;andc %3,%3,%2 606 1.1 mrg nand %4,%1,%0\;andc %3,%4,%2" 607 1.1 mrg [(set_attr "type" "fused_arith_logical") 608 1.1 mrg (set_attr "cost" "6") 609 1.1 mrg (set_attr "length" "8")]) 610 1.1 mrg 611 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 612 1.1 mrg ;; scalar nor -> andc 613 1.1 mrg (define_insn "*fuse_nor_andc" 614 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 615 1.1 mrg (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 616 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 617 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 618 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 619 1.1 mrg "(TARGET_P10_FUSION)" 620 1.1 mrg "@ 621 1.1 mrg nor %3,%1,%0\;andc %3,%3,%2 622 1.1 mrg nor %3,%1,%0\;andc %3,%3,%2 623 1.1 mrg nor %3,%1,%0\;andc %3,%3,%2 624 1.1 mrg nor %4,%1,%0\;andc %3,%4,%2" 625 1.1 mrg [(set_attr "type" "fused_arith_logical") 626 1.1 mrg (set_attr "cost" "6") 627 1.1 mrg (set_attr "length" "8")]) 628 1.1 mrg 629 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 630 1.1 mrg ;; scalar or -> andc 631 1.1 mrg (define_insn "*fuse_or_andc" 632 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 633 1.1 mrg (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 634 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 635 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 636 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 637 1.1 mrg "(TARGET_P10_FUSION)" 638 1.1 mrg "@ 639 1.1 mrg or %3,%1,%0\;andc %3,%3,%2 640 1.1 mrg or %3,%1,%0\;andc %3,%3,%2 641 1.1 mrg or %3,%1,%0\;andc %3,%3,%2 642 1.1 mrg or %4,%1,%0\;andc %3,%4,%2" 643 1.1 mrg [(set_attr "type" "fused_arith_logical") 644 1.1 mrg (set_attr "cost" "6") 645 1.1 mrg (set_attr "length" "8")]) 646 1.1 mrg 647 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 648 1.1 mrg ;; scalar orc -> andc 649 1.1 mrg (define_insn "*fuse_orc_andc" 650 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 651 1.1 mrg (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 652 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 653 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 654 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 655 1.1 mrg "(TARGET_P10_FUSION)" 656 1.1 mrg "@ 657 1.1 mrg orc %3,%1,%0\;andc %3,%3,%2 658 1.1 mrg orc %3,%1,%0\;andc %3,%3,%2 659 1.1 mrg orc %3,%1,%0\;andc %3,%3,%2 660 1.1 mrg orc %4,%1,%0\;andc %3,%4,%2" 661 1.1 mrg [(set_attr "type" "fused_arith_logical") 662 1.1 mrg (set_attr "cost" "6") 663 1.1 mrg (set_attr "length" "8")]) 664 1.1 mrg 665 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 666 1.1 mrg ;; scalar xor -> andc 667 1.1 mrg (define_insn "*fuse_xor_andc" 668 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 669 1.1 mrg (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 670 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 671 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 672 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 673 1.1 mrg "(TARGET_P10_FUSION)" 674 1.1 mrg "@ 675 1.1 mrg xor %3,%1,%0\;andc %3,%3,%2 676 1.1 mrg xor %3,%1,%0\;andc %3,%3,%2 677 1.1 mrg xor %3,%1,%0\;andc %3,%3,%2 678 1.1 mrg xor %4,%1,%0\;andc %3,%4,%2" 679 1.1 mrg [(set_attr "type" "fused_arith_logical") 680 1.1 mrg (set_attr "cost" "6") 681 1.1 mrg (set_attr "length" "8")]) 682 1.1 mrg 683 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 684 1.1 mrg ;; scalar and -> eqv 685 1.1 mrg (define_insn "*fuse_and_eqv" 686 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 687 1.1 mrg (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 688 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 689 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 690 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 691 1.1 mrg "(TARGET_P10_FUSION)" 692 1.1 mrg "@ 693 1.1 mrg and %3,%1,%0\;eqv %3,%3,%2 694 1.1 mrg and %3,%1,%0\;eqv %3,%3,%2 695 1.1 mrg and %3,%1,%0\;eqv %3,%3,%2 696 1.1 mrg and %4,%1,%0\;eqv %3,%4,%2" 697 1.1 mrg [(set_attr "type" "fused_arith_logical") 698 1.1 mrg (set_attr "cost" "6") 699 1.1 mrg (set_attr "length" "8")]) 700 1.1 mrg 701 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 702 1.1 mrg ;; scalar andc -> eqv 703 1.1 mrg (define_insn "*fuse_andc_eqv" 704 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 705 1.1 mrg (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 706 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 707 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 708 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 709 1.1 mrg "(TARGET_P10_FUSION)" 710 1.1 mrg "@ 711 1.1 mrg andc %3,%1,%0\;eqv %3,%3,%2 712 1.1 mrg andc %3,%1,%0\;eqv %3,%3,%2 713 1.1 mrg andc %3,%1,%0\;eqv %3,%3,%2 714 1.1 mrg andc %4,%1,%0\;eqv %3,%4,%2" 715 1.1 mrg [(set_attr "type" "fused_arith_logical") 716 1.1 mrg (set_attr "cost" "6") 717 1.1 mrg (set_attr "length" "8")]) 718 1.1 mrg 719 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 720 1.1 mrg ;; scalar eqv -> eqv 721 1.1 mrg (define_insn "*fuse_eqv_eqv" 722 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 723 1.1 mrg (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 724 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) 725 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 726 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 727 1.1 mrg "(TARGET_P10_FUSION)" 728 1.1 mrg "@ 729 1.1 mrg eqv %3,%1,%0\;eqv %3,%3,%2 730 1.1 mrg eqv %3,%1,%0\;eqv %3,%3,%2 731 1.1 mrg eqv %3,%1,%0\;eqv %3,%3,%2 732 1.1 mrg eqv %4,%1,%0\;eqv %3,%4,%2" 733 1.1 mrg [(set_attr "type" "fused_arith_logical") 734 1.1 mrg (set_attr "cost" "6") 735 1.1 mrg (set_attr "length" "8")]) 736 1.1 mrg 737 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 738 1.1 mrg ;; scalar nand -> eqv 739 1.1 mrg (define_insn "*fuse_nand_eqv" 740 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 741 1.1 mrg (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 742 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 743 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 744 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 745 1.1 mrg "(TARGET_P10_FUSION)" 746 1.1 mrg "@ 747 1.1 mrg nand %3,%1,%0\;eqv %3,%3,%2 748 1.1 mrg nand %3,%1,%0\;eqv %3,%3,%2 749 1.1 mrg nand %3,%1,%0\;eqv %3,%3,%2 750 1.1 mrg nand %4,%1,%0\;eqv %3,%4,%2" 751 1.1 mrg [(set_attr "type" "fused_arith_logical") 752 1.1 mrg (set_attr "cost" "6") 753 1.1 mrg (set_attr "length" "8")]) 754 1.1 mrg 755 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 756 1.1 mrg ;; scalar nor -> eqv 757 1.1 mrg (define_insn "*fuse_nor_eqv" 758 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 759 1.1 mrg (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 760 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 761 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 762 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 763 1.1 mrg "(TARGET_P10_FUSION)" 764 1.1 mrg "@ 765 1.1 mrg nor %3,%1,%0\;eqv %3,%3,%2 766 1.1 mrg nor %3,%1,%0\;eqv %3,%3,%2 767 1.1 mrg nor %3,%1,%0\;eqv %3,%3,%2 768 1.1 mrg nor %4,%1,%0\;eqv %3,%4,%2" 769 1.1 mrg [(set_attr "type" "fused_arith_logical") 770 1.1 mrg (set_attr "cost" "6") 771 1.1 mrg (set_attr "length" "8")]) 772 1.1 mrg 773 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 774 1.1 mrg ;; scalar or -> eqv 775 1.1 mrg (define_insn "*fuse_or_eqv" 776 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 777 1.1 mrg (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 778 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 779 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 780 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 781 1.1 mrg "(TARGET_P10_FUSION)" 782 1.1 mrg "@ 783 1.1 mrg or %3,%1,%0\;eqv %3,%3,%2 784 1.1 mrg or %3,%1,%0\;eqv %3,%3,%2 785 1.1 mrg or %3,%1,%0\;eqv %3,%3,%2 786 1.1 mrg or %4,%1,%0\;eqv %3,%4,%2" 787 1.1 mrg [(set_attr "type" "fused_arith_logical") 788 1.1 mrg (set_attr "cost" "6") 789 1.1 mrg (set_attr "length" "8")]) 790 1.1 mrg 791 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 792 1.1 mrg ;; scalar orc -> eqv 793 1.1 mrg (define_insn "*fuse_orc_eqv" 794 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 795 1.1 mrg (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 796 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 797 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 798 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 799 1.1 mrg "(TARGET_P10_FUSION)" 800 1.1 mrg "@ 801 1.1 mrg orc %3,%1,%0\;eqv %3,%3,%2 802 1.1 mrg orc %3,%1,%0\;eqv %3,%3,%2 803 1.1 mrg orc %3,%1,%0\;eqv %3,%3,%2 804 1.1 mrg orc %4,%1,%0\;eqv %3,%4,%2" 805 1.1 mrg [(set_attr "type" "fused_arith_logical") 806 1.1 mrg (set_attr "cost" "6") 807 1.1 mrg (set_attr "length" "8")]) 808 1.1 mrg 809 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 810 1.1 mrg ;; scalar xor -> eqv 811 1.1 mrg (define_insn "*fuse_xor_eqv" 812 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 813 1.1 mrg (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 814 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 815 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 816 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 817 1.1 mrg "(TARGET_P10_FUSION)" 818 1.1 mrg "@ 819 1.1 mrg xor %3,%1,%0\;eqv %3,%3,%2 820 1.1 mrg xor %3,%1,%0\;eqv %3,%3,%2 821 1.1 mrg xor %3,%1,%0\;eqv %3,%3,%2 822 1.1 mrg xor %4,%1,%0\;eqv %3,%4,%2" 823 1.1 mrg [(set_attr "type" "fused_arith_logical") 824 1.1 mrg (set_attr "cost" "6") 825 1.1 mrg (set_attr "length" "8")]) 826 1.1 mrg 827 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 828 1.1 mrg ;; scalar and -> nand 829 1.1 mrg (define_insn "*fuse_and_nand" 830 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 831 1.1 mrg (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 832 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 833 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 834 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 835 1.1 mrg "(TARGET_P10_FUSION)" 836 1.1 mrg "@ 837 1.1 mrg and %3,%1,%0\;nand %3,%3,%2 838 1.1 mrg and %3,%1,%0\;nand %3,%3,%2 839 1.1 mrg and %3,%1,%0\;nand %3,%3,%2 840 1.1 mrg and %4,%1,%0\;nand %3,%4,%2" 841 1.1 mrg [(set_attr "type" "fused_arith_logical") 842 1.1 mrg (set_attr "cost" "6") 843 1.1 mrg (set_attr "length" "8")]) 844 1.1 mrg 845 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 846 1.1 mrg ;; scalar andc -> nand 847 1.1 mrg (define_insn "*fuse_andc_nand" 848 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 849 1.1 mrg (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 850 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 851 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 852 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 853 1.1 mrg "(TARGET_P10_FUSION)" 854 1.1 mrg "@ 855 1.1 mrg andc %3,%1,%0\;nand %3,%3,%2 856 1.1 mrg andc %3,%1,%0\;nand %3,%3,%2 857 1.1 mrg andc %3,%1,%0\;nand %3,%3,%2 858 1.1 mrg andc %4,%1,%0\;nand %3,%4,%2" 859 1.1 mrg [(set_attr "type" "fused_arith_logical") 860 1.1 mrg (set_attr "cost" "6") 861 1.1 mrg (set_attr "length" "8")]) 862 1.1 mrg 863 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 864 1.1 mrg ;; scalar eqv -> nand 865 1.1 mrg (define_insn "*fuse_eqv_nand" 866 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 867 1.1 mrg (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 868 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 869 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 870 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 871 1.1 mrg "(TARGET_P10_FUSION)" 872 1.1 mrg "@ 873 1.1 mrg eqv %3,%1,%0\;nand %3,%3,%2 874 1.1 mrg eqv %3,%1,%0\;nand %3,%3,%2 875 1.1 mrg eqv %3,%1,%0\;nand %3,%3,%2 876 1.1 mrg eqv %4,%1,%0\;nand %3,%4,%2" 877 1.1 mrg [(set_attr "type" "fused_arith_logical") 878 1.1 mrg (set_attr "cost" "6") 879 1.1 mrg (set_attr "length" "8")]) 880 1.1 mrg 881 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 882 1.1 mrg ;; scalar nand -> nand 883 1.1 mrg (define_insn "*fuse_nand_nand" 884 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 885 1.1 mrg (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 886 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 887 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 888 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 889 1.1 mrg "(TARGET_P10_FUSION)" 890 1.1 mrg "@ 891 1.1 mrg nand %3,%1,%0\;nand %3,%3,%2 892 1.1 mrg nand %3,%1,%0\;nand %3,%3,%2 893 1.1 mrg nand %3,%1,%0\;nand %3,%3,%2 894 1.1 mrg nand %4,%1,%0\;nand %3,%4,%2" 895 1.1 mrg [(set_attr "type" "fused_arith_logical") 896 1.1 mrg (set_attr "cost" "6") 897 1.1 mrg (set_attr "length" "8")]) 898 1.1 mrg 899 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 900 1.1 mrg ;; scalar nor -> nand 901 1.1 mrg (define_insn "*fuse_nor_nand" 902 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 903 1.1 mrg (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 904 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 905 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 906 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 907 1.1 mrg "(TARGET_P10_FUSION)" 908 1.1 mrg "@ 909 1.1 mrg nor %3,%1,%0\;nand %3,%3,%2 910 1.1 mrg nor %3,%1,%0\;nand %3,%3,%2 911 1.1 mrg nor %3,%1,%0\;nand %3,%3,%2 912 1.1 mrg nor %4,%1,%0\;nand %3,%4,%2" 913 1.1 mrg [(set_attr "type" "fused_arith_logical") 914 1.1 mrg (set_attr "cost" "6") 915 1.1 mrg (set_attr "length" "8")]) 916 1.1 mrg 917 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 918 1.1 mrg ;; scalar or -> nand 919 1.1 mrg (define_insn "*fuse_or_nand" 920 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 921 1.1 mrg (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 922 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 923 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 924 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 925 1.1 mrg "(TARGET_P10_FUSION)" 926 1.1 mrg "@ 927 1.1 mrg or %3,%1,%0\;nand %3,%3,%2 928 1.1 mrg or %3,%1,%0\;nand %3,%3,%2 929 1.1 mrg or %3,%1,%0\;nand %3,%3,%2 930 1.1 mrg or %4,%1,%0\;nand %3,%4,%2" 931 1.1 mrg [(set_attr "type" "fused_arith_logical") 932 1.1 mrg (set_attr "cost" "6") 933 1.1 mrg (set_attr "length" "8")]) 934 1.1 mrg 935 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 936 1.1 mrg ;; scalar orc -> nand 937 1.1 mrg (define_insn "*fuse_orc_nand" 938 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 939 1.1 mrg (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 940 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 941 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 942 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 943 1.1 mrg "(TARGET_P10_FUSION)" 944 1.1 mrg "@ 945 1.1 mrg orc %3,%1,%0\;nand %3,%3,%2 946 1.1 mrg orc %3,%1,%0\;nand %3,%3,%2 947 1.1 mrg orc %3,%1,%0\;nand %3,%3,%2 948 1.1 mrg orc %4,%1,%0\;nand %3,%4,%2" 949 1.1 mrg [(set_attr "type" "fused_arith_logical") 950 1.1 mrg (set_attr "cost" "6") 951 1.1 mrg (set_attr "length" "8")]) 952 1.1 mrg 953 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 954 1.1 mrg ;; scalar xor -> nand 955 1.1 mrg (define_insn "*fuse_xor_nand" 956 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 957 1.1 mrg (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 958 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 959 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 960 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 961 1.1 mrg "(TARGET_P10_FUSION)" 962 1.1 mrg "@ 963 1.1 mrg xor %3,%1,%0\;nand %3,%3,%2 964 1.1 mrg xor %3,%1,%0\;nand %3,%3,%2 965 1.1 mrg xor %3,%1,%0\;nand %3,%3,%2 966 1.1 mrg xor %4,%1,%0\;nand %3,%4,%2" 967 1.1 mrg [(set_attr "type" "fused_arith_logical") 968 1.1 mrg (set_attr "cost" "6") 969 1.1 mrg (set_attr "length" "8")]) 970 1.1 mrg 971 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 972 1.1 mrg ;; scalar add -> nand 973 1.1 mrg (define_insn "*fuse_add_nand" 974 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 975 1.1 mrg (ior:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 976 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 977 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 978 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 979 1.1 mrg "(TARGET_P10_FUSION)" 980 1.1 mrg "@ 981 1.1 mrg add %3,%1,%0\;nand %3,%3,%2 982 1.1 mrg add %3,%1,%0\;nand %3,%3,%2 983 1.1 mrg add %3,%1,%0\;nand %3,%3,%2 984 1.1 mrg add %4,%1,%0\;nand %3,%4,%2" 985 1.1 mrg [(set_attr "type" "fused_arith_logical") 986 1.1 mrg (set_attr "cost" "6") 987 1.1 mrg (set_attr "length" "8")]) 988 1.1 mrg 989 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 990 1.1 mrg ;; scalar subf -> nand 991 1.1 mrg (define_insn "*fuse_subf_nand" 992 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 993 1.1 mrg (ior:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 994 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 995 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 996 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 997 1.1 mrg "(TARGET_P10_FUSION)" 998 1.1 mrg "@ 999 1.1 mrg subf %3,%1,%0\;nand %3,%3,%2 1000 1.1 mrg subf %3,%1,%0\;nand %3,%3,%2 1001 1.1 mrg subf %3,%1,%0\;nand %3,%3,%2 1002 1.1 mrg subf %4,%1,%0\;nand %3,%4,%2" 1003 1.1 mrg [(set_attr "type" "fused_arith_logical") 1004 1.1 mrg (set_attr "cost" "6") 1005 1.1 mrg (set_attr "length" "8")]) 1006 1.1 mrg 1007 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1008 1.1 mrg ;; scalar and -> nor 1009 1.1 mrg (define_insn "*fuse_and_nor" 1010 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1011 1.1 mrg (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1012 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1013 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1014 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1015 1.1 mrg "(TARGET_P10_FUSION)" 1016 1.1 mrg "@ 1017 1.1 mrg and %3,%1,%0\;nor %3,%3,%2 1018 1.1 mrg and %3,%1,%0\;nor %3,%3,%2 1019 1.1 mrg and %3,%1,%0\;nor %3,%3,%2 1020 1.1 mrg and %4,%1,%0\;nor %3,%4,%2" 1021 1.1 mrg [(set_attr "type" "fused_arith_logical") 1022 1.1 mrg (set_attr "cost" "6") 1023 1.1 mrg (set_attr "length" "8")]) 1024 1.1 mrg 1025 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1026 1.1 mrg ;; scalar andc -> nor 1027 1.1 mrg (define_insn "*fuse_andc_nor" 1028 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1029 1.1 mrg (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1030 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1031 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1032 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1033 1.1 mrg "(TARGET_P10_FUSION)" 1034 1.1 mrg "@ 1035 1.1 mrg andc %3,%1,%0\;nor %3,%3,%2 1036 1.1 mrg andc %3,%1,%0\;nor %3,%3,%2 1037 1.1 mrg andc %3,%1,%0\;nor %3,%3,%2 1038 1.1 mrg andc %4,%1,%0\;nor %3,%4,%2" 1039 1.1 mrg [(set_attr "type" "fused_arith_logical") 1040 1.1 mrg (set_attr "cost" "6") 1041 1.1 mrg (set_attr "length" "8")]) 1042 1.1 mrg 1043 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1044 1.1 mrg ;; scalar eqv -> nor 1045 1.1 mrg (define_insn "*fuse_eqv_nor" 1046 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1047 1.1 mrg (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1048 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1049 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1050 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1051 1.1 mrg "(TARGET_P10_FUSION)" 1052 1.1 mrg "@ 1053 1.1 mrg eqv %3,%1,%0\;nor %3,%3,%2 1054 1.1 mrg eqv %3,%1,%0\;nor %3,%3,%2 1055 1.1 mrg eqv %3,%1,%0\;nor %3,%3,%2 1056 1.1 mrg eqv %4,%1,%0\;nor %3,%4,%2" 1057 1.1 mrg [(set_attr "type" "fused_arith_logical") 1058 1.1 mrg (set_attr "cost" "6") 1059 1.1 mrg (set_attr "length" "8")]) 1060 1.1 mrg 1061 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1062 1.1 mrg ;; scalar nand -> nor 1063 1.1 mrg (define_insn "*fuse_nand_nor" 1064 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1065 1.1 mrg (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1066 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1067 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1068 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1069 1.1 mrg "(TARGET_P10_FUSION)" 1070 1.1 mrg "@ 1071 1.1 mrg nand %3,%1,%0\;nor %3,%3,%2 1072 1.1 mrg nand %3,%1,%0\;nor %3,%3,%2 1073 1.1 mrg nand %3,%1,%0\;nor %3,%3,%2 1074 1.1 mrg nand %4,%1,%0\;nor %3,%4,%2" 1075 1.1 mrg [(set_attr "type" "fused_arith_logical") 1076 1.1 mrg (set_attr "cost" "6") 1077 1.1 mrg (set_attr "length" "8")]) 1078 1.1 mrg 1079 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1080 1.1 mrg ;; scalar nor -> nor 1081 1.1 mrg (define_insn "*fuse_nor_nor" 1082 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1083 1.1 mrg (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1084 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1085 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1086 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1087 1.1 mrg "(TARGET_P10_FUSION)" 1088 1.1 mrg "@ 1089 1.1 mrg nor %3,%1,%0\;nor %3,%3,%2 1090 1.1 mrg nor %3,%1,%0\;nor %3,%3,%2 1091 1.1 mrg nor %3,%1,%0\;nor %3,%3,%2 1092 1.1 mrg nor %4,%1,%0\;nor %3,%4,%2" 1093 1.1 mrg [(set_attr "type" "fused_arith_logical") 1094 1.1 mrg (set_attr "cost" "6") 1095 1.1 mrg (set_attr "length" "8")]) 1096 1.1 mrg 1097 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1098 1.1 mrg ;; scalar or -> nor 1099 1.1 mrg (define_insn "*fuse_or_nor" 1100 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1101 1.1 mrg (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1102 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1103 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1104 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1105 1.1 mrg "(TARGET_P10_FUSION)" 1106 1.1 mrg "@ 1107 1.1 mrg or %3,%1,%0\;nor %3,%3,%2 1108 1.1 mrg or %3,%1,%0\;nor %3,%3,%2 1109 1.1 mrg or %3,%1,%0\;nor %3,%3,%2 1110 1.1 mrg or %4,%1,%0\;nor %3,%4,%2" 1111 1.1 mrg [(set_attr "type" "fused_arith_logical") 1112 1.1 mrg (set_attr "cost" "6") 1113 1.1 mrg (set_attr "length" "8")]) 1114 1.1 mrg 1115 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1116 1.1 mrg ;; scalar orc -> nor 1117 1.1 mrg (define_insn "*fuse_orc_nor" 1118 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1119 1.1 mrg (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1120 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1121 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1122 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1123 1.1 mrg "(TARGET_P10_FUSION)" 1124 1.1 mrg "@ 1125 1.1 mrg orc %3,%1,%0\;nor %3,%3,%2 1126 1.1 mrg orc %3,%1,%0\;nor %3,%3,%2 1127 1.1 mrg orc %3,%1,%0\;nor %3,%3,%2 1128 1.1 mrg orc %4,%1,%0\;nor %3,%4,%2" 1129 1.1 mrg [(set_attr "type" "fused_arith_logical") 1130 1.1 mrg (set_attr "cost" "6") 1131 1.1 mrg (set_attr "length" "8")]) 1132 1.1 mrg 1133 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1134 1.1 mrg ;; scalar xor -> nor 1135 1.1 mrg (define_insn "*fuse_xor_nor" 1136 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1137 1.1 mrg (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1138 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1139 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1140 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1141 1.1 mrg "(TARGET_P10_FUSION)" 1142 1.1 mrg "@ 1143 1.1 mrg xor %3,%1,%0\;nor %3,%3,%2 1144 1.1 mrg xor %3,%1,%0\;nor %3,%3,%2 1145 1.1 mrg xor %3,%1,%0\;nor %3,%3,%2 1146 1.1 mrg xor %4,%1,%0\;nor %3,%4,%2" 1147 1.1 mrg [(set_attr "type" "fused_arith_logical") 1148 1.1 mrg (set_attr "cost" "6") 1149 1.1 mrg (set_attr "length" "8")]) 1150 1.1 mrg 1151 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 1152 1.1 mrg ;; scalar add -> nor 1153 1.1 mrg (define_insn "*fuse_add_nor" 1154 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1155 1.1 mrg (and:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1156 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1157 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1158 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1159 1.1 mrg "(TARGET_P10_FUSION)" 1160 1.1 mrg "@ 1161 1.1 mrg add %3,%1,%0\;nor %3,%3,%2 1162 1.1 mrg add %3,%1,%0\;nor %3,%3,%2 1163 1.1 mrg add %3,%1,%0\;nor %3,%3,%2 1164 1.1 mrg add %4,%1,%0\;nor %3,%4,%2" 1165 1.1 mrg [(set_attr "type" "fused_arith_logical") 1166 1.1 mrg (set_attr "cost" "6") 1167 1.1 mrg (set_attr "length" "8")]) 1168 1.1 mrg 1169 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 1170 1.1 mrg ;; scalar subf -> nor 1171 1.1 mrg (define_insn "*fuse_subf_nor" 1172 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1173 1.1 mrg (and:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1174 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1175 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1176 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1177 1.1 mrg "(TARGET_P10_FUSION)" 1178 1.1 mrg "@ 1179 1.1 mrg subf %3,%1,%0\;nor %3,%3,%2 1180 1.1 mrg subf %3,%1,%0\;nor %3,%3,%2 1181 1.1 mrg subf %3,%1,%0\;nor %3,%3,%2 1182 1.1 mrg subf %4,%1,%0\;nor %3,%4,%2" 1183 1.1 mrg [(set_attr "type" "fused_arith_logical") 1184 1.1 mrg (set_attr "cost" "6") 1185 1.1 mrg (set_attr "length" "8")]) 1186 1.1 mrg 1187 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1188 1.1 mrg ;; scalar and -> or 1189 1.1 mrg (define_insn "*fuse_and_or" 1190 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1191 1.1 mrg (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1192 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1193 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1194 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1195 1.1 mrg "(TARGET_P10_FUSION)" 1196 1.1 mrg "@ 1197 1.1 mrg and %3,%1,%0\;or %3,%3,%2 1198 1.1 mrg and %3,%1,%0\;or %3,%3,%2 1199 1.1 mrg and %3,%1,%0\;or %3,%3,%2 1200 1.1 mrg and %4,%1,%0\;or %3,%4,%2" 1201 1.1 mrg [(set_attr "type" "fused_arith_logical") 1202 1.1 mrg (set_attr "cost" "6") 1203 1.1 mrg (set_attr "length" "8")]) 1204 1.1 mrg 1205 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1206 1.1 mrg ;; scalar andc -> or 1207 1.1 mrg (define_insn "*fuse_andc_or" 1208 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1209 1.1 mrg (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1210 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1211 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1212 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1213 1.1 mrg "(TARGET_P10_FUSION)" 1214 1.1 mrg "@ 1215 1.1 mrg andc %3,%1,%0\;or %3,%3,%2 1216 1.1 mrg andc %3,%1,%0\;or %3,%3,%2 1217 1.1 mrg andc %3,%1,%0\;or %3,%3,%2 1218 1.1 mrg andc %4,%1,%0\;or %3,%4,%2" 1219 1.1 mrg [(set_attr "type" "fused_arith_logical") 1220 1.1 mrg (set_attr "cost" "6") 1221 1.1 mrg (set_attr "length" "8")]) 1222 1.1 mrg 1223 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1224 1.1 mrg ;; scalar eqv -> or 1225 1.1 mrg (define_insn "*fuse_eqv_or" 1226 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1227 1.1 mrg (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1228 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1229 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1230 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1231 1.1 mrg "(TARGET_P10_FUSION)" 1232 1.1 mrg "@ 1233 1.1 mrg eqv %3,%1,%0\;or %3,%3,%2 1234 1.1 mrg eqv %3,%1,%0\;or %3,%3,%2 1235 1.1 mrg eqv %3,%1,%0\;or %3,%3,%2 1236 1.1 mrg eqv %4,%1,%0\;or %3,%4,%2" 1237 1.1 mrg [(set_attr "type" "fused_arith_logical") 1238 1.1 mrg (set_attr "cost" "6") 1239 1.1 mrg (set_attr "length" "8")]) 1240 1.1 mrg 1241 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1242 1.1 mrg ;; scalar nand -> or 1243 1.1 mrg (define_insn "*fuse_nand_or" 1244 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1245 1.1 mrg (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1246 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1247 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1248 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1249 1.1 mrg "(TARGET_P10_FUSION)" 1250 1.1 mrg "@ 1251 1.1 mrg nand %3,%1,%0\;or %3,%3,%2 1252 1.1 mrg nand %3,%1,%0\;or %3,%3,%2 1253 1.1 mrg nand %3,%1,%0\;or %3,%3,%2 1254 1.1 mrg nand %4,%1,%0\;or %3,%4,%2" 1255 1.1 mrg [(set_attr "type" "fused_arith_logical") 1256 1.1 mrg (set_attr "cost" "6") 1257 1.1 mrg (set_attr "length" "8")]) 1258 1.1 mrg 1259 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1260 1.1 mrg ;; scalar nor -> or 1261 1.1 mrg (define_insn "*fuse_nor_or" 1262 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1263 1.1 mrg (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1264 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1265 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1266 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1267 1.1 mrg "(TARGET_P10_FUSION)" 1268 1.1 mrg "@ 1269 1.1 mrg nor %3,%1,%0\;or %3,%3,%2 1270 1.1 mrg nor %3,%1,%0\;or %3,%3,%2 1271 1.1 mrg nor %3,%1,%0\;or %3,%3,%2 1272 1.1 mrg nor %4,%1,%0\;or %3,%4,%2" 1273 1.1 mrg [(set_attr "type" "fused_arith_logical") 1274 1.1 mrg (set_attr "cost" "6") 1275 1.1 mrg (set_attr "length" "8")]) 1276 1.1 mrg 1277 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1278 1.1 mrg ;; scalar or -> or 1279 1.1 mrg (define_insn "*fuse_or_or" 1280 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1281 1.1 mrg (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1282 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 1283 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1284 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1285 1.1 mrg "(TARGET_P10_FUSION)" 1286 1.1 mrg "@ 1287 1.1 mrg or %3,%1,%0\;or %3,%3,%2 1288 1.1 mrg or %3,%1,%0\;or %3,%3,%2 1289 1.1 mrg or %3,%1,%0\;or %3,%3,%2 1290 1.1 mrg or %4,%1,%0\;or %3,%4,%2" 1291 1.1 mrg [(set_attr "type" "fused_arith_logical") 1292 1.1 mrg (set_attr "cost" "6") 1293 1.1 mrg (set_attr "length" "8")]) 1294 1.1 mrg 1295 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1296 1.1 mrg ;; scalar orc -> or 1297 1.1 mrg (define_insn "*fuse_orc_or" 1298 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1299 1.1 mrg (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1300 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1301 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1302 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1303 1.1 mrg "(TARGET_P10_FUSION)" 1304 1.1 mrg "@ 1305 1.1 mrg orc %3,%1,%0\;or %3,%3,%2 1306 1.1 mrg orc %3,%1,%0\;or %3,%3,%2 1307 1.1 mrg orc %3,%1,%0\;or %3,%3,%2 1308 1.1 mrg orc %4,%1,%0\;or %3,%4,%2" 1309 1.1 mrg [(set_attr "type" "fused_arith_logical") 1310 1.1 mrg (set_attr "cost" "6") 1311 1.1 mrg (set_attr "length" "8")]) 1312 1.1 mrg 1313 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1314 1.1 mrg ;; scalar xor -> or 1315 1.1 mrg (define_insn "*fuse_xor_or" 1316 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1317 1.1 mrg (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1318 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1319 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1320 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1321 1.1 mrg "(TARGET_P10_FUSION)" 1322 1.1 mrg "@ 1323 1.1 mrg xor %3,%1,%0\;or %3,%3,%2 1324 1.1 mrg xor %3,%1,%0\;or %3,%3,%2 1325 1.1 mrg xor %3,%1,%0\;or %3,%3,%2 1326 1.1 mrg xor %4,%1,%0\;or %3,%4,%2" 1327 1.1 mrg [(set_attr "type" "fused_arith_logical") 1328 1.1 mrg (set_attr "cost" "6") 1329 1.1 mrg (set_attr "length" "8")]) 1330 1.1 mrg 1331 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 1332 1.1 mrg ;; scalar add -> or 1333 1.1 mrg (define_insn "*fuse_add_or" 1334 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1335 1.1 mrg (ior:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1336 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1337 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1338 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1339 1.1 mrg "(TARGET_P10_FUSION)" 1340 1.1 mrg "@ 1341 1.1 mrg add %3,%1,%0\;or %3,%3,%2 1342 1.1 mrg add %3,%1,%0\;or %3,%3,%2 1343 1.1 mrg add %3,%1,%0\;or %3,%3,%2 1344 1.1 mrg add %4,%1,%0\;or %3,%4,%2" 1345 1.1 mrg [(set_attr "type" "fused_arith_logical") 1346 1.1 mrg (set_attr "cost" "6") 1347 1.1 mrg (set_attr "length" "8")]) 1348 1.1 mrg 1349 1.1 mrg ;; add-logical fusion pattern generated by gen_logical_addsubf 1350 1.1 mrg ;; scalar subf -> or 1351 1.1 mrg (define_insn "*fuse_subf_or" 1352 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1353 1.1 mrg (ior:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1354 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1355 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1356 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1357 1.1 mrg "(TARGET_P10_FUSION)" 1358 1.1 mrg "@ 1359 1.1 mrg subf %3,%1,%0\;or %3,%3,%2 1360 1.1 mrg subf %3,%1,%0\;or %3,%3,%2 1361 1.1 mrg subf %3,%1,%0\;or %3,%3,%2 1362 1.1 mrg subf %4,%1,%0\;or %3,%4,%2" 1363 1.1 mrg [(set_attr "type" "fused_arith_logical") 1364 1.1 mrg (set_attr "cost" "6") 1365 1.1 mrg (set_attr "length" "8")]) 1366 1.1 mrg 1367 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1368 1.1 mrg ;; scalar and -> orc 1369 1.1 mrg (define_insn "*fuse_and_orc" 1370 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1371 1.1 mrg (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1372 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1373 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1374 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1375 1.1 mrg "(TARGET_P10_FUSION)" 1376 1.1 mrg "@ 1377 1.1 mrg and %3,%1,%0\;orc %3,%3,%2 1378 1.1 mrg and %3,%1,%0\;orc %3,%3,%2 1379 1.1 mrg and %3,%1,%0\;orc %3,%3,%2 1380 1.1 mrg and %4,%1,%0\;orc %3,%4,%2" 1381 1.1 mrg [(set_attr "type" "fused_arith_logical") 1382 1.1 mrg (set_attr "cost" "6") 1383 1.1 mrg (set_attr "length" "8")]) 1384 1.1 mrg 1385 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1386 1.1 mrg ;; scalar andc -> orc 1387 1.1 mrg (define_insn "*fuse_andc_orc" 1388 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1389 1.1 mrg (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1390 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1391 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1392 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1393 1.1 mrg "(TARGET_P10_FUSION)" 1394 1.1 mrg "@ 1395 1.1 mrg andc %3,%1,%0\;orc %3,%3,%2 1396 1.1 mrg andc %3,%1,%0\;orc %3,%3,%2 1397 1.1 mrg andc %3,%1,%0\;orc %3,%3,%2 1398 1.1 mrg andc %4,%1,%0\;orc %3,%4,%2" 1399 1.1 mrg [(set_attr "type" "fused_arith_logical") 1400 1.1 mrg (set_attr "cost" "6") 1401 1.1 mrg (set_attr "length" "8")]) 1402 1.1 mrg 1403 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1404 1.1 mrg ;; scalar eqv -> orc 1405 1.1 mrg (define_insn "*fuse_eqv_orc" 1406 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1407 1.1 mrg (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1408 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1409 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1410 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1411 1.1 mrg "(TARGET_P10_FUSION)" 1412 1.1 mrg "@ 1413 1.1 mrg eqv %3,%1,%0\;orc %3,%3,%2 1414 1.1 mrg eqv %3,%1,%0\;orc %3,%3,%2 1415 1.1 mrg eqv %3,%1,%0\;orc %3,%3,%2 1416 1.1 mrg eqv %4,%1,%0\;orc %3,%4,%2" 1417 1.1 mrg [(set_attr "type" "fused_arith_logical") 1418 1.1 mrg (set_attr "cost" "6") 1419 1.1 mrg (set_attr "length" "8")]) 1420 1.1 mrg 1421 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1422 1.1 mrg ;; scalar nand -> orc 1423 1.1 mrg (define_insn "*fuse_nand_orc" 1424 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1425 1.1 mrg (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1426 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1427 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1428 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1429 1.1 mrg "(TARGET_P10_FUSION)" 1430 1.1 mrg "@ 1431 1.1 mrg nand %3,%1,%0\;orc %3,%3,%2 1432 1.1 mrg nand %3,%1,%0\;orc %3,%3,%2 1433 1.1 mrg nand %3,%1,%0\;orc %3,%3,%2 1434 1.1 mrg nand %4,%1,%0\;orc %3,%4,%2" 1435 1.1 mrg [(set_attr "type" "fused_arith_logical") 1436 1.1 mrg (set_attr "cost" "6") 1437 1.1 mrg (set_attr "length" "8")]) 1438 1.1 mrg 1439 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1440 1.1 mrg ;; scalar nor -> orc 1441 1.1 mrg (define_insn "*fuse_nor_orc" 1442 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1443 1.1 mrg (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1444 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1445 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1446 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1447 1.1 mrg "(TARGET_P10_FUSION)" 1448 1.1 mrg "@ 1449 1.1 mrg nor %3,%1,%0\;orc %3,%3,%2 1450 1.1 mrg nor %3,%1,%0\;orc %3,%3,%2 1451 1.1 mrg nor %3,%1,%0\;orc %3,%3,%2 1452 1.1 mrg nor %4,%1,%0\;orc %3,%4,%2" 1453 1.1 mrg [(set_attr "type" "fused_arith_logical") 1454 1.1 mrg (set_attr "cost" "6") 1455 1.1 mrg (set_attr "length" "8")]) 1456 1.1 mrg 1457 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1458 1.1 mrg ;; scalar or -> orc 1459 1.1 mrg (define_insn "*fuse_or_orc" 1460 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1461 1.1 mrg (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1462 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1463 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1464 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1465 1.1 mrg "(TARGET_P10_FUSION)" 1466 1.1 mrg "@ 1467 1.1 mrg or %3,%1,%0\;orc %3,%3,%2 1468 1.1 mrg or %3,%1,%0\;orc %3,%3,%2 1469 1.1 mrg or %3,%1,%0\;orc %3,%3,%2 1470 1.1 mrg or %4,%1,%0\;orc %3,%4,%2" 1471 1.1 mrg [(set_attr "type" "fused_arith_logical") 1472 1.1 mrg (set_attr "cost" "6") 1473 1.1 mrg (set_attr "length" "8")]) 1474 1.1 mrg 1475 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1476 1.1 mrg ;; scalar orc -> orc 1477 1.1 mrg (define_insn "*fuse_orc_orc" 1478 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1479 1.1 mrg (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1480 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1481 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1482 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1483 1.1 mrg "(TARGET_P10_FUSION)" 1484 1.1 mrg "@ 1485 1.1 mrg orc %3,%1,%0\;orc %3,%3,%2 1486 1.1 mrg orc %3,%1,%0\;orc %3,%3,%2 1487 1.1 mrg orc %3,%1,%0\;orc %3,%3,%2 1488 1.1 mrg orc %4,%1,%0\;orc %3,%4,%2" 1489 1.1 mrg [(set_attr "type" "fused_arith_logical") 1490 1.1 mrg (set_attr "cost" "6") 1491 1.1 mrg (set_attr "length" "8")]) 1492 1.1 mrg 1493 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1494 1.1 mrg ;; scalar xor -> orc 1495 1.1 mrg (define_insn "*fuse_xor_orc" 1496 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1497 1.1 mrg (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1498 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1499 1.1 mrg (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1500 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1501 1.1 mrg "(TARGET_P10_FUSION)" 1502 1.1 mrg "@ 1503 1.1 mrg xor %3,%1,%0\;orc %3,%3,%2 1504 1.1 mrg xor %3,%1,%0\;orc %3,%3,%2 1505 1.1 mrg xor %3,%1,%0\;orc %3,%3,%2 1506 1.1 mrg xor %4,%1,%0\;orc %3,%4,%2" 1507 1.1 mrg [(set_attr "type" "fused_arith_logical") 1508 1.1 mrg (set_attr "cost" "6") 1509 1.1 mrg (set_attr "length" "8")]) 1510 1.1 mrg 1511 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1512 1.1 mrg ;; scalar and -> xor 1513 1.1 mrg (define_insn "*fuse_and_xor" 1514 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1515 1.1 mrg (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1516 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1517 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1518 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1519 1.1 mrg "(TARGET_P10_FUSION)" 1520 1.1 mrg "@ 1521 1.1 mrg and %3,%1,%0\;xor %3,%3,%2 1522 1.1 mrg and %3,%1,%0\;xor %3,%3,%2 1523 1.1 mrg and %3,%1,%0\;xor %3,%3,%2 1524 1.1 mrg and %4,%1,%0\;xor %3,%4,%2" 1525 1.1 mrg [(set_attr "type" "fused_arith_logical") 1526 1.1 mrg (set_attr "cost" "6") 1527 1.1 mrg (set_attr "length" "8")]) 1528 1.1 mrg 1529 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1530 1.1 mrg ;; scalar andc -> xor 1531 1.1 mrg (define_insn "*fuse_andc_xor" 1532 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1533 1.1 mrg (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1534 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1535 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1536 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1537 1.1 mrg "(TARGET_P10_FUSION)" 1538 1.1 mrg "@ 1539 1.1 mrg andc %3,%1,%0\;xor %3,%3,%2 1540 1.1 mrg andc %3,%1,%0\;xor %3,%3,%2 1541 1.1 mrg andc %3,%1,%0\;xor %3,%3,%2 1542 1.1 mrg andc %4,%1,%0\;xor %3,%4,%2" 1543 1.1 mrg [(set_attr "type" "fused_arith_logical") 1544 1.1 mrg (set_attr "cost" "6") 1545 1.1 mrg (set_attr "length" "8")]) 1546 1.1 mrg 1547 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1548 1.1 mrg ;; scalar eqv -> xor 1549 1.1 mrg (define_insn "*fuse_eqv_xor" 1550 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1551 1.1 mrg (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1552 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1553 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1554 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1555 1.1 mrg "(TARGET_P10_FUSION)" 1556 1.1 mrg "@ 1557 1.1 mrg eqv %3,%1,%0\;xor %3,%3,%2 1558 1.1 mrg eqv %3,%1,%0\;xor %3,%3,%2 1559 1.1 mrg eqv %3,%1,%0\;xor %3,%3,%2 1560 1.1 mrg eqv %4,%1,%0\;xor %3,%4,%2" 1561 1.1 mrg [(set_attr "type" "fused_arith_logical") 1562 1.1 mrg (set_attr "cost" "6") 1563 1.1 mrg (set_attr "length" "8")]) 1564 1.1 mrg 1565 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1566 1.1 mrg ;; scalar nand -> xor 1567 1.1 mrg (define_insn "*fuse_nand_xor" 1568 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1569 1.1 mrg (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1570 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1571 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1572 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1573 1.1 mrg "(TARGET_P10_FUSION)" 1574 1.1 mrg "@ 1575 1.1 mrg nand %3,%1,%0\;xor %3,%3,%2 1576 1.1 mrg nand %3,%1,%0\;xor %3,%3,%2 1577 1.1 mrg nand %3,%1,%0\;xor %3,%3,%2 1578 1.1 mrg nand %4,%1,%0\;xor %3,%4,%2" 1579 1.1 mrg [(set_attr "type" "fused_arith_logical") 1580 1.1 mrg (set_attr "cost" "6") 1581 1.1 mrg (set_attr "length" "8")]) 1582 1.1 mrg 1583 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1584 1.1 mrg ;; scalar nor -> xor 1585 1.1 mrg (define_insn "*fuse_nor_xor" 1586 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1587 1.1 mrg (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1588 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1589 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1590 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1591 1.1 mrg "(TARGET_P10_FUSION)" 1592 1.1 mrg "@ 1593 1.1 mrg nor %3,%1,%0\;xor %3,%3,%2 1594 1.1 mrg nor %3,%1,%0\;xor %3,%3,%2 1595 1.1 mrg nor %3,%1,%0\;xor %3,%3,%2 1596 1.1 mrg nor %4,%1,%0\;xor %3,%4,%2" 1597 1.1 mrg [(set_attr "type" "fused_arith_logical") 1598 1.1 mrg (set_attr "cost" "6") 1599 1.1 mrg (set_attr "length" "8")]) 1600 1.1 mrg 1601 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1602 1.1 mrg ;; scalar or -> xor 1603 1.1 mrg (define_insn "*fuse_or_xor" 1604 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1605 1.1 mrg (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1606 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1607 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1608 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1609 1.1 mrg "(TARGET_P10_FUSION)" 1610 1.1 mrg "@ 1611 1.1 mrg or %3,%1,%0\;xor %3,%3,%2 1612 1.1 mrg or %3,%1,%0\;xor %3,%3,%2 1613 1.1 mrg or %3,%1,%0\;xor %3,%3,%2 1614 1.1 mrg or %4,%1,%0\;xor %3,%4,%2" 1615 1.1 mrg [(set_attr "type" "fused_arith_logical") 1616 1.1 mrg (set_attr "cost" "6") 1617 1.1 mrg (set_attr "length" "8")]) 1618 1.1 mrg 1619 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1620 1.1 mrg ;; scalar orc -> xor 1621 1.1 mrg (define_insn "*fuse_orc_xor" 1622 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1623 1.1 mrg (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1624 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1625 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1626 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1627 1.1 mrg "(TARGET_P10_FUSION)" 1628 1.1 mrg "@ 1629 1.1 mrg orc %3,%1,%0\;xor %3,%3,%2 1630 1.1 mrg orc %3,%1,%0\;xor %3,%3,%2 1631 1.1 mrg orc %3,%1,%0\;xor %3,%3,%2 1632 1.1 mrg orc %4,%1,%0\;xor %3,%4,%2" 1633 1.1 mrg [(set_attr "type" "fused_arith_logical") 1634 1.1 mrg (set_attr "cost" "6") 1635 1.1 mrg (set_attr "length" "8")]) 1636 1.1 mrg 1637 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1638 1.1 mrg ;; scalar xor -> xor 1639 1.1 mrg (define_insn "*fuse_xor_xor" 1640 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1641 1.1 mrg (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1642 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 1643 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1644 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1645 1.1 mrg "(TARGET_P10_FUSION)" 1646 1.1 mrg "@ 1647 1.1 mrg xor %3,%1,%0\;xor %3,%3,%2 1648 1.1 mrg xor %3,%1,%0\;xor %3,%3,%2 1649 1.1 mrg xor %3,%1,%0\;xor %3,%3,%2 1650 1.1 mrg xor %4,%1,%0\;xor %3,%4,%2" 1651 1.1 mrg [(set_attr "type" "fused_arith_logical") 1652 1.1 mrg (set_attr "cost" "6") 1653 1.1 mrg (set_attr "length" "8")]) 1654 1.1 mrg 1655 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1656 1.1 mrg ;; scalar and -> add 1657 1.1 mrg (define_insn "*fuse_and_add" 1658 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1659 1.1 mrg (plus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1660 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1661 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1662 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1663 1.1 mrg "(TARGET_P10_FUSION)" 1664 1.1 mrg "@ 1665 1.1 mrg and %3,%1,%0\;add %3,%3,%2 1666 1.1 mrg and %3,%1,%0\;add %3,%3,%2 1667 1.1 mrg and %3,%1,%0\;add %3,%3,%2 1668 1.1 mrg and %4,%1,%0\;add %3,%4,%2" 1669 1.1 mrg [(set_attr "type" "fused_arith_logical") 1670 1.1 mrg (set_attr "cost" "6") 1671 1.1 mrg (set_attr "length" "8")]) 1672 1.1 mrg 1673 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1674 1.1 mrg ;; scalar nand -> add 1675 1.1 mrg (define_insn "*fuse_nand_add" 1676 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1677 1.1 mrg (plus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1678 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1679 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1680 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1681 1.1 mrg "(TARGET_P10_FUSION)" 1682 1.1 mrg "@ 1683 1.1 mrg nand %3,%1,%0\;add %3,%3,%2 1684 1.1 mrg nand %3,%1,%0\;add %3,%3,%2 1685 1.1 mrg nand %3,%1,%0\;add %3,%3,%2 1686 1.1 mrg nand %4,%1,%0\;add %3,%4,%2" 1687 1.1 mrg [(set_attr "type" "fused_arith_logical") 1688 1.1 mrg (set_attr "cost" "6") 1689 1.1 mrg (set_attr "length" "8")]) 1690 1.1 mrg 1691 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1692 1.1 mrg ;; scalar nor -> add 1693 1.1 mrg (define_insn "*fuse_nor_add" 1694 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1695 1.1 mrg (plus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1696 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1697 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1698 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1699 1.1 mrg "(TARGET_P10_FUSION)" 1700 1.1 mrg "@ 1701 1.1 mrg nor %3,%1,%0\;add %3,%3,%2 1702 1.1 mrg nor %3,%1,%0\;add %3,%3,%2 1703 1.1 mrg nor %3,%1,%0\;add %3,%3,%2 1704 1.1 mrg nor %4,%1,%0\;add %3,%4,%2" 1705 1.1 mrg [(set_attr "type" "fused_arith_logical") 1706 1.1 mrg (set_attr "cost" "6") 1707 1.1 mrg (set_attr "length" "8")]) 1708 1.1 mrg 1709 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1710 1.1 mrg ;; scalar or -> add 1711 1.1 mrg (define_insn "*fuse_or_add" 1712 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1713 1.1 mrg (plus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1714 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1715 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1716 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1717 1.1 mrg "(TARGET_P10_FUSION)" 1718 1.1 mrg "@ 1719 1.1 mrg or %3,%1,%0\;add %3,%3,%2 1720 1.1 mrg or %3,%1,%0\;add %3,%3,%2 1721 1.1 mrg or %3,%1,%0\;add %3,%3,%2 1722 1.1 mrg or %4,%1,%0\;add %3,%4,%2" 1723 1.1 mrg [(set_attr "type" "fused_arith_logical") 1724 1.1 mrg (set_attr "cost" "6") 1725 1.1 mrg (set_attr "length" "8")]) 1726 1.1 mrg 1727 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1728 1.1 mrg ;; scalar and -> subf 1729 1.1 mrg (define_insn "*fuse_and_subf" 1730 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1731 1.1 mrg (minus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1732 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1733 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1734 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1735 1.1 mrg "(TARGET_P10_FUSION)" 1736 1.1 mrg "@ 1737 1.1 mrg and %3,%1,%0\;subf %3,%2,%3 1738 1.1 mrg and %3,%1,%0\;subf %3,%2,%3 1739 1.1 mrg and %3,%1,%0\;subf %3,%2,%3 1740 1.1 mrg and %4,%1,%0\;subf %3,%2,%4" 1741 1.1 mrg [(set_attr "type" "fused_arith_logical") 1742 1.1 mrg (set_attr "cost" "6") 1743 1.1 mrg (set_attr "length" "8")]) 1744 1.1 mrg 1745 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1746 1.1 mrg ;; scalar nand -> subf 1747 1.1 mrg (define_insn "*fuse_nand_subf" 1748 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1749 1.1 mrg (minus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1750 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1751 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1752 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1753 1.1 mrg "(TARGET_P10_FUSION)" 1754 1.1 mrg "@ 1755 1.1 mrg nand %3,%1,%0\;subf %3,%2,%3 1756 1.1 mrg nand %3,%1,%0\;subf %3,%2,%3 1757 1.1 mrg nand %3,%1,%0\;subf %3,%2,%3 1758 1.1 mrg nand %4,%1,%0\;subf %3,%2,%4" 1759 1.1 mrg [(set_attr "type" "fused_arith_logical") 1760 1.1 mrg (set_attr "cost" "6") 1761 1.1 mrg (set_attr "length" "8")]) 1762 1.1 mrg 1763 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1764 1.1 mrg ;; scalar nor -> subf 1765 1.1 mrg (define_insn "*fuse_nor_subf" 1766 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1767 1.1 mrg (minus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1768 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1769 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1770 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1771 1.1 mrg "(TARGET_P10_FUSION)" 1772 1.1 mrg "@ 1773 1.1 mrg nor %3,%1,%0\;subf %3,%2,%3 1774 1.1 mrg nor %3,%1,%0\;subf %3,%2,%3 1775 1.1 mrg nor %3,%1,%0\;subf %3,%2,%3 1776 1.1 mrg nor %4,%1,%0\;subf %3,%2,%4" 1777 1.1 mrg [(set_attr "type" "fused_arith_logical") 1778 1.1 mrg (set_attr "cost" "6") 1779 1.1 mrg (set_attr "length" "8")]) 1780 1.1 mrg 1781 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1782 1.1 mrg ;; scalar or -> subf 1783 1.1 mrg (define_insn "*fuse_or_subf" 1784 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1785 1.1 mrg (minus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1786 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1787 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1788 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1789 1.1 mrg "(TARGET_P10_FUSION)" 1790 1.1 mrg "@ 1791 1.1 mrg or %3,%1,%0\;subf %3,%2,%3 1792 1.1 mrg or %3,%1,%0\;subf %3,%2,%3 1793 1.1 mrg or %3,%1,%0\;subf %3,%2,%3 1794 1.1 mrg or %4,%1,%0\;subf %3,%2,%4" 1795 1.1 mrg [(set_attr "type" "fused_arith_logical") 1796 1.1 mrg (set_attr "cost" "6") 1797 1.1 mrg (set_attr "length" "8")]) 1798 1.1 mrg 1799 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1800 1.1 mrg ;; scalar and -> rsubf 1801 1.1 mrg (define_insn "*fuse_and_rsubf" 1802 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1803 1.1 mrg (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1804 1.1 mrg (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1805 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1806 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1807 1.1 mrg "(TARGET_P10_FUSION)" 1808 1.1 mrg "@ 1809 1.1 mrg and %3,%1,%0\;subf %3,%3,%2 1810 1.1 mrg and %3,%1,%0\;subf %3,%3,%2 1811 1.1 mrg and %3,%1,%0\;subf %3,%3,%2 1812 1.1 mrg and %4,%1,%0\;subf %3,%4,%2" 1813 1.1 mrg [(set_attr "type" "fused_arith_logical") 1814 1.1 mrg (set_attr "cost" "6") 1815 1.1 mrg (set_attr "length" "8")]) 1816 1.1 mrg 1817 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1818 1.1 mrg ;; scalar nand -> rsubf 1819 1.1 mrg (define_insn "*fuse_nand_rsubf" 1820 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1821 1.1 mrg (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1822 1.1 mrg (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1823 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) 1824 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1825 1.1 mrg "(TARGET_P10_FUSION)" 1826 1.1 mrg "@ 1827 1.1 mrg nand %3,%1,%0\;subf %3,%3,%2 1828 1.1 mrg nand %3,%1,%0\;subf %3,%3,%2 1829 1.1 mrg nand %3,%1,%0\;subf %3,%3,%2 1830 1.1 mrg nand %4,%1,%0\;subf %3,%4,%2" 1831 1.1 mrg [(set_attr "type" "fused_arith_logical") 1832 1.1 mrg (set_attr "cost" "6") 1833 1.1 mrg (set_attr "length" "8")]) 1834 1.1 mrg 1835 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1836 1.1 mrg ;; scalar nor -> rsubf 1837 1.1 mrg (define_insn "*fuse_nor_rsubf" 1838 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1839 1.1 mrg (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1840 1.1 mrg (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1841 1.1 mrg (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) 1842 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1843 1.1 mrg "(TARGET_P10_FUSION)" 1844 1.1 mrg "@ 1845 1.1 mrg nor %3,%1,%0\;subf %3,%3,%2 1846 1.1 mrg nor %3,%1,%0\;subf %3,%3,%2 1847 1.1 mrg nor %3,%1,%0\;subf %3,%3,%2 1848 1.1 mrg nor %4,%1,%0\;subf %3,%4,%2" 1849 1.1 mrg [(set_attr "type" "fused_arith_logical") 1850 1.1 mrg (set_attr "cost" "6") 1851 1.1 mrg (set_attr "length" "8")]) 1852 1.1 mrg 1853 1.1 mrg ;; logical-add fusion pattern generated by gen_logical_addsubf 1854 1.1 mrg ;; scalar or -> rsubf 1855 1.1 mrg (define_insn "*fuse_or_rsubf" 1856 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1857 1.1 mrg (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1858 1.1 mrg (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1859 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1860 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1861 1.1 mrg "(TARGET_P10_FUSION)" 1862 1.1 mrg "@ 1863 1.1 mrg or %3,%1,%0\;subf %3,%3,%2 1864 1.1 mrg or %3,%1,%0\;subf %3,%3,%2 1865 1.1 mrg or %3,%1,%0\;subf %3,%3,%2 1866 1.1 mrg or %4,%1,%0\;subf %3,%4,%2" 1867 1.1 mrg [(set_attr "type" "fused_arith_logical") 1868 1.1 mrg (set_attr "cost" "6") 1869 1.1 mrg (set_attr "length" "8")]) 1870 1.1 mrg 1871 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1872 1.1 mrg ;; vector vand -> vand 1873 1.1 mrg (define_insn "*fuse_vand_vand" 1874 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1875 1.1 mrg (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 1876 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 1877 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1878 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1879 1.1 mrg "(TARGET_P10_FUSION)" 1880 1.1 mrg "@ 1881 1.1 mrg vand %3,%1,%0\;vand %3,%3,%2 1882 1.1 mrg vand %3,%1,%0\;vand %3,%3,%2 1883 1.1 mrg vand %3,%1,%0\;vand %3,%3,%2 1884 1.1 mrg vand %4,%1,%0\;vand %3,%4,%2" 1885 1.1 mrg [(set_attr "type" "fused_vector") 1886 1.1 mrg (set_attr "cost" "6") 1887 1.1 mrg (set_attr "length" "8")]) 1888 1.1 mrg 1889 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1890 1.1 mrg ;; vector vandc -> vand 1891 1.1 mrg (define_insn "*fuse_vandc_vand" 1892 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1893 1.1 mrg (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1894 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 1895 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1896 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1897 1.1 mrg "(TARGET_P10_FUSION)" 1898 1.1 mrg "@ 1899 1.1 mrg vandc %3,%1,%0\;vand %3,%3,%2 1900 1.1 mrg vandc %3,%1,%0\;vand %3,%3,%2 1901 1.1 mrg vandc %3,%1,%0\;vand %3,%3,%2 1902 1.1 mrg vandc %4,%1,%0\;vand %3,%4,%2" 1903 1.1 mrg [(set_attr "type" "fused_vector") 1904 1.1 mrg (set_attr "cost" "6") 1905 1.1 mrg (set_attr "length" "8")]) 1906 1.1 mrg 1907 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1908 1.1 mrg ;; vector veqv -> vand 1909 1.1 mrg (define_insn "*fuse_veqv_vand" 1910 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1911 1.1 mrg (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 1912 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 1913 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1914 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1915 1.1 mrg "(TARGET_P10_FUSION)" 1916 1.1 mrg "@ 1917 1.1 mrg veqv %3,%1,%0\;vand %3,%3,%2 1918 1.1 mrg veqv %3,%1,%0\;vand %3,%3,%2 1919 1.1 mrg veqv %3,%1,%0\;vand %3,%3,%2 1920 1.1 mrg veqv %4,%1,%0\;vand %3,%4,%2" 1921 1.1 mrg [(set_attr "type" "fused_vector") 1922 1.1 mrg (set_attr "cost" "6") 1923 1.1 mrg (set_attr "length" "8")]) 1924 1.1 mrg 1925 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1926 1.1 mrg ;; vector vnand -> vand 1927 1.1 mrg (define_insn "*fuse_vnand_vand" 1928 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1929 1.1 mrg (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1930 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 1931 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1932 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1933 1.1 mrg "(TARGET_P10_FUSION)" 1934 1.1 mrg "@ 1935 1.1 mrg vnand %3,%1,%0\;vand %3,%3,%2 1936 1.1 mrg vnand %3,%1,%0\;vand %3,%3,%2 1937 1.1 mrg vnand %3,%1,%0\;vand %3,%3,%2 1938 1.1 mrg vnand %4,%1,%0\;vand %3,%4,%2" 1939 1.1 mrg [(set_attr "type" "fused_vector") 1940 1.1 mrg (set_attr "cost" "6") 1941 1.1 mrg (set_attr "length" "8")]) 1942 1.1 mrg 1943 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1944 1.1 mrg ;; vector vnor -> vand 1945 1.1 mrg (define_insn "*fuse_vnor_vand" 1946 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1947 1.1 mrg (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1948 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 1949 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1950 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1951 1.1 mrg "(TARGET_P10_FUSION)" 1952 1.1 mrg "@ 1953 1.1 mrg vnor %3,%1,%0\;vand %3,%3,%2 1954 1.1 mrg vnor %3,%1,%0\;vand %3,%3,%2 1955 1.1 mrg vnor %3,%1,%0\;vand %3,%3,%2 1956 1.1 mrg vnor %4,%1,%0\;vand %3,%4,%2" 1957 1.1 mrg [(set_attr "type" "fused_vector") 1958 1.1 mrg (set_attr "cost" "6") 1959 1.1 mrg (set_attr "length" "8")]) 1960 1.1 mrg 1961 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1962 1.1 mrg ;; vector vor -> vand 1963 1.1 mrg (define_insn "*fuse_vor_vand" 1964 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1965 1.1 mrg (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 1966 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 1967 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1968 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1969 1.1 mrg "(TARGET_P10_FUSION)" 1970 1.1 mrg "@ 1971 1.1 mrg vor %3,%1,%0\;vand %3,%3,%2 1972 1.1 mrg vor %3,%1,%0\;vand %3,%3,%2 1973 1.1 mrg vor %3,%1,%0\;vand %3,%3,%2 1974 1.1 mrg vor %4,%1,%0\;vand %3,%4,%2" 1975 1.1 mrg [(set_attr "type" "fused_vector") 1976 1.1 mrg (set_attr "cost" "6") 1977 1.1 mrg (set_attr "length" "8")]) 1978 1.1 mrg 1979 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1980 1.1 mrg ;; vector vorc -> vand 1981 1.1 mrg (define_insn "*fuse_vorc_vand" 1982 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1983 1.1 mrg (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1984 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 1985 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1986 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1987 1.1 mrg "(TARGET_P10_FUSION)" 1988 1.1 mrg "@ 1989 1.1 mrg vorc %3,%1,%0\;vand %3,%3,%2 1990 1.1 mrg vorc %3,%1,%0\;vand %3,%3,%2 1991 1.1 mrg vorc %3,%1,%0\;vand %3,%3,%2 1992 1.1 mrg vorc %4,%1,%0\;vand %3,%4,%2" 1993 1.1 mrg [(set_attr "type" "fused_vector") 1994 1.1 mrg (set_attr "cost" "6") 1995 1.1 mrg (set_attr "length" "8")]) 1996 1.1 mrg 1997 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 1998 1.1 mrg ;; vector vxor -> vand 1999 1.1 mrg (define_insn "*fuse_vxor_vand" 2000 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2001 1.1 mrg (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2002 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2003 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2004 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2005 1.1 mrg "(TARGET_P10_FUSION)" 2006 1.1 mrg "@ 2007 1.1 mrg vxor %3,%1,%0\;vand %3,%3,%2 2008 1.1 mrg vxor %3,%1,%0\;vand %3,%3,%2 2009 1.1 mrg vxor %3,%1,%0\;vand %3,%3,%2 2010 1.1 mrg vxor %4,%1,%0\;vand %3,%4,%2" 2011 1.1 mrg [(set_attr "type" "fused_vector") 2012 1.1 mrg (set_attr "cost" "6") 2013 1.1 mrg (set_attr "length" "8")]) 2014 1.1 mrg 2015 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2016 1.1 mrg ;; vector vand -> vandc 2017 1.1 mrg (define_insn "*fuse_vand_vandc" 2018 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2019 1.1 mrg (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2020 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2021 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2022 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2023 1.1 mrg "(TARGET_P10_FUSION)" 2024 1.1 mrg "@ 2025 1.1 mrg vand %3,%1,%0\;vandc %3,%3,%2 2026 1.1 mrg vand %3,%1,%0\;vandc %3,%3,%2 2027 1.1 mrg vand %3,%1,%0\;vandc %3,%3,%2 2028 1.1 mrg vand %4,%1,%0\;vandc %3,%4,%2" 2029 1.1 mrg [(set_attr "type" "fused_vector") 2030 1.1 mrg (set_attr "cost" "6") 2031 1.1 mrg (set_attr "length" "8")]) 2032 1.1 mrg 2033 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2034 1.1 mrg ;; vector vandc -> vandc 2035 1.1 mrg (define_insn "*fuse_vandc_vandc" 2036 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2037 1.1 mrg (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2038 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2039 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2040 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2041 1.1 mrg "(TARGET_P10_FUSION)" 2042 1.1 mrg "@ 2043 1.1 mrg vandc %3,%1,%0\;vandc %3,%3,%2 2044 1.1 mrg vandc %3,%1,%0\;vandc %3,%3,%2 2045 1.1 mrg vandc %3,%1,%0\;vandc %3,%3,%2 2046 1.1 mrg vandc %4,%1,%0\;vandc %3,%4,%2" 2047 1.1 mrg [(set_attr "type" "fused_vector") 2048 1.1 mrg (set_attr "cost" "6") 2049 1.1 mrg (set_attr "length" "8")]) 2050 1.1 mrg 2051 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2052 1.1 mrg ;; vector veqv -> vandc 2053 1.1 mrg (define_insn "*fuse_veqv_vandc" 2054 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2055 1.1 mrg (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2056 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2057 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2058 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2059 1.1 mrg "(TARGET_P10_FUSION)" 2060 1.1 mrg "@ 2061 1.1 mrg veqv %3,%1,%0\;vandc %3,%3,%2 2062 1.1 mrg veqv %3,%1,%0\;vandc %3,%3,%2 2063 1.1 mrg veqv %3,%1,%0\;vandc %3,%3,%2 2064 1.1 mrg veqv %4,%1,%0\;vandc %3,%4,%2" 2065 1.1 mrg [(set_attr "type" "fused_vector") 2066 1.1 mrg (set_attr "cost" "6") 2067 1.1 mrg (set_attr "length" "8")]) 2068 1.1 mrg 2069 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2070 1.1 mrg ;; vector vnand -> vandc 2071 1.1 mrg (define_insn "*fuse_vnand_vandc" 2072 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2073 1.1 mrg (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2074 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2075 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2076 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2077 1.1 mrg "(TARGET_P10_FUSION)" 2078 1.1 mrg "@ 2079 1.1 mrg vnand %3,%1,%0\;vandc %3,%3,%2 2080 1.1 mrg vnand %3,%1,%0\;vandc %3,%3,%2 2081 1.1 mrg vnand %3,%1,%0\;vandc %3,%3,%2 2082 1.1 mrg vnand %4,%1,%0\;vandc %3,%4,%2" 2083 1.1 mrg [(set_attr "type" "fused_vector") 2084 1.1 mrg (set_attr "cost" "6") 2085 1.1 mrg (set_attr "length" "8")]) 2086 1.1 mrg 2087 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2088 1.1 mrg ;; vector vnor -> vandc 2089 1.1 mrg (define_insn "*fuse_vnor_vandc" 2090 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2091 1.1 mrg (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2092 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2093 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2094 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2095 1.1 mrg "(TARGET_P10_FUSION)" 2096 1.1 mrg "@ 2097 1.1 mrg vnor %3,%1,%0\;vandc %3,%3,%2 2098 1.1 mrg vnor %3,%1,%0\;vandc %3,%3,%2 2099 1.1 mrg vnor %3,%1,%0\;vandc %3,%3,%2 2100 1.1 mrg vnor %4,%1,%0\;vandc %3,%4,%2" 2101 1.1 mrg [(set_attr "type" "fused_vector") 2102 1.1 mrg (set_attr "cost" "6") 2103 1.1 mrg (set_attr "length" "8")]) 2104 1.1 mrg 2105 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2106 1.1 mrg ;; vector vor -> vandc 2107 1.1 mrg (define_insn "*fuse_vor_vandc" 2108 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2109 1.1 mrg (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2110 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2111 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2112 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2113 1.1 mrg "(TARGET_P10_FUSION)" 2114 1.1 mrg "@ 2115 1.1 mrg vor %3,%1,%0\;vandc %3,%3,%2 2116 1.1 mrg vor %3,%1,%0\;vandc %3,%3,%2 2117 1.1 mrg vor %3,%1,%0\;vandc %3,%3,%2 2118 1.1 mrg vor %4,%1,%0\;vandc %3,%4,%2" 2119 1.1 mrg [(set_attr "type" "fused_vector") 2120 1.1 mrg (set_attr "cost" "6") 2121 1.1 mrg (set_attr "length" "8")]) 2122 1.1 mrg 2123 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2124 1.1 mrg ;; vector vorc -> vandc 2125 1.1 mrg (define_insn "*fuse_vorc_vandc" 2126 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2127 1.1 mrg (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2128 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2129 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2130 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2131 1.1 mrg "(TARGET_P10_FUSION)" 2132 1.1 mrg "@ 2133 1.1 mrg vorc %3,%1,%0\;vandc %3,%3,%2 2134 1.1 mrg vorc %3,%1,%0\;vandc %3,%3,%2 2135 1.1 mrg vorc %3,%1,%0\;vandc %3,%3,%2 2136 1.1 mrg vorc %4,%1,%0\;vandc %3,%4,%2" 2137 1.1 mrg [(set_attr "type" "fused_vector") 2138 1.1 mrg (set_attr "cost" "6") 2139 1.1 mrg (set_attr "length" "8")]) 2140 1.1 mrg 2141 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2142 1.1 mrg ;; vector vxor -> vandc 2143 1.1 mrg (define_insn "*fuse_vxor_vandc" 2144 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2145 1.1 mrg (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2146 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2147 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2148 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2149 1.1 mrg "(TARGET_P10_FUSION)" 2150 1.1 mrg "@ 2151 1.1 mrg vxor %3,%1,%0\;vandc %3,%3,%2 2152 1.1 mrg vxor %3,%1,%0\;vandc %3,%3,%2 2153 1.1 mrg vxor %3,%1,%0\;vandc %3,%3,%2 2154 1.1 mrg vxor %4,%1,%0\;vandc %3,%4,%2" 2155 1.1 mrg [(set_attr "type" "fused_vector") 2156 1.1 mrg (set_attr "cost" "6") 2157 1.1 mrg (set_attr "length" "8")]) 2158 1.1 mrg 2159 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2160 1.1 mrg ;; vector vand -> veqv 2161 1.1 mrg (define_insn "*fuse_vand_veqv" 2162 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2163 1.1 mrg (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2164 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2165 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2166 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2167 1.1 mrg "(TARGET_P10_FUSION)" 2168 1.1 mrg "@ 2169 1.1 mrg vand %3,%1,%0\;veqv %3,%3,%2 2170 1.1 mrg vand %3,%1,%0\;veqv %3,%3,%2 2171 1.1 mrg vand %3,%1,%0\;veqv %3,%3,%2 2172 1.1 mrg vand %4,%1,%0\;veqv %3,%4,%2" 2173 1.1 mrg [(set_attr "type" "fused_vector") 2174 1.1 mrg (set_attr "cost" "6") 2175 1.1 mrg (set_attr "length" "8")]) 2176 1.1 mrg 2177 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2178 1.1 mrg ;; vector vandc -> veqv 2179 1.1 mrg (define_insn "*fuse_vandc_veqv" 2180 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2181 1.1 mrg (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2182 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2183 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2184 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2185 1.1 mrg "(TARGET_P10_FUSION)" 2186 1.1 mrg "@ 2187 1.1 mrg vandc %3,%1,%0\;veqv %3,%3,%2 2188 1.1 mrg vandc %3,%1,%0\;veqv %3,%3,%2 2189 1.1 mrg vandc %3,%1,%0\;veqv %3,%3,%2 2190 1.1 mrg vandc %4,%1,%0\;veqv %3,%4,%2" 2191 1.1 mrg [(set_attr "type" "fused_vector") 2192 1.1 mrg (set_attr "cost" "6") 2193 1.1 mrg (set_attr "length" "8")]) 2194 1.1 mrg 2195 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2196 1.1 mrg ;; vector veqv -> veqv 2197 1.1 mrg (define_insn "*fuse_veqv_veqv" 2198 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2199 1.1 mrg (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2200 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) 2201 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2202 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2203 1.1 mrg "(TARGET_P10_FUSION)" 2204 1.1 mrg "@ 2205 1.1 mrg veqv %3,%1,%0\;veqv %3,%3,%2 2206 1.1 mrg veqv %3,%1,%0\;veqv %3,%3,%2 2207 1.1 mrg veqv %3,%1,%0\;veqv %3,%3,%2 2208 1.1 mrg veqv %4,%1,%0\;veqv %3,%4,%2" 2209 1.1 mrg [(set_attr "type" "fused_vector") 2210 1.1 mrg (set_attr "cost" "6") 2211 1.1 mrg (set_attr "length" "8")]) 2212 1.1 mrg 2213 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2214 1.1 mrg ;; vector vnand -> veqv 2215 1.1 mrg (define_insn "*fuse_vnand_veqv" 2216 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2217 1.1 mrg (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2218 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2219 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2220 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2221 1.1 mrg "(TARGET_P10_FUSION)" 2222 1.1 mrg "@ 2223 1.1 mrg vnand %3,%1,%0\;veqv %3,%3,%2 2224 1.1 mrg vnand %3,%1,%0\;veqv %3,%3,%2 2225 1.1 mrg vnand %3,%1,%0\;veqv %3,%3,%2 2226 1.1 mrg vnand %4,%1,%0\;veqv %3,%4,%2" 2227 1.1 mrg [(set_attr "type" "fused_vector") 2228 1.1 mrg (set_attr "cost" "6") 2229 1.1 mrg (set_attr "length" "8")]) 2230 1.1 mrg 2231 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2232 1.1 mrg ;; vector vnor -> veqv 2233 1.1 mrg (define_insn "*fuse_vnor_veqv" 2234 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2235 1.1 mrg (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2236 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2237 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2238 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2239 1.1 mrg "(TARGET_P10_FUSION)" 2240 1.1 mrg "@ 2241 1.1 mrg vnor %3,%1,%0\;veqv %3,%3,%2 2242 1.1 mrg vnor %3,%1,%0\;veqv %3,%3,%2 2243 1.1 mrg vnor %3,%1,%0\;veqv %3,%3,%2 2244 1.1 mrg vnor %4,%1,%0\;veqv %3,%4,%2" 2245 1.1 mrg [(set_attr "type" "fused_vector") 2246 1.1 mrg (set_attr "cost" "6") 2247 1.1 mrg (set_attr "length" "8")]) 2248 1.1 mrg 2249 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2250 1.1 mrg ;; vector vor -> veqv 2251 1.1 mrg (define_insn "*fuse_vor_veqv" 2252 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2253 1.1 mrg (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2254 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2255 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2256 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2257 1.1 mrg "(TARGET_P10_FUSION)" 2258 1.1 mrg "@ 2259 1.1 mrg vor %3,%1,%0\;veqv %3,%3,%2 2260 1.1 mrg vor %3,%1,%0\;veqv %3,%3,%2 2261 1.1 mrg vor %3,%1,%0\;veqv %3,%3,%2 2262 1.1 mrg vor %4,%1,%0\;veqv %3,%4,%2" 2263 1.1 mrg [(set_attr "type" "fused_vector") 2264 1.1 mrg (set_attr "cost" "6") 2265 1.1 mrg (set_attr "length" "8")]) 2266 1.1 mrg 2267 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2268 1.1 mrg ;; vector vorc -> veqv 2269 1.1 mrg (define_insn "*fuse_vorc_veqv" 2270 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2271 1.1 mrg (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2272 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2273 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2274 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2275 1.1 mrg "(TARGET_P10_FUSION)" 2276 1.1 mrg "@ 2277 1.1 mrg vorc %3,%1,%0\;veqv %3,%3,%2 2278 1.1 mrg vorc %3,%1,%0\;veqv %3,%3,%2 2279 1.1 mrg vorc %3,%1,%0\;veqv %3,%3,%2 2280 1.1 mrg vorc %4,%1,%0\;veqv %3,%4,%2" 2281 1.1 mrg [(set_attr "type" "fused_vector") 2282 1.1 mrg (set_attr "cost" "6") 2283 1.1 mrg (set_attr "length" "8")]) 2284 1.1 mrg 2285 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2286 1.1 mrg ;; vector vxor -> veqv 2287 1.1 mrg (define_insn "*fuse_vxor_veqv" 2288 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2289 1.1 mrg (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2290 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2291 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2292 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2293 1.1 mrg "(TARGET_P10_FUSION)" 2294 1.1 mrg "@ 2295 1.1 mrg vxor %3,%1,%0\;veqv %3,%3,%2 2296 1.1 mrg vxor %3,%1,%0\;veqv %3,%3,%2 2297 1.1 mrg vxor %3,%1,%0\;veqv %3,%3,%2 2298 1.1 mrg vxor %4,%1,%0\;veqv %3,%4,%2" 2299 1.1 mrg [(set_attr "type" "fused_vector") 2300 1.1 mrg (set_attr "cost" "6") 2301 1.1 mrg (set_attr "length" "8")]) 2302 1.1 mrg 2303 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2304 1.1 mrg ;; vector vand -> vnand 2305 1.1 mrg (define_insn "*fuse_vand_vnand" 2306 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2307 1.1 mrg (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2308 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2309 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2310 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2311 1.1 mrg "(TARGET_P10_FUSION)" 2312 1.1 mrg "@ 2313 1.1 mrg vand %3,%1,%0\;vnand %3,%3,%2 2314 1.1 mrg vand %3,%1,%0\;vnand %3,%3,%2 2315 1.1 mrg vand %3,%1,%0\;vnand %3,%3,%2 2316 1.1 mrg vand %4,%1,%0\;vnand %3,%4,%2" 2317 1.1 mrg [(set_attr "type" "fused_vector") 2318 1.1 mrg (set_attr "cost" "6") 2319 1.1 mrg (set_attr "length" "8")]) 2320 1.1 mrg 2321 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2322 1.1 mrg ;; vector vandc -> vnand 2323 1.1 mrg (define_insn "*fuse_vandc_vnand" 2324 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2325 1.1 mrg (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2326 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2327 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2328 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2329 1.1 mrg "(TARGET_P10_FUSION)" 2330 1.1 mrg "@ 2331 1.1 mrg vandc %3,%1,%0\;vnand %3,%3,%2 2332 1.1 mrg vandc %3,%1,%0\;vnand %3,%3,%2 2333 1.1 mrg vandc %3,%1,%0\;vnand %3,%3,%2 2334 1.1 mrg vandc %4,%1,%0\;vnand %3,%4,%2" 2335 1.1 mrg [(set_attr "type" "fused_vector") 2336 1.1 mrg (set_attr "cost" "6") 2337 1.1 mrg (set_attr "length" "8")]) 2338 1.1 mrg 2339 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2340 1.1 mrg ;; vector veqv -> vnand 2341 1.1 mrg (define_insn "*fuse_veqv_vnand" 2342 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2343 1.1 mrg (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2344 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2345 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2346 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2347 1.1 mrg "(TARGET_P10_FUSION)" 2348 1.1 mrg "@ 2349 1.1 mrg veqv %3,%1,%0\;vnand %3,%3,%2 2350 1.1 mrg veqv %3,%1,%0\;vnand %3,%3,%2 2351 1.1 mrg veqv %3,%1,%0\;vnand %3,%3,%2 2352 1.1 mrg veqv %4,%1,%0\;vnand %3,%4,%2" 2353 1.1 mrg [(set_attr "type" "fused_vector") 2354 1.1 mrg (set_attr "cost" "6") 2355 1.1 mrg (set_attr "length" "8")]) 2356 1.1 mrg 2357 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2358 1.1 mrg ;; vector vnand -> vnand 2359 1.1 mrg (define_insn "*fuse_vnand_vnand" 2360 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2361 1.1 mrg (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2362 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2363 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2364 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2365 1.1 mrg "(TARGET_P10_FUSION)" 2366 1.1 mrg "@ 2367 1.1 mrg vnand %3,%1,%0\;vnand %3,%3,%2 2368 1.1 mrg vnand %3,%1,%0\;vnand %3,%3,%2 2369 1.1 mrg vnand %3,%1,%0\;vnand %3,%3,%2 2370 1.1 mrg vnand %4,%1,%0\;vnand %3,%4,%2" 2371 1.1 mrg [(set_attr "type" "fused_vector") 2372 1.1 mrg (set_attr "cost" "6") 2373 1.1 mrg (set_attr "length" "8")]) 2374 1.1 mrg 2375 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2376 1.1 mrg ;; vector vnor -> vnand 2377 1.1 mrg (define_insn "*fuse_vnor_vnand" 2378 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2379 1.1 mrg (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2380 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2381 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2382 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2383 1.1 mrg "(TARGET_P10_FUSION)" 2384 1.1 mrg "@ 2385 1.1 mrg vnor %3,%1,%0\;vnand %3,%3,%2 2386 1.1 mrg vnor %3,%1,%0\;vnand %3,%3,%2 2387 1.1 mrg vnor %3,%1,%0\;vnand %3,%3,%2 2388 1.1 mrg vnor %4,%1,%0\;vnand %3,%4,%2" 2389 1.1 mrg [(set_attr "type" "fused_vector") 2390 1.1 mrg (set_attr "cost" "6") 2391 1.1 mrg (set_attr "length" "8")]) 2392 1.1 mrg 2393 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2394 1.1 mrg ;; vector vor -> vnand 2395 1.1 mrg (define_insn "*fuse_vor_vnand" 2396 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2397 1.1 mrg (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2398 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2399 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2400 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2401 1.1 mrg "(TARGET_P10_FUSION)" 2402 1.1 mrg "@ 2403 1.1 mrg vor %3,%1,%0\;vnand %3,%3,%2 2404 1.1 mrg vor %3,%1,%0\;vnand %3,%3,%2 2405 1.1 mrg vor %3,%1,%0\;vnand %3,%3,%2 2406 1.1 mrg vor %4,%1,%0\;vnand %3,%4,%2" 2407 1.1 mrg [(set_attr "type" "fused_vector") 2408 1.1 mrg (set_attr "cost" "6") 2409 1.1 mrg (set_attr "length" "8")]) 2410 1.1 mrg 2411 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2412 1.1 mrg ;; vector vorc -> vnand 2413 1.1 mrg (define_insn "*fuse_vorc_vnand" 2414 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2415 1.1 mrg (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2416 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2417 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2418 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2419 1.1 mrg "(TARGET_P10_FUSION)" 2420 1.1 mrg "@ 2421 1.1 mrg vorc %3,%1,%0\;vnand %3,%3,%2 2422 1.1 mrg vorc %3,%1,%0\;vnand %3,%3,%2 2423 1.1 mrg vorc %3,%1,%0\;vnand %3,%3,%2 2424 1.1 mrg vorc %4,%1,%0\;vnand %3,%4,%2" 2425 1.1 mrg [(set_attr "type" "fused_vector") 2426 1.1 mrg (set_attr "cost" "6") 2427 1.1 mrg (set_attr "length" "8")]) 2428 1.1 mrg 2429 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2430 1.1 mrg ;; vector vxor -> vnand 2431 1.1 mrg (define_insn "*fuse_vxor_vnand" 2432 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2433 1.1 mrg (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2434 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2435 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2436 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2437 1.1 mrg "(TARGET_P10_FUSION)" 2438 1.1 mrg "@ 2439 1.1 mrg vxor %3,%1,%0\;vnand %3,%3,%2 2440 1.1 mrg vxor %3,%1,%0\;vnand %3,%3,%2 2441 1.1 mrg vxor %3,%1,%0\;vnand %3,%3,%2 2442 1.1 mrg vxor %4,%1,%0\;vnand %3,%4,%2" 2443 1.1 mrg [(set_attr "type" "fused_vector") 2444 1.1 mrg (set_attr "cost" "6") 2445 1.1 mrg (set_attr "length" "8")]) 2446 1.1 mrg 2447 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2448 1.1 mrg ;; vector vand -> vnor 2449 1.1 mrg (define_insn "*fuse_vand_vnor" 2450 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2451 1.1 mrg (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2452 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2453 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2454 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2455 1.1 mrg "(TARGET_P10_FUSION)" 2456 1.1 mrg "@ 2457 1.1 mrg vand %3,%1,%0\;vnor %3,%3,%2 2458 1.1 mrg vand %3,%1,%0\;vnor %3,%3,%2 2459 1.1 mrg vand %3,%1,%0\;vnor %3,%3,%2 2460 1.1 mrg vand %4,%1,%0\;vnor %3,%4,%2" 2461 1.1 mrg [(set_attr "type" "fused_vector") 2462 1.1 mrg (set_attr "cost" "6") 2463 1.1 mrg (set_attr "length" "8")]) 2464 1.1 mrg 2465 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2466 1.1 mrg ;; vector vandc -> vnor 2467 1.1 mrg (define_insn "*fuse_vandc_vnor" 2468 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2469 1.1 mrg (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2470 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2471 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2472 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2473 1.1 mrg "(TARGET_P10_FUSION)" 2474 1.1 mrg "@ 2475 1.1 mrg vandc %3,%1,%0\;vnor %3,%3,%2 2476 1.1 mrg vandc %3,%1,%0\;vnor %3,%3,%2 2477 1.1 mrg vandc %3,%1,%0\;vnor %3,%3,%2 2478 1.1 mrg vandc %4,%1,%0\;vnor %3,%4,%2" 2479 1.1 mrg [(set_attr "type" "fused_vector") 2480 1.1 mrg (set_attr "cost" "6") 2481 1.1 mrg (set_attr "length" "8")]) 2482 1.1 mrg 2483 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2484 1.1 mrg ;; vector veqv -> vnor 2485 1.1 mrg (define_insn "*fuse_veqv_vnor" 2486 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2487 1.1 mrg (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2488 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2489 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2490 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2491 1.1 mrg "(TARGET_P10_FUSION)" 2492 1.1 mrg "@ 2493 1.1 mrg veqv %3,%1,%0\;vnor %3,%3,%2 2494 1.1 mrg veqv %3,%1,%0\;vnor %3,%3,%2 2495 1.1 mrg veqv %3,%1,%0\;vnor %3,%3,%2 2496 1.1 mrg veqv %4,%1,%0\;vnor %3,%4,%2" 2497 1.1 mrg [(set_attr "type" "fused_vector") 2498 1.1 mrg (set_attr "cost" "6") 2499 1.1 mrg (set_attr "length" "8")]) 2500 1.1 mrg 2501 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2502 1.1 mrg ;; vector vnand -> vnor 2503 1.1 mrg (define_insn "*fuse_vnand_vnor" 2504 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2505 1.1 mrg (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2506 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2507 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2508 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2509 1.1 mrg "(TARGET_P10_FUSION)" 2510 1.1 mrg "@ 2511 1.1 mrg vnand %3,%1,%0\;vnor %3,%3,%2 2512 1.1 mrg vnand %3,%1,%0\;vnor %3,%3,%2 2513 1.1 mrg vnand %3,%1,%0\;vnor %3,%3,%2 2514 1.1 mrg vnand %4,%1,%0\;vnor %3,%4,%2" 2515 1.1 mrg [(set_attr "type" "fused_vector") 2516 1.1 mrg (set_attr "cost" "6") 2517 1.1 mrg (set_attr "length" "8")]) 2518 1.1 mrg 2519 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2520 1.1 mrg ;; vector vnor -> vnor 2521 1.1 mrg (define_insn "*fuse_vnor_vnor" 2522 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2523 1.1 mrg (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2524 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2525 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2526 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2527 1.1 mrg "(TARGET_P10_FUSION)" 2528 1.1 mrg "@ 2529 1.1 mrg vnor %3,%1,%0\;vnor %3,%3,%2 2530 1.1 mrg vnor %3,%1,%0\;vnor %3,%3,%2 2531 1.1 mrg vnor %3,%1,%0\;vnor %3,%3,%2 2532 1.1 mrg vnor %4,%1,%0\;vnor %3,%4,%2" 2533 1.1 mrg [(set_attr "type" "fused_vector") 2534 1.1 mrg (set_attr "cost" "6") 2535 1.1 mrg (set_attr "length" "8")]) 2536 1.1 mrg 2537 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2538 1.1 mrg ;; vector vor -> vnor 2539 1.1 mrg (define_insn "*fuse_vor_vnor" 2540 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2541 1.1 mrg (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2542 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2543 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2544 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2545 1.1 mrg "(TARGET_P10_FUSION)" 2546 1.1 mrg "@ 2547 1.1 mrg vor %3,%1,%0\;vnor %3,%3,%2 2548 1.1 mrg vor %3,%1,%0\;vnor %3,%3,%2 2549 1.1 mrg vor %3,%1,%0\;vnor %3,%3,%2 2550 1.1 mrg vor %4,%1,%0\;vnor %3,%4,%2" 2551 1.1 mrg [(set_attr "type" "fused_vector") 2552 1.1 mrg (set_attr "cost" "6") 2553 1.1 mrg (set_attr "length" "8")]) 2554 1.1 mrg 2555 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2556 1.1 mrg ;; vector vorc -> vnor 2557 1.1 mrg (define_insn "*fuse_vorc_vnor" 2558 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2559 1.1 mrg (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2560 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2561 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2562 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2563 1.1 mrg "(TARGET_P10_FUSION)" 2564 1.1 mrg "@ 2565 1.1 mrg vorc %3,%1,%0\;vnor %3,%3,%2 2566 1.1 mrg vorc %3,%1,%0\;vnor %3,%3,%2 2567 1.1 mrg vorc %3,%1,%0\;vnor %3,%3,%2 2568 1.1 mrg vorc %4,%1,%0\;vnor %3,%4,%2" 2569 1.1 mrg [(set_attr "type" "fused_vector") 2570 1.1 mrg (set_attr "cost" "6") 2571 1.1 mrg (set_attr "length" "8")]) 2572 1.1 mrg 2573 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2574 1.1 mrg ;; vector vxor -> vnor 2575 1.1 mrg (define_insn "*fuse_vxor_vnor" 2576 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2577 1.1 mrg (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2578 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2579 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2580 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2581 1.1 mrg "(TARGET_P10_FUSION)" 2582 1.1 mrg "@ 2583 1.1 mrg vxor %3,%1,%0\;vnor %3,%3,%2 2584 1.1 mrg vxor %3,%1,%0\;vnor %3,%3,%2 2585 1.1 mrg vxor %3,%1,%0\;vnor %3,%3,%2 2586 1.1 mrg vxor %4,%1,%0\;vnor %3,%4,%2" 2587 1.1 mrg [(set_attr "type" "fused_vector") 2588 1.1 mrg (set_attr "cost" "6") 2589 1.1 mrg (set_attr "length" "8")]) 2590 1.1 mrg 2591 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2592 1.1 mrg ;; vector vand -> vor 2593 1.1 mrg (define_insn "*fuse_vand_vor" 2594 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2595 1.1 mrg (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2596 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2597 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2598 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2599 1.1 mrg "(TARGET_P10_FUSION)" 2600 1.1 mrg "@ 2601 1.1 mrg vand %3,%1,%0\;vor %3,%3,%2 2602 1.1 mrg vand %3,%1,%0\;vor %3,%3,%2 2603 1.1 mrg vand %3,%1,%0\;vor %3,%3,%2 2604 1.1 mrg vand %4,%1,%0\;vor %3,%4,%2" 2605 1.1 mrg [(set_attr "type" "fused_vector") 2606 1.1 mrg (set_attr "cost" "6") 2607 1.1 mrg (set_attr "length" "8")]) 2608 1.1 mrg 2609 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2610 1.1 mrg ;; vector vandc -> vor 2611 1.1 mrg (define_insn "*fuse_vandc_vor" 2612 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2613 1.1 mrg (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2614 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2615 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2616 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2617 1.1 mrg "(TARGET_P10_FUSION)" 2618 1.1 mrg "@ 2619 1.1 mrg vandc %3,%1,%0\;vor %3,%3,%2 2620 1.1 mrg vandc %3,%1,%0\;vor %3,%3,%2 2621 1.1 mrg vandc %3,%1,%0\;vor %3,%3,%2 2622 1.1 mrg vandc %4,%1,%0\;vor %3,%4,%2" 2623 1.1 mrg [(set_attr "type" "fused_vector") 2624 1.1 mrg (set_attr "cost" "6") 2625 1.1 mrg (set_attr "length" "8")]) 2626 1.1 mrg 2627 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2628 1.1 mrg ;; vector veqv -> vor 2629 1.1 mrg (define_insn "*fuse_veqv_vor" 2630 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2631 1.1 mrg (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2632 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2633 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2634 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2635 1.1 mrg "(TARGET_P10_FUSION)" 2636 1.1 mrg "@ 2637 1.1 mrg veqv %3,%1,%0\;vor %3,%3,%2 2638 1.1 mrg veqv %3,%1,%0\;vor %3,%3,%2 2639 1.1 mrg veqv %3,%1,%0\;vor %3,%3,%2 2640 1.1 mrg veqv %4,%1,%0\;vor %3,%4,%2" 2641 1.1 mrg [(set_attr "type" "fused_vector") 2642 1.1 mrg (set_attr "cost" "6") 2643 1.1 mrg (set_attr "length" "8")]) 2644 1.1 mrg 2645 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2646 1.1 mrg ;; vector vnand -> vor 2647 1.1 mrg (define_insn "*fuse_vnand_vor" 2648 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2649 1.1 mrg (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2650 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2651 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2652 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2653 1.1 mrg "(TARGET_P10_FUSION)" 2654 1.1 mrg "@ 2655 1.1 mrg vnand %3,%1,%0\;vor %3,%3,%2 2656 1.1 mrg vnand %3,%1,%0\;vor %3,%3,%2 2657 1.1 mrg vnand %3,%1,%0\;vor %3,%3,%2 2658 1.1 mrg vnand %4,%1,%0\;vor %3,%4,%2" 2659 1.1 mrg [(set_attr "type" "fused_vector") 2660 1.1 mrg (set_attr "cost" "6") 2661 1.1 mrg (set_attr "length" "8")]) 2662 1.1 mrg 2663 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2664 1.1 mrg ;; vector vnor -> vor 2665 1.1 mrg (define_insn "*fuse_vnor_vor" 2666 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2667 1.1 mrg (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2668 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2669 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2670 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2671 1.1 mrg "(TARGET_P10_FUSION)" 2672 1.1 mrg "@ 2673 1.1 mrg vnor %3,%1,%0\;vor %3,%3,%2 2674 1.1 mrg vnor %3,%1,%0\;vor %3,%3,%2 2675 1.1 mrg vnor %3,%1,%0\;vor %3,%3,%2 2676 1.1 mrg vnor %4,%1,%0\;vor %3,%4,%2" 2677 1.1 mrg [(set_attr "type" "fused_vector") 2678 1.1 mrg (set_attr "cost" "6") 2679 1.1 mrg (set_attr "length" "8")]) 2680 1.1 mrg 2681 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2682 1.1 mrg ;; vector vor -> vor 2683 1.1 mrg (define_insn "*fuse_vor_vor" 2684 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2685 1.1 mrg (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2686 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 2687 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2688 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2689 1.1 mrg "(TARGET_P10_FUSION)" 2690 1.1 mrg "@ 2691 1.1 mrg vor %3,%1,%0\;vor %3,%3,%2 2692 1.1 mrg vor %3,%1,%0\;vor %3,%3,%2 2693 1.1 mrg vor %3,%1,%0\;vor %3,%3,%2 2694 1.1 mrg vor %4,%1,%0\;vor %3,%4,%2" 2695 1.1 mrg [(set_attr "type" "fused_vector") 2696 1.1 mrg (set_attr "cost" "6") 2697 1.1 mrg (set_attr "length" "8")]) 2698 1.1 mrg 2699 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2700 1.1 mrg ;; vector vorc -> vor 2701 1.1 mrg (define_insn "*fuse_vorc_vor" 2702 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2703 1.1 mrg (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2704 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2705 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2706 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2707 1.1 mrg "(TARGET_P10_FUSION)" 2708 1.1 mrg "@ 2709 1.1 mrg vorc %3,%1,%0\;vor %3,%3,%2 2710 1.1 mrg vorc %3,%1,%0\;vor %3,%3,%2 2711 1.1 mrg vorc %3,%1,%0\;vor %3,%3,%2 2712 1.1 mrg vorc %4,%1,%0\;vor %3,%4,%2" 2713 1.1 mrg [(set_attr "type" "fused_vector") 2714 1.1 mrg (set_attr "cost" "6") 2715 1.1 mrg (set_attr "length" "8")]) 2716 1.1 mrg 2717 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2718 1.1 mrg ;; vector vxor -> vor 2719 1.1 mrg (define_insn "*fuse_vxor_vor" 2720 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2721 1.1 mrg (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2722 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2723 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2724 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2725 1.1 mrg "(TARGET_P10_FUSION)" 2726 1.1 mrg "@ 2727 1.1 mrg vxor %3,%1,%0\;vor %3,%3,%2 2728 1.1 mrg vxor %3,%1,%0\;vor %3,%3,%2 2729 1.1 mrg vxor %3,%1,%0\;vor %3,%3,%2 2730 1.1 mrg vxor %4,%1,%0\;vor %3,%4,%2" 2731 1.1 mrg [(set_attr "type" "fused_vector") 2732 1.1 mrg (set_attr "cost" "6") 2733 1.1 mrg (set_attr "length" "8")]) 2734 1.1 mrg 2735 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2736 1.1 mrg ;; vector vand -> vorc 2737 1.1 mrg (define_insn "*fuse_vand_vorc" 2738 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2739 1.1 mrg (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2740 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2741 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2742 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2743 1.1 mrg "(TARGET_P10_FUSION)" 2744 1.1 mrg "@ 2745 1.1 mrg vand %3,%1,%0\;vorc %3,%3,%2 2746 1.1 mrg vand %3,%1,%0\;vorc %3,%3,%2 2747 1.1 mrg vand %3,%1,%0\;vorc %3,%3,%2 2748 1.1 mrg vand %4,%1,%0\;vorc %3,%4,%2" 2749 1.1 mrg [(set_attr "type" "fused_vector") 2750 1.1 mrg (set_attr "cost" "6") 2751 1.1 mrg (set_attr "length" "8")]) 2752 1.1 mrg 2753 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2754 1.1 mrg ;; vector vandc -> vorc 2755 1.1 mrg (define_insn "*fuse_vandc_vorc" 2756 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2757 1.1 mrg (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2758 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2759 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2760 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2761 1.1 mrg "(TARGET_P10_FUSION)" 2762 1.1 mrg "@ 2763 1.1 mrg vandc %3,%1,%0\;vorc %3,%3,%2 2764 1.1 mrg vandc %3,%1,%0\;vorc %3,%3,%2 2765 1.1 mrg vandc %3,%1,%0\;vorc %3,%3,%2 2766 1.1 mrg vandc %4,%1,%0\;vorc %3,%4,%2" 2767 1.1 mrg [(set_attr "type" "fused_vector") 2768 1.1 mrg (set_attr "cost" "6") 2769 1.1 mrg (set_attr "length" "8")]) 2770 1.1 mrg 2771 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2772 1.1 mrg ;; vector veqv -> vorc 2773 1.1 mrg (define_insn "*fuse_veqv_vorc" 2774 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2775 1.1 mrg (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2776 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2777 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2778 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2779 1.1 mrg "(TARGET_P10_FUSION)" 2780 1.1 mrg "@ 2781 1.1 mrg veqv %3,%1,%0\;vorc %3,%3,%2 2782 1.1 mrg veqv %3,%1,%0\;vorc %3,%3,%2 2783 1.1 mrg veqv %3,%1,%0\;vorc %3,%3,%2 2784 1.1 mrg veqv %4,%1,%0\;vorc %3,%4,%2" 2785 1.1 mrg [(set_attr "type" "fused_vector") 2786 1.1 mrg (set_attr "cost" "6") 2787 1.1 mrg (set_attr "length" "8")]) 2788 1.1 mrg 2789 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2790 1.1 mrg ;; vector vnand -> vorc 2791 1.1 mrg (define_insn "*fuse_vnand_vorc" 2792 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2793 1.1 mrg (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2794 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2795 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2796 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2797 1.1 mrg "(TARGET_P10_FUSION)" 2798 1.1 mrg "@ 2799 1.1 mrg vnand %3,%1,%0\;vorc %3,%3,%2 2800 1.1 mrg vnand %3,%1,%0\;vorc %3,%3,%2 2801 1.1 mrg vnand %3,%1,%0\;vorc %3,%3,%2 2802 1.1 mrg vnand %4,%1,%0\;vorc %3,%4,%2" 2803 1.1 mrg [(set_attr "type" "fused_vector") 2804 1.1 mrg (set_attr "cost" "6") 2805 1.1 mrg (set_attr "length" "8")]) 2806 1.1 mrg 2807 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2808 1.1 mrg ;; vector vnor -> vorc 2809 1.1 mrg (define_insn "*fuse_vnor_vorc" 2810 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2811 1.1 mrg (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2812 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2813 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2814 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2815 1.1 mrg "(TARGET_P10_FUSION)" 2816 1.1 mrg "@ 2817 1.1 mrg vnor %3,%1,%0\;vorc %3,%3,%2 2818 1.1 mrg vnor %3,%1,%0\;vorc %3,%3,%2 2819 1.1 mrg vnor %3,%1,%0\;vorc %3,%3,%2 2820 1.1 mrg vnor %4,%1,%0\;vorc %3,%4,%2" 2821 1.1 mrg [(set_attr "type" "fused_vector") 2822 1.1 mrg (set_attr "cost" "6") 2823 1.1 mrg (set_attr "length" "8")]) 2824 1.1 mrg 2825 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2826 1.1 mrg ;; vector vor -> vorc 2827 1.1 mrg (define_insn "*fuse_vor_vorc" 2828 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2829 1.1 mrg (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2830 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2831 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2832 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2833 1.1 mrg "(TARGET_P10_FUSION)" 2834 1.1 mrg "@ 2835 1.1 mrg vor %3,%1,%0\;vorc %3,%3,%2 2836 1.1 mrg vor %3,%1,%0\;vorc %3,%3,%2 2837 1.1 mrg vor %3,%1,%0\;vorc %3,%3,%2 2838 1.1 mrg vor %4,%1,%0\;vorc %3,%4,%2" 2839 1.1 mrg [(set_attr "type" "fused_vector") 2840 1.1 mrg (set_attr "cost" "6") 2841 1.1 mrg (set_attr "length" "8")]) 2842 1.1 mrg 2843 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2844 1.1 mrg ;; vector vorc -> vorc 2845 1.1 mrg (define_insn "*fuse_vorc_vorc" 2846 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2847 1.1 mrg (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2848 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2849 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2850 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2851 1.1 mrg "(TARGET_P10_FUSION)" 2852 1.1 mrg "@ 2853 1.1 mrg vorc %3,%1,%0\;vorc %3,%3,%2 2854 1.1 mrg vorc %3,%1,%0\;vorc %3,%3,%2 2855 1.1 mrg vorc %3,%1,%0\;vorc %3,%3,%2 2856 1.1 mrg vorc %4,%1,%0\;vorc %3,%4,%2" 2857 1.1 mrg [(set_attr "type" "fused_vector") 2858 1.1 mrg (set_attr "cost" "6") 2859 1.1 mrg (set_attr "length" "8")]) 2860 1.1 mrg 2861 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2862 1.1 mrg ;; vector vxor -> vorc 2863 1.1 mrg (define_insn "*fuse_vxor_vorc" 2864 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2865 1.1 mrg (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2866 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2867 1.1 mrg (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2868 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2869 1.1 mrg "(TARGET_P10_FUSION)" 2870 1.1 mrg "@ 2871 1.1 mrg vxor %3,%1,%0\;vorc %3,%3,%2 2872 1.1 mrg vxor %3,%1,%0\;vorc %3,%3,%2 2873 1.1 mrg vxor %3,%1,%0\;vorc %3,%3,%2 2874 1.1 mrg vxor %4,%1,%0\;vorc %3,%4,%2" 2875 1.1 mrg [(set_attr "type" "fused_vector") 2876 1.1 mrg (set_attr "cost" "6") 2877 1.1 mrg (set_attr "length" "8")]) 2878 1.1 mrg 2879 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2880 1.1 mrg ;; vector vand -> vxor 2881 1.1 mrg (define_insn "*fuse_vand_vxor" 2882 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2883 1.1 mrg (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2884 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2885 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2886 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2887 1.1 mrg "(TARGET_P10_FUSION)" 2888 1.1 mrg "@ 2889 1.1 mrg vand %3,%1,%0\;vxor %3,%3,%2 2890 1.1 mrg vand %3,%1,%0\;vxor %3,%3,%2 2891 1.1 mrg vand %3,%1,%0\;vxor %3,%3,%2 2892 1.1 mrg vand %4,%1,%0\;vxor %3,%4,%2" 2893 1.1 mrg [(set_attr "type" "fused_vector") 2894 1.1 mrg (set_attr "cost" "6") 2895 1.1 mrg (set_attr "length" "8")]) 2896 1.1 mrg 2897 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2898 1.1 mrg ;; vector vandc -> vxor 2899 1.1 mrg (define_insn "*fuse_vandc_vxor" 2900 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2901 1.1 mrg (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2902 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2903 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2904 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2905 1.1 mrg "(TARGET_P10_FUSION)" 2906 1.1 mrg "@ 2907 1.1 mrg vandc %3,%1,%0\;vxor %3,%3,%2 2908 1.1 mrg vandc %3,%1,%0\;vxor %3,%3,%2 2909 1.1 mrg vandc %3,%1,%0\;vxor %3,%3,%2 2910 1.1 mrg vandc %4,%1,%0\;vxor %3,%4,%2" 2911 1.1 mrg [(set_attr "type" "fused_vector") 2912 1.1 mrg (set_attr "cost" "6") 2913 1.1 mrg (set_attr "length" "8")]) 2914 1.1 mrg 2915 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2916 1.1 mrg ;; vector veqv -> vxor 2917 1.1 mrg (define_insn "*fuse_veqv_vxor" 2918 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2919 1.1 mrg (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2920 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2921 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2922 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2923 1.1 mrg "(TARGET_P10_FUSION)" 2924 1.1 mrg "@ 2925 1.1 mrg veqv %3,%1,%0\;vxor %3,%3,%2 2926 1.1 mrg veqv %3,%1,%0\;vxor %3,%3,%2 2927 1.1 mrg veqv %3,%1,%0\;vxor %3,%3,%2 2928 1.1 mrg veqv %4,%1,%0\;vxor %3,%4,%2" 2929 1.1 mrg [(set_attr "type" "fused_vector") 2930 1.1 mrg (set_attr "cost" "6") 2931 1.1 mrg (set_attr "length" "8")]) 2932 1.1 mrg 2933 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2934 1.1 mrg ;; vector vnand -> vxor 2935 1.1 mrg (define_insn "*fuse_vnand_vxor" 2936 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2937 1.1 mrg (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2938 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2939 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2940 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2941 1.1 mrg "(TARGET_P10_FUSION)" 2942 1.1 mrg "@ 2943 1.1 mrg vnand %3,%1,%0\;vxor %3,%3,%2 2944 1.1 mrg vnand %3,%1,%0\;vxor %3,%3,%2 2945 1.1 mrg vnand %3,%1,%0\;vxor %3,%3,%2 2946 1.1 mrg vnand %4,%1,%0\;vxor %3,%4,%2" 2947 1.1 mrg [(set_attr "type" "fused_vector") 2948 1.1 mrg (set_attr "cost" "6") 2949 1.1 mrg (set_attr "length" "8")]) 2950 1.1 mrg 2951 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2952 1.1 mrg ;; vector vnor -> vxor 2953 1.1 mrg (define_insn "*fuse_vnor_vxor" 2954 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2955 1.1 mrg (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2956 1.1 mrg (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2957 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2958 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2959 1.1 mrg "(TARGET_P10_FUSION)" 2960 1.1 mrg "@ 2961 1.1 mrg vnor %3,%1,%0\;vxor %3,%3,%2 2962 1.1 mrg vnor %3,%1,%0\;vxor %3,%3,%2 2963 1.1 mrg vnor %3,%1,%0\;vxor %3,%3,%2 2964 1.1 mrg vnor %4,%1,%0\;vxor %3,%4,%2" 2965 1.1 mrg [(set_attr "type" "fused_vector") 2966 1.1 mrg (set_attr "cost" "6") 2967 1.1 mrg (set_attr "length" "8")]) 2968 1.1 mrg 2969 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2970 1.1 mrg ;; vector vor -> vxor 2971 1.1 mrg (define_insn "*fuse_vor_vxor" 2972 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2973 1.1 mrg (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2974 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2975 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2976 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2977 1.1 mrg "(TARGET_P10_FUSION)" 2978 1.1 mrg "@ 2979 1.1 mrg vor %3,%1,%0\;vxor %3,%3,%2 2980 1.1 mrg vor %3,%1,%0\;vxor %3,%3,%2 2981 1.1 mrg vor %3,%1,%0\;vxor %3,%3,%2 2982 1.1 mrg vor %4,%1,%0\;vxor %3,%4,%2" 2983 1.1 mrg [(set_attr "type" "fused_vector") 2984 1.1 mrg (set_attr "cost" "6") 2985 1.1 mrg (set_attr "length" "8")]) 2986 1.1 mrg 2987 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 2988 1.1 mrg ;; vector vorc -> vxor 2989 1.1 mrg (define_insn "*fuse_vorc_vxor" 2990 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2991 1.1 mrg (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2992 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2993 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2994 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2995 1.1 mrg "(TARGET_P10_FUSION)" 2996 1.1 mrg "@ 2997 1.1 mrg vorc %3,%1,%0\;vxor %3,%3,%2 2998 1.1 mrg vorc %3,%1,%0\;vxor %3,%3,%2 2999 1.1 mrg vorc %3,%1,%0\;vxor %3,%3,%2 3000 1.1 mrg vorc %4,%1,%0\;vxor %3,%4,%2" 3001 1.1 mrg [(set_attr "type" "fused_vector") 3002 1.1 mrg (set_attr "cost" "6") 3003 1.1 mrg (set_attr "length" "8")]) 3004 1.1 mrg 3005 1.1 mrg ;; logical-logical fusion pattern generated by gen_logical_addsubf 3006 1.1 mrg ;; vector vxor -> vxor 3007 1.1 mrg (define_insn "*fuse_vxor_vxor" 3008 1.1 mrg [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 3009 1.1 mrg (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 3010 1.1 mrg (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 3011 1.1 mrg (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 3012 1.1 mrg (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 3013 1.1 mrg "(TARGET_P10_FUSION)" 3014 1.1 mrg "@ 3015 1.1 mrg vxor %3,%1,%0\;vxor %3,%3,%2 3016 1.1 mrg vxor %3,%1,%0\;vxor %3,%3,%2 3017 1.1 mrg vxor %3,%1,%0\;vxor %3,%3,%2 3018 1.1 mrg vxor %4,%1,%0\;vxor %3,%4,%2" 3019 1.1 mrg [(set_attr "type" "fused_vector") 3020 1.1 mrg (set_attr "cost" "6") 3021 1.1 mrg (set_attr "length" "8")]) 3022 1.1 mrg 3023 1.1 mrg ;; add-add fusion pattern generated by gen_addadd 3024 1.1 mrg (define_insn "*fuse_add_add" 3025 1.1 mrg [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 3026 1.1 mrg (plus:GPR 3027 1.1 mrg (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 3028 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 3029 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 3030 1.1 mrg (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 3031 1.1 mrg "(TARGET_P10_FUSION)" 3032 1.1 mrg "@ 3033 1.1 mrg add %3,%1,%0\;add %3,%3,%2 3034 1.1 mrg add %3,%1,%0\;add %3,%3,%2 3035 1.1 mrg add %3,%1,%0\;add %3,%3,%2 3036 1.1 mrg add %4,%1,%0\;add %3,%4,%2" 3037 1.1 mrg [(set_attr "type" "fused_arith_logical") 3038 1.1 mrg (set_attr "cost" "6") 3039 1.1 mrg (set_attr "length" "8")]) 3040 1.1 mrg 3041 1.1 mrg ;; vaddudm-vaddudm fusion pattern generated by gen_addadd 3042 1.1 mrg (define_insn "*fuse_vaddudm_vaddudm" 3043 1.1 mrg [(set (match_operand:V2DI 3 "altivec_register_operand" "=&0,&1,&v,v") 3044 1.1 mrg (plus:V2DI 3045 1.1 mrg (plus:V2DI (match_operand:V2DI 0 "altivec_register_operand" "v,v,v,v") 3046 1.1 mrg (match_operand:V2DI 1 "altivec_register_operand" "%v,v,v,v")) 3047 1.1 mrg (match_operand:V2DI 2 "altivec_register_operand" "v,v,v,v"))) 3048 1.1 mrg (clobber (match_scratch:V2DI 4 "=X,X,X,&v"))] 3049 1.1 mrg "(TARGET_P10_FUSION)" 3050 1.1 mrg "@ 3051 1.1 mrg vaddudm %3,%1,%0\;vaddudm %3,%3,%2 3052 1.1 mrg vaddudm %3,%1,%0\;vaddudm %3,%3,%2 3053 1.1 mrg vaddudm %3,%1,%0\;vaddudm %3,%3,%2 3054 1.1 mrg vaddudm %4,%1,%0\;vaddudm %3,%4,%2" 3055 1.1 mrg [(set_attr "type" "fused_vector") 3056 1.1 mrg (set_attr "cost" "6") 3057 1.1 mrg (set_attr "length" "8")]) 3058
Indexes created Sun Apr 19 00:22:55 UTC 2026