1 ;; Generated automatically by genfusion.pl 2 3 ;; Copyright (C) 2020-2022 Free Software Foundation, Inc. 4 ;; 5 ;; This file is part of GCC. 6 ;; 7 ;; GCC is free software; you can redistribute it and/or modify it under 8 ;; the terms of the GNU General Public License as published by the Free 9 ;; Software Foundation; either version 3, or (at your option) any later 10 ;; version. 11 ;; 12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 ;; for more details. 16 ;; 17 ;; You should have received a copy of the GNU General Public License 18 ;; along with GCC; see the file COPYING3. If not see 19 ;; <http://www.gnu.org/licenses/>. 20 21 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 22 ;; load mode is DI result mode is clobber compare mode is CC extend is none 23 (define_insn_and_split "*ld_cmpdi_cr0_DI_clobber_CC_none" 24 [(set (match_operand:CC 2 "cc_reg_operand" "=x") 25 (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") 26 (match_operand:DI 3 "const_m1_to_1_operand" "n"))) 27 (clobber (match_scratch:DI 0 "=r"))] 28 "(TARGET_P10_FUSION)" 29 "ld%X1 %0,%1\;cmpdi %2,%0,%3" 30 "&& reload_completed 31 && (cc_reg_not_cr0_operand (operands[2], CCmode) 32 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 33 DImode, NON_PREFIXED_DS))" 34 [(set (match_dup 0) (match_dup 1)) 35 (set (match_dup 2) 36 (compare:CC (match_dup 0) (match_dup 3)))] 37 "" 38 [(set_attr "type" "fused_load_cmpi") 39 (set_attr "cost" "8") 40 (set_attr "length" "8")]) 41 42 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 43 ;; load mode is DI result mode is clobber compare mode is CCUNS extend is none 44 (define_insn_and_split "*ld_cmpldi_cr0_DI_clobber_CCUNS_none" 45 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 46 (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") 47 (match_operand:DI 3 "const_0_to_1_operand" "n"))) 48 (clobber (match_scratch:DI 0 "=r"))] 49 "(TARGET_P10_FUSION)" 50 "ld%X1 %0,%1\;cmpldi %2,%0,%3" 51 "&& reload_completed 52 && (cc_reg_not_cr0_operand (operands[2], CCmode) 53 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 54 DImode, NON_PREFIXED_DS))" 55 [(set (match_dup 0) (match_dup 1)) 56 (set (match_dup 2) 57 (compare:CCUNS (match_dup 0) (match_dup 3)))] 58 "" 59 [(set_attr "type" "fused_load_cmpi") 60 (set_attr "cost" "8") 61 (set_attr "length" "8")]) 62 63 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 64 ;; load mode is DI result mode is DI compare mode is CC extend is none 65 (define_insn_and_split "*ld_cmpdi_cr0_DI_DI_CC_none" 66 [(set (match_operand:CC 2 "cc_reg_operand" "=x") 67 (compare:CC (match_operand:DI 1 "non_update_memory_operand" "YZ") 68 (match_operand:DI 3 "const_m1_to_1_operand" "n"))) 69 (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] 70 "(TARGET_P10_FUSION)" 71 "ld%X1 %0,%1\;cmpdi %2,%0,%3" 72 "&& reload_completed 73 && (cc_reg_not_cr0_operand (operands[2], CCmode) 74 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 75 DImode, NON_PREFIXED_DS))" 76 [(set (match_dup 0) (match_dup 1)) 77 (set (match_dup 2) 78 (compare:CC (match_dup 0) (match_dup 3)))] 79 "" 80 [(set_attr "type" "fused_load_cmpi") 81 (set_attr "cost" "8") 82 (set_attr "length" "8")]) 83 84 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 85 ;; load mode is DI result mode is DI compare mode is CCUNS extend is none 86 (define_insn_and_split "*ld_cmpldi_cr0_DI_DI_CCUNS_none" 87 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 88 (compare:CCUNS (match_operand:DI 1 "non_update_memory_operand" "YZ") 89 (match_operand:DI 3 "const_0_to_1_operand" "n"))) 90 (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] 91 "(TARGET_P10_FUSION)" 92 "ld%X1 %0,%1\;cmpldi %2,%0,%3" 93 "&& reload_completed 94 && (cc_reg_not_cr0_operand (operands[2], CCmode) 95 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 96 DImode, NON_PREFIXED_DS))" 97 [(set (match_dup 0) (match_dup 1)) 98 (set (match_dup 2) 99 (compare:CCUNS (match_dup 0) (match_dup 3)))] 100 "" 101 [(set_attr "type" "fused_load_cmpi") 102 (set_attr "cost" "8") 103 (set_attr "length" "8")]) 104 105 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 106 ;; load mode is SI result mode is clobber compare mode is CC extend is none 107 (define_insn_and_split "*lwz_cmpwi_cr0_SI_clobber_CC_none" 108 [(set (match_operand:CC 2 "cc_reg_operand" "=x") 109 (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") 110 (match_operand:SI 3 "const_m1_to_1_operand" "n"))) 111 (clobber (match_scratch:SI 0 "=r"))] 112 "(TARGET_P10_FUSION)" 113 "lwz%X1 %0,%1\;cmpwi %2,%0,%3" 114 "&& reload_completed 115 && (cc_reg_not_cr0_operand (operands[2], CCmode) 116 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 117 SImode, NON_PREFIXED_D))" 118 [(set (match_dup 0) (match_dup 1)) 119 (set (match_dup 2) 120 (compare:CC (match_dup 0) (match_dup 3)))] 121 "" 122 [(set_attr "type" "fused_load_cmpi") 123 (set_attr "cost" "8") 124 (set_attr "length" "8")]) 125 126 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 127 ;; load mode is SI result mode is clobber compare mode is CCUNS extend is none 128 (define_insn_and_split "*lwz_cmpldi_cr0_SI_clobber_CCUNS_none" 129 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 130 (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") 131 (match_operand:SI 3 "const_0_to_1_operand" "n"))) 132 (clobber (match_scratch:SI 0 "=r"))] 133 "(TARGET_P10_FUSION)" 134 "lwz%X1 %0,%1\;cmpldi %2,%0,%3" 135 "&& reload_completed 136 && (cc_reg_not_cr0_operand (operands[2], CCmode) 137 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 138 SImode, NON_PREFIXED_D))" 139 [(set (match_dup 0) (match_dup 1)) 140 (set (match_dup 2) 141 (compare:CCUNS (match_dup 0) (match_dup 3)))] 142 "" 143 [(set_attr "type" "fused_load_cmpi") 144 (set_attr "cost" "8") 145 (set_attr "length" "8")]) 146 147 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 148 ;; load mode is SI result mode is SI compare mode is CC extend is none 149 (define_insn_and_split "*lwz_cmpwi_cr0_SI_SI_CC_none" 150 [(set (match_operand:CC 2 "cc_reg_operand" "=x") 151 (compare:CC (match_operand:SI 1 "non_update_memory_operand" "m") 152 (match_operand:SI 3 "const_m1_to_1_operand" "n"))) 153 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] 154 "(TARGET_P10_FUSION)" 155 "lwz%X1 %0,%1\;cmpwi %2,%0,%3" 156 "&& reload_completed 157 && (cc_reg_not_cr0_operand (operands[2], CCmode) 158 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 159 SImode, NON_PREFIXED_D))" 160 [(set (match_dup 0) (match_dup 1)) 161 (set (match_dup 2) 162 (compare:CC (match_dup 0) (match_dup 3)))] 163 "" 164 [(set_attr "type" "fused_load_cmpi") 165 (set_attr "cost" "8") 166 (set_attr "length" "8")]) 167 168 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 169 ;; load mode is SI result mode is SI compare mode is CCUNS extend is none 170 (define_insn_and_split "*lwz_cmpldi_cr0_SI_SI_CCUNS_none" 171 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 172 (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") 173 (match_operand:SI 3 "const_0_to_1_operand" "n"))) 174 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] 175 "(TARGET_P10_FUSION)" 176 "lwz%X1 %0,%1\;cmpldi %2,%0,%3" 177 "&& reload_completed 178 && (cc_reg_not_cr0_operand (operands[2], CCmode) 179 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 180 SImode, NON_PREFIXED_D))" 181 [(set (match_dup 0) (match_dup 1)) 182 (set (match_dup 2) 183 (compare:CCUNS (match_dup 0) (match_dup 3)))] 184 "" 185 [(set_attr "type" "fused_load_cmpi") 186 (set_attr "cost" "8") 187 (set_attr "length" "8")]) 188 189 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 190 ;; load mode is SI result mode is EXTSI compare mode is CC extend is sign 191 (define_insn_and_split "*lwa_cmpdi_cr0_SI_EXTSI_CC_sign" 192 [(set (match_operand:CC 2 "cc_reg_operand" "=x") 193 (compare:CC (match_operand:SI 1 "non_update_memory_operand" "YZ") 194 (match_operand:SI 3 "const_m1_to_1_operand" "n"))) 195 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (sign_extend:EXTSI (match_dup 1)))] 196 "(TARGET_P10_FUSION)" 197 "lwa%X1 %0,%1\;cmpdi %2,%0,%3" 198 "&& reload_completed 199 && (cc_reg_not_cr0_operand (operands[2], CCmode) 200 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 201 SImode, NON_PREFIXED_DS))" 202 [(set (match_dup 0) (sign_extend:EXTSI (match_dup 1))) 203 (set (match_dup 2) 204 (compare:CC (match_dup 0) (match_dup 3)))] 205 "" 206 [(set_attr "type" "fused_load_cmpi") 207 (set_attr "cost" "8") 208 (set_attr "sign_extend" "yes") 209 (set_attr "length" "8")]) 210 211 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 212 ;; load mode is SI result mode is EXTSI compare mode is CCUNS extend is zero 213 (define_insn_and_split "*lwz_cmpldi_cr0_SI_EXTSI_CCUNS_zero" 214 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 215 (compare:CCUNS (match_operand:SI 1 "non_update_memory_operand" "m") 216 (match_operand:SI 3 "const_0_to_1_operand" "n"))) 217 (set (match_operand:EXTSI 0 "gpc_reg_operand" "=r") (zero_extend:EXTSI (match_dup 1)))] 218 "(TARGET_P10_FUSION)" 219 "lwz%X1 %0,%1\;cmpldi %2,%0,%3" 220 "&& reload_completed 221 && (cc_reg_not_cr0_operand (operands[2], CCmode) 222 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 223 SImode, NON_PREFIXED_D))" 224 [(set (match_dup 0) (zero_extend:EXTSI (match_dup 1))) 225 (set (match_dup 2) 226 (compare:CCUNS (match_dup 0) (match_dup 3)))] 227 "" 228 [(set_attr "type" "fused_load_cmpi") 229 (set_attr "cost" "8") 230 (set_attr "length" "8")]) 231 232 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 233 ;; load mode is HI result mode is clobber compare mode is CC extend is sign 234 (define_insn_and_split "*lha_cmpdi_cr0_HI_clobber_CC_sign" 235 [(set (match_operand:CC 2 "cc_reg_operand" "=x") 236 (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") 237 (match_operand:HI 3 "const_m1_to_1_operand" "n"))) 238 (clobber (match_scratch:GPR 0 "=r"))] 239 "(TARGET_P10_FUSION)" 240 "lha%X1 %0,%1\;cmpdi %2,%0,%3" 241 "&& reload_completed 242 && (cc_reg_not_cr0_operand (operands[2], CCmode) 243 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 244 HImode, NON_PREFIXED_D))" 245 [(set (match_dup 0) (sign_extend:GPR (match_dup 1))) 246 (set (match_dup 2) 247 (compare:CC (match_dup 0) (match_dup 3)))] 248 "" 249 [(set_attr "type" "fused_load_cmpi") 250 (set_attr "cost" "8") 251 (set_attr "length" "8")]) 252 253 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 254 ;; load mode is HI result mode is clobber compare mode is CCUNS extend is zero 255 (define_insn_and_split "*lhz_cmpldi_cr0_HI_clobber_CCUNS_zero" 256 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 257 (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") 258 (match_operand:HI 3 "const_0_to_1_operand" "n"))) 259 (clobber (match_scratch:GPR 0 "=r"))] 260 "(TARGET_P10_FUSION)" 261 "lhz%X1 %0,%1\;cmpldi %2,%0,%3" 262 "&& reload_completed 263 && (cc_reg_not_cr0_operand (operands[2], CCmode) 264 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 265 HImode, NON_PREFIXED_D))" 266 [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) 267 (set (match_dup 2) 268 (compare:CCUNS (match_dup 0) (match_dup 3)))] 269 "" 270 [(set_attr "type" "fused_load_cmpi") 271 (set_attr "cost" "8") 272 (set_attr "length" "8")]) 273 274 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 275 ;; load mode is HI result mode is EXTHI compare mode is CC extend is sign 276 (define_insn_and_split "*lha_cmpdi_cr0_HI_EXTHI_CC_sign" 277 [(set (match_operand:CC 2 "cc_reg_operand" "=x") 278 (compare:CC (match_operand:HI 1 "non_update_memory_operand" "m") 279 (match_operand:HI 3 "const_m1_to_1_operand" "n"))) 280 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (sign_extend:EXTHI (match_dup 1)))] 281 "(TARGET_P10_FUSION)" 282 "lha%X1 %0,%1\;cmpdi %2,%0,%3" 283 "&& reload_completed 284 && (cc_reg_not_cr0_operand (operands[2], CCmode) 285 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 286 HImode, NON_PREFIXED_D))" 287 [(set (match_dup 0) (sign_extend:EXTHI (match_dup 1))) 288 (set (match_dup 2) 289 (compare:CC (match_dup 0) (match_dup 3)))] 290 "" 291 [(set_attr "type" "fused_load_cmpi") 292 (set_attr "cost" "8") 293 (set_attr "length" "8")]) 294 295 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 296 ;; load mode is HI result mode is EXTHI compare mode is CCUNS extend is zero 297 (define_insn_and_split "*lhz_cmpldi_cr0_HI_EXTHI_CCUNS_zero" 298 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 299 (compare:CCUNS (match_operand:HI 1 "non_update_memory_operand" "m") 300 (match_operand:HI 3 "const_0_to_1_operand" "n"))) 301 (set (match_operand:EXTHI 0 "gpc_reg_operand" "=r") (zero_extend:EXTHI (match_dup 1)))] 302 "(TARGET_P10_FUSION)" 303 "lhz%X1 %0,%1\;cmpldi %2,%0,%3" 304 "&& reload_completed 305 && (cc_reg_not_cr0_operand (operands[2], CCmode) 306 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 307 HImode, NON_PREFIXED_D))" 308 [(set (match_dup 0) (zero_extend:EXTHI (match_dup 1))) 309 (set (match_dup 2) 310 (compare:CCUNS (match_dup 0) (match_dup 3)))] 311 "" 312 [(set_attr "type" "fused_load_cmpi") 313 (set_attr "cost" "8") 314 (set_attr "length" "8")]) 315 316 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 317 ;; load mode is QI result mode is clobber compare mode is CCUNS extend is zero 318 (define_insn_and_split "*lbz_cmpldi_cr0_QI_clobber_CCUNS_zero" 319 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 320 (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") 321 (match_operand:QI 3 "const_0_to_1_operand" "n"))) 322 (clobber (match_scratch:GPR 0 "=r"))] 323 "(TARGET_P10_FUSION)" 324 "lbz%X1 %0,%1\;cmpldi %2,%0,%3" 325 "&& reload_completed 326 && (cc_reg_not_cr0_operand (operands[2], CCmode) 327 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 328 QImode, NON_PREFIXED_D))" 329 [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) 330 (set (match_dup 2) 331 (compare:CCUNS (match_dup 0) (match_dup 3)))] 332 "" 333 [(set_attr "type" "fused_load_cmpi") 334 (set_attr "cost" "8") 335 (set_attr "length" "8")]) 336 337 ;; load-cmpi fusion pattern generated by gen_ld_cmpi_p10 338 ;; load mode is QI result mode is GPR compare mode is CCUNS extend is zero 339 (define_insn_and_split "*lbz_cmpldi_cr0_QI_GPR_CCUNS_zero" 340 [(set (match_operand:CCUNS 2 "cc_reg_operand" "=x") 341 (compare:CCUNS (match_operand:QI 1 "non_update_memory_operand" "m") 342 (match_operand:QI 3 "const_0_to_1_operand" "n"))) 343 (set (match_operand:GPR 0 "gpc_reg_operand" "=r") (zero_extend:GPR (match_dup 1)))] 344 "(TARGET_P10_FUSION)" 345 "lbz%X1 %0,%1\;cmpldi %2,%0,%3" 346 "&& reload_completed 347 && (cc_reg_not_cr0_operand (operands[2], CCmode) 348 || !address_is_non_pfx_d_or_x (XEXP (operands[1], 0), 349 QImode, NON_PREFIXED_D))" 350 [(set (match_dup 0) (zero_extend:GPR (match_dup 1))) 351 (set (match_dup 2) 352 (compare:CCUNS (match_dup 0) (match_dup 3)))] 353 "" 354 [(set_attr "type" "fused_load_cmpi") 355 (set_attr "cost" "8") 356 (set_attr "length" "8")]) 357 358 359 ;; logical-logical fusion pattern generated by gen_logical_addsubf 360 ;; scalar and -> and 361 (define_insn "*fuse_and_and" 362 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 363 (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 364 (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 365 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 366 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 367 "(TARGET_P10_FUSION)" 368 "@ 369 and %3,%1,%0\;and %3,%3,%2 370 and %3,%1,%0\;and %3,%3,%2 371 and %3,%1,%0\;and %3,%3,%2 372 and %4,%1,%0\;and %3,%4,%2" 373 [(set_attr "type" "fused_arith_logical") 374 (set_attr "cost" "6") 375 (set_attr "length" "8")]) 376 377 ;; logical-logical fusion pattern generated by gen_logical_addsubf 378 ;; scalar andc -> and 379 (define_insn "*fuse_andc_and" 380 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 381 (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 382 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 383 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 384 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 385 "(TARGET_P10_FUSION)" 386 "@ 387 andc %3,%1,%0\;and %3,%3,%2 388 andc %3,%1,%0\;and %3,%3,%2 389 andc %3,%1,%0\;and %3,%3,%2 390 andc %4,%1,%0\;and %3,%4,%2" 391 [(set_attr "type" "fused_arith_logical") 392 (set_attr "cost" "6") 393 (set_attr "length" "8")]) 394 395 ;; logical-logical fusion pattern generated by gen_logical_addsubf 396 ;; scalar eqv -> and 397 (define_insn "*fuse_eqv_and" 398 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 399 (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 400 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 401 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 402 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 403 "(TARGET_P10_FUSION)" 404 "@ 405 eqv %3,%1,%0\;and %3,%3,%2 406 eqv %3,%1,%0\;and %3,%3,%2 407 eqv %3,%1,%0\;and %3,%3,%2 408 eqv %4,%1,%0\;and %3,%4,%2" 409 [(set_attr "type" "fused_arith_logical") 410 (set_attr "cost" "6") 411 (set_attr "length" "8")]) 412 413 ;; logical-logical fusion pattern generated by gen_logical_addsubf 414 ;; scalar nand -> and 415 (define_insn "*fuse_nand_and" 416 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 417 (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 418 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 419 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 420 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 421 "(TARGET_P10_FUSION)" 422 "@ 423 nand %3,%1,%0\;and %3,%3,%2 424 nand %3,%1,%0\;and %3,%3,%2 425 nand %3,%1,%0\;and %3,%3,%2 426 nand %4,%1,%0\;and %3,%4,%2" 427 [(set_attr "type" "fused_arith_logical") 428 (set_attr "cost" "6") 429 (set_attr "length" "8")]) 430 431 ;; logical-logical fusion pattern generated by gen_logical_addsubf 432 ;; scalar nor -> and 433 (define_insn "*fuse_nor_and" 434 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 435 (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 436 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 437 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 438 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 439 "(TARGET_P10_FUSION)" 440 "@ 441 nor %3,%1,%0\;and %3,%3,%2 442 nor %3,%1,%0\;and %3,%3,%2 443 nor %3,%1,%0\;and %3,%3,%2 444 nor %4,%1,%0\;and %3,%4,%2" 445 [(set_attr "type" "fused_arith_logical") 446 (set_attr "cost" "6") 447 (set_attr "length" "8")]) 448 449 ;; logical-logical fusion pattern generated by gen_logical_addsubf 450 ;; scalar or -> and 451 (define_insn "*fuse_or_and" 452 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 453 (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 454 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 455 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 456 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 457 "(TARGET_P10_FUSION)" 458 "@ 459 or %3,%1,%0\;and %3,%3,%2 460 or %3,%1,%0\;and %3,%3,%2 461 or %3,%1,%0\;and %3,%3,%2 462 or %4,%1,%0\;and %3,%4,%2" 463 [(set_attr "type" "fused_arith_logical") 464 (set_attr "cost" "6") 465 (set_attr "length" "8")]) 466 467 ;; logical-logical fusion pattern generated by gen_logical_addsubf 468 ;; scalar orc -> and 469 (define_insn "*fuse_orc_and" 470 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 471 (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 472 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 473 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 474 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 475 "(TARGET_P10_FUSION)" 476 "@ 477 orc %3,%1,%0\;and %3,%3,%2 478 orc %3,%1,%0\;and %3,%3,%2 479 orc %3,%1,%0\;and %3,%3,%2 480 orc %4,%1,%0\;and %3,%4,%2" 481 [(set_attr "type" "fused_arith_logical") 482 (set_attr "cost" "6") 483 (set_attr "length" "8")]) 484 485 ;; logical-logical fusion pattern generated by gen_logical_addsubf 486 ;; scalar xor -> and 487 (define_insn "*fuse_xor_and" 488 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 489 (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 490 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 491 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 492 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 493 "(TARGET_P10_FUSION)" 494 "@ 495 xor %3,%1,%0\;and %3,%3,%2 496 xor %3,%1,%0\;and %3,%3,%2 497 xor %3,%1,%0\;and %3,%3,%2 498 xor %4,%1,%0\;and %3,%4,%2" 499 [(set_attr "type" "fused_arith_logical") 500 (set_attr "cost" "6") 501 (set_attr "length" "8")]) 502 503 ;; add-logical fusion pattern generated by gen_logical_addsubf 504 ;; scalar add -> and 505 (define_insn "*fuse_add_and" 506 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 507 (and:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 508 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 509 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 510 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 511 "(TARGET_P10_FUSION)" 512 "@ 513 add %3,%1,%0\;and %3,%3,%2 514 add %3,%1,%0\;and %3,%3,%2 515 add %3,%1,%0\;and %3,%3,%2 516 add %4,%1,%0\;and %3,%4,%2" 517 [(set_attr "type" "fused_arith_logical") 518 (set_attr "cost" "6") 519 (set_attr "length" "8")]) 520 521 ;; add-logical fusion pattern generated by gen_logical_addsubf 522 ;; scalar subf -> and 523 (define_insn "*fuse_subf_and" 524 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 525 (and:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 526 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 527 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 528 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 529 "(TARGET_P10_FUSION)" 530 "@ 531 subf %3,%1,%0\;and %3,%3,%2 532 subf %3,%1,%0\;and %3,%3,%2 533 subf %3,%1,%0\;and %3,%3,%2 534 subf %4,%1,%0\;and %3,%4,%2" 535 [(set_attr "type" "fused_arith_logical") 536 (set_attr "cost" "6") 537 (set_attr "length" "8")]) 538 539 ;; logical-logical fusion pattern generated by gen_logical_addsubf 540 ;; scalar and -> andc 541 (define_insn "*fuse_and_andc" 542 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 543 (and:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 544 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 545 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 546 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 547 "(TARGET_P10_FUSION)" 548 "@ 549 and %3,%1,%0\;andc %3,%3,%2 550 and %3,%1,%0\;andc %3,%3,%2 551 and %3,%1,%0\;andc %3,%3,%2 552 and %4,%1,%0\;andc %3,%4,%2" 553 [(set_attr "type" "fused_arith_logical") 554 (set_attr "cost" "6") 555 (set_attr "length" "8")]) 556 557 ;; logical-logical fusion pattern generated by gen_logical_addsubf 558 ;; scalar andc -> andc 559 (define_insn "*fuse_andc_andc" 560 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 561 (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 562 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 563 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 564 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 565 "(TARGET_P10_FUSION)" 566 "@ 567 andc %3,%1,%0\;andc %3,%3,%2 568 andc %3,%1,%0\;andc %3,%3,%2 569 andc %3,%1,%0\;andc %3,%3,%2 570 andc %4,%1,%0\;andc %3,%4,%2" 571 [(set_attr "type" "fused_arith_logical") 572 (set_attr "cost" "6") 573 (set_attr "length" "8")]) 574 575 ;; logical-logical fusion pattern generated by gen_logical_addsubf 576 ;; scalar eqv -> andc 577 (define_insn "*fuse_eqv_andc" 578 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 579 (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 580 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 581 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 582 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 583 "(TARGET_P10_FUSION)" 584 "@ 585 eqv %3,%1,%0\;andc %3,%3,%2 586 eqv %3,%1,%0\;andc %3,%3,%2 587 eqv %3,%1,%0\;andc %3,%3,%2 588 eqv %4,%1,%0\;andc %3,%4,%2" 589 [(set_attr "type" "fused_arith_logical") 590 (set_attr "cost" "6") 591 (set_attr "length" "8")]) 592 593 ;; logical-logical fusion pattern generated by gen_logical_addsubf 594 ;; scalar nand -> andc 595 (define_insn "*fuse_nand_andc" 596 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 597 (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 598 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 599 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 600 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 601 "(TARGET_P10_FUSION)" 602 "@ 603 nand %3,%1,%0\;andc %3,%3,%2 604 nand %3,%1,%0\;andc %3,%3,%2 605 nand %3,%1,%0\;andc %3,%3,%2 606 nand %4,%1,%0\;andc %3,%4,%2" 607 [(set_attr "type" "fused_arith_logical") 608 (set_attr "cost" "6") 609 (set_attr "length" "8")]) 610 611 ;; logical-logical fusion pattern generated by gen_logical_addsubf 612 ;; scalar nor -> andc 613 (define_insn "*fuse_nor_andc" 614 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 615 (and:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 616 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 617 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 618 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 619 "(TARGET_P10_FUSION)" 620 "@ 621 nor %3,%1,%0\;andc %3,%3,%2 622 nor %3,%1,%0\;andc %3,%3,%2 623 nor %3,%1,%0\;andc %3,%3,%2 624 nor %4,%1,%0\;andc %3,%4,%2" 625 [(set_attr "type" "fused_arith_logical") 626 (set_attr "cost" "6") 627 (set_attr "length" "8")]) 628 629 ;; logical-logical fusion pattern generated by gen_logical_addsubf 630 ;; scalar or -> andc 631 (define_insn "*fuse_or_andc" 632 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 633 (and:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 634 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 635 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 636 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 637 "(TARGET_P10_FUSION)" 638 "@ 639 or %3,%1,%0\;andc %3,%3,%2 640 or %3,%1,%0\;andc %3,%3,%2 641 or %3,%1,%0\;andc %3,%3,%2 642 or %4,%1,%0\;andc %3,%4,%2" 643 [(set_attr "type" "fused_arith_logical") 644 (set_attr "cost" "6") 645 (set_attr "length" "8")]) 646 647 ;; logical-logical fusion pattern generated by gen_logical_addsubf 648 ;; scalar orc -> andc 649 (define_insn "*fuse_orc_andc" 650 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 651 (and:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 652 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 653 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 654 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 655 "(TARGET_P10_FUSION)" 656 "@ 657 orc %3,%1,%0\;andc %3,%3,%2 658 orc %3,%1,%0\;andc %3,%3,%2 659 orc %3,%1,%0\;andc %3,%3,%2 660 orc %4,%1,%0\;andc %3,%4,%2" 661 [(set_attr "type" "fused_arith_logical") 662 (set_attr "cost" "6") 663 (set_attr "length" "8")]) 664 665 ;; logical-logical fusion pattern generated by gen_logical_addsubf 666 ;; scalar xor -> andc 667 (define_insn "*fuse_xor_andc" 668 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 669 (and:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 670 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 671 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 672 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 673 "(TARGET_P10_FUSION)" 674 "@ 675 xor %3,%1,%0\;andc %3,%3,%2 676 xor %3,%1,%0\;andc %3,%3,%2 677 xor %3,%1,%0\;andc %3,%3,%2 678 xor %4,%1,%0\;andc %3,%4,%2" 679 [(set_attr "type" "fused_arith_logical") 680 (set_attr "cost" "6") 681 (set_attr "length" "8")]) 682 683 ;; logical-logical fusion pattern generated by gen_logical_addsubf 684 ;; scalar and -> eqv 685 (define_insn "*fuse_and_eqv" 686 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 687 (not:GPR (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 688 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 689 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 690 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 691 "(TARGET_P10_FUSION)" 692 "@ 693 and %3,%1,%0\;eqv %3,%3,%2 694 and %3,%1,%0\;eqv %3,%3,%2 695 and %3,%1,%0\;eqv %3,%3,%2 696 and %4,%1,%0\;eqv %3,%4,%2" 697 [(set_attr "type" "fused_arith_logical") 698 (set_attr "cost" "6") 699 (set_attr "length" "8")]) 700 701 ;; logical-logical fusion pattern generated by gen_logical_addsubf 702 ;; scalar andc -> eqv 703 (define_insn "*fuse_andc_eqv" 704 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 705 (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 706 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 707 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 708 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 709 "(TARGET_P10_FUSION)" 710 "@ 711 andc %3,%1,%0\;eqv %3,%3,%2 712 andc %3,%1,%0\;eqv %3,%3,%2 713 andc %3,%1,%0\;eqv %3,%3,%2 714 andc %4,%1,%0\;eqv %3,%4,%2" 715 [(set_attr "type" "fused_arith_logical") 716 (set_attr "cost" "6") 717 (set_attr "length" "8")]) 718 719 ;; logical-logical fusion pattern generated by gen_logical_addsubf 720 ;; scalar eqv -> eqv 721 (define_insn "*fuse_eqv_eqv" 722 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 723 (not:GPR (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 724 (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r"))) 725 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 726 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 727 "(TARGET_P10_FUSION)" 728 "@ 729 eqv %3,%1,%0\;eqv %3,%3,%2 730 eqv %3,%1,%0\;eqv %3,%3,%2 731 eqv %3,%1,%0\;eqv %3,%3,%2 732 eqv %4,%1,%0\;eqv %3,%4,%2" 733 [(set_attr "type" "fused_arith_logical") 734 (set_attr "cost" "6") 735 (set_attr "length" "8")]) 736 737 ;; logical-logical fusion pattern generated by gen_logical_addsubf 738 ;; scalar nand -> eqv 739 (define_insn "*fuse_nand_eqv" 740 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 741 (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 742 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 743 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 744 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 745 "(TARGET_P10_FUSION)" 746 "@ 747 nand %3,%1,%0\;eqv %3,%3,%2 748 nand %3,%1,%0\;eqv %3,%3,%2 749 nand %3,%1,%0\;eqv %3,%3,%2 750 nand %4,%1,%0\;eqv %3,%4,%2" 751 [(set_attr "type" "fused_arith_logical") 752 (set_attr "cost" "6") 753 (set_attr "length" "8")]) 754 755 ;; logical-logical fusion pattern generated by gen_logical_addsubf 756 ;; scalar nor -> eqv 757 (define_insn "*fuse_nor_eqv" 758 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 759 (not:GPR (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 760 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 761 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 762 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 763 "(TARGET_P10_FUSION)" 764 "@ 765 nor %3,%1,%0\;eqv %3,%3,%2 766 nor %3,%1,%0\;eqv %3,%3,%2 767 nor %3,%1,%0\;eqv %3,%3,%2 768 nor %4,%1,%0\;eqv %3,%4,%2" 769 [(set_attr "type" "fused_arith_logical") 770 (set_attr "cost" "6") 771 (set_attr "length" "8")]) 772 773 ;; logical-logical fusion pattern generated by gen_logical_addsubf 774 ;; scalar or -> eqv 775 (define_insn "*fuse_or_eqv" 776 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 777 (not:GPR (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 778 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 779 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 780 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 781 "(TARGET_P10_FUSION)" 782 "@ 783 or %3,%1,%0\;eqv %3,%3,%2 784 or %3,%1,%0\;eqv %3,%3,%2 785 or %3,%1,%0\;eqv %3,%3,%2 786 or %4,%1,%0\;eqv %3,%4,%2" 787 [(set_attr "type" "fused_arith_logical") 788 (set_attr "cost" "6") 789 (set_attr "length" "8")]) 790 791 ;; logical-logical fusion pattern generated by gen_logical_addsubf 792 ;; scalar orc -> eqv 793 (define_insn "*fuse_orc_eqv" 794 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 795 (not:GPR (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 796 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 797 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 798 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 799 "(TARGET_P10_FUSION)" 800 "@ 801 orc %3,%1,%0\;eqv %3,%3,%2 802 orc %3,%1,%0\;eqv %3,%3,%2 803 orc %3,%1,%0\;eqv %3,%3,%2 804 orc %4,%1,%0\;eqv %3,%4,%2" 805 [(set_attr "type" "fused_arith_logical") 806 (set_attr "cost" "6") 807 (set_attr "length" "8")]) 808 809 ;; logical-logical fusion pattern generated by gen_logical_addsubf 810 ;; scalar xor -> eqv 811 (define_insn "*fuse_xor_eqv" 812 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 813 (not:GPR (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 814 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 815 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 816 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 817 "(TARGET_P10_FUSION)" 818 "@ 819 xor %3,%1,%0\;eqv %3,%3,%2 820 xor %3,%1,%0\;eqv %3,%3,%2 821 xor %3,%1,%0\;eqv %3,%3,%2 822 xor %4,%1,%0\;eqv %3,%4,%2" 823 [(set_attr "type" "fused_arith_logical") 824 (set_attr "cost" "6") 825 (set_attr "length" "8")]) 826 827 ;; logical-logical fusion pattern generated by gen_logical_addsubf 828 ;; scalar and -> nand 829 (define_insn "*fuse_and_nand" 830 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 831 (ior:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 832 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 833 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 834 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 835 "(TARGET_P10_FUSION)" 836 "@ 837 and %3,%1,%0\;nand %3,%3,%2 838 and %3,%1,%0\;nand %3,%3,%2 839 and %3,%1,%0\;nand %3,%3,%2 840 and %4,%1,%0\;nand %3,%4,%2" 841 [(set_attr "type" "fused_arith_logical") 842 (set_attr "cost" "6") 843 (set_attr "length" "8")]) 844 845 ;; logical-logical fusion pattern generated by gen_logical_addsubf 846 ;; scalar andc -> nand 847 (define_insn "*fuse_andc_nand" 848 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 849 (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 850 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 851 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 852 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 853 "(TARGET_P10_FUSION)" 854 "@ 855 andc %3,%1,%0\;nand %3,%3,%2 856 andc %3,%1,%0\;nand %3,%3,%2 857 andc %3,%1,%0\;nand %3,%3,%2 858 andc %4,%1,%0\;nand %3,%4,%2" 859 [(set_attr "type" "fused_arith_logical") 860 (set_attr "cost" "6") 861 (set_attr "length" "8")]) 862 863 ;; logical-logical fusion pattern generated by gen_logical_addsubf 864 ;; scalar eqv -> nand 865 (define_insn "*fuse_eqv_nand" 866 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 867 (ior:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 868 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 869 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 870 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 871 "(TARGET_P10_FUSION)" 872 "@ 873 eqv %3,%1,%0\;nand %3,%3,%2 874 eqv %3,%1,%0\;nand %3,%3,%2 875 eqv %3,%1,%0\;nand %3,%3,%2 876 eqv %4,%1,%0\;nand %3,%4,%2" 877 [(set_attr "type" "fused_arith_logical") 878 (set_attr "cost" "6") 879 (set_attr "length" "8")]) 880 881 ;; logical-logical fusion pattern generated by gen_logical_addsubf 882 ;; scalar nand -> nand 883 (define_insn "*fuse_nand_nand" 884 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 885 (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 886 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 887 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 888 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 889 "(TARGET_P10_FUSION)" 890 "@ 891 nand %3,%1,%0\;nand %3,%3,%2 892 nand %3,%1,%0\;nand %3,%3,%2 893 nand %3,%1,%0\;nand %3,%3,%2 894 nand %4,%1,%0\;nand %3,%4,%2" 895 [(set_attr "type" "fused_arith_logical") 896 (set_attr "cost" "6") 897 (set_attr "length" "8")]) 898 899 ;; logical-logical fusion pattern generated by gen_logical_addsubf 900 ;; scalar nor -> nand 901 (define_insn "*fuse_nor_nand" 902 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 903 (ior:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 904 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 905 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 906 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 907 "(TARGET_P10_FUSION)" 908 "@ 909 nor %3,%1,%0\;nand %3,%3,%2 910 nor %3,%1,%0\;nand %3,%3,%2 911 nor %3,%1,%0\;nand %3,%3,%2 912 nor %4,%1,%0\;nand %3,%4,%2" 913 [(set_attr "type" "fused_arith_logical") 914 (set_attr "cost" "6") 915 (set_attr "length" "8")]) 916 917 ;; logical-logical fusion pattern generated by gen_logical_addsubf 918 ;; scalar or -> nand 919 (define_insn "*fuse_or_nand" 920 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 921 (ior:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 922 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 923 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 924 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 925 "(TARGET_P10_FUSION)" 926 "@ 927 or %3,%1,%0\;nand %3,%3,%2 928 or %3,%1,%0\;nand %3,%3,%2 929 or %3,%1,%0\;nand %3,%3,%2 930 or %4,%1,%0\;nand %3,%4,%2" 931 [(set_attr "type" "fused_arith_logical") 932 (set_attr "cost" "6") 933 (set_attr "length" "8")]) 934 935 ;; logical-logical fusion pattern generated by gen_logical_addsubf 936 ;; scalar orc -> nand 937 (define_insn "*fuse_orc_nand" 938 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 939 (ior:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 940 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 941 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 942 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 943 "(TARGET_P10_FUSION)" 944 "@ 945 orc %3,%1,%0\;nand %3,%3,%2 946 orc %3,%1,%0\;nand %3,%3,%2 947 orc %3,%1,%0\;nand %3,%3,%2 948 orc %4,%1,%0\;nand %3,%4,%2" 949 [(set_attr "type" "fused_arith_logical") 950 (set_attr "cost" "6") 951 (set_attr "length" "8")]) 952 953 ;; logical-logical fusion pattern generated by gen_logical_addsubf 954 ;; scalar xor -> nand 955 (define_insn "*fuse_xor_nand" 956 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 957 (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 958 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 959 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 960 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 961 "(TARGET_P10_FUSION)" 962 "@ 963 xor %3,%1,%0\;nand %3,%3,%2 964 xor %3,%1,%0\;nand %3,%3,%2 965 xor %3,%1,%0\;nand %3,%3,%2 966 xor %4,%1,%0\;nand %3,%4,%2" 967 [(set_attr "type" "fused_arith_logical") 968 (set_attr "cost" "6") 969 (set_attr "length" "8")]) 970 971 ;; add-logical fusion pattern generated by gen_logical_addsubf 972 ;; scalar add -> nand 973 (define_insn "*fuse_add_nand" 974 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 975 (ior:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 976 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 977 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 978 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 979 "(TARGET_P10_FUSION)" 980 "@ 981 add %3,%1,%0\;nand %3,%3,%2 982 add %3,%1,%0\;nand %3,%3,%2 983 add %3,%1,%0\;nand %3,%3,%2 984 add %4,%1,%0\;nand %3,%4,%2" 985 [(set_attr "type" "fused_arith_logical") 986 (set_attr "cost" "6") 987 (set_attr "length" "8")]) 988 989 ;; add-logical fusion pattern generated by gen_logical_addsubf 990 ;; scalar subf -> nand 991 (define_insn "*fuse_subf_nand" 992 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 993 (ior:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 994 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 995 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 996 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 997 "(TARGET_P10_FUSION)" 998 "@ 999 subf %3,%1,%0\;nand %3,%3,%2 1000 subf %3,%1,%0\;nand %3,%3,%2 1001 subf %3,%1,%0\;nand %3,%3,%2 1002 subf %4,%1,%0\;nand %3,%4,%2" 1003 [(set_attr "type" "fused_arith_logical") 1004 (set_attr "cost" "6") 1005 (set_attr "length" "8")]) 1006 1007 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1008 ;; scalar and -> nor 1009 (define_insn "*fuse_and_nor" 1010 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1011 (and:GPR (not:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1012 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1013 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1014 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1015 "(TARGET_P10_FUSION)" 1016 "@ 1017 and %3,%1,%0\;nor %3,%3,%2 1018 and %3,%1,%0\;nor %3,%3,%2 1019 and %3,%1,%0\;nor %3,%3,%2 1020 and %4,%1,%0\;nor %3,%4,%2" 1021 [(set_attr "type" "fused_arith_logical") 1022 (set_attr "cost" "6") 1023 (set_attr "length" "8")]) 1024 1025 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1026 ;; scalar andc -> nor 1027 (define_insn "*fuse_andc_nor" 1028 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1029 (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1030 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1031 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1032 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1033 "(TARGET_P10_FUSION)" 1034 "@ 1035 andc %3,%1,%0\;nor %3,%3,%2 1036 andc %3,%1,%0\;nor %3,%3,%2 1037 andc %3,%1,%0\;nor %3,%3,%2 1038 andc %4,%1,%0\;nor %3,%4,%2" 1039 [(set_attr "type" "fused_arith_logical") 1040 (set_attr "cost" "6") 1041 (set_attr "length" "8")]) 1042 1043 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1044 ;; scalar eqv -> nor 1045 (define_insn "*fuse_eqv_nor" 1046 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1047 (and:GPR (not:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1048 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1049 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1050 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1051 "(TARGET_P10_FUSION)" 1052 "@ 1053 eqv %3,%1,%0\;nor %3,%3,%2 1054 eqv %3,%1,%0\;nor %3,%3,%2 1055 eqv %3,%1,%0\;nor %3,%3,%2 1056 eqv %4,%1,%0\;nor %3,%4,%2" 1057 [(set_attr "type" "fused_arith_logical") 1058 (set_attr "cost" "6") 1059 (set_attr "length" "8")]) 1060 1061 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1062 ;; scalar nand -> nor 1063 (define_insn "*fuse_nand_nor" 1064 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1065 (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1066 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1067 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1068 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1069 "(TARGET_P10_FUSION)" 1070 "@ 1071 nand %3,%1,%0\;nor %3,%3,%2 1072 nand %3,%1,%0\;nor %3,%3,%2 1073 nand %3,%1,%0\;nor %3,%3,%2 1074 nand %4,%1,%0\;nor %3,%4,%2" 1075 [(set_attr "type" "fused_arith_logical") 1076 (set_attr "cost" "6") 1077 (set_attr "length" "8")]) 1078 1079 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1080 ;; scalar nor -> nor 1081 (define_insn "*fuse_nor_nor" 1082 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1083 (and:GPR (not:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1084 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1085 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1086 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1087 "(TARGET_P10_FUSION)" 1088 "@ 1089 nor %3,%1,%0\;nor %3,%3,%2 1090 nor %3,%1,%0\;nor %3,%3,%2 1091 nor %3,%1,%0\;nor %3,%3,%2 1092 nor %4,%1,%0\;nor %3,%4,%2" 1093 [(set_attr "type" "fused_arith_logical") 1094 (set_attr "cost" "6") 1095 (set_attr "length" "8")]) 1096 1097 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1098 ;; scalar or -> nor 1099 (define_insn "*fuse_or_nor" 1100 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1101 (and:GPR (not:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1102 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1103 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1104 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1105 "(TARGET_P10_FUSION)" 1106 "@ 1107 or %3,%1,%0\;nor %3,%3,%2 1108 or %3,%1,%0\;nor %3,%3,%2 1109 or %3,%1,%0\;nor %3,%3,%2 1110 or %4,%1,%0\;nor %3,%4,%2" 1111 [(set_attr "type" "fused_arith_logical") 1112 (set_attr "cost" "6") 1113 (set_attr "length" "8")]) 1114 1115 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1116 ;; scalar orc -> nor 1117 (define_insn "*fuse_orc_nor" 1118 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1119 (and:GPR (not:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1120 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1121 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1122 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1123 "(TARGET_P10_FUSION)" 1124 "@ 1125 orc %3,%1,%0\;nor %3,%3,%2 1126 orc %3,%1,%0\;nor %3,%3,%2 1127 orc %3,%1,%0\;nor %3,%3,%2 1128 orc %4,%1,%0\;nor %3,%4,%2" 1129 [(set_attr "type" "fused_arith_logical") 1130 (set_attr "cost" "6") 1131 (set_attr "length" "8")]) 1132 1133 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1134 ;; scalar xor -> nor 1135 (define_insn "*fuse_xor_nor" 1136 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1137 (and:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1138 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1139 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1140 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1141 "(TARGET_P10_FUSION)" 1142 "@ 1143 xor %3,%1,%0\;nor %3,%3,%2 1144 xor %3,%1,%0\;nor %3,%3,%2 1145 xor %3,%1,%0\;nor %3,%3,%2 1146 xor %4,%1,%0\;nor %3,%4,%2" 1147 [(set_attr "type" "fused_arith_logical") 1148 (set_attr "cost" "6") 1149 (set_attr "length" "8")]) 1150 1151 ;; add-logical fusion pattern generated by gen_logical_addsubf 1152 ;; scalar add -> nor 1153 (define_insn "*fuse_add_nor" 1154 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1155 (and:GPR (not:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1156 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1157 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1158 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1159 "(TARGET_P10_FUSION)" 1160 "@ 1161 add %3,%1,%0\;nor %3,%3,%2 1162 add %3,%1,%0\;nor %3,%3,%2 1163 add %3,%1,%0\;nor %3,%3,%2 1164 add %4,%1,%0\;nor %3,%4,%2" 1165 [(set_attr "type" "fused_arith_logical") 1166 (set_attr "cost" "6") 1167 (set_attr "length" "8")]) 1168 1169 ;; add-logical fusion pattern generated by gen_logical_addsubf 1170 ;; scalar subf -> nor 1171 (define_insn "*fuse_subf_nor" 1172 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1173 (and:GPR (not:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1174 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1175 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1176 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1177 "(TARGET_P10_FUSION)" 1178 "@ 1179 subf %3,%1,%0\;nor %3,%3,%2 1180 subf %3,%1,%0\;nor %3,%3,%2 1181 subf %3,%1,%0\;nor %3,%3,%2 1182 subf %4,%1,%0\;nor %3,%4,%2" 1183 [(set_attr "type" "fused_arith_logical") 1184 (set_attr "cost" "6") 1185 (set_attr "length" "8")]) 1186 1187 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1188 ;; scalar and -> or 1189 (define_insn "*fuse_and_or" 1190 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1191 (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1192 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1193 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1194 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1195 "(TARGET_P10_FUSION)" 1196 "@ 1197 and %3,%1,%0\;or %3,%3,%2 1198 and %3,%1,%0\;or %3,%3,%2 1199 and %3,%1,%0\;or %3,%3,%2 1200 and %4,%1,%0\;or %3,%4,%2" 1201 [(set_attr "type" "fused_arith_logical") 1202 (set_attr "cost" "6") 1203 (set_attr "length" "8")]) 1204 1205 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1206 ;; scalar andc -> or 1207 (define_insn "*fuse_andc_or" 1208 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1209 (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1210 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1211 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1212 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1213 "(TARGET_P10_FUSION)" 1214 "@ 1215 andc %3,%1,%0\;or %3,%3,%2 1216 andc %3,%1,%0\;or %3,%3,%2 1217 andc %3,%1,%0\;or %3,%3,%2 1218 andc %4,%1,%0\;or %3,%4,%2" 1219 [(set_attr "type" "fused_arith_logical") 1220 (set_attr "cost" "6") 1221 (set_attr "length" "8")]) 1222 1223 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1224 ;; scalar eqv -> or 1225 (define_insn "*fuse_eqv_or" 1226 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1227 (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1228 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1229 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1230 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1231 "(TARGET_P10_FUSION)" 1232 "@ 1233 eqv %3,%1,%0\;or %3,%3,%2 1234 eqv %3,%1,%0\;or %3,%3,%2 1235 eqv %3,%1,%0\;or %3,%3,%2 1236 eqv %4,%1,%0\;or %3,%4,%2" 1237 [(set_attr "type" "fused_arith_logical") 1238 (set_attr "cost" "6") 1239 (set_attr "length" "8")]) 1240 1241 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1242 ;; scalar nand -> or 1243 (define_insn "*fuse_nand_or" 1244 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1245 (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1246 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1247 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1248 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1249 "(TARGET_P10_FUSION)" 1250 "@ 1251 nand %3,%1,%0\;or %3,%3,%2 1252 nand %3,%1,%0\;or %3,%3,%2 1253 nand %3,%1,%0\;or %3,%3,%2 1254 nand %4,%1,%0\;or %3,%4,%2" 1255 [(set_attr "type" "fused_arith_logical") 1256 (set_attr "cost" "6") 1257 (set_attr "length" "8")]) 1258 1259 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1260 ;; scalar nor -> or 1261 (define_insn "*fuse_nor_or" 1262 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1263 (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1264 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1265 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1266 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1267 "(TARGET_P10_FUSION)" 1268 "@ 1269 nor %3,%1,%0\;or %3,%3,%2 1270 nor %3,%1,%0\;or %3,%3,%2 1271 nor %3,%1,%0\;or %3,%3,%2 1272 nor %4,%1,%0\;or %3,%4,%2" 1273 [(set_attr "type" "fused_arith_logical") 1274 (set_attr "cost" "6") 1275 (set_attr "length" "8")]) 1276 1277 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1278 ;; scalar or -> or 1279 (define_insn "*fuse_or_or" 1280 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1281 (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1282 (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 1283 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1284 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1285 "(TARGET_P10_FUSION)" 1286 "@ 1287 or %3,%1,%0\;or %3,%3,%2 1288 or %3,%1,%0\;or %3,%3,%2 1289 or %3,%1,%0\;or %3,%3,%2 1290 or %4,%1,%0\;or %3,%4,%2" 1291 [(set_attr "type" "fused_arith_logical") 1292 (set_attr "cost" "6") 1293 (set_attr "length" "8")]) 1294 1295 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1296 ;; scalar orc -> or 1297 (define_insn "*fuse_orc_or" 1298 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1299 (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1300 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1301 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1302 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1303 "(TARGET_P10_FUSION)" 1304 "@ 1305 orc %3,%1,%0\;or %3,%3,%2 1306 orc %3,%1,%0\;or %3,%3,%2 1307 orc %3,%1,%0\;or %3,%3,%2 1308 orc %4,%1,%0\;or %3,%4,%2" 1309 [(set_attr "type" "fused_arith_logical") 1310 (set_attr "cost" "6") 1311 (set_attr "length" "8")]) 1312 1313 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1314 ;; scalar xor -> or 1315 (define_insn "*fuse_xor_or" 1316 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1317 (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1318 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1319 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1320 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1321 "(TARGET_P10_FUSION)" 1322 "@ 1323 xor %3,%1,%0\;or %3,%3,%2 1324 xor %3,%1,%0\;or %3,%3,%2 1325 xor %3,%1,%0\;or %3,%3,%2 1326 xor %4,%1,%0\;or %3,%4,%2" 1327 [(set_attr "type" "fused_arith_logical") 1328 (set_attr "cost" "6") 1329 (set_attr "length" "8")]) 1330 1331 ;; add-logical fusion pattern generated by gen_logical_addsubf 1332 ;; scalar add -> or 1333 (define_insn "*fuse_add_or" 1334 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1335 (ior:GPR (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1336 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1337 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1338 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1339 "(TARGET_P10_FUSION)" 1340 "@ 1341 add %3,%1,%0\;or %3,%3,%2 1342 add %3,%1,%0\;or %3,%3,%2 1343 add %3,%1,%0\;or %3,%3,%2 1344 add %4,%1,%0\;or %3,%4,%2" 1345 [(set_attr "type" "fused_arith_logical") 1346 (set_attr "cost" "6") 1347 (set_attr "length" "8")]) 1348 1349 ;; add-logical fusion pattern generated by gen_logical_addsubf 1350 ;; scalar subf -> or 1351 (define_insn "*fuse_subf_or" 1352 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1353 (ior:GPR (minus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1354 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1355 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1356 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1357 "(TARGET_P10_FUSION)" 1358 "@ 1359 subf %3,%1,%0\;or %3,%3,%2 1360 subf %3,%1,%0\;or %3,%3,%2 1361 subf %3,%1,%0\;or %3,%3,%2 1362 subf %4,%1,%0\;or %3,%4,%2" 1363 [(set_attr "type" "fused_arith_logical") 1364 (set_attr "cost" "6") 1365 (set_attr "length" "8")]) 1366 1367 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1368 ;; scalar and -> orc 1369 (define_insn "*fuse_and_orc" 1370 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1371 (ior:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1372 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1373 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1374 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1375 "(TARGET_P10_FUSION)" 1376 "@ 1377 and %3,%1,%0\;orc %3,%3,%2 1378 and %3,%1,%0\;orc %3,%3,%2 1379 and %3,%1,%0\;orc %3,%3,%2 1380 and %4,%1,%0\;orc %3,%4,%2" 1381 [(set_attr "type" "fused_arith_logical") 1382 (set_attr "cost" "6") 1383 (set_attr "length" "8")]) 1384 1385 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1386 ;; scalar andc -> orc 1387 (define_insn "*fuse_andc_orc" 1388 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1389 (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1390 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1391 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1392 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1393 "(TARGET_P10_FUSION)" 1394 "@ 1395 andc %3,%1,%0\;orc %3,%3,%2 1396 andc %3,%1,%0\;orc %3,%3,%2 1397 andc %3,%1,%0\;orc %3,%3,%2 1398 andc %4,%1,%0\;orc %3,%4,%2" 1399 [(set_attr "type" "fused_arith_logical") 1400 (set_attr "cost" "6") 1401 (set_attr "length" "8")]) 1402 1403 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1404 ;; scalar eqv -> orc 1405 (define_insn "*fuse_eqv_orc" 1406 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1407 (ior:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1408 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1409 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1410 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1411 "(TARGET_P10_FUSION)" 1412 "@ 1413 eqv %3,%1,%0\;orc %3,%3,%2 1414 eqv %3,%1,%0\;orc %3,%3,%2 1415 eqv %3,%1,%0\;orc %3,%3,%2 1416 eqv %4,%1,%0\;orc %3,%4,%2" 1417 [(set_attr "type" "fused_arith_logical") 1418 (set_attr "cost" "6") 1419 (set_attr "length" "8")]) 1420 1421 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1422 ;; scalar nand -> orc 1423 (define_insn "*fuse_nand_orc" 1424 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1425 (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1426 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1427 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1428 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1429 "(TARGET_P10_FUSION)" 1430 "@ 1431 nand %3,%1,%0\;orc %3,%3,%2 1432 nand %3,%1,%0\;orc %3,%3,%2 1433 nand %3,%1,%0\;orc %3,%3,%2 1434 nand %4,%1,%0\;orc %3,%4,%2" 1435 [(set_attr "type" "fused_arith_logical") 1436 (set_attr "cost" "6") 1437 (set_attr "length" "8")]) 1438 1439 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1440 ;; scalar nor -> orc 1441 (define_insn "*fuse_nor_orc" 1442 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1443 (ior:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1444 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1445 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1446 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1447 "(TARGET_P10_FUSION)" 1448 "@ 1449 nor %3,%1,%0\;orc %3,%3,%2 1450 nor %3,%1,%0\;orc %3,%3,%2 1451 nor %3,%1,%0\;orc %3,%3,%2 1452 nor %4,%1,%0\;orc %3,%4,%2" 1453 [(set_attr "type" "fused_arith_logical") 1454 (set_attr "cost" "6") 1455 (set_attr "length" "8")]) 1456 1457 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1458 ;; scalar or -> orc 1459 (define_insn "*fuse_or_orc" 1460 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1461 (ior:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1462 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1463 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1464 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1465 "(TARGET_P10_FUSION)" 1466 "@ 1467 or %3,%1,%0\;orc %3,%3,%2 1468 or %3,%1,%0\;orc %3,%3,%2 1469 or %3,%1,%0\;orc %3,%3,%2 1470 or %4,%1,%0\;orc %3,%4,%2" 1471 [(set_attr "type" "fused_arith_logical") 1472 (set_attr "cost" "6") 1473 (set_attr "length" "8")]) 1474 1475 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1476 ;; scalar orc -> orc 1477 (define_insn "*fuse_orc_orc" 1478 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1479 (ior:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1480 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1481 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1482 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1483 "(TARGET_P10_FUSION)" 1484 "@ 1485 orc %3,%1,%0\;orc %3,%3,%2 1486 orc %3,%1,%0\;orc %3,%3,%2 1487 orc %3,%1,%0\;orc %3,%3,%2 1488 orc %4,%1,%0\;orc %3,%4,%2" 1489 [(set_attr "type" "fused_arith_logical") 1490 (set_attr "cost" "6") 1491 (set_attr "length" "8")]) 1492 1493 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1494 ;; scalar xor -> orc 1495 (define_insn "*fuse_xor_orc" 1496 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1497 (ior:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1498 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1499 (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r")))) 1500 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1501 "(TARGET_P10_FUSION)" 1502 "@ 1503 xor %3,%1,%0\;orc %3,%3,%2 1504 xor %3,%1,%0\;orc %3,%3,%2 1505 xor %3,%1,%0\;orc %3,%3,%2 1506 xor %4,%1,%0\;orc %3,%4,%2" 1507 [(set_attr "type" "fused_arith_logical") 1508 (set_attr "cost" "6") 1509 (set_attr "length" "8")]) 1510 1511 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1512 ;; scalar and -> xor 1513 (define_insn "*fuse_and_xor" 1514 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1515 (xor:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1516 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1517 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1518 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1519 "(TARGET_P10_FUSION)" 1520 "@ 1521 and %3,%1,%0\;xor %3,%3,%2 1522 and %3,%1,%0\;xor %3,%3,%2 1523 and %3,%1,%0\;xor %3,%3,%2 1524 and %4,%1,%0\;xor %3,%4,%2" 1525 [(set_attr "type" "fused_arith_logical") 1526 (set_attr "cost" "6") 1527 (set_attr "length" "8")]) 1528 1529 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1530 ;; scalar andc -> xor 1531 (define_insn "*fuse_andc_xor" 1532 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1533 (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1534 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1535 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1536 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1537 "(TARGET_P10_FUSION)" 1538 "@ 1539 andc %3,%1,%0\;xor %3,%3,%2 1540 andc %3,%1,%0\;xor %3,%3,%2 1541 andc %3,%1,%0\;xor %3,%3,%2 1542 andc %4,%1,%0\;xor %3,%4,%2" 1543 [(set_attr "type" "fused_arith_logical") 1544 (set_attr "cost" "6") 1545 (set_attr "length" "8")]) 1546 1547 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1548 ;; scalar eqv -> xor 1549 (define_insn "*fuse_eqv_xor" 1550 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1551 (xor:GPR (not:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1552 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1553 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1554 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1555 "(TARGET_P10_FUSION)" 1556 "@ 1557 eqv %3,%1,%0\;xor %3,%3,%2 1558 eqv %3,%1,%0\;xor %3,%3,%2 1559 eqv %3,%1,%0\;xor %3,%3,%2 1560 eqv %4,%1,%0\;xor %3,%4,%2" 1561 [(set_attr "type" "fused_arith_logical") 1562 (set_attr "cost" "6") 1563 (set_attr "length" "8")]) 1564 1565 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1566 ;; scalar nand -> xor 1567 (define_insn "*fuse_nand_xor" 1568 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1569 (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1570 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1571 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1572 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1573 "(TARGET_P10_FUSION)" 1574 "@ 1575 nand %3,%1,%0\;xor %3,%3,%2 1576 nand %3,%1,%0\;xor %3,%3,%2 1577 nand %3,%1,%0\;xor %3,%3,%2 1578 nand %4,%1,%0\;xor %3,%4,%2" 1579 [(set_attr "type" "fused_arith_logical") 1580 (set_attr "cost" "6") 1581 (set_attr "length" "8")]) 1582 1583 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1584 ;; scalar nor -> xor 1585 (define_insn "*fuse_nor_xor" 1586 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1587 (xor:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1588 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1589 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1590 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1591 "(TARGET_P10_FUSION)" 1592 "@ 1593 nor %3,%1,%0\;xor %3,%3,%2 1594 nor %3,%1,%0\;xor %3,%3,%2 1595 nor %3,%1,%0\;xor %3,%3,%2 1596 nor %4,%1,%0\;xor %3,%4,%2" 1597 [(set_attr "type" "fused_arith_logical") 1598 (set_attr "cost" "6") 1599 (set_attr "length" "8")]) 1600 1601 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1602 ;; scalar or -> xor 1603 (define_insn "*fuse_or_xor" 1604 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1605 (xor:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1606 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1607 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1608 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1609 "(TARGET_P10_FUSION)" 1610 "@ 1611 or %3,%1,%0\;xor %3,%3,%2 1612 or %3,%1,%0\;xor %3,%3,%2 1613 or %3,%1,%0\;xor %3,%3,%2 1614 or %4,%1,%0\;xor %3,%4,%2" 1615 [(set_attr "type" "fused_arith_logical") 1616 (set_attr "cost" "6") 1617 (set_attr "length" "8")]) 1618 1619 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1620 ;; scalar orc -> xor 1621 (define_insn "*fuse_orc_xor" 1622 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1623 (xor:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1624 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1625 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1626 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1627 "(TARGET_P10_FUSION)" 1628 "@ 1629 orc %3,%1,%0\;xor %3,%3,%2 1630 orc %3,%1,%0\;xor %3,%3,%2 1631 orc %3,%1,%0\;xor %3,%3,%2 1632 orc %4,%1,%0\;xor %3,%4,%2" 1633 [(set_attr "type" "fused_arith_logical") 1634 (set_attr "cost" "6") 1635 (set_attr "length" "8")]) 1636 1637 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1638 ;; scalar xor -> xor 1639 (define_insn "*fuse_xor_xor" 1640 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1641 (xor:GPR (xor:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1642 (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 1643 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1644 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1645 "(TARGET_P10_FUSION)" 1646 "@ 1647 xor %3,%1,%0\;xor %3,%3,%2 1648 xor %3,%1,%0\;xor %3,%3,%2 1649 xor %3,%1,%0\;xor %3,%3,%2 1650 xor %4,%1,%0\;xor %3,%4,%2" 1651 [(set_attr "type" "fused_arith_logical") 1652 (set_attr "cost" "6") 1653 (set_attr "length" "8")]) 1654 1655 ;; logical-add fusion pattern generated by gen_logical_addsubf 1656 ;; scalar and -> add 1657 (define_insn "*fuse_and_add" 1658 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1659 (plus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1660 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1661 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1662 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1663 "(TARGET_P10_FUSION)" 1664 "@ 1665 and %3,%1,%0\;add %3,%3,%2 1666 and %3,%1,%0\;add %3,%3,%2 1667 and %3,%1,%0\;add %3,%3,%2 1668 and %4,%1,%0\;add %3,%4,%2" 1669 [(set_attr "type" "fused_arith_logical") 1670 (set_attr "cost" "6") 1671 (set_attr "length" "8")]) 1672 1673 ;; logical-add fusion pattern generated by gen_logical_addsubf 1674 ;; scalar nand -> add 1675 (define_insn "*fuse_nand_add" 1676 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1677 (plus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1678 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1679 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1680 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1681 "(TARGET_P10_FUSION)" 1682 "@ 1683 nand %3,%1,%0\;add %3,%3,%2 1684 nand %3,%1,%0\;add %3,%3,%2 1685 nand %3,%1,%0\;add %3,%3,%2 1686 nand %4,%1,%0\;add %3,%4,%2" 1687 [(set_attr "type" "fused_arith_logical") 1688 (set_attr "cost" "6") 1689 (set_attr "length" "8")]) 1690 1691 ;; logical-add fusion pattern generated by gen_logical_addsubf 1692 ;; scalar nor -> add 1693 (define_insn "*fuse_nor_add" 1694 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1695 (plus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1696 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1697 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1698 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1699 "(TARGET_P10_FUSION)" 1700 "@ 1701 nor %3,%1,%0\;add %3,%3,%2 1702 nor %3,%1,%0\;add %3,%3,%2 1703 nor %3,%1,%0\;add %3,%3,%2 1704 nor %4,%1,%0\;add %3,%4,%2" 1705 [(set_attr "type" "fused_arith_logical") 1706 (set_attr "cost" "6") 1707 (set_attr "length" "8")]) 1708 1709 ;; logical-add fusion pattern generated by gen_logical_addsubf 1710 ;; scalar or -> add 1711 (define_insn "*fuse_or_add" 1712 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1713 (plus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1714 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1715 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1716 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1717 "(TARGET_P10_FUSION)" 1718 "@ 1719 or %3,%1,%0\;add %3,%3,%2 1720 or %3,%1,%0\;add %3,%3,%2 1721 or %3,%1,%0\;add %3,%3,%2 1722 or %4,%1,%0\;add %3,%4,%2" 1723 [(set_attr "type" "fused_arith_logical") 1724 (set_attr "cost" "6") 1725 (set_attr "length" "8")]) 1726 1727 ;; logical-add fusion pattern generated by gen_logical_addsubf 1728 ;; scalar and -> subf 1729 (define_insn "*fuse_and_subf" 1730 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1731 (minus:GPR (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1732 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1733 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1734 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1735 "(TARGET_P10_FUSION)" 1736 "@ 1737 and %3,%1,%0\;subf %3,%2,%3 1738 and %3,%1,%0\;subf %3,%2,%3 1739 and %3,%1,%0\;subf %3,%2,%3 1740 and %4,%1,%0\;subf %3,%2,%4" 1741 [(set_attr "type" "fused_arith_logical") 1742 (set_attr "cost" "6") 1743 (set_attr "length" "8")]) 1744 1745 ;; logical-add fusion pattern generated by gen_logical_addsubf 1746 ;; scalar nand -> subf 1747 (define_insn "*fuse_nand_subf" 1748 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1749 (minus:GPR (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1750 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1751 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1752 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1753 "(TARGET_P10_FUSION)" 1754 "@ 1755 nand %3,%1,%0\;subf %3,%2,%3 1756 nand %3,%1,%0\;subf %3,%2,%3 1757 nand %3,%1,%0\;subf %3,%2,%3 1758 nand %4,%1,%0\;subf %3,%2,%4" 1759 [(set_attr "type" "fused_arith_logical") 1760 (set_attr "cost" "6") 1761 (set_attr "length" "8")]) 1762 1763 ;; logical-add fusion pattern generated by gen_logical_addsubf 1764 ;; scalar nor -> subf 1765 (define_insn "*fuse_nor_subf" 1766 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1767 (minus:GPR (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1768 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))) 1769 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1770 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1771 "(TARGET_P10_FUSION)" 1772 "@ 1773 nor %3,%1,%0\;subf %3,%2,%3 1774 nor %3,%1,%0\;subf %3,%2,%3 1775 nor %3,%1,%0\;subf %3,%2,%3 1776 nor %4,%1,%0\;subf %3,%2,%4" 1777 [(set_attr "type" "fused_arith_logical") 1778 (set_attr "cost" "6") 1779 (set_attr "length" "8")]) 1780 1781 ;; logical-add fusion pattern generated by gen_logical_addsubf 1782 ;; scalar or -> subf 1783 (define_insn "*fuse_or_subf" 1784 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1785 (minus:GPR (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1786 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")) 1787 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 1788 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1789 "(TARGET_P10_FUSION)" 1790 "@ 1791 or %3,%1,%0\;subf %3,%2,%3 1792 or %3,%1,%0\;subf %3,%2,%3 1793 or %3,%1,%0\;subf %3,%2,%3 1794 or %4,%1,%0\;subf %3,%2,%4" 1795 [(set_attr "type" "fused_arith_logical") 1796 (set_attr "cost" "6") 1797 (set_attr "length" "8")]) 1798 1799 ;; logical-add fusion pattern generated by gen_logical_addsubf 1800 ;; scalar and -> rsubf 1801 (define_insn "*fuse_and_rsubf" 1802 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1803 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1804 (and:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1805 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1806 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1807 "(TARGET_P10_FUSION)" 1808 "@ 1809 and %3,%1,%0\;subf %3,%3,%2 1810 and %3,%1,%0\;subf %3,%3,%2 1811 and %3,%1,%0\;subf %3,%3,%2 1812 and %4,%1,%0\;subf %3,%4,%2" 1813 [(set_attr "type" "fused_arith_logical") 1814 (set_attr "cost" "6") 1815 (set_attr "length" "8")]) 1816 1817 ;; logical-add fusion pattern generated by gen_logical_addsubf 1818 ;; scalar nand -> rsubf 1819 (define_insn "*fuse_nand_rsubf" 1820 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1821 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1822 (ior:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1823 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) 1824 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1825 "(TARGET_P10_FUSION)" 1826 "@ 1827 nand %3,%1,%0\;subf %3,%3,%2 1828 nand %3,%1,%0\;subf %3,%3,%2 1829 nand %3,%1,%0\;subf %3,%3,%2 1830 nand %4,%1,%0\;subf %3,%4,%2" 1831 [(set_attr "type" "fused_arith_logical") 1832 (set_attr "cost" "6") 1833 (set_attr "length" "8")]) 1834 1835 ;; logical-add fusion pattern generated by gen_logical_addsubf 1836 ;; scalar nor -> rsubf 1837 (define_insn "*fuse_nor_rsubf" 1838 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1839 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1840 (and:GPR (not:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r")) 1841 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r"))))) 1842 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1843 "(TARGET_P10_FUSION)" 1844 "@ 1845 nor %3,%1,%0\;subf %3,%3,%2 1846 nor %3,%1,%0\;subf %3,%3,%2 1847 nor %3,%1,%0\;subf %3,%3,%2 1848 nor %4,%1,%0\;subf %3,%4,%2" 1849 [(set_attr "type" "fused_arith_logical") 1850 (set_attr "cost" "6") 1851 (set_attr "length" "8")]) 1852 1853 ;; logical-add fusion pattern generated by gen_logical_addsubf 1854 ;; scalar or -> rsubf 1855 (define_insn "*fuse_or_rsubf" 1856 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 1857 (minus:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r") 1858 (ior:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 1859 (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r")))) 1860 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 1861 "(TARGET_P10_FUSION)" 1862 "@ 1863 or %3,%1,%0\;subf %3,%3,%2 1864 or %3,%1,%0\;subf %3,%3,%2 1865 or %3,%1,%0\;subf %3,%3,%2 1866 or %4,%1,%0\;subf %3,%4,%2" 1867 [(set_attr "type" "fused_arith_logical") 1868 (set_attr "cost" "6") 1869 (set_attr "length" "8")]) 1870 1871 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1872 ;; vector vand -> vand 1873 (define_insn "*fuse_vand_vand" 1874 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1875 (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 1876 (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 1877 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1878 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1879 "(TARGET_P10_FUSION)" 1880 "@ 1881 vand %3,%1,%0\;vand %3,%3,%2 1882 vand %3,%1,%0\;vand %3,%3,%2 1883 vand %3,%1,%0\;vand %3,%3,%2 1884 vand %4,%1,%0\;vand %3,%4,%2" 1885 [(set_attr "type" "fused_vector") 1886 (set_attr "cost" "6") 1887 (set_attr "length" "8")]) 1888 1889 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1890 ;; vector vandc -> vand 1891 (define_insn "*fuse_vandc_vand" 1892 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1893 (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1894 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 1895 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1896 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1897 "(TARGET_P10_FUSION)" 1898 "@ 1899 vandc %3,%1,%0\;vand %3,%3,%2 1900 vandc %3,%1,%0\;vand %3,%3,%2 1901 vandc %3,%1,%0\;vand %3,%3,%2 1902 vandc %4,%1,%0\;vand %3,%4,%2" 1903 [(set_attr "type" "fused_vector") 1904 (set_attr "cost" "6") 1905 (set_attr "length" "8")]) 1906 1907 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1908 ;; vector veqv -> vand 1909 (define_insn "*fuse_veqv_vand" 1910 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1911 (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 1912 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 1913 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1914 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1915 "(TARGET_P10_FUSION)" 1916 "@ 1917 veqv %3,%1,%0\;vand %3,%3,%2 1918 veqv %3,%1,%0\;vand %3,%3,%2 1919 veqv %3,%1,%0\;vand %3,%3,%2 1920 veqv %4,%1,%0\;vand %3,%4,%2" 1921 [(set_attr "type" "fused_vector") 1922 (set_attr "cost" "6") 1923 (set_attr "length" "8")]) 1924 1925 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1926 ;; vector vnand -> vand 1927 (define_insn "*fuse_vnand_vand" 1928 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1929 (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1930 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 1931 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1932 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1933 "(TARGET_P10_FUSION)" 1934 "@ 1935 vnand %3,%1,%0\;vand %3,%3,%2 1936 vnand %3,%1,%0\;vand %3,%3,%2 1937 vnand %3,%1,%0\;vand %3,%3,%2 1938 vnand %4,%1,%0\;vand %3,%4,%2" 1939 [(set_attr "type" "fused_vector") 1940 (set_attr "cost" "6") 1941 (set_attr "length" "8")]) 1942 1943 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1944 ;; vector vnor -> vand 1945 (define_insn "*fuse_vnor_vand" 1946 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1947 (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1948 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 1949 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1950 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1951 "(TARGET_P10_FUSION)" 1952 "@ 1953 vnor %3,%1,%0\;vand %3,%3,%2 1954 vnor %3,%1,%0\;vand %3,%3,%2 1955 vnor %3,%1,%0\;vand %3,%3,%2 1956 vnor %4,%1,%0\;vand %3,%4,%2" 1957 [(set_attr "type" "fused_vector") 1958 (set_attr "cost" "6") 1959 (set_attr "length" "8")]) 1960 1961 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1962 ;; vector vor -> vand 1963 (define_insn "*fuse_vor_vand" 1964 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1965 (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 1966 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 1967 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1968 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1969 "(TARGET_P10_FUSION)" 1970 "@ 1971 vor %3,%1,%0\;vand %3,%3,%2 1972 vor %3,%1,%0\;vand %3,%3,%2 1973 vor %3,%1,%0\;vand %3,%3,%2 1974 vor %4,%1,%0\;vand %3,%4,%2" 1975 [(set_attr "type" "fused_vector") 1976 (set_attr "cost" "6") 1977 (set_attr "length" "8")]) 1978 1979 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1980 ;; vector vorc -> vand 1981 (define_insn "*fuse_vorc_vand" 1982 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 1983 (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 1984 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 1985 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 1986 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 1987 "(TARGET_P10_FUSION)" 1988 "@ 1989 vorc %3,%1,%0\;vand %3,%3,%2 1990 vorc %3,%1,%0\;vand %3,%3,%2 1991 vorc %3,%1,%0\;vand %3,%3,%2 1992 vorc %4,%1,%0\;vand %3,%4,%2" 1993 [(set_attr "type" "fused_vector") 1994 (set_attr "cost" "6") 1995 (set_attr "length" "8")]) 1996 1997 ;; logical-logical fusion pattern generated by gen_logical_addsubf 1998 ;; vector vxor -> vand 1999 (define_insn "*fuse_vxor_vand" 2000 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2001 (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2002 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2003 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2004 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2005 "(TARGET_P10_FUSION)" 2006 "@ 2007 vxor %3,%1,%0\;vand %3,%3,%2 2008 vxor %3,%1,%0\;vand %3,%3,%2 2009 vxor %3,%1,%0\;vand %3,%3,%2 2010 vxor %4,%1,%0\;vand %3,%4,%2" 2011 [(set_attr "type" "fused_vector") 2012 (set_attr "cost" "6") 2013 (set_attr "length" "8")]) 2014 2015 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2016 ;; vector vand -> vandc 2017 (define_insn "*fuse_vand_vandc" 2018 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2019 (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2020 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2021 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2022 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2023 "(TARGET_P10_FUSION)" 2024 "@ 2025 vand %3,%1,%0\;vandc %3,%3,%2 2026 vand %3,%1,%0\;vandc %3,%3,%2 2027 vand %3,%1,%0\;vandc %3,%3,%2 2028 vand %4,%1,%0\;vandc %3,%4,%2" 2029 [(set_attr "type" "fused_vector") 2030 (set_attr "cost" "6") 2031 (set_attr "length" "8")]) 2032 2033 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2034 ;; vector vandc -> vandc 2035 (define_insn "*fuse_vandc_vandc" 2036 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2037 (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2038 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2039 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2040 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2041 "(TARGET_P10_FUSION)" 2042 "@ 2043 vandc %3,%1,%0\;vandc %3,%3,%2 2044 vandc %3,%1,%0\;vandc %3,%3,%2 2045 vandc %3,%1,%0\;vandc %3,%3,%2 2046 vandc %4,%1,%0\;vandc %3,%4,%2" 2047 [(set_attr "type" "fused_vector") 2048 (set_attr "cost" "6") 2049 (set_attr "length" "8")]) 2050 2051 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2052 ;; vector veqv -> vandc 2053 (define_insn "*fuse_veqv_vandc" 2054 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2055 (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2056 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2057 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2058 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2059 "(TARGET_P10_FUSION)" 2060 "@ 2061 veqv %3,%1,%0\;vandc %3,%3,%2 2062 veqv %3,%1,%0\;vandc %3,%3,%2 2063 veqv %3,%1,%0\;vandc %3,%3,%2 2064 veqv %4,%1,%0\;vandc %3,%4,%2" 2065 [(set_attr "type" "fused_vector") 2066 (set_attr "cost" "6") 2067 (set_attr "length" "8")]) 2068 2069 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2070 ;; vector vnand -> vandc 2071 (define_insn "*fuse_vnand_vandc" 2072 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2073 (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2074 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2075 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2076 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2077 "(TARGET_P10_FUSION)" 2078 "@ 2079 vnand %3,%1,%0\;vandc %3,%3,%2 2080 vnand %3,%1,%0\;vandc %3,%3,%2 2081 vnand %3,%1,%0\;vandc %3,%3,%2 2082 vnand %4,%1,%0\;vandc %3,%4,%2" 2083 [(set_attr "type" "fused_vector") 2084 (set_attr "cost" "6") 2085 (set_attr "length" "8")]) 2086 2087 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2088 ;; vector vnor -> vandc 2089 (define_insn "*fuse_vnor_vandc" 2090 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2091 (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2092 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2093 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2094 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2095 "(TARGET_P10_FUSION)" 2096 "@ 2097 vnor %3,%1,%0\;vandc %3,%3,%2 2098 vnor %3,%1,%0\;vandc %3,%3,%2 2099 vnor %3,%1,%0\;vandc %3,%3,%2 2100 vnor %4,%1,%0\;vandc %3,%4,%2" 2101 [(set_attr "type" "fused_vector") 2102 (set_attr "cost" "6") 2103 (set_attr "length" "8")]) 2104 2105 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2106 ;; vector vor -> vandc 2107 (define_insn "*fuse_vor_vandc" 2108 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2109 (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2110 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2111 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2112 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2113 "(TARGET_P10_FUSION)" 2114 "@ 2115 vor %3,%1,%0\;vandc %3,%3,%2 2116 vor %3,%1,%0\;vandc %3,%3,%2 2117 vor %3,%1,%0\;vandc %3,%3,%2 2118 vor %4,%1,%0\;vandc %3,%4,%2" 2119 [(set_attr "type" "fused_vector") 2120 (set_attr "cost" "6") 2121 (set_attr "length" "8")]) 2122 2123 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2124 ;; vector vorc -> vandc 2125 (define_insn "*fuse_vorc_vandc" 2126 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2127 (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2128 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2129 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2130 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2131 "(TARGET_P10_FUSION)" 2132 "@ 2133 vorc %3,%1,%0\;vandc %3,%3,%2 2134 vorc %3,%1,%0\;vandc %3,%3,%2 2135 vorc %3,%1,%0\;vandc %3,%3,%2 2136 vorc %4,%1,%0\;vandc %3,%4,%2" 2137 [(set_attr "type" "fused_vector") 2138 (set_attr "cost" "6") 2139 (set_attr "length" "8")]) 2140 2141 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2142 ;; vector vxor -> vandc 2143 (define_insn "*fuse_vxor_vandc" 2144 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2145 (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2146 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2147 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2148 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2149 "(TARGET_P10_FUSION)" 2150 "@ 2151 vxor %3,%1,%0\;vandc %3,%3,%2 2152 vxor %3,%1,%0\;vandc %3,%3,%2 2153 vxor %3,%1,%0\;vandc %3,%3,%2 2154 vxor %4,%1,%0\;vandc %3,%4,%2" 2155 [(set_attr "type" "fused_vector") 2156 (set_attr "cost" "6") 2157 (set_attr "length" "8")]) 2158 2159 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2160 ;; vector vand -> veqv 2161 (define_insn "*fuse_vand_veqv" 2162 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2163 (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2164 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2165 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2166 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2167 "(TARGET_P10_FUSION)" 2168 "@ 2169 vand %3,%1,%0\;veqv %3,%3,%2 2170 vand %3,%1,%0\;veqv %3,%3,%2 2171 vand %3,%1,%0\;veqv %3,%3,%2 2172 vand %4,%1,%0\;veqv %3,%4,%2" 2173 [(set_attr "type" "fused_vector") 2174 (set_attr "cost" "6") 2175 (set_attr "length" "8")]) 2176 2177 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2178 ;; vector vandc -> veqv 2179 (define_insn "*fuse_vandc_veqv" 2180 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2181 (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2182 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2183 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2184 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2185 "(TARGET_P10_FUSION)" 2186 "@ 2187 vandc %3,%1,%0\;veqv %3,%3,%2 2188 vandc %3,%1,%0\;veqv %3,%3,%2 2189 vandc %3,%1,%0\;veqv %3,%3,%2 2190 vandc %4,%1,%0\;veqv %3,%4,%2" 2191 [(set_attr "type" "fused_vector") 2192 (set_attr "cost" "6") 2193 (set_attr "length" "8")]) 2194 2195 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2196 ;; vector veqv -> veqv 2197 (define_insn "*fuse_veqv_veqv" 2198 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2199 (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2200 (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) 2201 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2202 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2203 "(TARGET_P10_FUSION)" 2204 "@ 2205 veqv %3,%1,%0\;veqv %3,%3,%2 2206 veqv %3,%1,%0\;veqv %3,%3,%2 2207 veqv %3,%1,%0\;veqv %3,%3,%2 2208 veqv %4,%1,%0\;veqv %3,%4,%2" 2209 [(set_attr "type" "fused_vector") 2210 (set_attr "cost" "6") 2211 (set_attr "length" "8")]) 2212 2213 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2214 ;; vector vnand -> veqv 2215 (define_insn "*fuse_vnand_veqv" 2216 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2217 (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2218 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2219 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2220 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2221 "(TARGET_P10_FUSION)" 2222 "@ 2223 vnand %3,%1,%0\;veqv %3,%3,%2 2224 vnand %3,%1,%0\;veqv %3,%3,%2 2225 vnand %3,%1,%0\;veqv %3,%3,%2 2226 vnand %4,%1,%0\;veqv %3,%4,%2" 2227 [(set_attr "type" "fused_vector") 2228 (set_attr "cost" "6") 2229 (set_attr "length" "8")]) 2230 2231 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2232 ;; vector vnor -> veqv 2233 (define_insn "*fuse_vnor_veqv" 2234 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2235 (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2236 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2237 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2238 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2239 "(TARGET_P10_FUSION)" 2240 "@ 2241 vnor %3,%1,%0\;veqv %3,%3,%2 2242 vnor %3,%1,%0\;veqv %3,%3,%2 2243 vnor %3,%1,%0\;veqv %3,%3,%2 2244 vnor %4,%1,%0\;veqv %3,%4,%2" 2245 [(set_attr "type" "fused_vector") 2246 (set_attr "cost" "6") 2247 (set_attr "length" "8")]) 2248 2249 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2250 ;; vector vor -> veqv 2251 (define_insn "*fuse_vor_veqv" 2252 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2253 (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2254 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2255 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2256 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2257 "(TARGET_P10_FUSION)" 2258 "@ 2259 vor %3,%1,%0\;veqv %3,%3,%2 2260 vor %3,%1,%0\;veqv %3,%3,%2 2261 vor %3,%1,%0\;veqv %3,%3,%2 2262 vor %4,%1,%0\;veqv %3,%4,%2" 2263 [(set_attr "type" "fused_vector") 2264 (set_attr "cost" "6") 2265 (set_attr "length" "8")]) 2266 2267 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2268 ;; vector vorc -> veqv 2269 (define_insn "*fuse_vorc_veqv" 2270 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2271 (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2272 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2273 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2274 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2275 "(TARGET_P10_FUSION)" 2276 "@ 2277 vorc %3,%1,%0\;veqv %3,%3,%2 2278 vorc %3,%1,%0\;veqv %3,%3,%2 2279 vorc %3,%1,%0\;veqv %3,%3,%2 2280 vorc %4,%1,%0\;veqv %3,%4,%2" 2281 [(set_attr "type" "fused_vector") 2282 (set_attr "cost" "6") 2283 (set_attr "length" "8")]) 2284 2285 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2286 ;; vector vxor -> veqv 2287 (define_insn "*fuse_vxor_veqv" 2288 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2289 (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2290 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2291 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2292 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2293 "(TARGET_P10_FUSION)" 2294 "@ 2295 vxor %3,%1,%0\;veqv %3,%3,%2 2296 vxor %3,%1,%0\;veqv %3,%3,%2 2297 vxor %3,%1,%0\;veqv %3,%3,%2 2298 vxor %4,%1,%0\;veqv %3,%4,%2" 2299 [(set_attr "type" "fused_vector") 2300 (set_attr "cost" "6") 2301 (set_attr "length" "8")]) 2302 2303 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2304 ;; vector vand -> vnand 2305 (define_insn "*fuse_vand_vnand" 2306 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2307 (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2308 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2309 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2310 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2311 "(TARGET_P10_FUSION)" 2312 "@ 2313 vand %3,%1,%0\;vnand %3,%3,%2 2314 vand %3,%1,%0\;vnand %3,%3,%2 2315 vand %3,%1,%0\;vnand %3,%3,%2 2316 vand %4,%1,%0\;vnand %3,%4,%2" 2317 [(set_attr "type" "fused_vector") 2318 (set_attr "cost" "6") 2319 (set_attr "length" "8")]) 2320 2321 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2322 ;; vector vandc -> vnand 2323 (define_insn "*fuse_vandc_vnand" 2324 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2325 (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2326 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2327 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2328 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2329 "(TARGET_P10_FUSION)" 2330 "@ 2331 vandc %3,%1,%0\;vnand %3,%3,%2 2332 vandc %3,%1,%0\;vnand %3,%3,%2 2333 vandc %3,%1,%0\;vnand %3,%3,%2 2334 vandc %4,%1,%0\;vnand %3,%4,%2" 2335 [(set_attr "type" "fused_vector") 2336 (set_attr "cost" "6") 2337 (set_attr "length" "8")]) 2338 2339 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2340 ;; vector veqv -> vnand 2341 (define_insn "*fuse_veqv_vnand" 2342 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2343 (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2344 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2345 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2346 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2347 "(TARGET_P10_FUSION)" 2348 "@ 2349 veqv %3,%1,%0\;vnand %3,%3,%2 2350 veqv %3,%1,%0\;vnand %3,%3,%2 2351 veqv %3,%1,%0\;vnand %3,%3,%2 2352 veqv %4,%1,%0\;vnand %3,%4,%2" 2353 [(set_attr "type" "fused_vector") 2354 (set_attr "cost" "6") 2355 (set_attr "length" "8")]) 2356 2357 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2358 ;; vector vnand -> vnand 2359 (define_insn "*fuse_vnand_vnand" 2360 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2361 (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2362 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2363 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2364 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2365 "(TARGET_P10_FUSION)" 2366 "@ 2367 vnand %3,%1,%0\;vnand %3,%3,%2 2368 vnand %3,%1,%0\;vnand %3,%3,%2 2369 vnand %3,%1,%0\;vnand %3,%3,%2 2370 vnand %4,%1,%0\;vnand %3,%4,%2" 2371 [(set_attr "type" "fused_vector") 2372 (set_attr "cost" "6") 2373 (set_attr "length" "8")]) 2374 2375 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2376 ;; vector vnor -> vnand 2377 (define_insn "*fuse_vnor_vnand" 2378 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2379 (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2380 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2381 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2382 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2383 "(TARGET_P10_FUSION)" 2384 "@ 2385 vnor %3,%1,%0\;vnand %3,%3,%2 2386 vnor %3,%1,%0\;vnand %3,%3,%2 2387 vnor %3,%1,%0\;vnand %3,%3,%2 2388 vnor %4,%1,%0\;vnand %3,%4,%2" 2389 [(set_attr "type" "fused_vector") 2390 (set_attr "cost" "6") 2391 (set_attr "length" "8")]) 2392 2393 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2394 ;; vector vor -> vnand 2395 (define_insn "*fuse_vor_vnand" 2396 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2397 (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2398 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2399 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2400 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2401 "(TARGET_P10_FUSION)" 2402 "@ 2403 vor %3,%1,%0\;vnand %3,%3,%2 2404 vor %3,%1,%0\;vnand %3,%3,%2 2405 vor %3,%1,%0\;vnand %3,%3,%2 2406 vor %4,%1,%0\;vnand %3,%4,%2" 2407 [(set_attr "type" "fused_vector") 2408 (set_attr "cost" "6") 2409 (set_attr "length" "8")]) 2410 2411 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2412 ;; vector vorc -> vnand 2413 (define_insn "*fuse_vorc_vnand" 2414 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2415 (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2416 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2417 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2418 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2419 "(TARGET_P10_FUSION)" 2420 "@ 2421 vorc %3,%1,%0\;vnand %3,%3,%2 2422 vorc %3,%1,%0\;vnand %3,%3,%2 2423 vorc %3,%1,%0\;vnand %3,%3,%2 2424 vorc %4,%1,%0\;vnand %3,%4,%2" 2425 [(set_attr "type" "fused_vector") 2426 (set_attr "cost" "6") 2427 (set_attr "length" "8")]) 2428 2429 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2430 ;; vector vxor -> vnand 2431 (define_insn "*fuse_vxor_vnand" 2432 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2433 (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2434 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2435 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2436 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2437 "(TARGET_P10_FUSION)" 2438 "@ 2439 vxor %3,%1,%0\;vnand %3,%3,%2 2440 vxor %3,%1,%0\;vnand %3,%3,%2 2441 vxor %3,%1,%0\;vnand %3,%3,%2 2442 vxor %4,%1,%0\;vnand %3,%4,%2" 2443 [(set_attr "type" "fused_vector") 2444 (set_attr "cost" "6") 2445 (set_attr "length" "8")]) 2446 2447 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2448 ;; vector vand -> vnor 2449 (define_insn "*fuse_vand_vnor" 2450 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2451 (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2452 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2453 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2454 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2455 "(TARGET_P10_FUSION)" 2456 "@ 2457 vand %3,%1,%0\;vnor %3,%3,%2 2458 vand %3,%1,%0\;vnor %3,%3,%2 2459 vand %3,%1,%0\;vnor %3,%3,%2 2460 vand %4,%1,%0\;vnor %3,%4,%2" 2461 [(set_attr "type" "fused_vector") 2462 (set_attr "cost" "6") 2463 (set_attr "length" "8")]) 2464 2465 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2466 ;; vector vandc -> vnor 2467 (define_insn "*fuse_vandc_vnor" 2468 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2469 (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2470 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2471 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2472 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2473 "(TARGET_P10_FUSION)" 2474 "@ 2475 vandc %3,%1,%0\;vnor %3,%3,%2 2476 vandc %3,%1,%0\;vnor %3,%3,%2 2477 vandc %3,%1,%0\;vnor %3,%3,%2 2478 vandc %4,%1,%0\;vnor %3,%4,%2" 2479 [(set_attr "type" "fused_vector") 2480 (set_attr "cost" "6") 2481 (set_attr "length" "8")]) 2482 2483 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2484 ;; vector veqv -> vnor 2485 (define_insn "*fuse_veqv_vnor" 2486 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2487 (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2488 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2489 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2490 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2491 "(TARGET_P10_FUSION)" 2492 "@ 2493 veqv %3,%1,%0\;vnor %3,%3,%2 2494 veqv %3,%1,%0\;vnor %3,%3,%2 2495 veqv %3,%1,%0\;vnor %3,%3,%2 2496 veqv %4,%1,%0\;vnor %3,%4,%2" 2497 [(set_attr "type" "fused_vector") 2498 (set_attr "cost" "6") 2499 (set_attr "length" "8")]) 2500 2501 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2502 ;; vector vnand -> vnor 2503 (define_insn "*fuse_vnand_vnor" 2504 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2505 (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2506 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2507 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2508 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2509 "(TARGET_P10_FUSION)" 2510 "@ 2511 vnand %3,%1,%0\;vnor %3,%3,%2 2512 vnand %3,%1,%0\;vnor %3,%3,%2 2513 vnand %3,%1,%0\;vnor %3,%3,%2 2514 vnand %4,%1,%0\;vnor %3,%4,%2" 2515 [(set_attr "type" "fused_vector") 2516 (set_attr "cost" "6") 2517 (set_attr "length" "8")]) 2518 2519 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2520 ;; vector vnor -> vnor 2521 (define_insn "*fuse_vnor_vnor" 2522 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2523 (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2524 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) 2525 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2526 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2527 "(TARGET_P10_FUSION)" 2528 "@ 2529 vnor %3,%1,%0\;vnor %3,%3,%2 2530 vnor %3,%1,%0\;vnor %3,%3,%2 2531 vnor %3,%1,%0\;vnor %3,%3,%2 2532 vnor %4,%1,%0\;vnor %3,%4,%2" 2533 [(set_attr "type" "fused_vector") 2534 (set_attr "cost" "6") 2535 (set_attr "length" "8")]) 2536 2537 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2538 ;; vector vor -> vnor 2539 (define_insn "*fuse_vor_vnor" 2540 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2541 (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2542 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2543 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2544 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2545 "(TARGET_P10_FUSION)" 2546 "@ 2547 vor %3,%1,%0\;vnor %3,%3,%2 2548 vor %3,%1,%0\;vnor %3,%3,%2 2549 vor %3,%1,%0\;vnor %3,%3,%2 2550 vor %4,%1,%0\;vnor %3,%4,%2" 2551 [(set_attr "type" "fused_vector") 2552 (set_attr "cost" "6") 2553 (set_attr "length" "8")]) 2554 2555 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2556 ;; vector vorc -> vnor 2557 (define_insn "*fuse_vorc_vnor" 2558 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2559 (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2560 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2561 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2562 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2563 "(TARGET_P10_FUSION)" 2564 "@ 2565 vorc %3,%1,%0\;vnor %3,%3,%2 2566 vorc %3,%1,%0\;vnor %3,%3,%2 2567 vorc %3,%1,%0\;vnor %3,%3,%2 2568 vorc %4,%1,%0\;vnor %3,%4,%2" 2569 [(set_attr "type" "fused_vector") 2570 (set_attr "cost" "6") 2571 (set_attr "length" "8")]) 2572 2573 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2574 ;; vector vxor -> vnor 2575 (define_insn "*fuse_vxor_vnor" 2576 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2577 (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2578 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2579 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2580 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2581 "(TARGET_P10_FUSION)" 2582 "@ 2583 vxor %3,%1,%0\;vnor %3,%3,%2 2584 vxor %3,%1,%0\;vnor %3,%3,%2 2585 vxor %3,%1,%0\;vnor %3,%3,%2 2586 vxor %4,%1,%0\;vnor %3,%4,%2" 2587 [(set_attr "type" "fused_vector") 2588 (set_attr "cost" "6") 2589 (set_attr "length" "8")]) 2590 2591 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2592 ;; vector vand -> vor 2593 (define_insn "*fuse_vand_vor" 2594 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2595 (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2596 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2597 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2598 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2599 "(TARGET_P10_FUSION)" 2600 "@ 2601 vand %3,%1,%0\;vor %3,%3,%2 2602 vand %3,%1,%0\;vor %3,%3,%2 2603 vand %3,%1,%0\;vor %3,%3,%2 2604 vand %4,%1,%0\;vor %3,%4,%2" 2605 [(set_attr "type" "fused_vector") 2606 (set_attr "cost" "6") 2607 (set_attr "length" "8")]) 2608 2609 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2610 ;; vector vandc -> vor 2611 (define_insn "*fuse_vandc_vor" 2612 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2613 (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2614 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2615 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2616 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2617 "(TARGET_P10_FUSION)" 2618 "@ 2619 vandc %3,%1,%0\;vor %3,%3,%2 2620 vandc %3,%1,%0\;vor %3,%3,%2 2621 vandc %3,%1,%0\;vor %3,%3,%2 2622 vandc %4,%1,%0\;vor %3,%4,%2" 2623 [(set_attr "type" "fused_vector") 2624 (set_attr "cost" "6") 2625 (set_attr "length" "8")]) 2626 2627 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2628 ;; vector veqv -> vor 2629 (define_insn "*fuse_veqv_vor" 2630 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2631 (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2632 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2633 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2634 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2635 "(TARGET_P10_FUSION)" 2636 "@ 2637 veqv %3,%1,%0\;vor %3,%3,%2 2638 veqv %3,%1,%0\;vor %3,%3,%2 2639 veqv %3,%1,%0\;vor %3,%3,%2 2640 veqv %4,%1,%0\;vor %3,%4,%2" 2641 [(set_attr "type" "fused_vector") 2642 (set_attr "cost" "6") 2643 (set_attr "length" "8")]) 2644 2645 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2646 ;; vector vnand -> vor 2647 (define_insn "*fuse_vnand_vor" 2648 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2649 (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2650 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2651 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2652 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2653 "(TARGET_P10_FUSION)" 2654 "@ 2655 vnand %3,%1,%0\;vor %3,%3,%2 2656 vnand %3,%1,%0\;vor %3,%3,%2 2657 vnand %3,%1,%0\;vor %3,%3,%2 2658 vnand %4,%1,%0\;vor %3,%4,%2" 2659 [(set_attr "type" "fused_vector") 2660 (set_attr "cost" "6") 2661 (set_attr "length" "8")]) 2662 2663 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2664 ;; vector vnor -> vor 2665 (define_insn "*fuse_vnor_vor" 2666 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2667 (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2668 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2669 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2670 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2671 "(TARGET_P10_FUSION)" 2672 "@ 2673 vnor %3,%1,%0\;vor %3,%3,%2 2674 vnor %3,%1,%0\;vor %3,%3,%2 2675 vnor %3,%1,%0\;vor %3,%3,%2 2676 vnor %4,%1,%0\;vor %3,%4,%2" 2677 [(set_attr "type" "fused_vector") 2678 (set_attr "cost" "6") 2679 (set_attr "length" "8")]) 2680 2681 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2682 ;; vector vor -> vor 2683 (define_insn "*fuse_vor_vor" 2684 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2685 (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2686 (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 2687 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2688 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2689 "(TARGET_P10_FUSION)" 2690 "@ 2691 vor %3,%1,%0\;vor %3,%3,%2 2692 vor %3,%1,%0\;vor %3,%3,%2 2693 vor %3,%1,%0\;vor %3,%3,%2 2694 vor %4,%1,%0\;vor %3,%4,%2" 2695 [(set_attr "type" "fused_vector") 2696 (set_attr "cost" "6") 2697 (set_attr "length" "8")]) 2698 2699 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2700 ;; vector vorc -> vor 2701 (define_insn "*fuse_vorc_vor" 2702 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2703 (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2704 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2705 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2706 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2707 "(TARGET_P10_FUSION)" 2708 "@ 2709 vorc %3,%1,%0\;vor %3,%3,%2 2710 vorc %3,%1,%0\;vor %3,%3,%2 2711 vorc %3,%1,%0\;vor %3,%3,%2 2712 vorc %4,%1,%0\;vor %3,%4,%2" 2713 [(set_attr "type" "fused_vector") 2714 (set_attr "cost" "6") 2715 (set_attr "length" "8")]) 2716 2717 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2718 ;; vector vxor -> vor 2719 (define_insn "*fuse_vxor_vor" 2720 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2721 (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2722 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2723 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2724 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2725 "(TARGET_P10_FUSION)" 2726 "@ 2727 vxor %3,%1,%0\;vor %3,%3,%2 2728 vxor %3,%1,%0\;vor %3,%3,%2 2729 vxor %3,%1,%0\;vor %3,%3,%2 2730 vxor %4,%1,%0\;vor %3,%4,%2" 2731 [(set_attr "type" "fused_vector") 2732 (set_attr "cost" "6") 2733 (set_attr "length" "8")]) 2734 2735 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2736 ;; vector vand -> vorc 2737 (define_insn "*fuse_vand_vorc" 2738 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2739 (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2740 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2741 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2742 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2743 "(TARGET_P10_FUSION)" 2744 "@ 2745 vand %3,%1,%0\;vorc %3,%3,%2 2746 vand %3,%1,%0\;vorc %3,%3,%2 2747 vand %3,%1,%0\;vorc %3,%3,%2 2748 vand %4,%1,%0\;vorc %3,%4,%2" 2749 [(set_attr "type" "fused_vector") 2750 (set_attr "cost" "6") 2751 (set_attr "length" "8")]) 2752 2753 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2754 ;; vector vandc -> vorc 2755 (define_insn "*fuse_vandc_vorc" 2756 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2757 (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2758 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2759 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2760 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2761 "(TARGET_P10_FUSION)" 2762 "@ 2763 vandc %3,%1,%0\;vorc %3,%3,%2 2764 vandc %3,%1,%0\;vorc %3,%3,%2 2765 vandc %3,%1,%0\;vorc %3,%3,%2 2766 vandc %4,%1,%0\;vorc %3,%4,%2" 2767 [(set_attr "type" "fused_vector") 2768 (set_attr "cost" "6") 2769 (set_attr "length" "8")]) 2770 2771 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2772 ;; vector veqv -> vorc 2773 (define_insn "*fuse_veqv_vorc" 2774 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2775 (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2776 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2777 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2778 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2779 "(TARGET_P10_FUSION)" 2780 "@ 2781 veqv %3,%1,%0\;vorc %3,%3,%2 2782 veqv %3,%1,%0\;vorc %3,%3,%2 2783 veqv %3,%1,%0\;vorc %3,%3,%2 2784 veqv %4,%1,%0\;vorc %3,%4,%2" 2785 [(set_attr "type" "fused_vector") 2786 (set_attr "cost" "6") 2787 (set_attr "length" "8")]) 2788 2789 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2790 ;; vector vnand -> vorc 2791 (define_insn "*fuse_vnand_vorc" 2792 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2793 (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2794 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2795 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2796 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2797 "(TARGET_P10_FUSION)" 2798 "@ 2799 vnand %3,%1,%0\;vorc %3,%3,%2 2800 vnand %3,%1,%0\;vorc %3,%3,%2 2801 vnand %3,%1,%0\;vorc %3,%3,%2 2802 vnand %4,%1,%0\;vorc %3,%4,%2" 2803 [(set_attr "type" "fused_vector") 2804 (set_attr "cost" "6") 2805 (set_attr "length" "8")]) 2806 2807 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2808 ;; vector vnor -> vorc 2809 (define_insn "*fuse_vnor_vorc" 2810 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2811 (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2812 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2813 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2814 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2815 "(TARGET_P10_FUSION)" 2816 "@ 2817 vnor %3,%1,%0\;vorc %3,%3,%2 2818 vnor %3,%1,%0\;vorc %3,%3,%2 2819 vnor %3,%1,%0\;vorc %3,%3,%2 2820 vnor %4,%1,%0\;vorc %3,%4,%2" 2821 [(set_attr "type" "fused_vector") 2822 (set_attr "cost" "6") 2823 (set_attr "length" "8")]) 2824 2825 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2826 ;; vector vor -> vorc 2827 (define_insn "*fuse_vor_vorc" 2828 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2829 (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2830 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2831 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2832 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2833 "(TARGET_P10_FUSION)" 2834 "@ 2835 vor %3,%1,%0\;vorc %3,%3,%2 2836 vor %3,%1,%0\;vorc %3,%3,%2 2837 vor %3,%1,%0\;vorc %3,%3,%2 2838 vor %4,%1,%0\;vorc %3,%4,%2" 2839 [(set_attr "type" "fused_vector") 2840 (set_attr "cost" "6") 2841 (set_attr "length" "8")]) 2842 2843 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2844 ;; vector vorc -> vorc 2845 (define_insn "*fuse_vorc_vorc" 2846 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2847 (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2848 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2849 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2850 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2851 "(TARGET_P10_FUSION)" 2852 "@ 2853 vorc %3,%1,%0\;vorc %3,%3,%2 2854 vorc %3,%1,%0\;vorc %3,%3,%2 2855 vorc %3,%1,%0\;vorc %3,%3,%2 2856 vorc %4,%1,%0\;vorc %3,%4,%2" 2857 [(set_attr "type" "fused_vector") 2858 (set_attr "cost" "6") 2859 (set_attr "length" "8")]) 2860 2861 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2862 ;; vector vxor -> vorc 2863 (define_insn "*fuse_vxor_vorc" 2864 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2865 (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2866 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2867 (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) 2868 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2869 "(TARGET_P10_FUSION)" 2870 "@ 2871 vxor %3,%1,%0\;vorc %3,%3,%2 2872 vxor %3,%1,%0\;vorc %3,%3,%2 2873 vxor %3,%1,%0\;vorc %3,%3,%2 2874 vxor %4,%1,%0\;vorc %3,%4,%2" 2875 [(set_attr "type" "fused_vector") 2876 (set_attr "cost" "6") 2877 (set_attr "length" "8")]) 2878 2879 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2880 ;; vector vand -> vxor 2881 (define_insn "*fuse_vand_vxor" 2882 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2883 (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2884 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2885 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2886 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2887 "(TARGET_P10_FUSION)" 2888 "@ 2889 vand %3,%1,%0\;vxor %3,%3,%2 2890 vand %3,%1,%0\;vxor %3,%3,%2 2891 vand %3,%1,%0\;vxor %3,%3,%2 2892 vand %4,%1,%0\;vxor %3,%4,%2" 2893 [(set_attr "type" "fused_vector") 2894 (set_attr "cost" "6") 2895 (set_attr "length" "8")]) 2896 2897 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2898 ;; vector vandc -> vxor 2899 (define_insn "*fuse_vandc_vxor" 2900 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2901 (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2902 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2903 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2904 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2905 "(TARGET_P10_FUSION)" 2906 "@ 2907 vandc %3,%1,%0\;vxor %3,%3,%2 2908 vandc %3,%1,%0\;vxor %3,%3,%2 2909 vandc %3,%1,%0\;vxor %3,%3,%2 2910 vandc %4,%1,%0\;vxor %3,%4,%2" 2911 [(set_attr "type" "fused_vector") 2912 (set_attr "cost" "6") 2913 (set_attr "length" "8")]) 2914 2915 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2916 ;; vector veqv -> vxor 2917 (define_insn "*fuse_veqv_vxor" 2918 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2919 (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2920 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2921 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2922 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2923 "(TARGET_P10_FUSION)" 2924 "@ 2925 veqv %3,%1,%0\;vxor %3,%3,%2 2926 veqv %3,%1,%0\;vxor %3,%3,%2 2927 veqv %3,%1,%0\;vxor %3,%3,%2 2928 veqv %4,%1,%0\;vxor %3,%4,%2" 2929 [(set_attr "type" "fused_vector") 2930 (set_attr "cost" "6") 2931 (set_attr "length" "8")]) 2932 2933 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2934 ;; vector vnand -> vxor 2935 (define_insn "*fuse_vnand_vxor" 2936 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2937 (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2938 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2939 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2940 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2941 "(TARGET_P10_FUSION)" 2942 "@ 2943 vnand %3,%1,%0\;vxor %3,%3,%2 2944 vnand %3,%1,%0\;vxor %3,%3,%2 2945 vnand %3,%1,%0\;vxor %3,%3,%2 2946 vnand %4,%1,%0\;vxor %3,%4,%2" 2947 [(set_attr "type" "fused_vector") 2948 (set_attr "cost" "6") 2949 (set_attr "length" "8")]) 2950 2951 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2952 ;; vector vnor -> vxor 2953 (define_insn "*fuse_vnor_vxor" 2954 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2955 (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2956 (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) 2957 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2958 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2959 "(TARGET_P10_FUSION)" 2960 "@ 2961 vnor %3,%1,%0\;vxor %3,%3,%2 2962 vnor %3,%1,%0\;vxor %3,%3,%2 2963 vnor %3,%1,%0\;vxor %3,%3,%2 2964 vnor %4,%1,%0\;vxor %3,%4,%2" 2965 [(set_attr "type" "fused_vector") 2966 (set_attr "cost" "6") 2967 (set_attr "length" "8")]) 2968 2969 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2970 ;; vector vor -> vxor 2971 (define_insn "*fuse_vor_vxor" 2972 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2973 (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 2974 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2975 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2976 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2977 "(TARGET_P10_FUSION)" 2978 "@ 2979 vor %3,%1,%0\;vxor %3,%3,%2 2980 vor %3,%1,%0\;vxor %3,%3,%2 2981 vor %3,%1,%0\;vxor %3,%3,%2 2982 vor %4,%1,%0\;vxor %3,%4,%2" 2983 [(set_attr "type" "fused_vector") 2984 (set_attr "cost" "6") 2985 (set_attr "length" "8")]) 2986 2987 ;; logical-logical fusion pattern generated by gen_logical_addsubf 2988 ;; vector vorc -> vxor 2989 (define_insn "*fuse_vorc_vxor" 2990 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 2991 (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) 2992 (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) 2993 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 2994 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 2995 "(TARGET_P10_FUSION)" 2996 "@ 2997 vorc %3,%1,%0\;vxor %3,%3,%2 2998 vorc %3,%1,%0\;vxor %3,%3,%2 2999 vorc %3,%1,%0\;vxor %3,%3,%2 3000 vorc %4,%1,%0\;vxor %3,%4,%2" 3001 [(set_attr "type" "fused_vector") 3002 (set_attr "cost" "6") 3003 (set_attr "length" "8")]) 3004 3005 ;; logical-logical fusion pattern generated by gen_logical_addsubf 3006 ;; vector vxor -> vxor 3007 (define_insn "*fuse_vxor_vxor" 3008 [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") 3009 (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") 3010 (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) 3011 (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) 3012 (clobber (match_scratch:VM 4 "=X,X,X,&v"))] 3013 "(TARGET_P10_FUSION)" 3014 "@ 3015 vxor %3,%1,%0\;vxor %3,%3,%2 3016 vxor %3,%1,%0\;vxor %3,%3,%2 3017 vxor %3,%1,%0\;vxor %3,%3,%2 3018 vxor %4,%1,%0\;vxor %3,%4,%2" 3019 [(set_attr "type" "fused_vector") 3020 (set_attr "cost" "6") 3021 (set_attr "length" "8")]) 3022 3023 ;; add-add fusion pattern generated by gen_addadd 3024 (define_insn "*fuse_add_add" 3025 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r") 3026 (plus:GPR 3027 (plus:GPR (match_operand:GPR 0 "gpc_reg_operand" "r,r,r,r") 3028 (match_operand:GPR 1 "gpc_reg_operand" "%r,r,r,r")) 3029 (match_operand:GPR 2 "gpc_reg_operand" "r,r,r,r"))) 3030 (clobber (match_scratch:GPR 4 "=X,X,X,&r"))] 3031 "(TARGET_P10_FUSION)" 3032 "@ 3033 add %3,%1,%0\;add %3,%3,%2 3034 add %3,%1,%0\;add %3,%3,%2 3035 add %3,%1,%0\;add %3,%3,%2 3036 add %4,%1,%0\;add %3,%4,%2" 3037 [(set_attr "type" "fused_arith_logical") 3038 (set_attr "cost" "6") 3039 (set_attr "length" "8")]) 3040 3041 ;; vaddudm-vaddudm fusion pattern generated by gen_addadd 3042 (define_insn "*fuse_vaddudm_vaddudm" 3043 [(set (match_operand:V2DI 3 "altivec_register_operand" "=&0,&1,&v,v") 3044 (plus:V2DI 3045 (plus:V2DI (match_operand:V2DI 0 "altivec_register_operand" "v,v,v,v") 3046 (match_operand:V2DI 1 "altivec_register_operand" "%v,v,v,v")) 3047 (match_operand:V2DI 2 "altivec_register_operand" "v,v,v,v"))) 3048 (clobber (match_scratch:V2DI 4 "=X,X,X,&v"))] 3049 "(TARGET_P10_FUSION)" 3050 "@ 3051 vaddudm %3,%1,%0\;vaddudm %3,%3,%2 3052 vaddudm %3,%1,%0\;vaddudm %3,%3,%2 3053 vaddudm %3,%1,%0\;vaddudm %3,%3,%2 3054 vaddudm %4,%1,%0\;vaddudm %3,%4,%2" 3055 [(set_attr "type" "fused_vector") 3056 (set_attr "cost" "6") 3057 (set_attr "length" "8")]) 3058
Indexes created Sun Apr 19 00:22:55 UTC 2026