1 ;; Scheduling description for IBM POWER6 processor. 2 ;; Copyright (C) 2006-2022 Free Software Foundation, Inc. 3 ;; Contributed by Peter Steinmetz (steinmtz (a] us.ibm.com) 4 ;; 5 ;; This file is part of GCC. 6 ;; 7 ;; GCC is free software; you can redistribute it and/or modify it 8 ;; under the terms of the GNU General Public License as published 9 ;; by the Free Software Foundation; either version 3, or (at your 10 ;; option) any later version. 11 ;; 12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT 13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 ;; License for more details. 16 ;; 17 ;; You should have received a copy of the GNU General Public License 18 ;; along with GCC; see the file COPYING3. If not see 19 ;; <http://www.gnu.org/licenses/>. 20 21 ;; Sources: 22 23 ;; The POWER6 has 2 iu, 2 fpu, 2 lsu, and 1 bu/cru unit per engine 24 ;; (2 engines per chip). The chip can issue up to 5 internal ops 25 ;; per cycle. 26 27 (define_automaton "power6iu,power6lsu,power6fpu,power6bu") 28 29 (define_cpu_unit "iu1_power6,iu2_power6" "power6iu") 30 (define_cpu_unit "lsu1_power6,lsu2_power6" "power6lsu") 31 (define_cpu_unit "bpu_power6" "power6bu") 32 (define_cpu_unit "fpu1_power6,fpu2_power6" "power6fpu") 33 34 (define_reservation "LS2_power6" 35 "lsu1_power6+lsu2_power6") 36 37 (define_reservation "FPU_power6" 38 "fpu1_power6|fpu2_power6") 39 40 (define_reservation "BRU_power6" 41 "bpu_power6") 42 43 (define_reservation "LSU_power6" 44 "lsu1_power6|lsu2_power6") 45 46 (define_reservation "LSF_power6" 47 "(lsu1_power6+fpu1_power6)\ 48 |(lsu1_power6+fpu2_power6)\ 49 |(lsu2_power6+fpu1_power6)\ 50 |(lsu2_power6+fpu2_power6)") 51 52 (define_reservation "LX2_power6" 53 "(iu1_power6+iu2_power6+lsu1_power6)\ 54 |(iu1_power6+iu2_power6+lsu2_power6)") 55 56 (define_reservation "FX2_power6" 57 "iu1_power6+iu2_power6") 58 59 (define_reservation "BX2_power6" 60 "iu1_power6+iu2_power6+bpu_power6") 61 62 (define_reservation "LSX_power6" 63 "(iu1_power6+lsu1_power6)\ 64 |(iu1_power6+lsu2_power6)\ 65 |(iu2_power6+lsu1_power6)\ 66 |(iu2_power6+lsu2_power6)") 67 68 (define_reservation "FXU_power6" 69 "iu1_power6|iu2_power6") 70 71 (define_reservation "XLF_power6" 72 "(iu1_power6+lsu1_power6+fpu1_power6)\ 73 |(iu1_power6+lsu1_power6+fpu2_power6)\ 74 |(iu1_power6+lsu2_power6+fpu1_power6)\ 75 |(iu1_power6+lsu2_power6+fpu2_power6)\ 76 |(iu2_power6+lsu1_power6+fpu1_power6)\ 77 |(iu2_power6+lsu1_power6+fpu2_power6)\ 78 |(iu2_power6+lsu2_power6+fpu1_power6)\ 79 |(iu2_power6+lsu2_power6+fpu2_power6)") 80 81 (define_reservation "BRX_power6" 82 "(bpu_power6+iu1_power6)\ 83 |(bpu_power6+iu2_power6)") 84 85 ; Load/store 86 87 ; The default for a value written by a fixed point load 88 ; that is read/written by a subsequent fixed point op. 89 (define_insn_reservation "power6-load" 2 ; fx 90 (and (eq_attr "type" "load") 91 (eq_attr "sign_extend" "no") 92 (eq_attr "update" "no") 93 (eq_attr "cpu" "power6")) 94 "LSU_power6") 95 96 ; define the bypass for the case where the value written 97 ; by a fixed point load is used as the source value on 98 ; a store. 99 (define_bypass 1 "power6-load,\ 100 power6-load-update,\ 101 power6-load-update-indexed" 102 "power6-store,\ 103 power6-store-update,\ 104 power6-store-update-indexed,\ 105 power6-fpstore,\ 106 power6-fpstore-update" 107 "rs6000_store_data_bypass_p") 108 109 (define_insn_reservation "power6-load-ext" 4 ; fx 110 (and (eq_attr "type" "load") 111 (eq_attr "sign_extend" "yes") 112 (eq_attr "update" "no") 113 (eq_attr "cpu" "power6")) 114 "LSU_power6") 115 116 ; define the bypass for the case where the value written 117 ; by a fixed point load ext is used as the source value on 118 ; a store. 119 (define_bypass 1 "power6-load-ext,\ 120 power6-load-ext-update,\ 121 power6-load-ext-update-indexed" 122 "power6-store,\ 123 power6-store-update,\ 124 power6-store-update-indexed,\ 125 power6-fpstore,\ 126 power6-fpstore-update" 127 "rs6000_store_data_bypass_p") 128 129 (define_insn_reservation "power6-load-update" 2 ; fx 130 (and (eq_attr "type" "load") 131 (eq_attr "sign_extend" "no") 132 (eq_attr "update" "yes") 133 (eq_attr "indexed" "no") 134 (eq_attr "cpu" "power6")) 135 "LSX_power6") 136 137 (define_insn_reservation "power6-load-update-indexed" 2 ; fx 138 (and (eq_attr "type" "load") 139 (eq_attr "sign_extend" "no") 140 (eq_attr "update" "yes") 141 (eq_attr "indexed" "yes") 142 (eq_attr "cpu" "power6")) 143 "LSX_power6") 144 145 (define_insn_reservation "power6-load-ext-update" 4 ; fx 146 (and (eq_attr "type" "load") 147 (eq_attr "sign_extend" "yes") 148 (eq_attr "update" "yes") 149 (eq_attr "indexed" "no") 150 (eq_attr "cpu" "power6")) 151 "LSX_power6") 152 153 (define_insn_reservation "power6-load-ext-update-indexed" 4 ; fx 154 (and (eq_attr "type" "load") 155 (eq_attr "sign_extend" "yes") 156 (eq_attr "update" "yes") 157 (eq_attr "indexed" "yes") 158 (eq_attr "cpu" "power6")) 159 "LSX_power6") 160 161 (define_insn_reservation "power6-fpload" 1 162 (and (eq_attr "type" "fpload") 163 (eq_attr "update" "no") 164 (eq_attr "cpu" "power6")) 165 "LSU_power6") 166 167 (define_insn_reservation "power6-fpload-update" 1 168 (and (eq_attr "type" "fpload") 169 (eq_attr "update" "yes") 170 (eq_attr "cpu" "power6")) 171 "LSX_power6") 172 173 (define_insn_reservation "power6-store" 14 174 (and (eq_attr "type" "store") 175 (eq_attr "update" "no") 176 (eq_attr "cpu" "power6")) 177 "LSU_power6") 178 179 (define_insn_reservation "power6-store-update" 14 180 (and (eq_attr "type" "store") 181 (eq_attr "update" "yes") 182 (eq_attr "indexed" "no") 183 (eq_attr "cpu" "power6")) 184 "LSX_power6") 185 186 (define_insn_reservation "power6-store-update-indexed" 14 187 (and (eq_attr "type" "store") 188 (eq_attr "update" "yes") 189 (eq_attr "indexed" "yes") 190 (eq_attr "cpu" "power6")) 191 "LX2_power6") 192 193 (define_insn_reservation "power6-fpstore" 14 194 (and (eq_attr "type" "fpstore") 195 (eq_attr "update" "no") 196 (eq_attr "cpu" "power6")) 197 "LSF_power6") 198 199 (define_insn_reservation "power6-fpstore-update" 14 200 (and (eq_attr "type" "fpstore") 201 (eq_attr "update" "yes") 202 (eq_attr "cpu" "power6")) 203 "XLF_power6") 204 205 (define_insn_reservation "power6-larx" 3 206 (and (eq_attr "type" "load_l") 207 (eq_attr "cpu" "power6")) 208 "LS2_power6") 209 210 (define_insn_reservation "power6-stcx" 10 ; best case 211 (and (eq_attr "type" "store_c") 212 (eq_attr "cpu" "power6")) 213 "LSX_power6") 214 215 (define_insn_reservation "power6-sync" 11 ; N/A 216 (and (eq_attr "type" "sync") 217 (eq_attr "cpu" "power6")) 218 "LSU_power6") 219 220 (define_insn_reservation "power6-integer" 1 221 (and (ior (eq_attr "type" "integer") 222 (and (eq_attr "type" "add,logical") 223 (eq_attr "dot" "no"))) 224 (eq_attr "cpu" "power6")) 225 "FXU_power6") 226 227 (define_insn_reservation "power6-isel" 1 228 (and (eq_attr "type" "isel") 229 (eq_attr "cpu" "power6")) 230 "FXU_power6") 231 232 (define_insn_reservation "power6-exts" 1 233 (and (eq_attr "type" "exts") 234 (eq_attr "dot" "no") 235 (eq_attr "cpu" "power6")) 236 "FXU_power6") 237 238 (define_insn_reservation "power6-shift" 1 239 (and (eq_attr "type" "shift") 240 (eq_attr "var_shift" "no") 241 (eq_attr "dot" "no") 242 (eq_attr "cpu" "power6")) 243 "FXU_power6") 244 245 (define_insn_reservation "power6-popcnt" 1 246 (and (eq_attr "type" "popcnt") 247 (eq_attr "cpu" "power6")) 248 "FXU_power6") 249 250 (define_insn_reservation "power6-insert" 1 251 (and (eq_attr "type" "insert") 252 (eq_attr "size" "32") 253 (eq_attr "cpu" "power6")) 254 "FX2_power6") 255 256 (define_insn_reservation "power6-insert-dword" 1 257 (and (eq_attr "type" "insert") 258 (eq_attr "size" "64") 259 (eq_attr "cpu" "power6")) 260 "FX2_power6") 261 262 ; define the bypass for the case where the value written 263 ; by a fixed point op is used as the source value on a 264 ; store. 265 (define_bypass 1 "power6-integer,\ 266 power6-exts,\ 267 power6-shift,\ 268 power6-insert,\ 269 power6-insert-dword" 270 "power6-store,\ 271 power6-store-update,\ 272 power6-store-update-indexed,\ 273 power6-fpstore,\ 274 power6-fpstore-update" 275 "rs6000_store_data_bypass_p") 276 277 (define_insn_reservation "power6-cntlz" 2 278 (and (eq_attr "type" "cntlz") 279 (eq_attr "cpu" "power6")) 280 "FXU_power6") 281 282 (define_bypass 1 "power6-cntlz" 283 "power6-store,\ 284 power6-store-update,\ 285 power6-store-update-indexed,\ 286 power6-fpstore,\ 287 power6-fpstore-update" 288 "rs6000_store_data_bypass_p") 289 290 (define_insn_reservation "power6-var-rotate" 4 291 (and (eq_attr "type" "shift") 292 (eq_attr "var_shift" "yes") 293 (eq_attr "dot" "no") 294 (eq_attr "cpu" "power6")) 295 "FXU_power6") 296 297 (define_insn_reservation "power6-trap" 1 ; N/A 298 (and (eq_attr "type" "trap") 299 (eq_attr "cpu" "power6")) 300 "BRX_power6") 301 302 (define_insn_reservation "power6-two" 1 303 (and (eq_attr "type" "two") 304 (eq_attr "cpu" "power6")) 305 "(iu1_power6,iu1_power6)\ 306 |(iu1_power6+iu2_power6,nothing)\ 307 |(iu1_power6,iu2_power6)\ 308 |(iu2_power6,iu1_power6)\ 309 |(iu2_power6,iu2_power6)") 310 311 (define_insn_reservation "power6-three" 1 312 (and (eq_attr "type" "three") 313 (eq_attr "cpu" "power6")) 314 "(iu1_power6,iu1_power6,iu1_power6)\ 315 |(iu1_power6,iu1_power6,iu2_power6)\ 316 |(iu1_power6,iu2_power6,iu1_power6)\ 317 |(iu1_power6,iu2_power6,iu2_power6)\ 318 |(iu2_power6,iu1_power6,iu1_power6)\ 319 |(iu2_power6,iu1_power6,iu2_power6)\ 320 |(iu2_power6,iu2_power6,iu1_power6)\ 321 |(iu2_power6,iu2_power6,iu2_power6)\ 322 |(iu1_power6+iu2_power6,iu1_power6)\ 323 |(iu1_power6+iu2_power6,iu2_power6)\ 324 |(iu1_power6,iu1_power6+iu2_power6)\ 325 |(iu2_power6,iu1_power6+iu2_power6)") 326 327 (define_insn_reservation "power6-cmp" 1 328 (and (eq_attr "type" "cmp") 329 (eq_attr "cpu" "power6")) 330 "FXU_power6") 331 332 (define_insn_reservation "power6-compare" 1 333 (and (eq_attr "type" "exts") 334 (eq_attr "dot" "yes") 335 (eq_attr "cpu" "power6")) 336 "FXU_power6") 337 338 (define_insn_reservation "power6-fast-compare" 1 339 (and (eq_attr "type" "add,logical") 340 (eq_attr "dot" "yes") 341 (eq_attr "cpu" "power6")) 342 "FXU_power6") 343 344 ; define the bypass for the case where the value written 345 ; by a fixed point rec form op is used as the source value 346 ; on a store. 347 (define_bypass 1 "power6-compare,\ 348 power6-fast-compare" 349 "power6-store,\ 350 power6-store-update,\ 351 power6-store-update-indexed,\ 352 power6-fpstore,\ 353 power6-fpstore-update" 354 "rs6000_store_data_bypass_p") 355 356 (define_insn_reservation "power6-delayed-compare" 2 ; N/A 357 (and (eq_attr "type" "shift") 358 (eq_attr "var_shift" "no") 359 (eq_attr "dot" "yes") 360 (eq_attr "cpu" "power6")) 361 "FXU_power6") 362 363 (define_insn_reservation "power6-var-delayed-compare" 4 364 (and (eq_attr "type" "shift") 365 (eq_attr "var_shift" "yes") 366 (eq_attr "dot" "yes") 367 (eq_attr "cpu" "power6")) 368 "FXU_power6") 369 370 (define_insn_reservation "power6-lmul-cmp" 16 371 (and (eq_attr "type" "mul") 372 (eq_attr "dot" "yes") 373 (eq_attr "size" "64") 374 (eq_attr "cpu" "power6")) 375 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ 376 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); 377 378 (define_insn_reservation "power6-imul-cmp" 16 379 (and (eq_attr "type" "mul") 380 (eq_attr "dot" "yes") 381 (eq_attr "size" "32") 382 (eq_attr "cpu" "power6")) 383 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ 384 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); 385 386 (define_insn_reservation "power6-lmul" 16 387 (and (eq_attr "type" "mul") 388 (eq_attr "dot" "no") 389 (eq_attr "size" "64") 390 (eq_attr "cpu" "power6")) 391 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ 392 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); 393 394 (define_insn_reservation "power6-imul" 16 395 (and (eq_attr "type" "mul") 396 (eq_attr "dot" "no") 397 (eq_attr "size" "32") 398 (eq_attr "cpu" "power6")) 399 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ 400 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); 401 402 (define_insn_reservation "power6-imul3" 16 403 (and (eq_attr "type" "mul") 404 (eq_attr "size" "8,16") 405 (eq_attr "cpu" "power6")) 406 "(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\ 407 |(iu1_power6*16+iu2_power6*16+fpu2_power6*16)"); 408 409 (define_bypass 9 "power6-imul,\ 410 power6-lmul,\ 411 power6-imul-cmp,\ 412 power6-lmul-cmp,\ 413 power6-imul3" 414 "power6-store,\ 415 power6-store-update,\ 416 power6-store-update-indexed,\ 417 power6-fpstore,\ 418 power6-fpstore-update" 419 "rs6000_store_data_bypass_p") 420 421 (define_insn_reservation "power6-idiv" 44 422 (and (eq_attr "type" "div") 423 (eq_attr "size" "32") 424 (eq_attr "cpu" "power6")) 425 "(iu1_power6*44+iu2_power6*44+fpu1_power6*44)\ 426 |(iu1_power6*44+iu2_power6*44+fpu2_power6*44)"); 427 428 ; The latency for this bypass is yet to be defined 429 ;(define_bypass ? "power6-idiv" 430 ; "power6-store,\ 431 ; power6-store-update,\ 432 ; power6-store-update-indexed,\ 433 ; power6-fpstore,\ 434 ; power6-fpstore-update" 435 ; "rs6000_store_data_bypass_p") 436 437 (define_insn_reservation "power6-ldiv" 56 438 (and (eq_attr "type" "div") 439 (eq_attr "size" "64") 440 (eq_attr "cpu" "power6")) 441 "(iu1_power6*56+iu2_power6*56+fpu1_power6*56)\ 442 |(iu1_power6*56+iu2_power6*56+fpu2_power6*56)"); 443 444 ; The latency for this bypass is yet to be defined 445 ;(define_bypass ? "power6-ldiv" 446 ; "power6-store,\ 447 ; power6-store-update,\ 448 ; power6-store-update-indexed,\ 449 ; power6-fpstore,\ 450 ; power6-fpstore-update" 451 ; "rs6000_store_data_bypass_p") 452 453 (define_insn_reservation "power6-mtjmpr" 2 454 (and (eq_attr "type" "mtjmpr,mfjmpr") 455 (eq_attr "cpu" "power6")) 456 "BX2_power6") 457 458 (define_bypass 5 "power6-mtjmpr" "power6-branch") 459 460 (define_insn_reservation "power6-branch" 2 461 (and (eq_attr "type" "jmpreg,branch") 462 (eq_attr "cpu" "power6")) 463 "BRU_power6") 464 465 (define_bypass 5 "power6-branch" "power6-mtjmpr") 466 467 (define_insn_reservation "power6-crlogical" 3 468 (and (eq_attr "type" "cr_logical") 469 (eq_attr "cpu" "power6")) 470 "BRU_power6") 471 472 (define_bypass 3 "power6-crlogical" "power6-branch") 473 474 (define_insn_reservation "power6-mfcr" 6 ; N/A 475 (and (eq_attr "type" "mfcr") 476 (eq_attr "cpu" "power6")) 477 "BX2_power6") 478 479 ; mfcrf (1 field) 480 (define_insn_reservation "power6-mfcrf" 3 ; N/A 481 (and (eq_attr "type" "mfcrf") 482 (eq_attr "cpu" "power6")) 483 "BX2_power6") ; 484 485 ; mtcrf (1 field) 486 (define_insn_reservation "power6-mtcr" 4 ; N/A 487 (and (eq_attr "type" "mtcr") 488 (eq_attr "cpu" "power6")) 489 "BX2_power6") 490 491 (define_bypass 9 "power6-mtcr" "power6-branch") 492 493 (define_insn_reservation "power6-fp" 6 494 (and (eq_attr "type" "fp,fpsimple,dmul,dfp") 495 (eq_attr "cpu" "power6")) 496 "FPU_power6") 497 498 ; Any fp instruction that updates a CR has a latency 499 ; of 6 to a dependent branch 500 (define_bypass 6 "power6-fp" "power6-branch") 501 502 (define_bypass 1 "power6-fp" 503 "power6-fpstore,power6-fpstore-update" 504 "rs6000_store_data_bypass_p") 505 506 (define_insn_reservation "power6-fpcompare" 8 507 (and (eq_attr "type" "fpcompare") 508 (eq_attr "cpu" "power6")) 509 "FPU_power6") 510 511 (define_bypass 12 "power6-fpcompare" 512 "power6-branch,power6-crlogical") 513 514 (define_insn_reservation "power6-sdiv" 26 515 (and (eq_attr "type" "sdiv") 516 (eq_attr "cpu" "power6")) 517 "FPU_power6") 518 519 (define_insn_reservation "power6-ddiv" 32 520 (and (eq_attr "type" "ddiv") 521 (eq_attr "cpu" "power6")) 522 "FPU_power6") 523 524 (define_insn_reservation "power6-sqrt" 30 525 (and (eq_attr "type" "ssqrt") 526 (eq_attr "cpu" "power6")) 527 "FPU_power6") 528 529 (define_insn_reservation "power6-dsqrt" 42 530 (and (eq_attr "type" "dsqrt") 531 (eq_attr "cpu" "power6")) 532 "FPU_power6") 533 534 (define_insn_reservation "power6-isync" 2 ; N/A 535 (and (eq_attr "type" "isync") 536 (eq_attr "cpu" "power6")) 537 "FXU_power6") 538 539 (define_insn_reservation "power6-vecload" 1 540 (and (eq_attr "type" "vecload") 541 (eq_attr "cpu" "power6")) 542 "LSU_power6") 543 544 (define_insn_reservation "power6-vecstore" 1 545 (and (eq_attr "type" "vecstore") 546 (eq_attr "cpu" "power6")) 547 "LSF_power6") 548 549 (define_insn_reservation "power6-vecsimple" 3 550 (and (eq_attr "type" "vecsimple,veclogical,vecmove") 551 (eq_attr "cpu" "power6")) 552 "FPU_power6") 553 554 (define_bypass 6 "power6-vecsimple" "power6-veccomplex,\ 555 power6-vecperm") 556 557 (define_bypass 5 "power6-vecsimple" "power6-vecfloat") 558 559 (define_bypass 4 "power6-vecsimple" "power6-vecstore" ) 560 561 (define_insn_reservation "power6-veccmp" 1 562 (and (eq_attr "type" "veccmp,veccmpfx") 563 (eq_attr "cpu" "power6")) 564 "FPU_power6") 565 566 (define_bypass 10 "power6-veccmp" "power6-branch") 567 568 (define_insn_reservation "power6-vecfloat" 7 569 (and (eq_attr "type" "vecfloat") 570 (eq_attr "cpu" "power6")) 571 "FPU_power6") 572 573 (define_bypass 10 "power6-vecfloat" "power6-vecsimple") 574 575 (define_bypass 11 "power6-vecfloat" "power6-veccomplex,\ 576 power6-vecperm") 577 578 (define_bypass 9 "power6-vecfloat" "power6-vecstore" ) 579 580 (define_insn_reservation "power6-veccomplex" 7 581 (and (eq_attr "type" "vecsimple") 582 (eq_attr "cpu" "power6")) 583 "FPU_power6") 584 585 (define_bypass 10 "power6-veccomplex" "power6-vecsimple,\ 586 power6-vecfloat" ) 587 588 (define_bypass 9 "power6-veccomplex" "power6-vecperm" ) 589 590 (define_bypass 8 "power6-veccomplex" "power6-vecstore" ) 591 592 (define_insn_reservation "power6-vecperm" 4 593 (and (eq_attr "type" "vecperm") 594 (eq_attr "cpu" "power6")) 595 "FPU_power6") 596 597 (define_bypass 7 "power6-vecperm" "power6-vecsimple,\ 598 power6-vecfloat" ) 599 600 (define_bypass 6 "power6-vecperm" "power6-veccomplex" ) 601 602 (define_bypass 5 "power6-vecperm" "power6-vecstore" ) 603 604
Indexes created Wed Apr 15 00:22:22 UTC 2026