1 1.1 mrg /* IBM RS/6000 CPU names.. 2 1.10 mrg Copyright (C) 1991-2022 Free Software Foundation, Inc. 3 1.1 mrg Contributed by Richard Kenner (kenner (at) vlsi1.ultra.nyu.edu) 4 1.1 mrg 5 1.1 mrg This file is part of GCC. 6 1.1 mrg 7 1.1 mrg GCC is free software; you can redistribute it and/or modify it 8 1.1 mrg under the terms of the GNU General Public License as published 9 1.1 mrg by the Free Software Foundation; either version 3, or (at your 10 1.1 mrg option) any later version. 11 1.1 mrg 12 1.1 mrg GCC is distributed in the hope that it will be useful, but WITHOUT 13 1.1 mrg ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 1.1 mrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 1.1 mrg License for more details. 16 1.1 mrg 17 1.1 mrg You should have received a copy of the GNU General Public License 18 1.1 mrg along with GCC; see the file COPYING3. If not see 19 1.1 mrg <http://www.gnu.org/licenses/>. */ 20 1.1 mrg 21 1.1 mrg /* ISA masks. */ 22 1.1 mrg #ifndef ISA_2_1_MASKS 23 1.1 mrg #define ISA_2_1_MASKS OPTION_MASK_MFCRF 24 1.1 mrg #define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) 25 1.1 mrg #define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) 26 1.1 mrg 27 1.9 mrg /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on 28 1.9 mrg power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented 29 1.9 mrg as optional. Group masks by server and embedded. */ 30 1.1 mrg #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \ 31 1.1 mrg | OPTION_MASK_CMPB \ 32 1.1 mrg | OPTION_MASK_RECIP_PRECISION \ 33 1.1 mrg | OPTION_MASK_PPC_GFXOPT \ 34 1.1 mrg | OPTION_MASK_PPC_GPOPT) 35 1.1 mrg 36 1.1 mrg #define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) 37 1.1 mrg 38 1.1 mrg /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but 39 1.1 mrg altivec is a win so enable it. */ 40 1.1 mrg #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) 41 1.1 mrg #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ 42 1.1 mrg | OPTION_MASK_POPCNTD \ 43 1.1 mrg | OPTION_MASK_ALTIVEC \ 44 1.7 mrg | OPTION_MASK_VSX) 45 1.1 mrg 46 1.8 mrg /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 47 1.10 mrg fusion here, instead set it in rs6000.cc if we are tuning for a power8 48 1.8 mrg system. */ 49 1.1 mrg #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ 50 1.10 mrg | OPTION_MASK_POWER8 \ 51 1.1 mrg | OPTION_MASK_P8_VECTOR \ 52 1.1 mrg | OPTION_MASK_CRYPTO \ 53 1.3 mrg | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ 54 1.1 mrg | OPTION_MASK_QUAD_MEMORY \ 55 1.7 mrg | OPTION_MASK_QUAD_MEMORY_ATOMIC) 56 1.1 mrg 57 1.9 mrg /* ISA masks setting fusion options. */ 58 1.9 mrg #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ 59 1.9 mrg | OPTION_MASK_P8_FUSION_SIGN) 60 1.9 mrg 61 1.4 mrg /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add 62 1.4 mrg FLOAT128_HW here until we are ready to make -mfloat128 on by default. */ 63 1.9 mrg #define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \ 64 1.9 mrg | OPTION_MASK_ISEL \ 65 1.9 mrg | OPTION_MASK_MODULO \ 66 1.9 mrg | OPTION_MASK_P9_MINMAX \ 67 1.9 mrg | OPTION_MASK_P9_MISC \ 68 1.9 mrg | OPTION_MASK_P9_VECTOR) \ 69 1.9 mrg & ~OTHER_FUSION_MASKS) 70 1.4 mrg 71 1.4 mrg /* Support for the IEEE 128-bit floating point hardware requires a lot of the 72 1.4 mrg VSX instructions that are part of ISA 3.0. */ 73 1.4 mrg #define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \ 74 1.4 mrg | OPTION_MASK_P8_VECTOR \ 75 1.9 mrg | OPTION_MASK_P9_VECTOR) 76 1.9 mrg 77 1.9 mrg /* Flags that need to be turned off if -mno-power10. */ 78 1.10 mrg /* We comment out PCREL_OPT here to disable it by default because SPEC2017 79 1.10 mrg performance was degraded by it. */ 80 1.9 mrg #define OTHER_POWER10_MASKS (OPTION_MASK_MMA \ 81 1.9 mrg | OPTION_MASK_PCREL \ 82 1.10 mrg /* | OPTION_MASK_PCREL_OPT */ \ 83 1.9 mrg | OPTION_MASK_PREFIXED) 84 1.9 mrg 85 1.9 mrg #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ 86 1.9 mrg | OPTION_MASK_POWER10 \ 87 1.10 mrg | OTHER_POWER10_MASKS \ 88 1.10 mrg | OPTION_MASK_P10_FUSION) 89 1.6 mrg 90 1.6 mrg /* Flags that need to be turned off if -mno-power9-vector. */ 91 1.6 mrg #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ 92 1.6 mrg | OPTION_MASK_P9_MINMAX) 93 1.6 mrg 94 1.6 mrg /* Flags that need to be turned off if -mno-power8-vector. */ 95 1.6 mrg #define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \ 96 1.6 mrg | OPTION_MASK_P9_VECTOR \ 97 1.7 mrg | OPTION_MASK_CRYPTO) 98 1.6 mrg 99 1.6 mrg /* Flags that need to be turned off if -mno-vsx. */ 100 1.6 mrg #define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \ 101 1.6 mrg | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ 102 1.6 mrg | OPTION_MASK_FLOAT128_KEYWORD \ 103 1.7 mrg | OPTION_MASK_P8_VECTOR) 104 1.4 mrg 105 1.9 mrg /* Flags that need to be turned off if -mno-altivec. */ 106 1.9 mrg #define OTHER_ALTIVEC_MASKS (OTHER_VSX_VECTOR_MASKS \ 107 1.9 mrg | OPTION_MASK_VSX) 108 1.9 mrg 109 1.1 mrg #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) 110 1.1 mrg 111 1.1 mrg /* Deal with ports that do not have -mstrict-align. */ 112 1.1 mrg #ifdef OPTION_MASK_STRICT_ALIGN 113 1.1 mrg #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN 114 1.1 mrg #else 115 1.1 mrg #define OPTION_MASK_STRICT_ALIGN 0 116 1.1 mrg #define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0 117 1.1 mrg #ifndef MASK_STRICT_ALIGN 118 1.1 mrg #define MASK_STRICT_ALIGN 0 119 1.1 mrg #endif 120 1.1 mrg #endif 121 1.1 mrg 122 1.1 mrg /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ 123 1.1 mrg #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ 124 1.1 mrg | OPTION_MASK_CMPB \ 125 1.1 mrg | OPTION_MASK_CRYPTO \ 126 1.1 mrg | OPTION_MASK_DFP \ 127 1.1 mrg | OPTION_MASK_DLMZB \ 128 1.3 mrg | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ 129 1.6 mrg | OPTION_MASK_FLOAT128_HW \ 130 1.6 mrg | OPTION_MASK_FLOAT128_KEYWORD \ 131 1.1 mrg | OPTION_MASK_FPRND \ 132 1.9 mrg | OPTION_MASK_POWER10 \ 133 1.10 mrg | OPTION_MASK_P10_FUSION \ 134 1.1 mrg | OPTION_MASK_HTM \ 135 1.1 mrg | OPTION_MASK_ISEL \ 136 1.1 mrg | OPTION_MASK_MFCRF \ 137 1.9 mrg | OPTION_MASK_MMA \ 138 1.4 mrg | OPTION_MASK_MODULO \ 139 1.1 mrg | OPTION_MASK_MULHW \ 140 1.1 mrg | OPTION_MASK_NO_UPDATE \ 141 1.10 mrg | OPTION_MASK_POWER8 \ 142 1.1 mrg | OPTION_MASK_P8_FUSION \ 143 1.1 mrg | OPTION_MASK_P8_VECTOR \ 144 1.4 mrg | OPTION_MASK_P9_MINMAX \ 145 1.4 mrg | OPTION_MASK_P9_MISC \ 146 1.4 mrg | OPTION_MASK_P9_VECTOR \ 147 1.9 mrg | OPTION_MASK_PCREL \ 148 1.10 mrg | OPTION_MASK_PCREL_OPT \ 149 1.1 mrg | OPTION_MASK_POPCNTB \ 150 1.1 mrg | OPTION_MASK_POPCNTD \ 151 1.1 mrg | OPTION_MASK_POWERPC64 \ 152 1.1 mrg | OPTION_MASK_PPC_GFXOPT \ 153 1.1 mrg | OPTION_MASK_PPC_GPOPT \ 154 1.9 mrg | OPTION_MASK_PREFIXED \ 155 1.1 mrg | OPTION_MASK_QUAD_MEMORY \ 156 1.1 mrg | OPTION_MASK_QUAD_MEMORY_ATOMIC \ 157 1.1 mrg | OPTION_MASK_RECIP_PRECISION \ 158 1.1 mrg | OPTION_MASK_SOFT_FLOAT \ 159 1.1 mrg | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ 160 1.7 mrg | OPTION_MASK_VSX) 161 1.1 mrg 162 1.1 mrg #endif 163 1.1 mrg 164 1.1 mrg /* This table occasionally claims that a processor does not support a 165 1.1 mrg particular feature even though it does, but the feature is slower than the 166 1.1 mrg alternative. Thus, it shouldn't be relied on as a complete description of 167 1.1 mrg the processor's support. 168 1.1 mrg 169 1.1 mrg Please keep this list in order, and don't forget to update the documentation 170 1.1 mrg in invoke.texi when adding a new processor or flag. 171 1.1 mrg 172 1.1 mrg Before including this file, define a macro: 173 1.1 mrg 174 1.1 mrg RS6000_CPU (NAME, CPU, FLAGS) 175 1.1 mrg 176 1.1 mrg where the arguments are the fields of struct rs6000_ptt. */ 177 1.1 mrg 178 1.1 mrg RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) 179 1.1 mrg RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) 180 1.1 mrg RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) 181 1.1 mrg RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB) 182 1.1 mrg RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) 183 1.1 mrg RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) 184 1.1 mrg RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) 185 1.1 mrg RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) 186 1.1 mrg RS6000_CPU ("476", PROCESSOR_PPC476, 187 1.1 mrg MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB 188 1.1 mrg | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) 189 1.1 mrg RS6000_CPU ("476fp", PROCESSOR_PPC476, 190 1.1 mrg MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND 191 1.1 mrg | MASK_CMPB | MASK_MULHW | MASK_DLMZB) 192 1.1 mrg RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) 193 1.7 mrg RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE) 194 1.1 mrg RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) 195 1.1 mrg RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) 196 1.1 mrg RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) 197 1.1 mrg RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) 198 1.1 mrg RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) 199 1.1 mrg RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64) 200 1.1 mrg RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) 201 1.1 mrg RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT) 202 1.1 mrg RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) 203 1.1 mrg RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) 204 1.1 mrg RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) 205 1.1 mrg RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 206 1.1 mrg RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 207 1.1 mrg RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 208 1.1 mrg RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) 209 1.1 mrg RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) 210 1.1 mrg RS6000_CPU ("a2", PROCESSOR_PPCA2, 211 1.1 mrg MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB 212 1.1 mrg | MASK_NO_UPDATE) 213 1.1 mrg RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) 214 1.1 mrg RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) 215 1.1 mrg RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) 216 1.1 mrg RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, 217 1.1 mrg MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) 218 1.1 mrg RS6000_CPU ("e5500", PROCESSOR_PPCE5500, 219 1.1 mrg MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) 220 1.1 mrg RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 221 1.1 mrg | MASK_MFCRF | MASK_ISEL) 222 1.1 mrg RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 223 1.1 mrg RS6000_CPU ("970", PROCESSOR_POWER4, 224 1.1 mrg POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) 225 1.1 mrg RS6000_CPU ("cell", PROCESSOR_CELL, 226 1.1 mrg POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) 227 1.1 mrg RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) 228 1.1 mrg RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) 229 1.1 mrg RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) 230 1.1 mrg RS6000_CPU ("G5", PROCESSOR_POWER4, 231 1.1 mrg POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) 232 1.1 mrg RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) 233 1.1 mrg RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) 234 1.1 mrg RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT 235 1.1 mrg | MASK_PPC_GFXOPT | MASK_MFCRF) 236 1.1 mrg RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT 237 1.1 mrg | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) 238 1.1 mrg RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT 239 1.1 mrg | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) 240 1.1 mrg RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT 241 1.1 mrg | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND 242 1.1 mrg | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) 243 1.1 mrg RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT 244 1.1 mrg | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND 245 1.9 mrg | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) 246 1.7 mrg RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) 247 1.10 mrg RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER 248 1.10 mrg | OPTION_MASK_HTM) 249 1.10 mrg RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER 250 1.10 mrg | OPTION_MASK_HTM) 251 1.9 mrg RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) 252 1.1 mrg RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) 253 1.1 mrg RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) 254 1.10 mrg RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER 255 1.10 mrg | OPTION_MASK_HTM) 256 1.1 mrg RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) 257
Indexes created Wed Apr 22 00:22:44 UTC 2026