1 /* IBM RS/6000 CPU names.. 2 Copyright (C) 1991-2022 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner (at) vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 /* ISA masks. */ 22 #ifndef ISA_2_1_MASKS 23 #define ISA_2_1_MASKS OPTION_MASK_MFCRF 24 #define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB) 25 #define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND) 26 27 /* For ISA 2.05, don't add ALTIVEC, since in general it isn't a win on 28 power6. In ISA 2.04, fsel, fre, fsqrt, etc. were no longer documented 29 as optional. Group masks by server and embedded. */ 30 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \ 31 | OPTION_MASK_CMPB \ 32 | OPTION_MASK_RECIP_PRECISION \ 33 | OPTION_MASK_PPC_GFXOPT \ 34 | OPTION_MASK_PPC_GPOPT) 35 36 #define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP) 37 38 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but 39 altivec is a win so enable it. */ 40 #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD) 41 #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \ 42 | OPTION_MASK_POPCNTD \ 43 | OPTION_MASK_ALTIVEC \ 44 | OPTION_MASK_VSX) 45 46 /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 47 fusion here, instead set it in rs6000.cc if we are tuning for a power8 48 system. */ 49 #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ 50 | OPTION_MASK_POWER8 \ 51 | OPTION_MASK_P8_VECTOR \ 52 | OPTION_MASK_CRYPTO \ 53 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ 54 | OPTION_MASK_QUAD_MEMORY \ 55 | OPTION_MASK_QUAD_MEMORY_ATOMIC) 56 57 /* ISA masks setting fusion options. */ 58 #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ 59 | OPTION_MASK_P8_FUSION_SIGN) 60 61 /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add 62 FLOAT128_HW here until we are ready to make -mfloat128 on by default. */ 63 #define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \ 64 | OPTION_MASK_ISEL \ 65 | OPTION_MASK_MODULO \ 66 | OPTION_MASK_P9_MINMAX \ 67 | OPTION_MASK_P9_MISC \ 68 | OPTION_MASK_P9_VECTOR) \ 69 & ~OTHER_FUSION_MASKS) 70 71 /* Support for the IEEE 128-bit floating point hardware requires a lot of the 72 VSX instructions that are part of ISA 3.0. */ 73 #define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \ 74 | OPTION_MASK_P8_VECTOR \ 75 | OPTION_MASK_P9_VECTOR) 76 77 /* Flags that need to be turned off if -mno-power10. */ 78 /* We comment out PCREL_OPT here to disable it by default because SPEC2017 79 performance was degraded by it. */ 80 #define OTHER_POWER10_MASKS (OPTION_MASK_MMA \ 81 | OPTION_MASK_PCREL \ 82 /* | OPTION_MASK_PCREL_OPT */ \ 83 | OPTION_MASK_PREFIXED) 84 85 #define ISA_3_1_MASKS_SERVER (ISA_3_0_MASKS_SERVER \ 86 | OPTION_MASK_POWER10 \ 87 | OTHER_POWER10_MASKS \ 88 | OPTION_MASK_P10_FUSION) 89 90 /* Flags that need to be turned off if -mno-power9-vector. */ 91 #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ 92 | OPTION_MASK_P9_MINMAX) 93 94 /* Flags that need to be turned off if -mno-power8-vector. */ 95 #define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \ 96 | OPTION_MASK_P9_VECTOR \ 97 | OPTION_MASK_CRYPTO) 98 99 /* Flags that need to be turned off if -mno-vsx. */ 100 #define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \ 101 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ 102 | OPTION_MASK_FLOAT128_KEYWORD \ 103 | OPTION_MASK_P8_VECTOR) 104 105 /* Flags that need to be turned off if -mno-altivec. */ 106 #define OTHER_ALTIVEC_MASKS (OTHER_VSX_VECTOR_MASKS \ 107 | OPTION_MASK_VSX) 108 109 #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC) 110 111 /* Deal with ports that do not have -mstrict-align. */ 112 #ifdef OPTION_MASK_STRICT_ALIGN 113 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN 114 #else 115 #define OPTION_MASK_STRICT_ALIGN 0 116 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0 117 #ifndef MASK_STRICT_ALIGN 118 #define MASK_STRICT_ALIGN 0 119 #endif 120 #endif 121 122 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */ 123 #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \ 124 | OPTION_MASK_CMPB \ 125 | OPTION_MASK_CRYPTO \ 126 | OPTION_MASK_DFP \ 127 | OPTION_MASK_DLMZB \ 128 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ 129 | OPTION_MASK_FLOAT128_HW \ 130 | OPTION_MASK_FLOAT128_KEYWORD \ 131 | OPTION_MASK_FPRND \ 132 | OPTION_MASK_POWER10 \ 133 | OPTION_MASK_P10_FUSION \ 134 | OPTION_MASK_HTM \ 135 | OPTION_MASK_ISEL \ 136 | OPTION_MASK_MFCRF \ 137 | OPTION_MASK_MMA \ 138 | OPTION_MASK_MODULO \ 139 | OPTION_MASK_MULHW \ 140 | OPTION_MASK_NO_UPDATE \ 141 | OPTION_MASK_POWER8 \ 142 | OPTION_MASK_P8_FUSION \ 143 | OPTION_MASK_P8_VECTOR \ 144 | OPTION_MASK_P9_MINMAX \ 145 | OPTION_MASK_P9_MISC \ 146 | OPTION_MASK_P9_VECTOR \ 147 | OPTION_MASK_PCREL \ 148 | OPTION_MASK_PCREL_OPT \ 149 | OPTION_MASK_POPCNTB \ 150 | OPTION_MASK_POPCNTD \ 151 | OPTION_MASK_POWERPC64 \ 152 | OPTION_MASK_PPC_GFXOPT \ 153 | OPTION_MASK_PPC_GPOPT \ 154 | OPTION_MASK_PREFIXED \ 155 | OPTION_MASK_QUAD_MEMORY \ 156 | OPTION_MASK_QUAD_MEMORY_ATOMIC \ 157 | OPTION_MASK_RECIP_PRECISION \ 158 | OPTION_MASK_SOFT_FLOAT \ 159 | OPTION_MASK_STRICT_ALIGN_OPTIONAL \ 160 | OPTION_MASK_VSX) 161 162 #endif 163 164 /* This table occasionally claims that a processor does not support a 165 particular feature even though it does, but the feature is slower than the 166 alternative. Thus, it shouldn't be relied on as a complete description of 167 the processor's support. 168 169 Please keep this list in order, and don't forget to update the documentation 170 in invoke.texi when adding a new processor or flag. 171 172 Before including this file, define a macro: 173 174 RS6000_CPU (NAME, CPU, FLAGS) 175 176 where the arguments are the fields of struct rs6000_ptt. */ 177 178 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT) 179 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN) 180 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) 181 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB) 182 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) 183 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) 184 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB) 185 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB) 186 RS6000_CPU ("476", PROCESSOR_PPC476, 187 MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB 188 | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB) 189 RS6000_CPU ("476fp", PROCESSOR_PPC476, 190 MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND 191 | MASK_CMPB | MASK_MULHW | MASK_DLMZB) 192 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0) 193 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE) 194 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT) 195 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT) 196 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT) 197 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT) 198 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT) 199 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64) 200 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) 201 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT) 202 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK) 203 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK) 204 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT) 205 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 206 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 207 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 208 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL) 209 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL) 210 RS6000_CPU ("a2", PROCESSOR_PPCA2, 211 MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB 212 | MASK_NO_UPDATE) 213 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT) 214 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0) 215 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL) 216 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64, 217 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) 218 RS6000_CPU ("e5500", PROCESSOR_PPCE5500, 219 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL) 220 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64 221 | MASK_MFCRF | MASK_ISEL) 222 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT) 223 RS6000_CPU ("970", PROCESSOR_POWER4, 224 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) 225 RS6000_CPU ("cell", PROCESSOR_CELL, 226 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) 227 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT) 228 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT) 229 RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK) 230 RS6000_CPU ("G5", PROCESSOR_POWER4, 231 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64) 232 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB) 233 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64) 234 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT 235 | MASK_PPC_GFXOPT | MASK_MFCRF) 236 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT 237 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB) 238 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT 239 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND) 240 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT 241 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND 242 | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) 243 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT 244 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND 245 | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION) 246 RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER) 247 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER 248 | OPTION_MASK_HTM) 249 RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER 250 | OPTION_MASK_HTM) 251 RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 | ISA_3_1_MASKS_SERVER) 252 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0) 253 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64) 254 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER 255 | OPTION_MASK_HTM) 256 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64) 257
Indexes created Wed Apr 22 00:22:44 UTC 2026