1 ;;- Machine description for GNU compiler -- S/390 / zSeries version. 2 ;; Copyright (C) 1999-2022 Free Software Foundation, Inc. 3 ;; Contributed by Hartmut Penner (hpenner (a] de.ibm.com) and 4 ;; Ulrich Weigand (uweigand (a] de.ibm.com) and 5 ;; Andreas Krebbel (Andreas.Krebbel (a] de.ibm.com) 6 7 ;; This file is part of GCC. 8 9 ;; GCC is free software; you can redistribute it and/or modify it under 10 ;; the terms of the GNU General Public License as published by the Free 11 ;; Software Foundation; either version 3, or (at your option) any later 12 ;; version. 13 14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17 ;; for more details. 18 19 ;; You should have received a copy of the GNU General Public License 20 ;; along with GCC; see the file COPYING3. If not see 21 ;; <http://www.gnu.org/licenses/>. 22 23 ;; 24 ;; See constraints.md for a description of constraints specific to s390. 25 ;; 26 27 ;; Special formats used for outputting 390 instructions. 28 ;; 29 ;; %C: print opcode suffix for branch condition. 30 ;; %D: print opcode suffix for inverse branch condition. 31 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix 32 ;; %G: print the size of the operand in bytes. 33 ;; %O: print only the displacement of a memory reference. 34 ;; %R: print only the base register of a memory reference. 35 ;; %S: print S-type memory reference (base+displacement). 36 ;; %N: print the second word of a DImode operand. 37 ;; %M: print the second word of a TImode operand. 38 ;; %Y: print shift count operand. 39 ;; 40 ;; %b: print integer X as if it's an unsigned byte. 41 ;; %c: print integer X as if it's an signed byte. 42 ;; %x: print integer X as if it's an unsigned halfword. 43 ;; %h: print integer X as if it's a signed halfword. 44 ;; %i: print the first nonzero HImode part of X. 45 ;; %j: print the first HImode part unequal to -1 of X. 46 ;; %k: print the first nonzero SImode part of X. 47 ;; %m: print the first SImode part unequal to -1 of X. 48 ;; %o: print integer X as if it's an unsigned 32bit word. 49 ;; 50 ;; We have a special constraint for pattern matching. 51 ;; 52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. 53 ;; 54 55 ;; 56 ;; UNSPEC usage 57 ;; 58 59 (define_c_enum "unspec" [ 60 ; Miscellaneous 61 UNSPEC_ROUND 62 UNSPEC_ICM 63 UNSPEC_TIE 64 65 ; Convert CC into a str comparison result and copy it into an 66 ; integer register 67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1) 68 UNSPEC_STRCMPCC_TO_INT 69 70 ; Copy CC as is into the lower 2 bits of an integer register 71 UNSPEC_CC_TO_INT 72 73 ; The right hand side of an setmem 74 UNSPEC_REPLICATE_BYTE 75 76 ; GOT/PLT and lt-relative accesses 77 UNSPEC_LTREL_OFFSET 78 UNSPEC_POOL_OFFSET 79 UNSPEC_GOTENT 80 UNSPEC_GOT 81 UNSPEC_GOTOFF 82 UNSPEC_PLT31 83 UNSPEC_PLTOFF 84 85 ; Literal pool 86 UNSPEC_RELOAD_BASE 87 UNSPEC_MAIN_BASE 88 UNSPEC_LTREF 89 UNSPEC_INSN 90 UNSPEC_EXECUTE 91 UNSPEC_EXECUTE_JUMP 92 93 ; Atomic Support 94 UNSPEC_MB 95 UNSPEC_MOVA 96 97 ; TLS relocation specifiers 98 UNSPEC_TLSGD 99 UNSPEC_TLSLDM 100 UNSPEC_NTPOFF 101 UNSPEC_DTPOFF 102 UNSPEC_GOTNTPOFF 103 UNSPEC_INDNTPOFF 104 105 ; TLS support 106 UNSPEC_TLSLDM_NTPOFF 107 UNSPEC_TLS_LOAD 108 UNSPEC_GET_TP 109 110 ; String Functions 111 UNSPEC_SRST 112 UNSPEC_MVST 113 114 ; Stack Smashing Protector 115 UNSPEC_SP_SET 116 UNSPEC_SP_TEST 117 118 ; Split stack support 119 UNSPEC_STACK_CHECK 120 121 ; Test Data Class (TDC) 122 UNSPEC_TDC_INSN 123 124 ; Byte-wise Population Count 125 UNSPEC_POPCNT 126 UNSPEC_COPYSIGN 127 128 ; Load FP Integer 129 UNSPEC_FPINT_FLOOR 130 UNSPEC_FPINT_BTRUNC 131 UNSPEC_FPINT_ROUND 132 UNSPEC_FPINT_CEIL 133 UNSPEC_FPINT_NEARBYINT 134 UNSPEC_FPINT_RINT 135 136 UNSPEC_LCBB 137 138 ; Vector 139 UNSPEC_VEC_SMULT_HI 140 UNSPEC_VEC_UMULT_HI 141 UNSPEC_VEC_SMULT_LO 142 UNSPEC_VEC_SMULT_EVEN 143 UNSPEC_VEC_UMULT_EVEN 144 UNSPEC_VEC_SMULT_ODD 145 UNSPEC_VEC_UMULT_ODD 146 147 UNSPEC_VEC_VMAL 148 UNSPEC_VEC_VMAH 149 UNSPEC_VEC_VMALH 150 UNSPEC_VEC_VMAE 151 UNSPEC_VEC_VMALE 152 UNSPEC_VEC_VMAO 153 UNSPEC_VEC_VMALO 154 155 UNSPEC_VEC_GATHER 156 UNSPEC_VEC_EXTRACT 157 UNSPEC_VEC_INSERT_AND_ZERO 158 UNSPEC_VEC_LOAD_BNDRY 159 UNSPEC_VEC_LOAD_LEN 160 UNSPEC_VEC_LOAD_LEN_R 161 UNSPEC_VEC_PACK 162 UNSPEC_VEC_PACK_SATURATE 163 UNSPEC_VEC_PACK_SATURATE_CC 164 UNSPEC_VEC_PACK_SATURATE_GENCC 165 UNSPEC_VEC_PACK_UNSIGNED_SATURATE 166 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC 167 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC 168 UNSPEC_VEC_PERM 169 UNSPEC_VEC_EXTEND 170 UNSPEC_VEC_STORE_LEN 171 UNSPEC_VEC_STORE_LEN_R 172 UNSPEC_VEC_VBPERM 173 UNSPEC_VEC_UNPACKH 174 UNSPEC_VEC_UNPACKH_L 175 UNSPEC_VEC_UNPACKL 176 UNSPEC_VEC_UNPACKL_L 177 UNSPEC_VEC_ADDC 178 UNSPEC_VEC_ADDE_U128 179 UNSPEC_VEC_ADDEC_U128 180 UNSPEC_VEC_AVG 181 UNSPEC_VEC_AVGU 182 UNSPEC_VEC_CHECKSUM 183 UNSPEC_VEC_GFMSUM 184 UNSPEC_VEC_GFMSUM_128 185 UNSPEC_VEC_GFMSUM_ACCUM 186 UNSPEC_VEC_GFMSUM_ACCUM_128 187 UNSPEC_VEC_SET 188 189 UNSPEC_VEC_VSUMG 190 UNSPEC_VEC_VSUMQ 191 UNSPEC_VEC_VSUM 192 UNSPEC_VEC_RL_MASK 193 UNSPEC_VEC_SLL 194 UNSPEC_VEC_SLB 195 UNSPEC_VEC_SLDBYTE 196 UNSPEC_VEC_SLDBIT 197 UNSPEC_VEC_SRDBIT 198 UNSPEC_VEC_SRAL 199 UNSPEC_VEC_SRAB 200 UNSPEC_VEC_SRL 201 UNSPEC_VEC_SRLB 202 203 UNSPEC_VEC_SUBC 204 UNSPEC_VEC_SUBE_U128 205 UNSPEC_VEC_SUBEC_U128 206 207 UNSPEC_VEC_TEST_MASK 208 209 UNSPEC_VEC_VFAE 210 UNSPEC_VEC_VFAECC 211 212 UNSPEC_VEC_VFEE 213 UNSPEC_VEC_VFEECC 214 UNSPEC_VEC_VFENE 215 UNSPEC_VEC_VFENECC 216 217 UNSPEC_VEC_VISTR 218 UNSPEC_VEC_VISTRCC 219 220 UNSPEC_VEC_VSTRC 221 UNSPEC_VEC_VSTRCCC 222 223 UNSPEC_VEC_VSTRS 224 UNSPEC_VEC_VSTRSCC 225 226 UNSPEC_VEC_VCDGB 227 UNSPEC_VEC_VCDLGB 228 229 UNSPEC_VEC_VCGDB 230 UNSPEC_VEC_VCLGDB 231 232 UNSPEC_VEC_VFI 233 234 UNSPEC_VEC_VFLL ; vector fp load lengthened 235 UNSPEC_VEC_VFLR ; vector fp load rounded 236 237 UNSPEC_VEC_VFTCI 238 UNSPEC_VEC_VFTCICC 239 240 UNSPEC_VEC_MSUM 241 242 UNSPEC_VEC_VFMIN 243 UNSPEC_VEC_VFMAX 244 245 UNSPEC_VEC_ELTSWAP 246 247 UNSPEC_TF_TO_FPRX2 248 249 UNSPEC_NNPA_VCLFNHS_V8HI 250 UNSPEC_NNPA_VCLFNLS_V8HI 251 UNSPEC_NNPA_VCRNFS_V8HI 252 253 UNSPEC_NNPA_VCFN_V8HI 254 UNSPEC_NNPA_VCNF_V8HI 255 ]) 256 257 ;; 258 ;; UNSPEC_VOLATILE usage 259 ;; 260 261 (define_c_enum "unspecv" [ 262 ; Blockage 263 UNSPECV_BLOCKAGE 264 265 ; TPF Support 266 UNSPECV_TPF_PROLOGUE 267 UNSPECV_TPF_EPILOGUE 268 269 ; Literal pool 270 UNSPECV_POOL 271 UNSPECV_POOL_SECTION 272 UNSPECV_POOL_ALIGN 273 UNSPECV_POOL_ENTRY 274 UNSPECV_MAIN_POOL 275 276 ; TLS support 277 UNSPECV_SET_TP 278 279 ; Atomic Support 280 UNSPECV_CAS 281 UNSPECV_ATOMIC_OP 282 283 ; Non-branch nops used for compare-and-branch adjustments on z10 284 UNSPECV_NOP_LR_0 285 UNSPECV_NOP_LR_1 286 287 ; Hotpatching (unremovable NOPs) 288 UNSPECV_NOP_2_BYTE 289 UNSPECV_NOP_4_BYTE 290 UNSPECV_NOP_6_BYTE 291 292 ; Transactional Execution support 293 UNSPECV_TBEGIN 294 UNSPECV_TBEGIN_TDB 295 UNSPECV_TBEGINC 296 UNSPECV_TEND 297 UNSPECV_TABORT 298 UNSPECV_ETND 299 UNSPECV_NTSTG 300 UNSPECV_PPA 301 302 ; Set and get floating point control register 303 UNSPECV_SFPC 304 UNSPECV_EFPC 305 306 ; Split stack support 307 UNSPECV_SPLIT_STACK_CALL 308 309 UNSPECV_OSC_BREAK 310 ]) 311 312 ;; 313 ;; Registers 314 ;; 315 316 ; Registers with special meaning 317 318 (define_constants 319 [ 320 ; Sibling call register. 321 (SIBCALL_REGNUM 1) 322 ; A call-clobbered reg which can be used in indirect branch thunks 323 (INDIRECT_BRANCH_THUNK_REGNUM 1) 324 ; Literal pool base register. 325 (BASE_REGNUM 13) 326 ; Return address register. 327 (RETURN_REGNUM 14) 328 ; Stack pointer register. 329 (STACK_REGNUM 15) 330 ; Condition code register. 331 (CC_REGNUM 33) 332 ; Thread local storage pointer register. 333 (TP_REGNUM 36) 334 ]) 335 336 ; Hardware register names 337 338 (define_constants 339 [ 340 ; General purpose registers 341 (GPR0_REGNUM 0) 342 (GPR1_REGNUM 1) 343 (GPR2_REGNUM 2) 344 (GPR6_REGNUM 6) 345 ; Floating point registers. 346 (FPR0_REGNUM 16) 347 (FPR1_REGNUM 20) 348 (FPR2_REGNUM 17) 349 (FPR3_REGNUM 21) 350 (FPR4_REGNUM 18) 351 (FPR5_REGNUM 22) 352 (FPR6_REGNUM 19) 353 (FPR7_REGNUM 23) 354 (FPR8_REGNUM 24) 355 (FPR9_REGNUM 28) 356 (FPR10_REGNUM 25) 357 (FPR11_REGNUM 29) 358 (FPR12_REGNUM 26) 359 (FPR13_REGNUM 30) 360 (FPR14_REGNUM 27) 361 (FPR15_REGNUM 31) 362 (VR0_REGNUM 16) 363 (VR16_REGNUM 38) 364 (VR23_REGNUM 45) 365 (VR24_REGNUM 46) 366 (VR31_REGNUM 53) 367 ]) 368 369 ; Rounding modes for binary floating point numbers 370 (define_constants 371 [(BFP_RND_CURRENT 0) 372 (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) 373 (BFP_RND_PREP_FOR_SHORT_PREC 3) 374 (BFP_RND_NEAREST_TIE_TO_EVEN 4) 375 (BFP_RND_TOWARD_0 5) 376 (BFP_RND_TOWARD_INF 6) 377 (BFP_RND_TOWARD_MINF 7)]) 378 379 ; Rounding modes for decimal floating point numbers 380 ; 1-7 were introduced with the floating point extension facility 381 ; available with z196 382 ; With these rounding modes (1-7) a quantum exception might occur 383 ; which is suppressed for the other modes. 384 (define_constants 385 [(DFP_RND_CURRENT 0) 386 (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) 387 (DFP_RND_CURRENT_QUANTEXC 2) 388 (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) 389 (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) 390 (DFP_RND_TOWARD_0_QUANTEXC 5) 391 (DFP_RND_TOWARD_INF_QUANTEXC 6) 392 (DFP_RND_TOWARD_MINF_QUANTEXC 7) 393 (DFP_RND_NEAREST_TIE_TO_EVEN 8) 394 (DFP_RND_TOWARD_0 9) 395 (DFP_RND_TOWARD_INF 10) 396 (DFP_RND_TOWARD_MINF 11) 397 (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) 398 (DFP_RND_NEAREST_TIE_TO_0 13) 399 (DFP_RND_AWAY_FROM_0 14) 400 (DFP_RND_PREP_FOR_SHORT_PREC 15)]) 401 402 ;; 403 ;; PFPO GPR0 argument format 404 ;; 405 406 (define_constants 407 [ 408 ; PFPO operation type 409 (PFPO_CONVERT 0x1000000) 410 ; PFPO operand types 411 (PFPO_OP_TYPE_SF 0x5) 412 (PFPO_OP_TYPE_DF 0x6) 413 (PFPO_OP_TYPE_TF 0x7) 414 (PFPO_OP_TYPE_FPRX2 0x7) 415 (PFPO_OP_TYPE_SD 0x8) 416 (PFPO_OP_TYPE_DD 0x9) 417 (PFPO_OP_TYPE_TD 0xa) 418 ; Bitposition of operand types 419 (PFPO_OP0_TYPE_SHIFT 16) 420 (PFPO_OP1_TYPE_SHIFT 8) 421 ; Decide whether current DFP or BFD rounding mode should be used 422 ; for the conversion. 423 (PFPO_RND_MODE_DFP 0) 424 (PFPO_RND_MODE_BFP 1) 425 ]) 426 427 ;; PPA constants 428 429 ; Immediate values which can be used as the third operand to the 430 ; perform processor assist instruction 431 432 (define_constants 433 [(PPA_TX_ABORT 1) 434 (PPA_OOO_BARRIER 15)]) 435 436 ; Immediate operands for tbegin and tbeginc 437 (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c 438 (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 439 440 ;; Instruction operand type as used in the Principles of Operation. 441 ;; Used to determine defaults for length and other attribute values. 442 443 (define_attr "op_type" 444 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" 445 (const_string "NN")) 446 447 ;; Instruction type attribute used for scheduling. 448 449 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, 450 cs,vs,store,sem,idiv, 451 imulhi,imulsi,imuldi, 452 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, 453 floadtf,floaddf,floadsf,fstoredf,fstoresf, 454 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, 455 ftoi,fsqrttf,fsqrtdf,fsqrtsf, 456 fmadddf,fmaddsf, 457 ftrunctf,ftruncdf, ftruncsd, ftruncdd, 458 itoftf, itofdf, itofsf, itofdd, itoftd, 459 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, 460 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, 461 ftoidfp, other" 462 (cond [(eq_attr "op_type" "NN") (const_string "other") 463 (eq_attr "op_type" "SS") (const_string "cs")] 464 (const_string "integer"))) 465 466 ;; Another attribute used for scheduling purposes: 467 ;; agen: Instruction uses the address generation unit 468 ;; reg: Instruction does not use the agen unit 469 470 (define_attr "atype" "agen,reg" 471 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") 472 (const_string "reg") 473 (const_string "agen"))) 474 475 ;; Properties concerning Z10 execution grouping and value forwarding. 476 ;; z10_super: instruction is superscalar. 477 ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. 478 ;; z10_fwd: The instruction reads the value of an operand and stores it into a 479 ;; target register. It can forward this value to a second instruction that reads 480 ;; the same register if that second instruction is issued in the same group. 481 ;; z10_rec: The instruction is in the T pipeline and reads a register. If the 482 ;; instruction in the S pipe writes to the register, then the T instruction 483 ;; can immediately read the new value. 484 ;; z10_fr: union of Z10_fwd and z10_rec. 485 ;; z10_c: second operand of instruction is a register and read with complemented bits. 486 ;; 487 ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. 488 489 490 (define_attr "z10prop" "none, 491 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, 492 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, 493 z10_rec, 494 z10_fr, z10_fr_A3, z10_fr_E1, 495 z10_c" 496 (const_string "none")) 497 498 ;; Properties concerning Z196 decoding 499 ;; z196_alone: must group alone 500 ;; z196_end: ends a group 501 ;; z196_cracked: instruction is cracked or expanded 502 (define_attr "z196prop" "none, 503 z196_alone, z196_ends, 504 z196_cracked" 505 (const_string "none")) 506 507 ; mnemonics which only get defined through if_then_else currently 508 ; don't get added to the list values automatically and hence need to 509 ; be listed here. 510 (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown")) 511 512 ;; Length in bytes. 513 514 (define_attr "length" "" 515 (cond [(eq_attr "op_type" "E,RR") (const_int 2) 516 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] 517 (const_int 6))) 518 519 520 ;; Processor type. This attribute must exactly match the processor_type 521 ;; enumeration in s390.h. 522 523 (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,z15,z16" 524 (const (symbol_ref "s390_tune_attr"))) 525 526 (define_attr "cpu_facility" 527 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe,z15,vxe2,z16,nnpa" 528 (const_string "standard")) 529 530 (define_attr "enabled" "" 531 (cond [(eq_attr "cpu_facility" "standard") 532 (const_int 1) 533 534 (and (eq_attr "cpu_facility" "ieee") 535 (match_test "TARGET_CPU_IEEE_FLOAT")) 536 (const_int 1) 537 538 (and (eq_attr "cpu_facility" "zarch") 539 (match_test "TARGET_ZARCH")) 540 (const_int 1) 541 542 (and (eq_attr "cpu_facility" "longdisp") 543 (match_test "TARGET_LONG_DISPLACEMENT")) 544 (const_int 1) 545 546 (and (eq_attr "cpu_facility" "extimm") 547 (match_test "TARGET_EXTIMM")) 548 (const_int 1) 549 550 (and (eq_attr "cpu_facility" "dfp") 551 (match_test "TARGET_DFP")) 552 (const_int 1) 553 554 (eq_attr "cpu_facility" "cpu_zarch") 555 (const_int 1) 556 557 (and (eq_attr "cpu_facility" "z10") 558 (match_test "TARGET_Z10")) 559 (const_int 1) 560 561 (and (eq_attr "cpu_facility" "z196") 562 (match_test "TARGET_Z196")) 563 (const_int 1) 564 565 (and (eq_attr "cpu_facility" "zEC12") 566 (match_test "TARGET_ZEC12")) 567 (const_int 1) 568 569 (and (eq_attr "cpu_facility" "vx") 570 (match_test "TARGET_VX")) 571 (const_int 1) 572 573 (and (eq_attr "cpu_facility" "z13") 574 (match_test "TARGET_Z13")) 575 (const_int 1) 576 577 (and (eq_attr "cpu_facility" "z14") 578 (match_test "TARGET_Z14")) 579 (const_int 1) 580 581 (and (eq_attr "cpu_facility" "vxe") 582 (match_test "TARGET_VXE")) 583 (const_int 1) 584 585 (and (eq_attr "cpu_facility" "z15") 586 (match_test "TARGET_Z15")) 587 (const_int 1) 588 589 (and (eq_attr "cpu_facility" "vxe2") 590 (match_test "TARGET_VXE2")) 591 (const_int 1) 592 593 (and (eq_attr "cpu_facility" "z16") 594 (match_test "TARGET_Z16")) 595 (const_int 1) 596 597 (and (eq_attr "cpu_facility" "nnpa") 598 (match_test "TARGET_NNPA")) 599 (const_int 1) 600 ] 601 (const_int 0))) 602 603 ;; Whether an instruction supports relative long addressing. 604 ;; Currently this corresponds to RIL-b and RIL-c instruction formats, 605 ;; but having a separate attribute, as opposed to reusing op_type, 606 ;; provides additional flexibility. 607 608 (define_attr "relative_long" "no,yes" (const_string "no")) 609 610 ;; Pipeline description for z900. 611 (include "2064.md") 612 613 ;; Pipeline description for z990, z9-109 and z9-ec. 614 (include "2084.md") 615 616 ;; Pipeline description for z10 617 (include "2097.md") 618 619 ;; Pipeline description for z196 620 (include "2817.md") 621 622 ;; Pipeline description for zEC12 623 (include "2827.md") 624 625 ;; Pipeline description for z13 626 (include "2964.md") 627 628 ;; Pipeline description for z14 629 (include "3906.md") 630 631 ;; Pipeline description for z15 632 (include "8561.md") 633 634 ;; Pipeline description for z16 635 (include "3931.md") 636 637 ;; Predicates 638 (include "predicates.md") 639 640 ;; Constraint definitions 641 (include "constraints.md") 642 643 ;; Other includes 644 (include "tpf.md") 645 646 ;; Iterators 647 648 (define_mode_iterator ALL [TI DI SI HI QI TF FPRX2 DF SF TD DD SD V1QI V2QI 649 V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI 650 V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) 651 652 ;; These mode iterators allow floating point patterns to be generated from the 653 ;; same template. 654 (define_mode_iterator FP_ALL [(TF "!TARGET_VXE") (FPRX2 "TARGET_VXE") DF SF 655 (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") 656 (SD "TARGET_HARD_DFP")]) 657 (define_mode_iterator FP [(TF "!TARGET_VXE") (FPRX2 "TARGET_VXE") DF SF 658 (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) 659 ;; Like FP, but without a condition on TF. Useful for expanders that must be 660 ;; the same for FP and VR variants of TF. 661 (define_mode_iterator FP_ANYTF [TF (FPRX2 "TARGET_VXE") DF SF 662 (TD "TARGET_HARD_DFP") 663 (DD "TARGET_HARD_DFP")]) 664 (define_mode_iterator BFP [(TF "!TARGET_VXE") (FPRX2 "TARGET_VXE") DF SF]) 665 (define_mode_iterator DFP [TD DD]) 666 (define_mode_iterator DFP_ALL [TD DD SD]) 667 (define_mode_iterator DSF [DF SF]) 668 (define_mode_iterator SD_SF [SF SD]) 669 (define_mode_iterator DD_DF [DF DD]) 670 (define_mode_iterator TD_TF [(TF "!TARGET_VXE") (FPRX2 "TARGET_VXE") TD]) 671 672 ; 32 bit int<->fp conversion instructions are available since VXE2 (z15). 673 (define_mode_iterator VX_CONV_BFP [DF (SF "TARGET_VXE2")]) 674 (define_mode_iterator VX_CONV_INT [DI (SI "TARGET_VXE2")]) 675 676 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated 677 ;; from the same template. 678 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) 679 (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) 680 (define_mode_iterator DSI [DI SI]) 681 (define_mode_iterator TDI [TI DI]) 682 683 ;; These mode iterators allow :P to be used for patterns that operate on 684 ;; pointer-sized quantities. Exactly one of the two alternatives will match. 685 (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) 686 687 ;; These macros refer to the actual word_mode of the configuration. 688 ;; This is equal to Pmode except on 31-bit machines in zarch mode. 689 (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) 690 (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) 691 692 ;; Used by the umul pattern to express modes having half the size. 693 (define_mode_attr DWH [(TI "DI") (DI "SI")]) 694 (define_mode_attr dwh [(TI "di") (DI "si")]) 695 696 ;; This mode iterator allows the QI and HI patterns to be defined from 697 ;; the same template. 698 (define_mode_iterator HQI [HI QI]) 699 700 ;; This mode iterator allows the integer patterns to be defined from the 701 ;; same template. 702 (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) 703 (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) 704 (define_mode_iterator SINT [SI HI QI]) 705 706 ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from 707 ;; the same template. 708 (define_code_iterator SHIFT [ashift lshiftrt]) 709 710 ;; This iterator allows r[ox]sbg to be defined with the same template 711 (define_code_iterator IXOR [ior xor]) 712 713 ;; This is used for merging the nand/nor and and/or with complement patterns 714 (define_code_iterator ANDOR [and ior]) 715 (define_code_attr bitops_name [(and "and") (ior "or")]) 716 (define_code_attr inv_bitops_name [(and "or") (ior "and")]) 717 (define_code_attr inv_no [(and "o") (ior "n")]) 718 719 ;; This iterator is used to expand the patterns for the nearest 720 ;; integer functions. 721 (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC 722 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL 723 UNSPEC_FPINT_NEARBYINT]) 724 (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") 725 (UNSPEC_FPINT_BTRUNC "btrunc") 726 (UNSPEC_FPINT_ROUND "round") 727 (UNSPEC_FPINT_CEIL "ceil") 728 (UNSPEC_FPINT_NEARBYINT "nearbyint")]) 729 (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") 730 (UNSPEC_FPINT_BTRUNC "5") 731 (UNSPEC_FPINT_ROUND "1") 732 (UNSPEC_FPINT_CEIL "6") 733 (UNSPEC_FPINT_NEARBYINT "0")]) 734 735 ;; This iterator and attribute allow to combine most atomic operations. 736 (define_code_iterator ATOMIC [and ior xor plus minus mult]) 737 (define_code_iterator ATOMIC_Z196 [and ior xor plus]) 738 (define_code_attr atomic [(and "and") (ior "or") (xor "xor") 739 (plus "add") (minus "sub") (mult "nand")]) 740 (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) 741 742 ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in 743 ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. 744 (define_mode_attr xde [(TF "x") (FPRX2 "x") (DF "d") (SF "e") (TD "x") 745 (DD "d") (SD "e") (V4SF "e") (V2DF "d")]) 746 747 ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in 748 ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in 749 ;; SDmode. 750 (define_mode_attr xdee [(TF "x") (FPRX2 "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) 751 752 ;; The decimal floating point variants of add, sub, div and mul support 3 753 ;; fp register operands. The following attributes allow to merge the bfp and 754 ;; dfp variants in a single insn definition. 755 756 ;; These mode attributes are supposed to be used in the `enabled' insn 757 ;; attribute to disable certain alternatives for certain modes. 758 (define_mode_attr nBFP [(TF "0") (FPRX2 "0") (DF "0") (SF "0") (TD "*") 759 (DD "*") (DD "*")]) 760 (define_mode_attr nDFP [(TF "*") (FPRX2 "*") (DF "*") (SF "*") (TD "0") 761 (DD "0") (DD "0")]) 762 (define_mode_attr DSF [(TF "0") (FPRX2 "0") (DF "*") (SF "*") (TD "0") 763 (DD "0") (SD "0")]) 764 (define_mode_attr DFDI [(TF "0") (FPRX2 "0") (DF "*") (SF "0") 765 (TD "0") (DD "0") (DD "0") 766 (TI "0") (DI "*") (SI "0")]) 767 (define_mode_attr SFSI [(TF "0") (FPRX2 "0") (DF "0") (SF "*") 768 (TD "0") (DD "0") (DD "0") 769 (TI "0") (DI "0") (SI "*")]) 770 (define_mode_attr DF [(TF "0") (FPRX2 "0") (DF "*") (SF "0") 771 (TD "0") (DD "0") (DD "0") 772 (TI "0") (DI "0") (SI "0")]) 773 (define_mode_attr SF [(TF "0") (FPRX2 "0") (DF "0") (SF "*") 774 (TD "0") (DD "0") (DD "0") 775 (TI "0") (DI "0") (SI "0")]) 776 777 ;; This attribute is used in the operand constraint list 778 ;; for instructions dealing with the sign bit of 32 or 64bit fp values. 779 ;; TFmode values are represented by a fp register pair. Since the 780 ;; sign bit instructions only handle single source and target fp registers 781 ;; these instructions can only be used for TFmode values if the source and 782 ;; target operand uses the same fp register. 783 (define_mode_attr fT0 [(TF "0") (FPRX2 "0") (DF "f") (SF "f")]) 784 785 ;; This attribute adds b for bfp instructions and t for dfp instructions and is used 786 ;; within instruction mnemonics. 787 (define_mode_attr bt [(TF "b") (FPRX2 "b") (DF "b") (SF "b") (TD "t") (DD "t") 788 (SD "t")]) 789 790 ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp 791 ;; modes and to an empty string for bfp modes. 792 (define_mode_attr _d [(TF "") (FPRX2 "") (DF "") (SF "") (TD "d") (DD "d") 793 (SD "d")]) 794 795 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode 796 ;; and "0" in SImode. This allows to combine instructions of which the 31bit 797 ;; version only operates on one register. 798 (define_mode_attr d0 [(DI "d") (SI "0")]) 799 800 ;; In combination with d0 this allows to combine instructions of which the 31bit 801 ;; version only operates on one register. The DImode version needs an additional 802 ;; register for the assembler output. 803 (define_mode_attr 1 [(DI "%1,") (SI "")]) 804 805 ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in 806 ;; 'ashift' and "srdl" in 'lshiftrt'. 807 (define_code_attr lr [(ashift "l") (lshiftrt "r")]) 808 809 ;; In SHIFT templates, this attribute holds the correct standard name for the 810 ;; pattern itself and the corresponding function calls. 811 (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) 812 813 ;; This attribute handles differences in the instruction 'type' and will result 814 ;; in "RRE" for DImode and "RR" for SImode. 815 (define_mode_attr E [(DI "E") (SI "")]) 816 817 ;; This attribute handles differences in the instruction 'type' and makes RX<Y> 818 ;; to result in "RXY" for DImode and "RX" for SImode. 819 (define_mode_attr Y [(DI "Y") (SI "")]) 820 821 ;; This attribute handles differences in the instruction 'type' and will result 822 ;; in "RSE" for TImode and "RS" for DImode. 823 (define_mode_attr TE [(TI "E") (DI "")]) 824 825 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode 826 ;; and "lcr" in SImode. 827 (define_mode_attr g [(DI "g") (SI "")]) 828 829 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode 830 ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions 831 ;; were enhanced with long displacements whereas 31bit instructions got a ..y 832 ;; variant for long displacements. 833 (define_mode_attr y [(DI "g") (SI "y")]) 834 835 ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode 836 ;; and "cds" in DImode. 837 (define_mode_attr tg [(TI "g") (DI "")]) 838 839 ;; In TDI templates, a string like "c<d>sg". 840 (define_mode_attr td [(TI "d") (DI "")]) 841 842 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode 843 ;; and "cfdbr" in SImode. 844 (define_mode_attr gf [(DI "g") (SI "f")]) 845 846 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI 847 ;; and sllk for SI. This way it is possible to merge the new z196 SI 848 ;; 3 operands shift instructions into the existing patterns. 849 (define_mode_attr gk [(DI "g") (SI "k")]) 850 851 ;; ICM mask required to load MODE value into the lowest subreg 852 ;; of a SImode register. 853 (define_mode_attr icm_lo [(HI "3") (QI "1")]) 854 855 ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in 856 ;; HImode and "llgc" in QImode. 857 (define_mode_attr hc [(HI "h") (QI "c")]) 858 859 ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" 860 ;; in SImode. 861 (define_mode_attr DBL [(DI "TI") (SI "DI")]) 862 863 ;; This attribute expands to DF for TFmode and to DD for TDmode . It is 864 ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. 865 (define_mode_attr HALF_TMODE [(TF "DF") (FPRX2 "DF") (TD "DD")]) 866 867 ;; Maximum unsigned integer that fits in MODE. 868 (define_mode_attr max_uint [(HI "65535") (QI "255")]) 869 870 ;; Start and end field computations for RISBG et al. 871 (define_mode_attr bfstart [(DI "s") (SI "t")]) 872 (define_mode_attr bfend [(DI "e") (SI "f")]) 873 874 ;; In place of GET_MODE_BITSIZE (<MODE>mode) 875 (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) 876 ;; 64 - bitsize 877 (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) 878 (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) 879 880 ;; In place of GET_MODE_SIZE (<MODE>mode) 881 (define_mode_attr modesize [(DI "8") (SI "4")]) 882 883 ;; Allow return and simple_return to be defined from a single template. 884 (define_code_iterator ANY_RETURN [return simple_return]) 885 886 ;; Facilitate dispatching TFmode expanders on z14+. 887 (define_mode_attr tf_fpr [(TF "_fpr") (FPRX2 "") (DF "") (SF "") (TD "") 888 (DD "") (SD "")]) 889 890 ;; Mode names as seen in type mode_attr values. 891 (define_mode_attr type [(TF "tf") (FPRX2 "tf") (DF "df") (SF "sf") (TD "td") 892 (DD "dd") (SD "sd")]) 893 894 895 ; Condition code modes generated by vector fp comparisons. These will 896 ; be used also in single element mode. 897 (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) 898 ; Used with VFCMP to expand part of the mnemonic 899 ; For fp we have a mismatch: eq in the insn name - e in asm 900 (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) 901 (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) 902 903 ;; Subst pattern definitions 904 (include "subst.md") 905 906 (include "vector.md") 907 908 ;; 909 ;;- Compare instructions. 910 ;; 911 912 ; Test-under-Mask instructions 913 914 (define_insn "*tmqi_mem" 915 [(set (reg CC_REGNUM) 916 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") 917 (match_operand:QI 1 "immediate_operand" "n,n")) 918 (match_operand:QI 2 "immediate_operand" "n,n")))] 919 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" 920 "@ 921 tm\t%S0,%b1 922 tmy\t%S0,%b1" 923 [(set_attr "op_type" "SI,SIY") 924 (set_attr "cpu_facility" "*,longdisp") 925 (set_attr "z10prop" "z10_super,z10_super")]) 926 927 (define_insn "*tmdi_reg" 928 [(set (reg CC_REGNUM) 929 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") 930 (match_operand:DI 1 "immediate_operand" 931 "N0HD0,N1HD0,N2HD0,N3HD0")) 932 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] 933 "TARGET_ZARCH 934 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) 935 && s390_single_part (operands[1], DImode, HImode, 0) >= 0" 936 "@ 937 tmhh\t%0,%i1 938 tmhl\t%0,%i1 939 tmlh\t%0,%i1 940 tmll\t%0,%i1" 941 [(set_attr "op_type" "RI") 942 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) 943 944 (define_insn "*tmsi_reg" 945 [(set (reg CC_REGNUM) 946 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") 947 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) 948 (match_operand:SI 2 "immediate_operand" "n,n")))] 949 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) 950 && s390_single_part (operands[1], SImode, HImode, 0) >= 0" 951 "@ 952 tmh\t%0,%i1 953 tml\t%0,%i1" 954 [(set_attr "op_type" "RI") 955 (set_attr "z10prop" "z10_super,z10_super")]) 956 957 (define_insn "*tm<mode>_full" 958 [(set (reg CC_REGNUM) 959 (compare (match_operand:HQI 0 "register_operand" "d") 960 (match_operand:HQI 1 "immediate_operand" "n")))] 961 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" 962 "tml\t%0,<max_uint>" 963 [(set_attr "op_type" "RI") 964 (set_attr "z10prop" "z10_super")]) 965 966 967 ; 968 ; Load-and-Test instructions 969 ; 970 971 ; tst(di|si) instruction pattern(s). 972 973 (define_insn "*tstdi_sign" 974 [(set (reg CC_REGNUM) 975 (compare 976 (ashiftrt:DI 977 (ashift:DI 978 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) 979 (const_int 32)) (const_int 32)) 980 (match_operand:DI 1 "const0_operand" ""))) 981 (set (match_operand:DI 2 "register_operand" "=d,d") 982 (sign_extend:DI (match_dup 0)))] 983 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" 984 "ltgfr\t%2,%0 985 ltgf\t%2,%0" 986 [(set_attr "op_type" "RRE,RXY") 987 (set_attr "cpu_facility" "*,z10") 988 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) 989 990 ; ltr, lt, ltgr, ltg 991 (define_insn "*tst<mode>_extimm" 992 [(set (reg CC_REGNUM) 993 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") 994 (match_operand:GPR 1 "const0_operand" ""))) 995 (set (match_operand:GPR 2 "register_operand" "=d,d") 996 (match_dup 0))] 997 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" 998 "@ 999 lt<g>r\t%2,%0 1000 lt<g>\t%2,%0" 1001 [(set_attr "op_type" "RR<E>,RXY") 1002 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) 1003 1004 ; Peephole to combine a load-and-test from volatile memory which combine does 1005 ; not do. 1006 (define_peephole2 1007 [(set (match_operand:GPR 0 "register_operand") 1008 (match_operand:GPR 2 "memory_operand")) 1009 (set (reg CC_REGNUM) 1010 (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] 1011 "s390_match_ccmode (peep2_next_insn (1), CCSmode) && TARGET_EXTIMM 1012 && GENERAL_REG_P (operands[0]) 1013 && satisfies_constraint_T (operands[2]) 1014 && !contains_constant_pool_address_p (operands[2])" 1015 [(parallel 1016 [(set (reg:CCS CC_REGNUM) 1017 (compare:CCS (match_dup 2) (match_dup 1))) 1018 (set (match_dup 0) (match_dup 2))])]) 1019 1020 ; ltr, lt, ltgr, ltg 1021 (define_insn "*tst<mode>_cconly_extimm" 1022 [(set (reg CC_REGNUM) 1023 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") 1024 (match_operand:GPR 1 "const0_operand" ""))) 1025 (clobber (match_scratch:GPR 2 "=X,d"))] 1026 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" 1027 "@ 1028 lt<g>r\t%0,%0 1029 lt<g>\t%2,%0" 1030 [(set_attr "op_type" "RR<E>,RXY") 1031 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) 1032 1033 (define_insn "*tstdi" 1034 [(set (reg CC_REGNUM) 1035 (compare (match_operand:DI 0 "register_operand" "d") 1036 (match_operand:DI 1 "const0_operand" ""))) 1037 (set (match_operand:DI 2 "register_operand" "=d") 1038 (match_dup 0))] 1039 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" 1040 "ltgr\t%2,%0" 1041 [(set_attr "op_type" "RRE") 1042 (set_attr "z10prop" "z10_fr_E1")]) 1043 1044 (define_insn "*tstsi" 1045 [(set (reg CC_REGNUM) 1046 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 1047 (match_operand:SI 1 "const0_operand" ""))) 1048 (set (match_operand:SI 2 "register_operand" "=d,d,d") 1049 (match_dup 0))] 1050 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" 1051 "@ 1052 ltr\t%2,%0 1053 icm\t%2,15,%S0 1054 icmy\t%2,15,%S0" 1055 [(set_attr "op_type" "RR,RS,RSY") 1056 (set_attr "cpu_facility" "*,*,longdisp") 1057 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) 1058 1059 (define_insn "*tstsi_cconly" 1060 [(set (reg CC_REGNUM) 1061 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 1062 (match_operand:SI 1 "const0_operand" ""))) 1063 (clobber (match_scratch:SI 2 "=X,d,d"))] 1064 "s390_match_ccmode(insn, CCSmode)" 1065 "@ 1066 ltr\t%0,%0 1067 icm\t%2,15,%S0 1068 icmy\t%2,15,%S0" 1069 [(set_attr "op_type" "RR,RS,RSY") 1070 (set_attr "cpu_facility" "*,*,longdisp") 1071 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) 1072 1073 (define_insn "*tstdi_cconly_31" 1074 [(set (reg CC_REGNUM) 1075 (compare (match_operand:DI 0 "register_operand" "d") 1076 (match_operand:DI 1 "const0_operand" "")))] 1077 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" 1078 "srda\t%0,0" 1079 [(set_attr "op_type" "RS") 1080 (set_attr "atype" "reg")]) 1081 1082 ; ltr, ltgr 1083 (define_insn "*tst<mode>_cconly2" 1084 [(set (reg CC_REGNUM) 1085 (compare (match_operand:GPR 0 "register_operand" "d") 1086 (match_operand:GPR 1 "const0_operand" "")))] 1087 "s390_match_ccmode(insn, CCSmode)" 1088 "lt<g>r\t%0,%0" 1089 [(set_attr "op_type" "RR<E>") 1090 (set_attr "z10prop" "z10_fr_E1")]) 1091 1092 ; tst(hi|qi) instruction pattern(s). 1093 1094 (define_insn "*tst<mode>CCT" 1095 [(set (reg CC_REGNUM) 1096 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") 1097 (match_operand:HQI 1 "const0_operand" ""))) 1098 (set (match_operand:HQI 2 "register_operand" "=d,d,0") 1099 (match_dup 0))] 1100 "s390_match_ccmode(insn, CCTmode)" 1101 "@ 1102 icm\t%2,<icm_lo>,%S0 1103 icmy\t%2,<icm_lo>,%S0 1104 tml\t%0,<max_uint>" 1105 [(set_attr "op_type" "RS,RSY,RI") 1106 (set_attr "cpu_facility" "*,longdisp,*") 1107 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) 1108 1109 (define_insn "*tsthiCCT_cconly" 1110 [(set (reg CC_REGNUM) 1111 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") 1112 (match_operand:HI 1 "const0_operand" ""))) 1113 (clobber (match_scratch:HI 2 "=d,d,X"))] 1114 "s390_match_ccmode(insn, CCTmode)" 1115 "@ 1116 icm\t%2,3,%S0 1117 icmy\t%2,3,%S0 1118 tml\t%0,65535" 1119 [(set_attr "op_type" "RS,RSY,RI") 1120 (set_attr "cpu_facility" "*,longdisp,*") 1121 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) 1122 1123 (define_insn "*tstqiCCT_cconly" 1124 [(set (reg CC_REGNUM) 1125 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") 1126 (match_operand:QI 1 "const0_operand" "")))] 1127 "s390_match_ccmode(insn, CCTmode)" 1128 "@ 1129 cli\t%S0,0 1130 cliy\t%S0,0 1131 tml\t%0,255" 1132 [(set_attr "op_type" "SI,SIY,RI") 1133 (set_attr "cpu_facility" "*,longdisp,*") 1134 (set_attr "z10prop" "z10_super,z10_super,z10_super")]) 1135 1136 (define_insn "*tst<mode>" 1137 [(set (reg CC_REGNUM) 1138 (compare (match_operand:HQI 0 "s_operand" "Q,S") 1139 (match_operand:HQI 1 "const0_operand" ""))) 1140 (set (match_operand:HQI 2 "register_operand" "=d,d") 1141 (match_dup 0))] 1142 "s390_match_ccmode(insn, CCSmode)" 1143 "@ 1144 icm\t%2,<icm_lo>,%S0 1145 icmy\t%2,<icm_lo>,%S0" 1146 [(set_attr "op_type" "RS,RSY") 1147 (set_attr "cpu_facility" "*,longdisp") 1148 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 1149 1150 (define_insn "*tst<mode>_cconly" 1151 [(set (reg CC_REGNUM) 1152 (compare (match_operand:HQI 0 "s_operand" "Q,S") 1153 (match_operand:HQI 1 "const0_operand" ""))) 1154 (clobber (match_scratch:HQI 2 "=d,d"))] 1155 "s390_match_ccmode(insn, CCSmode)" 1156 "@ 1157 icm\t%2,<icm_lo>,%S0 1158 icmy\t%2,<icm_lo>,%S0" 1159 [(set_attr "op_type" "RS,RSY") 1160 (set_attr "cpu_facility" "*,longdisp") 1161 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 1162 1163 1164 ; Compare (equality) instructions 1165 1166 (define_insn "*cmpdi_cct" 1167 [(set (reg CC_REGNUM) 1168 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") 1169 (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] 1170 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" 1171 "@ 1172 cgr\t%0,%1 1173 cghi\t%0,%h1 1174 cgfi\t%0,%1 1175 cg\t%0,%1 1176 #" 1177 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") 1178 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) 1179 1180 (define_insn "*cmpsi_cct" 1181 [(set (reg CC_REGNUM) 1182 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") 1183 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] 1184 "s390_match_ccmode (insn, CCTmode)" 1185 "@ 1186 cr\t%0,%1 1187 chi\t%0,%h1 1188 cfi\t%0,%1 1189 c\t%0,%1 1190 cy\t%0,%1 1191 #" 1192 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") 1193 (set_attr "cpu_facility" "*,*,*,*,longdisp,*") 1194 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) 1195 1196 ; Compare (signed) instructions 1197 1198 (define_insn "*cmpdi_ccs_sign" 1199 [(set (reg CC_REGNUM) 1200 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" 1201 "d,T,b")) 1202 (match_operand:DI 0 "register_operand" "d, d,d")))] 1203 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" 1204 "@ 1205 cgfr\t%0,%1 1206 cgf\t%0,%1 1207 cgfrl\t%0,%1" 1208 [(set_attr "op_type" "RRE,RXY,RIL") 1209 (set_attr "z10prop" "z10_c,*,*") 1210 (set_attr "type" "*,*,larl") 1211 (set_attr "relative_long" "*,*,yes")]) 1212 1213 1214 1215 (define_insn "*cmpsi_ccs_sign" 1216 [(set (reg CC_REGNUM) 1217 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) 1218 (match_operand:SI 0 "register_operand" "d,d,d")))] 1219 "s390_match_ccmode(insn, CCSRmode)" 1220 "@ 1221 ch\t%0,%1 1222 chy\t%0,%1 1223 chrl\t%0,%1" 1224 [(set_attr "op_type" "RX,RXY,RIL") 1225 (set_attr "cpu_facility" "*,longdisp,z10") 1226 (set_attr "type" "*,*,larl") 1227 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked") 1228 (set_attr "relative_long" "*,*,yes")]) 1229 1230 (define_insn "*cmphi_ccs_z10" 1231 [(set (reg CC_REGNUM) 1232 (compare (match_operand:HI 0 "s_operand" "Q") 1233 (match_operand:HI 1 "immediate_operand" "K")))] 1234 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" 1235 "chhsi\t%0,%1" 1236 [(set_attr "op_type" "SIL") 1237 (set_attr "z196prop" "z196_cracked")]) 1238 1239 (define_insn "*cmpdi_ccs_signhi_rl" 1240 [(set (reg CC_REGNUM) 1241 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) 1242 (match_operand:GPR 0 "register_operand" "d,d")))] 1243 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" 1244 "@ 1245 cgh\t%0,%1 1246 cghrl\t%0,%1" 1247 [(set_attr "op_type" "RXY,RIL") 1248 (set_attr "type" "*,larl") 1249 (set_attr "relative_long" "*,yes")]) 1250 1251 ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl 1252 (define_insn "*cmp<mode>_ccs" 1253 [(set (reg CC_REGNUM) 1254 (compare (match_operand:GPR 0 "nonimmediate_operand" 1255 "d,d,Q, d,d,d,d") 1256 (match_operand:GPR 1 "general_operand" 1257 "d,K,K,Os,R,T,b")))] 1258 "s390_match_ccmode(insn, CCSmode)" 1259 "@ 1260 c<g>r\t%0,%1 1261 c<g>hi\t%0,%h1 1262 c<g>hsi\t%0,%h1 1263 c<g>fi\t%0,%1 1264 c<g>\t%0,%1 1265 c<y>\t%0,%1 1266 c<g>rl\t%0,%1" 1267 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") 1268 (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") 1269 (set_attr "type" "*,*,*,*,*,*,larl") 1270 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super") 1271 (set_attr "relative_long" "*,*,*,*,*,*,yes")]) 1272 1273 1274 ; Compare (unsigned) instructions 1275 1276 (define_insn "*cmpsi_ccu_zerohi_rlsi" 1277 [(set (reg CC_REGNUM) 1278 (compare (zero_extend:SI (mem:HI (match_operand:SI 1 1279 "larl_operand" "X"))) 1280 (match_operand:SI 0 "register_operand" "d")))] 1281 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" 1282 "clhrl\t%0,%1" 1283 [(set_attr "op_type" "RIL") 1284 (set_attr "type" "larl") 1285 (set_attr "z10prop" "z10_super") 1286 (set_attr "relative_long" "yes")]) 1287 1288 ; clhrl, clghrl 1289 (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" 1290 [(set (reg CC_REGNUM) 1291 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 1292 "larl_operand" "X"))) 1293 (match_operand:GPR 0 "register_operand" "d")))] 1294 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" 1295 "cl<g>hrl\t%0,%1" 1296 [(set_attr "op_type" "RIL") 1297 (set_attr "type" "larl") 1298 (set_attr "z10prop" "z10_super") 1299 (set_attr "relative_long" "yes")]) 1300 1301 (define_insn "*cmpdi_ccu_zero" 1302 [(set (reg CC_REGNUM) 1303 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" 1304 "d,T,b")) 1305 (match_operand:DI 0 "register_operand" "d,d,d")))] 1306 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" 1307 "@ 1308 clgfr\t%0,%1 1309 clgf\t%0,%1 1310 clgfrl\t%0,%1" 1311 [(set_attr "op_type" "RRE,RXY,RIL") 1312 (set_attr "cpu_facility" "*,*,z10") 1313 (set_attr "type" "*,*,larl") 1314 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super") 1315 (set_attr "relative_long" "*,*,yes")]) 1316 1317 (define_insn "*cmpdi_ccu" 1318 [(set (reg CC_REGNUM) 1319 (compare (match_operand:DI 0 "nonimmediate_operand" 1320 "d, d,d,Q,d, Q,BQ") 1321 (match_operand:DI 1 "general_operand" 1322 "d,Op,b,D,T,BQ,Q")))] 1323 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" 1324 "@ 1325 clgr\t%0,%1 1326 clgfi\t%0,%1 1327 clgrl\t%0,%1 1328 clghsi\t%0,%x1 1329 clg\t%0,%1 1330 # 1331 #" 1332 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") 1333 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") 1334 (set_attr "type" "*,*,larl,*,*,*,*") 1335 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*") 1336 (set_attr "relative_long" "*,*,yes,*,*,*,*")]) 1337 1338 (define_insn "*cmpsi_ccu" 1339 [(set (reg CC_REGNUM) 1340 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") 1341 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] 1342 "s390_match_ccmode (insn, CCUmode)" 1343 "@ 1344 clr\t%0,%1 1345 clfi\t%0,%o1 1346 clrl\t%0,%1 1347 clfhsi\t%0,%x1 1348 cl\t%0,%1 1349 cly\t%0,%1 1350 # 1351 #" 1352 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") 1353 (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") 1354 (set_attr "type" "*,*,larl,*,*,*,*,*") 1355 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*") 1356 (set_attr "relative_long" "*,*,yes,*,*,*,*,*")]) 1357 1358 (define_insn "*cmphi_ccu" 1359 [(set (reg CC_REGNUM) 1360 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") 1361 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] 1362 "s390_match_ccmode (insn, CCUmode) 1363 && !register_operand (operands[1], HImode)" 1364 "@ 1365 clm\t%0,3,%S1 1366 clmy\t%0,3,%S1 1367 clhhsi\t%0,%1 1368 # 1369 #" 1370 [(set_attr "op_type" "RS,RSY,SIL,SS,SS") 1371 (set_attr "cpu_facility" "*,longdisp,z10,*,*") 1372 (set_attr "z10prop" "*,*,z10_super,*,*")]) 1373 1374 (define_insn "*cmpqi_ccu" 1375 [(set (reg CC_REGNUM) 1376 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") 1377 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] 1378 "s390_match_ccmode (insn, CCUmode) 1379 && !register_operand (operands[1], QImode)" 1380 "@ 1381 clm\t%0,1,%S1 1382 clmy\t%0,1,%S1 1383 cli\t%S0,%b1 1384 cliy\t%S0,%b1 1385 # 1386 #" 1387 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") 1388 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") 1389 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) 1390 1391 1392 ; Block compare (CLC) instruction patterns. 1393 1394 (define_insn "*clc" 1395 [(set (reg CC_REGNUM) 1396 (compare (match_operand:BLK 0 "memory_operand" "Q") 1397 (match_operand:BLK 1 "memory_operand" "Q"))) 1398 (use (match_operand 2 "const_int_operand" "n"))] 1399 "s390_match_ccmode (insn, CCUmode) 1400 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 1401 "clc\t%O0(%2,%R0),%S1" 1402 [(set_attr "op_type" "SS")]) 1403 1404 (define_split 1405 [(set (reg CC_REGNUM) 1406 (compare (match_operand 0 "memory_operand" "") 1407 (match_operand 1 "memory_operand" "")))] 1408 "reload_completed 1409 && s390_match_ccmode (insn, CCUmode) 1410 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 1411 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 1412 [(parallel 1413 [(set (match_dup 0) (match_dup 1)) 1414 (use (match_dup 2))])] 1415 { 1416 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 1417 operands[0] = adjust_address (operands[0], BLKmode, 0); 1418 operands[1] = adjust_address (operands[1], BLKmode, 0); 1419 1420 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), 1421 operands[0], operands[1]); 1422 operands[0] = SET_DEST (PATTERN (curr_insn)); 1423 }) 1424 1425 1426 ; (TF|DF|SF|TD|DD|SD) instructions 1427 1428 1429 ; load and test instructions turn a signaling NaN into a quiet NaN. Thus they 1430 ; may only be used if the target register is dead afterwards or if fast math 1431 ; is enabled. The former is done via a peephole optimization. Note, load and 1432 ; test instructions may only be used for (in)equality comparisons because 1433 ; relational comparisons must treat a quiet NaN like a signaling NaN which is 1434 ; not the case for load and test instructions. For fast math insn 1435 ; "cmp<mode>_ccs_0_fastmath" applies. 1436 ; See testcases load-and-test-fp-{1,2}.c 1437 1438 (define_peephole2 1439 [(set (match_operand:FP 0 "register_operand") 1440 (match_operand:FP 1 "const0_operand")) 1441 (set (reg:CCZ CC_REGNUM) 1442 (compare:CCZ (match_operand:FP 2 "register_operand") 1443 (match_operand:FP 3 "register_operand")))] 1444 "TARGET_HARD_FLOAT 1445 && FP_REG_P (operands[2]) 1446 && REGNO (operands[0]) == REGNO (operands[3]) 1447 && peep2_reg_dead_p (2, operands[0]) 1448 && peep2_reg_dead_p (2, operands[2])" 1449 [(parallel 1450 [(set (reg:CCZ CC_REGNUM) 1451 (compare:CCZ (match_dup 2) (match_dup 1))) 1452 (clobber (match_dup 2))])] 1453 "") 1454 1455 ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr 1456 (define_insn "*cmp<mode>_ccz_0" 1457 [(set (reg:CCZ CC_REGNUM) 1458 (compare:CCZ (match_operand:FP 0 "register_operand" "f") 1459 (match_operand:FP 1 "const0_operand"))) 1460 (clobber (match_operand:FP 2 "register_operand" "=0"))] 1461 "TARGET_HARD_FLOAT" 1462 "lt<xde><bt>r\t%0,%0" 1463 [(set_attr "op_type" "RRE") 1464 (set_attr "type" "fsimp<type>")]) 1465 1466 (define_insn "*cmp<mode>_ccs_0_fastmath" 1467 [(set (reg CC_REGNUM) 1468 (compare (match_operand:FP 0 "register_operand" "f") 1469 (match_operand:FP 1 "const0_operand")))] 1470 "s390_match_ccmode (insn, CCSmode) 1471 && TARGET_HARD_FLOAT 1472 && !flag_trapping_math 1473 && !flag_signaling_nans" 1474 "lt<xde><bt>r\t%0,%0" 1475 [(set_attr "op_type" "RRE") 1476 (set_attr "type" "fsimp<type>")]) 1477 1478 ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb 1479 ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb 1480 (define_insn "*cmp<mode>_ccs" 1481 [(set (reg CC_REGNUM) 1482 (compare (match_operand:FP 0 "register_operand" "f,f,v,v") 1483 (match_operand:FP 1 "general_operand" "f,R,v,v")))] 1484 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" 1485 "@ 1486 c<xde><bt>r\t%0,%1 1487 c<xde>b\t%0,%1 1488 wfcdb\t%0,%1 1489 wfcsb\t%0,%1" 1490 [(set_attr "op_type" "RRE,RXE,VRR,VRR") 1491 (set_attr "cpu_facility" "*,*,vx,vxe") 1492 (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) 1493 1494 ; VX: TFmode in VR: use wfcxb 1495 (define_insn "*cmptf_ccs" 1496 [(set (reg CC_REGNUM) 1497 (compare (match_operand:TF 0 "register_operand" "v") 1498 (match_operand:TF 1 "register_operand" "v")))] 1499 "s390_match_ccmode(insn, CCSmode) && TARGET_VXE" 1500 "wfcxb\t%0,%1" 1501 [(set_attr "op_type" "VRR") 1502 (set_attr "cpu_facility" "vxe")]) 1503 1504 ; VX: TFmode in FPR pairs: use kxbr instead of wfkxb 1505 ; kxtr, kdtr, kxbr, kdbr, kebr, kdb, keb, wfksb, wfkdb 1506 (define_insn "*cmp<mode>_ccsfps" 1507 [(set (reg CC_REGNUM) 1508 (compare (match_operand:FP 0 "register_operand" "f,f,v,v") 1509 (match_operand:FP 1 "general_operand" "f,R,v,v")))] 1510 "s390_match_ccmode (insn, CCSFPSmode) && TARGET_HARD_FLOAT" 1511 "@ 1512 k<xde><bt>r\t%0,%1 1513 k<xde>b\t%0,%1 1514 wfkdb\t%0,%1 1515 wfksb\t%0,%1" 1516 [(set_attr "op_type" "RRE,RXE,VRR,VRR") 1517 (set_attr "cpu_facility" "*,*,vx,vxe") 1518 (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) 1519 1520 ; VX: TFmode in VR: use wfkxb 1521 (define_insn "*cmptf_ccsfps" 1522 [(set (reg CC_REGNUM) 1523 (compare (match_operand:TF 0 "register_operand" "v") 1524 (match_operand:TF 1 "register_operand" "v")))] 1525 "s390_match_ccmode (insn, CCSFPSmode) && TARGET_VXE" 1526 "wfkxb\t%0,%1" 1527 [(set_attr "op_type" "VRR") 1528 (set_attr "cpu_facility" "vxe")]) 1529 1530 ; Compare and Branch instructions 1531 1532 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr 1533 ; The following instructions do a complementary access of their second 1534 ; operand (z01 only): crj_c, cgrjc, cr, cgr 1535 (define_insn "*cmp_and_br_signed_<mode>" 1536 [(set (pc) 1537 (if_then_else (match_operator 0 "s390_signed_integer_comparison" 1538 [(match_operand:GPR 1 "register_operand" "d,d") 1539 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) 1540 (label_ref (match_operand 3 "" "")) 1541 (pc))) 1542 (clobber (reg:CC CC_REGNUM))] 1543 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1544 { 1545 if (get_attr_length (insn) == 6) 1546 return which_alternative ? 1547 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; 1548 else 1549 return which_alternative ? 1550 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; 1551 } 1552 [(set_attr "op_type" "RIE") 1553 (set_attr "type" "branch") 1554 (set_attr "z10prop" "z10_super_c,z10_super") 1555 (set (attr "length") 1556 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1557 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg 1558 ; 10 byte for cgr/jg 1559 1560 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr 1561 ; The following instructions do a complementary access of their second 1562 ; operand (z10 only): clrj, clgrj, clr, clgr 1563 (define_insn "*cmp_and_br_unsigned_<mode>" 1564 [(set (pc) 1565 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" 1566 [(match_operand:GPR 1 "register_operand" "d,d") 1567 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) 1568 (label_ref (match_operand 3 "" "")) 1569 (pc))) 1570 (clobber (reg:CC CC_REGNUM))] 1571 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1572 { 1573 if (get_attr_length (insn) == 6) 1574 return which_alternative ? 1575 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; 1576 else 1577 return which_alternative ? 1578 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; 1579 } 1580 [(set_attr "op_type" "RIE") 1581 (set_attr "type" "branch") 1582 (set_attr "z10prop" "z10_super_c,z10_super") 1583 (set (attr "length") 1584 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1585 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg 1586 ; 10 byte for clgr/jg 1587 1588 ; And now the same two patterns as above but with a negated CC mask. 1589 1590 ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr 1591 ; The following instructions do a complementary access of their second 1592 ; operand (z01 only): crj_c, cgrjc, cr, cgr 1593 (define_insn "*icmp_and_br_signed_<mode>" 1594 [(set (pc) 1595 (if_then_else (match_operator 0 "s390_signed_integer_comparison" 1596 [(match_operand:GPR 1 "register_operand" "d,d") 1597 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) 1598 (pc) 1599 (label_ref (match_operand 3 "" "")))) 1600 (clobber (reg:CC CC_REGNUM))] 1601 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1602 { 1603 if (get_attr_length (insn) == 6) 1604 return which_alternative ? 1605 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; 1606 else 1607 return which_alternative ? 1608 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; 1609 } 1610 [(set_attr "op_type" "RIE") 1611 (set_attr "type" "branch") 1612 (set_attr "z10prop" "z10_super_c,z10_super") 1613 (set (attr "length") 1614 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1615 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg 1616 ; 10 byte for cgr/jg 1617 1618 ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr 1619 ; The following instructions do a complementary access of their second 1620 ; operand (z10 only): clrj, clgrj, clr, clgr 1621 (define_insn "*icmp_and_br_unsigned_<mode>" 1622 [(set (pc) 1623 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" 1624 [(match_operand:GPR 1 "register_operand" "d,d") 1625 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) 1626 (pc) 1627 (label_ref (match_operand 3 "" "")))) 1628 (clobber (reg:CC CC_REGNUM))] 1629 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1630 { 1631 if (get_attr_length (insn) == 6) 1632 return which_alternative ? 1633 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; 1634 else 1635 return which_alternative ? 1636 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; 1637 } 1638 [(set_attr "op_type" "RIE") 1639 (set_attr "type" "branch") 1640 (set_attr "z10prop" "z10_super_c,z10_super") 1641 (set (attr "length") 1642 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1643 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg 1644 ; 10 byte for clgr/jg 1645 1646 ;; 1647 ;;- Move instructions. 1648 ;; 1649 1650 ; 1651 ; movti instruction pattern(s). 1652 ; 1653 1654 1655 ; Separate out the register pair alternative since constraints (P) are 1656 ; not able to deal with const_wide_int's. But predicates do. 1657 (define_insn "*movti_bigconst" 1658 [(set (match_operand:TI 0 "register_operand" "=d") 1659 (match_operand:TI 1 "reload_const_wide_int_operand" ""))] 1660 "TARGET_ZARCH" 1661 "#") 1662 1663 ; FIXME: More constants are possible by enabling jxx, jyy constraints 1664 ; for TImode (use double-int for the calculations) 1665 (define_insn "movti" 1666 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o") 1667 (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))] 1668 "TARGET_ZARCH" 1669 "@ 1670 lmg\t%0,%N0,%S1 1671 stmg\t%1,%N1,%S0 1672 vlr\t%v0,%v1 1673 vzero\t%v0 1674 vone\t%v0 1675 vlvgp\t%v0,%1,%N1 1676 # 1677 vl\t%v0,%1%A1 1678 vst\t%v1,%0%A0 1679 # 1680 # 1681 # 1682 # 1683 # 1684 #" 1685 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*") 1686 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*") 1687 (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")]) 1688 1689 (define_split 1690 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1691 (match_operand:TI 1 "general_operand" ""))] 1692 "TARGET_ZARCH && reload_completed 1693 && !s_operand (operands[0], TImode) 1694 && !s_operand (operands[1], TImode) 1695 && s390_split_ok_p (operands[0], operands[1], TImode, 0)" 1696 [(set (match_dup 2) (match_dup 4)) 1697 (set (match_dup 3) (match_dup 5))] 1698 { 1699 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1700 operands[3] = operand_subword (operands[0], 1, 0, TImode); 1701 operands[4] = operand_subword (operands[1], 0, 0, TImode); 1702 operands[5] = operand_subword (operands[1], 1, 0, TImode); 1703 }) 1704 1705 (define_split 1706 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1707 (match_operand:TI 1 "general_operand" ""))] 1708 "TARGET_ZARCH && reload_completed 1709 && !s_operand (operands[0], TImode) 1710 && !s_operand (operands[1], TImode) 1711 && s390_split_ok_p (operands[0], operands[1], TImode, 1)" 1712 [(set (match_dup 2) (match_dup 4)) 1713 (set (match_dup 3) (match_dup 5))] 1714 { 1715 operands[2] = operand_subword (operands[0], 1, 0, TImode); 1716 operands[3] = operand_subword (operands[0], 0, 0, TImode); 1717 operands[4] = operand_subword (operands[1], 1, 0, TImode); 1718 operands[5] = operand_subword (operands[1], 0, 0, TImode); 1719 }) 1720 1721 ; Use part of the TImode target reg to perform the address 1722 ; calculation. If the TImode value is supposed to be copied into a VR 1723 ; this splitter is not necessary. 1724 (define_split 1725 [(set (match_operand:TI 0 "register_operand" "") 1726 (match_operand:TI 1 "memory_operand" ""))] 1727 "TARGET_ZARCH && reload_completed 1728 && !VECTOR_REG_P (operands[0]) 1729 && !s_operand (operands[1], VOIDmode)" 1730 [(set (match_dup 0) (match_dup 1))] 1731 { 1732 rtx addr = operand_subword (operands[0], 1, 0, TImode); 1733 addr = gen_lowpart (Pmode, addr); 1734 s390_load_address (addr, XEXP (operands[1], 0)); 1735 operands[1] = replace_equiv_address (operands[1], addr); 1736 }) 1737 1738 1739 ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. 1740 ; For the higher order bits we do simply a DImode move while the 1741 ; second part is done via vec extract. Both will end up as vlgvg. 1742 (define_split 1743 [(set (match_operand:TI 0 "register_operand" "") 1744 (match_operand:TI 1 "register_operand" ""))] 1745 "TARGET_VX && reload_completed 1746 && GENERAL_REG_P (operands[0]) 1747 && VECTOR_REG_P (operands[1])" 1748 [(set (match_dup 2) (match_dup 4)) 1749 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] 1750 UNSPEC_VEC_EXTRACT))] 1751 { 1752 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1753 operands[3] = operand_subword (operands[0], 1, 0, TImode); 1754 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); 1755 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); 1756 }) 1757 1758 ; 1759 ; Patterns used for secondary reloads 1760 ; 1761 1762 ; z10 provides move instructions accepting larl memory operands. 1763 ; Unfortunately there is no such variant for QI, TI and FP mode moves. 1764 ; These patterns are also used for unaligned SI and DI accesses. 1765 1766 (define_expand "reload<ALL:mode><P:mode>_tomem_z10" 1767 [(parallel [(match_operand:ALL 0 "memory_operand" "") 1768 (match_operand:ALL 1 "register_operand" "=d") 1769 (match_operand:P 2 "register_operand" "=&a")])] 1770 "TARGET_Z10" 1771 { 1772 s390_reload_symref_address (operands[1], operands[0], operands[2], 1); 1773 DONE; 1774 }) 1775 1776 (define_expand "reload<ALL:mode><P:mode>_toreg_z10" 1777 [(parallel [(match_operand:ALL 0 "register_operand" "=d") 1778 (match_operand:ALL 1 "memory_operand" "") 1779 (match_operand:P 2 "register_operand" "=a")])] 1780 "TARGET_Z10" 1781 { 1782 s390_reload_symref_address (operands[0], operands[1], operands[2], 0); 1783 DONE; 1784 }) 1785 1786 (define_expand "reload<P:mode>_larl_odd_addend_z10" 1787 [(parallel [(match_operand:P 0 "register_operand" "=d") 1788 (match_operand:P 1 "larl_operand" "") 1789 (match_operand:P 2 "register_operand" "=a")])] 1790 "TARGET_Z10" 1791 { 1792 s390_reload_larl_operand (operands[0], operands[1], operands[2]); 1793 DONE; 1794 }) 1795 1796 ; Handles loading a PLUS (load address) expression 1797 1798 (define_expand "reload<mode>_plus" 1799 [(parallel [(match_operand:P 0 "register_operand" "=a") 1800 (match_operand:P 1 "s390_plus_operand" "") 1801 (match_operand:P 2 "register_operand" "=&a")])] 1802 "" 1803 { 1804 s390_expand_plus_operand (operands[0], operands[1], operands[2]); 1805 DONE; 1806 }) 1807 1808 ; Not all the indirect memory access instructions support the full 1809 ; format (long disp + index + base). So whenever a move from/to such 1810 ; an address is required and the instruction cannot deal with it we do 1811 ; a load address into a scratch register first and use this as the new 1812 ; base register. 1813 ; This in particular is used for: 1814 ; - non-offsetable memory accesses for multiword moves 1815 ; - full vector reg moves with long displacements 1816 1817 (define_expand "reload<mode>_la_in" 1818 [(parallel [(match_operand 0 "register_operand" "") 1819 (match_operand 1 "" "") 1820 (match_operand:P 2 "register_operand" "=&a")])] 1821 "" 1822 { 1823 gcc_assert (MEM_P (operands[1])); 1824 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); 1825 operands[1] = replace_equiv_address (operands[1], operands[2]); 1826 emit_move_insn (operands[0], operands[1]); 1827 DONE; 1828 }) 1829 1830 (define_expand "reload<mode>_la_out" 1831 [(parallel [(match_operand 0 "" "") 1832 (match_operand 1 "register_operand" "") 1833 (match_operand:P 2 "register_operand" "=&a")])] 1834 "" 1835 { 1836 gcc_assert (MEM_P (operands[0])); 1837 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); 1838 operands[0] = replace_equiv_address (operands[0], operands[2]); 1839 emit_move_insn (operands[0], operands[1]); 1840 DONE; 1841 }) 1842 1843 (define_expand "reload<mode>_PIC_addr" 1844 [(parallel [(match_operand 0 "register_operand" "=d") 1845 (match_operand 1 "larl_operand" "") 1846 (match_operand:P 2 "register_operand" "=a")])] 1847 "" 1848 { 1849 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); 1850 emit_move_insn (operands[0], new_rtx); 1851 }) 1852 1853 ; 1854 ; movdi instruction pattern(s). 1855 ; 1856 1857 (define_expand "movdi" 1858 [(set (match_operand:DI 0 "general_operand" "") 1859 (match_operand:DI 1 "general_operand" ""))] 1860 "" 1861 { 1862 /* Handle symbolic constants. */ 1863 if (TARGET_64BIT 1864 && (SYMBOLIC_CONST (operands[1]) 1865 || (GET_CODE (operands[1]) == PLUS 1866 && XEXP (operands[1], 0) == pic_offset_table_rtx 1867 && SYMBOLIC_CONST (XEXP (operands[1], 1))))) 1868 emit_symbolic_move (operands); 1869 }) 1870 1871 (define_insn "*movdi_64" 1872 [(set (match_operand:DI 0 "nonimmediate_operand" 1873 "=d, d, d, d, d, d, d, d,f,d,!*f,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d") 1874 (match_operand:DI 1 "general_operand" 1875 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,j00,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))] 1876 "TARGET_ZARCH" 1877 "@ 1878 lghi\t%0,%h1 1879 llihh\t%0,%i1 1880 llihl\t%0,%i1 1881 llilh\t%0,%i1 1882 llill\t%0,%i1 1883 lgfi\t%0,%1 1884 llihf\t%0,%k1 1885 llilf\t%0,%k1 1886 ldgr\t%0,%1 1887 lgdr\t%0,%1 1888 lzdr\t%0 1889 lay\t%0,%a1 1890 lgrl\t%0,%1 1891 lgr\t%0,%1 1892 lg\t%0,%1 1893 stg\t%1,%0 1894 ldr\t%0,%1 1895 ld\t%0,%1 1896 ldy\t%0,%1 1897 std\t%1,%0 1898 stdy\t%1,%0 1899 stgrl\t%1,%0 1900 mvghi\t%0,%1 1901 # 1902 # 1903 stam\t%1,%N1,%S0 1904 lam\t%0,%N0,%S1 1905 vleig\t%v0,%h1,0 1906 vlr\t%v0,%v1 1907 vlvgg\t%v0,%1,0 1908 vlgvg\t%0,%v1,0 1909 vleg\t%v0,%1,0 1910 vsteg\t%v1,%0,0 1911 larl\t%0,%1%K1" 1912 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RRE,RXY,RIL,RRE,RXY, 1913 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS, 1914 VRX,VRX,RIL") 1915 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,fsimpdf,la,larl,lr,load,store, 1916 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, 1917 *,*,*,*,*,*,*,larl") 1918 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,*,longdisp, 1919 z10,*,*,*,*,*,longdisp,*,longdisp, 1920 z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*") 1921 (set_attr "z10prop" "z10_fwd_A1, 1922 z10_fwd_E1, 1923 z10_fwd_E1, 1924 z10_fwd_E1, 1925 z10_fwd_E1, 1926 z10_fwd_A1, 1927 z10_fwd_E1, 1928 z10_fwd_E1, 1929 *, 1930 *, 1931 *, 1932 z10_fwd_A1, 1933 z10_fwd_A3, 1934 z10_fr_E1, 1935 z10_fwd_A3, 1936 z10_rec, 1937 *, 1938 *, 1939 *, 1940 *, 1941 *, 1942 z10_rec, 1943 z10_super, 1944 *, 1945 *, 1946 *, 1947 *,*,*,*,*,*,*, 1948 z10_super_A1") 1949 (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,*, 1950 *,yes,*,*,*,*,*,*,*,*, 1951 yes,*,*,*,*,*,*,*,*,*, 1952 *,*,yes") 1953 ]) 1954 1955 ; Splitters for loading TLS pointer from UNSPEC_GET_TP. 1956 ; UNSPEC_GET_TP is used instead of %a0:P, since the latter is a hard register, 1957 ; and those are not handled by Partial Redundancy Elimination (gcse.cc), which 1958 ; results in generation of redundant thread pointer loads. 1959 1960 (define_insn_and_split "*get_tp_31" 1961 [(set (match_operand:SI 0 "register_operand" "=r") 1962 (unspec:SI [(match_operand:SI 1 "register_operand" "t")] 1963 UNSPEC_GET_TP))] 1964 "" 1965 "#" 1966 "&& reload_completed" 1967 [(set (match_dup 0) (match_dup 1))]) 1968 1969 (define_insn_and_split "*get_tp_64" 1970 [(set (match_operand:DI 0 "register_operand" "=r") 1971 (unspec:DI [(match_operand:DI 1 "register_operand" "t")] 1972 UNSPEC_GET_TP))] 1973 "TARGET_ZARCH" 1974 "#" 1975 "&& reload_completed" 1976 [(set (match_dup 2) (match_dup 3)) 1977 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 1978 (set (strict_low_part (match_dup 2)) (match_dup 4))] 1979 "operands[2] = gen_lowpart (SImode, operands[0]); 1980 s390_split_access_reg (operands[1], &operands[4], &operands[3]);") 1981 1982 ; Splitters for storing TLS pointer to %a0:DI. 1983 1984 (define_split 1985 [(set (match_operand:DI 0 "register_operand" "") 1986 (match_operand:DI 1 "register_operand" ""))] 1987 "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && reload_completed 1988 && dead_or_set_p (insn, operands[1])" 1989 [(set (match_dup 3) (match_dup 2)) 1990 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) 1991 (set (match_dup 4) (match_dup 2))] 1992 "operands[2] = gen_lowpart (SImode, operands[1]); 1993 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") 1994 1995 (define_split 1996 [(set (match_operand:DI 0 "register_operand" "") 1997 (match_operand:DI 1 "register_operand" ""))] 1998 "TARGET_ZARCH && ACCESS_REG_P (operands[0]) && reload_completed 1999 && !dead_or_set_p (insn, operands[1])" 2000 [(set (match_dup 3) (match_dup 2)) 2001 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) 2002 (set (match_dup 4) (match_dup 2)) 2003 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] 2004 "operands[2] = gen_lowpart (SImode, operands[1]); 2005 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") 2006 2007 (define_insn "*movdi_31" 2008 [(set (match_operand:DI 0 "nonimmediate_operand" 2009 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!*f,!R,!T,d") 2010 (match_operand:DI 1 "general_operand" 2011 " Q,S,d,d,dPT,d, *f, R, T,j00,*f,*f,b"))] 2012 "!TARGET_ZARCH" 2013 "@ 2014 lm\t%0,%N0,%S1 2015 lmy\t%0,%N0,%S1 2016 stm\t%1,%N1,%S0 2017 stmy\t%1,%N1,%S0 2018 # 2019 # 2020 ldr\t%0,%1 2021 ld\t%0,%1 2022 ldy\t%0,%1 2023 lzdr\t%0 2024 std\t%1,%0 2025 stdy\t%1,%0 2026 #" 2027 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RRE,RX,RXY,*") 2028 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fsimpdf,fstoredf,fstoredf,*") 2029 (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,*,longdisp,z10")]) 2030 2031 ; For a load from a symbol ref we can use one of the target registers 2032 ; together with larl to load the address. 2033 (define_split 2034 [(set (match_operand:DI 0 "register_operand" "") 2035 (match_operand:DI 1 "memory_operand" ""))] 2036 "!TARGET_ZARCH && reload_completed && TARGET_Z10 2037 && larl_operand (XEXP (operands[1], 0), SImode)" 2038 [(set (match_dup 2) (match_dup 3)) 2039 (set (match_dup 0) (match_dup 1))] 2040 { 2041 operands[2] = operand_subword (operands[0], 1, 0, DImode); 2042 operands[3] = XEXP (operands[1], 0); 2043 operands[1] = replace_equiv_address (operands[1], operands[2]); 2044 }) 2045 2046 (define_split 2047 [(set (match_operand:DI 0 "nonimmediate_operand" "") 2048 (match_operand:DI 1 "general_operand" ""))] 2049 "!TARGET_ZARCH && reload_completed 2050 && !s_operand (operands[0], DImode) 2051 && !s_operand (operands[1], DImode) 2052 && s390_split_ok_p (operands[0], operands[1], DImode, 0)" 2053 [(set (match_dup 2) (match_dup 4)) 2054 (set (match_dup 3) (match_dup 5))] 2055 { 2056 operands[2] = operand_subword (operands[0], 0, 0, DImode); 2057 operands[3] = operand_subword (operands[0], 1, 0, DImode); 2058 operands[4] = operand_subword (operands[1], 0, 0, DImode); 2059 operands[5] = operand_subword (operands[1], 1, 0, DImode); 2060 }) 2061 2062 (define_split 2063 [(set (match_operand:DI 0 "nonimmediate_operand" "") 2064 (match_operand:DI 1 "general_operand" ""))] 2065 "!TARGET_ZARCH && reload_completed 2066 && !s_operand (operands[0], DImode) 2067 && !s_operand (operands[1], DImode) 2068 && s390_split_ok_p (operands[0], operands[1], DImode, 1)" 2069 [(set (match_dup 2) (match_dup 4)) 2070 (set (match_dup 3) (match_dup 5))] 2071 { 2072 operands[2] = operand_subword (operands[0], 1, 0, DImode); 2073 operands[3] = operand_subword (operands[0], 0, 0, DImode); 2074 operands[4] = operand_subword (operands[1], 1, 0, DImode); 2075 operands[5] = operand_subword (operands[1], 0, 0, DImode); 2076 }) 2077 2078 (define_split 2079 [(set (match_operand:DI 0 "register_operand" "") 2080 (match_operand:DI 1 "memory_operand" ""))] 2081 "!TARGET_ZARCH && reload_completed 2082 && !FP_REG_P (operands[0]) 2083 && !s_operand (operands[1], VOIDmode)" 2084 [(set (match_dup 0) (match_dup 1))] 2085 { 2086 rtx addr = operand_subword (operands[0], 1, 0, DImode); 2087 s390_load_address (addr, XEXP (operands[1], 0)); 2088 operands[1] = replace_equiv_address (operands[1], addr); 2089 }) 2090 2091 (define_peephole2 2092 [(set (match_operand:DI 0 "register_operand" "") 2093 (mem:DI (match_operand 1 "address_operand" "")))] 2094 "TARGET_ZARCH 2095 && !FP_REG_P (operands[0]) 2096 && GET_CODE (operands[1]) == SYMBOL_REF 2097 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2098 && get_pool_mode (operands[1]) == DImode 2099 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 2100 [(set (match_dup 0) (match_dup 2))] 2101 "operands[2] = get_pool_constant (operands[1]);") 2102 2103 (define_insn "*la_64" 2104 [(set (match_operand:DI 0 "register_operand" "=d,d") 2105 (match_operand:QI 1 "address_operand" "ZR,ZT"))] 2106 "TARGET_64BIT" 2107 "@ 2108 la\t%0,%a1 2109 lay\t%0,%a1" 2110 [(set_attr "op_type" "RX,RXY") 2111 (set_attr "type" "la") 2112 (set_attr "cpu_facility" "*,longdisp") 2113 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2114 2115 (define_peephole2 2116 [(parallel 2117 [(set (match_operand:DI 0 "register_operand" "") 2118 (match_operand:QI 1 "address_operand" "")) 2119 (clobber (reg:CC CC_REGNUM))])] 2120 "TARGET_64BIT 2121 && preferred_la_operand_p (operands[1], const0_rtx)" 2122 [(set (match_dup 0) (match_dup 1))] 2123 "") 2124 2125 (define_peephole2 2126 [(set (match_operand:DI 0 "register_operand" "") 2127 (match_operand:DI 1 "register_operand" "")) 2128 (parallel 2129 [(set (match_dup 0) 2130 (plus:DI (match_dup 0) 2131 (match_operand:DI 2 "nonmemory_operand" ""))) 2132 (clobber (reg:CC CC_REGNUM))])] 2133 "TARGET_64BIT 2134 && !reg_overlap_mentioned_p (operands[0], operands[2]) 2135 && preferred_la_operand_p (operands[1], operands[2])" 2136 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] 2137 "") 2138 2139 ; Split loading of 64-bit constants into GPRs into llihf + oilf - 2140 ; counterintuitively, using oilf is faster than iilf. oilf clobbers 2141 ; cc, so cc must be dead. 2142 (define_peephole2 2143 [(set (match_operand:DI 0 "register_operand" "") 2144 (match_operand:DI 1 "memory_operand" ""))] 2145 "TARGET_64BIT 2146 && TARGET_EXTIMM 2147 && GENERAL_REG_P (operands[0]) 2148 && s390_const_int_pool_entry_p (operands[1], nullptr) 2149 && peep2_reg_dead_p (1, gen_rtx_REG (CCmode, CC_REGNUM))" 2150 [(set (match_dup 0) (match_dup 2)) 2151 (parallel 2152 [(set (match_dup 0) (ior:DI (match_dup 0) (match_dup 3))) 2153 (clobber (reg:CC CC_REGNUM))])] 2154 { 2155 HOST_WIDE_INT val; 2156 bool ok = s390_const_int_pool_entry_p (operands[1], &val); 2157 gcc_assert (ok); 2158 operands[2] = GEN_INT (val & 0xFFFFFFFF00000000ULL); 2159 operands[3] = GEN_INT (val & 0x00000000FFFFFFFFULL); 2160 }) 2161 2162 ; 2163 ; movsi instruction pattern(s). 2164 ; 2165 2166 (define_expand "movsi" 2167 [(set (match_operand:SI 0 "general_operand" "") 2168 (match_operand:SI 1 "general_operand" ""))] 2169 "" 2170 { 2171 /* Handle symbolic constants. */ 2172 if (!TARGET_64BIT 2173 && (SYMBOLIC_CONST (operands[1]) 2174 || (GET_CODE (operands[1]) == PLUS 2175 && XEXP (operands[1], 0) == pic_offset_table_rtx 2176 && SYMBOLIC_CONST (XEXP(operands[1], 1))))) 2177 emit_symbolic_move (operands); 2178 }) 2179 2180 (define_insn "*movsi_larl" 2181 [(set (match_operand:SI 0 "register_operand" "=d") 2182 (match_operand:SI 1 "larl_operand" "X"))] 2183 "!TARGET_64BIT 2184 && !FP_REG_P (operands[0])" 2185 "larl\t%0,%1%K1" 2186 [(set_attr "op_type" "RIL") 2187 (set_attr "type" "larl") 2188 (set_attr "z10prop" "z10_fwd_A1") 2189 (set_attr "relative_long" "yes")]) 2190 2191 (define_insn "*movsi_zarch" 2192 [(set (match_operand:SI 0 "nonimmediate_operand" 2193 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") 2194 (match_operand:SI 1 "general_operand" 2195 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] 2196 "TARGET_ZARCH" 2197 "@ 2198 lhi\t%0,%h1 2199 llilh\t%0,%i1 2200 llill\t%0,%i1 2201 iilf\t%0,%o1 2202 lay\t%0,%a1 2203 lrl\t%0,%1 2204 lr\t%0,%1 2205 l\t%0,%1 2206 ly\t%0,%1 2207 st\t%1,%0 2208 sty\t%1,%0 2209 ldr\t%0,%1 2210 ler\t%0,%1 2211 lde\t%0,%1 2212 le\t%0,%1 2213 ley\t%0,%1 2214 ste\t%1,%0 2215 stey\t%1,%0 2216 ear\t%0,%1 2217 sar\t%0,%1 2218 stam\t%1,%1,%S0 2219 strl\t%1,%0 2220 mvhi\t%0,%1 2221 lam\t%0,%0,%S1 2222 vleif\t%v0,%h1,0 2223 vlr\t%v0,%v1 2224 vlvgf\t%v0,%1,0 2225 vlgvf\t%0,%v1,0 2226 vlef\t%v0,%1,0 2227 vstef\t%v1,%0,0" 2228 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, 2229 RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") 2230 (set_attr "type" "*, 2231 *, 2232 *, 2233 *, 2234 la, 2235 larl, 2236 lr, 2237 load, 2238 load, 2239 store, 2240 store, 2241 floadsf, 2242 floadsf, 2243 floadsf, 2244 floadsf, 2245 floadsf, 2246 fstoresf, 2247 fstoresf, 2248 *, 2249 *, 2250 *, 2251 larl, 2252 *, 2253 *,*,*,*,*,*,*") 2254 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, 2255 vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") 2256 (set_attr "z10prop" "z10_fwd_A1, 2257 z10_fwd_E1, 2258 z10_fwd_E1, 2259 z10_fwd_A1, 2260 z10_fwd_A1, 2261 z10_fwd_A3, 2262 z10_fr_E1, 2263 z10_fwd_A3, 2264 z10_fwd_A3, 2265 z10_rec, 2266 z10_rec, 2267 *, 2268 *, 2269 *, 2270 *, 2271 *, 2272 *, 2273 *, 2274 z10_super_E1, 2275 z10_super, 2276 *, 2277 z10_rec, 2278 z10_super, 2279 *,*,*,*,*,*,*") 2280 (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*, 2281 *,*,*,*,*,*,*,*,*,*, 2282 *,yes,*,*,*,*,*,*,*,*")]) 2283 2284 (define_insn "*movsi_esa" 2285 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") 2286 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] 2287 "!TARGET_ZARCH" 2288 "@ 2289 lhi\t%0,%h1 2290 lr\t%0,%1 2291 l\t%0,%1 2292 st\t%1,%0 2293 ldr\t%0,%1 2294 ler\t%0,%1 2295 lde\t%0,%1 2296 le\t%0,%1 2297 ste\t%1,%0 2298 ear\t%0,%1 2299 sar\t%0,%1 2300 stam\t%1,%1,%S0 2301 lam\t%0,%0,%S1" 2302 [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") 2303 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") 2304 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, 2305 z10_super,*,*") 2306 (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") 2307 ]) 2308 2309 (define_peephole2 2310 [(set (match_operand:SI 0 "register_operand" "") 2311 (mem:SI (match_operand 1 "address_operand" "")))] 2312 "!FP_REG_P (operands[0]) 2313 && GET_CODE (operands[1]) == SYMBOL_REF 2314 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2315 && get_pool_mode (operands[1]) == SImode 2316 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 2317 [(set (match_dup 0) (match_dup 2))] 2318 "operands[2] = get_pool_constant (operands[1]);") 2319 2320 (define_insn "*la_31" 2321 [(set (match_operand:SI 0 "register_operand" "=d,d") 2322 (match_operand:QI 1 "address_operand" "ZR,ZT"))] 2323 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" 2324 "@ 2325 la\t%0,%a1 2326 lay\t%0,%a1" 2327 [(set_attr "op_type" "RX,RXY") 2328 (set_attr "type" "la") 2329 (set_attr "cpu_facility" "*,longdisp") 2330 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2331 2332 (define_peephole2 2333 [(parallel 2334 [(set (match_operand:SI 0 "register_operand" "") 2335 (match_operand:QI 1 "address_operand" "")) 2336 (clobber (reg:CC CC_REGNUM))])] 2337 "!TARGET_64BIT 2338 && preferred_la_operand_p (operands[1], const0_rtx)" 2339 [(set (match_dup 0) (match_dup 1))] 2340 "") 2341 2342 (define_peephole2 2343 [(set (match_operand:SI 0 "register_operand" "") 2344 (match_operand:SI 1 "register_operand" "")) 2345 (parallel 2346 [(set (match_dup 0) 2347 (plus:SI (match_dup 0) 2348 (match_operand:SI 2 "nonmemory_operand" ""))) 2349 (clobber (reg:CC CC_REGNUM))])] 2350 "!TARGET_64BIT 2351 && !reg_overlap_mentioned_p (operands[0], operands[2]) 2352 && preferred_la_operand_p (operands[1], operands[2])" 2353 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] 2354 "") 2355 2356 (define_insn "*la_31_and" 2357 [(set (match_operand:SI 0 "register_operand" "=d,d") 2358 (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") 2359 (const_int 2147483647)))] 2360 "!TARGET_64BIT" 2361 "@ 2362 la\t%0,%a1 2363 lay\t%0,%a1" 2364 [(set_attr "op_type" "RX,RXY") 2365 (set_attr "type" "la") 2366 (set_attr "cpu_facility" "*,longdisp") 2367 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2368 2369 (define_insn_and_split "*la_31_and_cc" 2370 [(set (match_operand:SI 0 "register_operand" "=d") 2371 (and:SI (match_operand:QI 1 "address_operand" "p") 2372 (const_int 2147483647))) 2373 (clobber (reg:CC CC_REGNUM))] 2374 "!TARGET_64BIT" 2375 "#" 2376 "&& reload_completed" 2377 [(set (match_dup 0) 2378 (and:SI (match_dup 1) (const_int 2147483647)))] 2379 "" 2380 [(set_attr "op_type" "RX") 2381 (set_attr "type" "la")]) 2382 2383 (define_insn "force_la_31" 2384 [(set (match_operand:SI 0 "register_operand" "=d,d") 2385 (match_operand:QI 1 "address_operand" "ZR,ZT")) 2386 (use (const_int 0))] 2387 "!TARGET_64BIT" 2388 "@ 2389 la\t%0,%a1 2390 lay\t%0,%a1" 2391 [(set_attr "op_type" "RX") 2392 (set_attr "type" "la") 2393 (set_attr "cpu_facility" "*,longdisp") 2394 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2395 2396 ; 2397 ; movhi instruction pattern(s). 2398 ; 2399 2400 (define_expand "movhi" 2401 [(set (match_operand:HI 0 "nonimmediate_operand" "") 2402 (match_operand:HI 1 "general_operand" ""))] 2403 "" 2404 { 2405 /* Make it explicit that loading a register from memory 2406 always sign-extends (at least) to SImode. */ 2407 if (optimize && can_create_pseudo_p () 2408 && register_operand (operands[0], VOIDmode) 2409 && GET_CODE (operands[1]) == MEM) 2410 { 2411 rtx tmp = gen_reg_rtx (SImode); 2412 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); 2413 emit_insn (gen_rtx_SET (tmp, ext)); 2414 operands[1] = gen_lowpart (HImode, tmp); 2415 } 2416 }) 2417 2418 (define_insn "*movhi" 2419 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") 2420 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] 2421 "" 2422 "@ 2423 lr\t%0,%1 2424 lhi\t%0,%h1 2425 lh\t%0,%1 2426 lhy\t%0,%1 2427 lhrl\t%0,%1 2428 sth\t%1,%0 2429 sthy\t%1,%0 2430 sthrl\t%1,%0 2431 mvhhi\t%0,%1 2432 vleih\t%v0,%h1,0 2433 vlr\t%v0,%v1 2434 vlvgh\t%v0,%1,0 2435 vlgvh\t%0,%v1,0 2436 vleh\t%v0,%1,0 2437 vsteh\t%v1,%0,0" 2438 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") 2439 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") 2440 (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") 2441 (set_attr "z10prop" "z10_fr_E1, 2442 z10_fwd_A1, 2443 z10_super_E1, 2444 z10_super_E1, 2445 z10_super_E1, 2446 z10_rec, 2447 z10_rec, 2448 z10_rec, 2449 z10_super,*,*,*,*,*,*") 2450 (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")]) 2451 2452 (define_peephole2 2453 [(set (match_operand:HI 0 "register_operand" "") 2454 (mem:HI (match_operand 1 "address_operand" "")))] 2455 "GET_CODE (operands[1]) == SYMBOL_REF 2456 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2457 && get_pool_mode (operands[1]) == HImode 2458 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 2459 [(set (match_dup 0) (match_dup 2))] 2460 "operands[2] = get_pool_constant (operands[1]);") 2461 2462 ; 2463 ; movqi instruction pattern(s). 2464 ; 2465 2466 (define_expand "movqi" 2467 [(set (match_operand:QI 0 "nonimmediate_operand" "") 2468 (match_operand:QI 1 "general_operand" ""))] 2469 "" 2470 { 2471 /* On z/Architecture, zero-extending from memory to register 2472 is just as fast as a QImode load. */ 2473 if (TARGET_ZARCH && optimize && can_create_pseudo_p () 2474 && register_operand (operands[0], VOIDmode) 2475 && GET_CODE (operands[1]) == MEM) 2476 { 2477 rtx tmp = gen_reg_rtx (DImode); 2478 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); 2479 emit_insn (gen_rtx_SET (tmp, ext)); 2480 operands[1] = gen_lowpart (QImode, tmp); 2481 } 2482 }) 2483 2484 (define_insn "*movqi" 2485 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") 2486 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] 2487 "" 2488 "@ 2489 lr\t%0,%1 2490 lhi\t%0,%b1 2491 ic\t%0,%1 2492 icy\t%0,%1 2493 stc\t%1,%0 2494 stcy\t%1,%0 2495 mvi\t%S0,%b1 2496 mviy\t%S0,%b1 2497 # 2498 vleib\t%v0,%b1,0 2499 vlr\t%v0,%v1 2500 vlvgb\t%v0,%1,0 2501 vlgvb\t%0,%v1,0 2502 vleb\t%v0,%1,0 2503 vsteb\t%v1,%0,0" 2504 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") 2505 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") 2506 (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") 2507 (set_attr "z10prop" "z10_fr_E1, 2508 z10_fwd_A1, 2509 z10_super_E1, 2510 z10_super_E1, 2511 z10_rec, 2512 z10_rec, 2513 z10_super, 2514 z10_super, 2515 *,*,*,*,*,*,*")]) 2516 2517 (define_peephole2 2518 [(set (match_operand:QI 0 "nonimmediate_operand" "") 2519 (mem:QI (match_operand 1 "address_operand" "")))] 2520 "GET_CODE (operands[1]) == SYMBOL_REF 2521 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2522 && get_pool_mode (operands[1]) == QImode 2523 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 2524 [(set (match_dup 0) (match_dup 2))] 2525 "operands[2] = get_pool_constant (operands[1]);") 2526 2527 2528 ; 2529 ; movstrict instruction pattern(s). 2530 ; 2531 2532 (define_insn "movstrictqi" 2533 [(set (strict_low_part (match_operand:QI 0 "subreg_register_operand" "+d,d")) 2534 (match_operand:QI 1 "memory_operand" "R,T"))] 2535 "" 2536 "@ 2537 ic\t%0,%1 2538 icy\t%0,%1" 2539 [(set_attr "op_type" "RX,RXY") 2540 (set_attr "cpu_facility" "*,longdisp") 2541 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 2542 2543 (define_insn "movstricthi" 2544 [(set (strict_low_part (match_operand:HI 0 "subreg_register_operand" "+d,d")) 2545 (match_operand:HI 1 "memory_operand" "Q,S")) 2546 (clobber (reg:CC CC_REGNUM))] 2547 "" 2548 "@ 2549 icm\t%0,3,%S1 2550 icmy\t%0,3,%S1" 2551 [(set_attr "op_type" "RS,RSY") 2552 (set_attr "cpu_facility" "*,longdisp") 2553 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 2554 2555 (define_insn "movstrictsi" 2556 [(set (strict_low_part (match_operand:SI 0 "subreg_register_operand" "+d,d,d,d")) 2557 (match_operand:SI 1 "general_operand" "d,R,T,t"))] 2558 "TARGET_ZARCH" 2559 "@ 2560 lr\t%0,%1 2561 l\t%0,%1 2562 ly\t%0,%1 2563 ear\t%0,%1" 2564 [(set_attr "op_type" "RR,RX,RXY,RRE") 2565 (set_attr "type" "lr,load,load,*") 2566 (set_attr "cpu_facility" "*,*,longdisp,*") 2567 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) 2568 2569 ; 2570 ; mov(tf|td) instruction pattern(s). 2571 ; 2572 2573 (define_expand "mov<mode><tf_fpr>" 2574 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2575 (match_operand:TD_TF 1 "general_operand" ""))] 2576 "" 2577 "") 2578 2579 (define_insn "*mov<mode>_64" 2580 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") 2581 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] 2582 "TARGET_ZARCH" 2583 "@ 2584 lzxr\t%0 2585 lxr\t%0,%1 2586 # 2587 # 2588 lmg\t%0,%N0,%S1 2589 stmg\t%1,%N1,%S0 2590 # 2591 #" 2592 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") 2593 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") 2594 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) 2595 2596 (define_insn "*mov<mode>_31" 2597 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") 2598 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] 2599 "!TARGET_ZARCH" 2600 "@ 2601 lzxr\t%0 2602 lxr\t%0,%1 2603 # 2604 #" 2605 [(set_attr "op_type" "RRE,RRE,*,*") 2606 (set_attr "type" "fsimptf,fsimptf,*,*") 2607 (set_attr "cpu_facility" "z196,*,*,*")]) 2608 2609 ; TFmode in GPRs splitters 2610 2611 (define_split 2612 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2613 (match_operand:TD_TF 1 "general_operand" ""))] 2614 "TARGET_ZARCH && reload_completed 2615 && !s_operand (operands[0], <MODE>mode) 2616 && !s_operand (operands[1], <MODE>mode) 2617 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 2618 [(set (match_dup 2) (match_dup 4)) 2619 (set (match_dup 3) (match_dup 5))] 2620 { 2621 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 2622 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 2623 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); 2624 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); 2625 }) 2626 2627 (define_split 2628 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2629 (match_operand:TD_TF 1 "general_operand" ""))] 2630 "TARGET_ZARCH && reload_completed 2631 && !s_operand (operands[0], <MODE>mode) 2632 && !s_operand (operands[1], <MODE>mode) 2633 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 2634 [(set (match_dup 2) (match_dup 4)) 2635 (set (match_dup 3) (match_dup 5))] 2636 { 2637 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 2638 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); 2639 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); 2640 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); 2641 }) 2642 2643 (define_split 2644 [(set (match_operand:TD_TF 0 "register_operand" "") 2645 (match_operand:TD_TF 1 "memory_operand" ""))] 2646 "TARGET_ZARCH && reload_completed 2647 && GENERAL_REG_P (operands[0]) 2648 && !s_operand (operands[1], VOIDmode)" 2649 [(set (match_dup 0) (match_dup 1))] 2650 { 2651 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 2652 addr = gen_lowpart (Pmode, addr); 2653 s390_load_address (addr, XEXP (operands[1], 0)); 2654 operands[1] = replace_equiv_address (operands[1], addr); 2655 }) 2656 2657 ; TFmode in BFPs splitters 2658 2659 (define_split 2660 [(set (match_operand:TD_TF 0 "register_operand" "") 2661 (match_operand:TD_TF 1 "memory_operand" ""))] 2662 "reload_completed && offsettable_memref_p (operands[1]) 2663 && FP_REG_P (operands[0])" 2664 [(set (match_dup 2) (match_dup 4)) 2665 (set (match_dup 3) (match_dup 5))] 2666 { 2667 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], 2668 <MODE>mode, 0); 2669 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], 2670 <MODE>mode, 8); 2671 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); 2672 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); 2673 }) 2674 2675 (define_split 2676 [(set (match_operand:TD_TF 0 "memory_operand" "") 2677 (match_operand:TD_TF 1 "register_operand" ""))] 2678 "reload_completed && offsettable_memref_p (operands[0]) 2679 && FP_REG_P (operands[1])" 2680 [(set (match_dup 2) (match_dup 4)) 2681 (set (match_dup 3) (match_dup 5))] 2682 { 2683 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); 2684 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); 2685 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], 2686 <MODE>mode, 0); 2687 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], 2688 <MODE>mode, 8); 2689 }) 2690 2691 ; 2692 ; mov(df|dd) instruction pattern(s). 2693 ; 2694 2695 (define_expand "mov<mode>" 2696 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2697 (match_operand:DD_DF 1 "general_operand" ""))] 2698 "" 2699 "") 2700 2701 (define_insn "*mov<mode>_64dfp" 2702 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2703 "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") 2704 (match_operand:DD_DF 1 "general_operand" 2705 " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] 2706 "TARGET_DFP" 2707 "@ 2708 lzdr\t%0 2709 ldr\t%0,%1 2710 ldgr\t%0,%1 2711 lgdr\t%0,%1 2712 ld\t%0,%1 2713 ldy\t%0,%1 2714 std\t%1,%0 2715 stdy\t%1,%0 2716 lghi\t%0,0 2717 lgr\t%0,%1 2718 lgrl\t%0,%1 2719 lg\t%0,%1 2720 stgrl\t%1,%0 2721 stg\t%1,%0 2722 vlr\t%v0,%v1 2723 vleig\t%v0,0,0 2724 vlvgg\t%v0,%1,0 2725 vlgvg\t%0,%v1,0 2726 vleg\t%0,%1,0 2727 vsteg\t%1,%0,0" 2728 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") 2729 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, 2730 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") 2731 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") 2732 (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx") 2733 (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")]) 2734 2735 (define_insn "*mov<mode>_64" 2736 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") 2737 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] 2738 "TARGET_ZARCH" 2739 "@ 2740 lzdr\t%0 2741 ldr\t%0,%1 2742 ld\t%0,%1 2743 ldy\t%0,%1 2744 std\t%1,%0 2745 stdy\t%1,%0 2746 lghi\t%0,0 2747 lgr\t%0,%1 2748 lgrl\t%0,%1 2749 lg\t%0,%1 2750 stgrl\t%1,%0 2751 stg\t%1,%0" 2752 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") 2753 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, 2754 fstore<mode>,fstore<mode>,*,lr,load,load,store,store") 2755 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") 2756 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*") 2757 (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")]) 2758 2759 (define_insn "*mov<mode>_31" 2760 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2761 "=f,f,f,f,R,T,d,d,Q,S, d,o") 2762 (match_operand:DD_DF 1 "general_operand" 2763 " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] 2764 "!TARGET_ZARCH" 2765 "@ 2766 lzdr\t%0 2767 ldr\t%0,%1 2768 ld\t%0,%1 2769 ldy\t%0,%1 2770 std\t%1,%0 2771 stdy\t%1,%0 2772 lm\t%0,%N0,%S1 2773 lmy\t%0,%N0,%S1 2774 stm\t%1,%N1,%S0 2775 stmy\t%1,%N1,%S0 2776 # 2777 #" 2778 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") 2779 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, 2780 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") 2781 (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) 2782 2783 (define_split 2784 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2785 (match_operand:DD_DF 1 "general_operand" ""))] 2786 "!TARGET_ZARCH && reload_completed 2787 && !s_operand (operands[0], <MODE>mode) 2788 && !s_operand (operands[1], <MODE>mode) 2789 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 2790 [(set (match_dup 2) (match_dup 4)) 2791 (set (match_dup 3) (match_dup 5))] 2792 { 2793 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 2794 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 2795 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); 2796 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); 2797 }) 2798 2799 (define_split 2800 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2801 (match_operand:DD_DF 1 "general_operand" ""))] 2802 "!TARGET_ZARCH && reload_completed 2803 && !s_operand (operands[0], <MODE>mode) 2804 && !s_operand (operands[1], <MODE>mode) 2805 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 2806 [(set (match_dup 2) (match_dup 4)) 2807 (set (match_dup 3) (match_dup 5))] 2808 { 2809 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 2810 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); 2811 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); 2812 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); 2813 }) 2814 2815 (define_split 2816 [(set (match_operand:DD_DF 0 "register_operand" "") 2817 (match_operand:DD_DF 1 "memory_operand" ""))] 2818 "!TARGET_ZARCH && reload_completed 2819 && !FP_REG_P (operands[0]) 2820 && !s_operand (operands[1], VOIDmode)" 2821 [(set (match_dup 0) (match_dup 1))] 2822 { 2823 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 2824 s390_load_address (addr, XEXP (operands[1], 0)); 2825 operands[1] = replace_equiv_address (operands[1], addr); 2826 }) 2827 2828 ; 2829 ; mov(sf|sd) instruction pattern(s). 2830 ; 2831 2832 (define_insn "mov<mode>" 2833 [(set (match_operand:SD_SF 0 "nonimmediate_operand" 2834 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") 2835 (match_operand:SD_SF 1 "general_operand" 2836 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] 2837 "" 2838 "@ 2839 lzer\t%0 2840 ldr\t%0,%1 2841 ler\t%0,%1 2842 lde\t%0,%1 2843 le\t%0,%1 2844 ley\t%0,%1 2845 ste\t%1,%0 2846 stey\t%1,%0 2847 lhi\t%0,0 2848 lr\t%0,%1 2849 lrl\t%0,%1 2850 l\t%0,%1 2851 ly\t%0,%1 2852 strl\t%1,%0 2853 st\t%1,%0 2854 sty\t%1,%0 2855 vlr\t%v0,%v1 2856 vleif\t%v0,0,0 2857 vlvgf\t%v0,%1,0 2858 vlgvf\t%0,%v1,0 2859 vlef\t%0,%1,0 2860 vstef\t%1,%0,0" 2861 [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") 2862 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, 2863 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") 2864 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") 2865 (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx") 2866 (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")]) 2867 2868 ; 2869 ; movcc instruction pattern 2870 ; 2871 2872 (define_insn "movcc" 2873 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") 2874 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] 2875 "" 2876 "@ 2877 lr\t%0,%1 2878 tmh\t%1,12288 2879 ipm\t%0 2880 l\t%0,%1 2881 ly\t%0,%1 2882 st\t%1,%0 2883 sty\t%1,%0" 2884 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") 2885 (set_attr "type" "lr,*,*,load,load,store,store") 2886 (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") 2887 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") 2888 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) 2889 2890 ; 2891 ; Block move (MVC) patterns. 2892 ; 2893 2894 (define_insn "*mvc" 2895 [(set (match_operand:BLK 0 "memory_operand" "=Q") 2896 (match_operand:BLK 1 "memory_operand" "Q")) 2897 (use (match_operand 2 "const_int_operand" "n"))] 2898 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 2899 "mvc\t%O0(%2,%R0),%S1" 2900 [(set_attr "op_type" "SS")]) 2901 2902 ; This splitter converts a QI to QI mode copy into a BLK mode copy in 2903 ; order to have it implemented with mvc. 2904 2905 (define_split 2906 [(set (match_operand:QI 0 "memory_operand" "") 2907 (match_operand:QI 1 "memory_operand" ""))] 2908 "reload_completed" 2909 [(parallel 2910 [(set (match_dup 0) (match_dup 1)) 2911 (use (const_int 1))])] 2912 { 2913 operands[0] = adjust_address (operands[0], BLKmode, 0); 2914 operands[1] = adjust_address (operands[1], BLKmode, 0); 2915 }) 2916 2917 2918 (define_peephole2 2919 [(parallel 2920 [(set (match_operand:BLK 0 "memory_operand" "") 2921 (match_operand:BLK 1 "memory_operand" "")) 2922 (use (match_operand 2 "const_int_operand" ""))]) 2923 (parallel 2924 [(set (match_operand:BLK 3 "memory_operand" "") 2925 (match_operand:BLK 4 "memory_operand" "")) 2926 (use (match_operand 5 "const_int_operand" ""))])] 2927 "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) 2928 || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) 2929 && s390_offset_p (operands[0], operands[3], operands[2]) 2930 && s390_offset_p (operands[1], operands[4], operands[2]) 2931 && !s390_overlap_p (operands[0], operands[1], 2932 INTVAL (operands[2]) + INTVAL (operands[5])) 2933 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 2934 [(parallel 2935 [(set (match_dup 6) (match_dup 7)) 2936 (use (match_dup 8))])] 2937 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 2938 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 2939 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 2940 2941 (define_peephole2 2942 [(parallel 2943 [(set (match_operand:BLK 0 "plus16_Q_operand" "") 2944 (match_operand:BLK 1 "plus16_Q_operand" "")) 2945 (use (match_operand 2 "const_int_operand" ""))])] 2946 "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" 2947 [(parallel 2948 [(set (match_dup 0) (match_dup 1)) 2949 (use (const_int 16))]) 2950 (parallel 2951 [(set (match_dup 3) (match_dup 4)) 2952 (use (match_dup 5))])] 2953 "operands[3] = change_address (operands[0], VOIDmode, 2954 plus_constant (Pmode, XEXP (operands[0], 0), 16)); 2955 operands[4] = change_address (operands[1], VOIDmode, 2956 plus_constant (Pmode, XEXP (operands[1], 0), 16)); 2957 operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") 2958 2959 2960 ; 2961 ; load_multiple pattern(s). 2962 ; 2963 ; ??? Due to reload problems with replacing registers inside match_parallel 2964 ; we currently support load_multiple/store_multiple only after reload. 2965 ; 2966 2967 (define_expand "load_multiple" 2968 [(match_par_dup 3 [(set (match_operand 0 "" "") 2969 (match_operand 1 "" "")) 2970 (use (match_operand 2 "" ""))])] 2971 "reload_completed" 2972 { 2973 machine_mode mode; 2974 int regno; 2975 int count; 2976 rtx from; 2977 int i, off; 2978 2979 /* Support only loading a constant number of fixed-point registers from 2980 memory and only bother with this if more than two */ 2981 if (GET_CODE (operands[2]) != CONST_INT 2982 || INTVAL (operands[2]) < 2 2983 || INTVAL (operands[2]) > 16 2984 || GET_CODE (operands[1]) != MEM 2985 || GET_CODE (operands[0]) != REG 2986 || REGNO (operands[0]) >= 16) 2987 FAIL; 2988 2989 count = INTVAL (operands[2]); 2990 regno = REGNO (operands[0]); 2991 mode = GET_MODE (operands[0]); 2992 if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) 2993 FAIL; 2994 2995 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 2996 if (!can_create_pseudo_p ()) 2997 { 2998 if (GET_CODE (XEXP (operands[1], 0)) == REG) 2999 { 3000 from = XEXP (operands[1], 0); 3001 off = 0; 3002 } 3003 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS 3004 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG 3005 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) 3006 { 3007 from = XEXP (XEXP (operands[1], 0), 0); 3008 off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 3009 } 3010 else 3011 FAIL; 3012 } 3013 else 3014 { 3015 from = force_reg (Pmode, XEXP (operands[1], 0)); 3016 off = 0; 3017 } 3018 3019 for (i = 0; i < count; i++) 3020 XVECEXP (operands[3], 0, i) 3021 = gen_rtx_SET (gen_rtx_REG (mode, regno + i), 3022 change_address (operands[1], mode, 3023 plus_constant (Pmode, from, 3024 off + i * GET_MODE_SIZE (mode)))); 3025 }) 3026 3027 (define_insn "*load_multiple_di" 3028 [(match_parallel 0 "load_multiple_operation" 3029 [(set (match_operand:DI 1 "register_operand" "=r") 3030 (match_operand:DI 2 "s_operand" "S"))])] 3031 "reload_completed && TARGET_ZARCH" 3032 { 3033 int words = XVECLEN (operands[0], 0); 3034 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); 3035 return "lmg\t%1,%0,%S2"; 3036 } 3037 [(set_attr "op_type" "RSY") 3038 (set_attr "type" "lm")]) 3039 3040 (define_insn "*load_multiple_si" 3041 [(match_parallel 0 "load_multiple_operation" 3042 [(set (match_operand:SI 1 "register_operand" "=r,r") 3043 (match_operand:SI 2 "s_operand" "Q,S"))])] 3044 "reload_completed" 3045 { 3046 int words = XVECLEN (operands[0], 0); 3047 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); 3048 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; 3049 } 3050 [(set_attr "op_type" "RS,RSY") 3051 (set_attr "cpu_facility" "*,longdisp") 3052 (set_attr "type" "lm")]) 3053 3054 ; 3055 ; store multiple pattern(s). 3056 ; 3057 3058 (define_expand "store_multiple" 3059 [(match_par_dup 3 [(set (match_operand 0 "" "") 3060 (match_operand 1 "" "")) 3061 (use (match_operand 2 "" ""))])] 3062 "reload_completed" 3063 { 3064 machine_mode mode; 3065 int regno; 3066 int count; 3067 rtx to; 3068 int i, off; 3069 3070 /* Support only storing a constant number of fixed-point registers to 3071 memory and only bother with this if more than two. */ 3072 if (GET_CODE (operands[2]) != CONST_INT 3073 || INTVAL (operands[2]) < 2 3074 || INTVAL (operands[2]) > 16 3075 || GET_CODE (operands[0]) != MEM 3076 || GET_CODE (operands[1]) != REG 3077 || REGNO (operands[1]) >= 16) 3078 FAIL; 3079 3080 count = INTVAL (operands[2]); 3081 regno = REGNO (operands[1]); 3082 mode = GET_MODE (operands[1]); 3083 if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) 3084 FAIL; 3085 3086 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 3087 3088 if (!can_create_pseudo_p ()) 3089 { 3090 if (GET_CODE (XEXP (operands[0], 0)) == REG) 3091 { 3092 to = XEXP (operands[0], 0); 3093 off = 0; 3094 } 3095 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS 3096 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG 3097 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) 3098 { 3099 to = XEXP (XEXP (operands[0], 0), 0); 3100 off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 3101 } 3102 else 3103 FAIL; 3104 } 3105 else 3106 { 3107 to = force_reg (Pmode, XEXP (operands[0], 0)); 3108 off = 0; 3109 } 3110 3111 for (i = 0; i < count; i++) 3112 XVECEXP (operands[3], 0, i) 3113 = gen_rtx_SET (change_address (operands[0], mode, 3114 plus_constant (Pmode, to, 3115 off + i * GET_MODE_SIZE (mode))), 3116 gen_rtx_REG (mode, regno + i)); 3117 }) 3118 3119 (define_insn "*store_multiple_di" 3120 [(match_parallel 0 "store_multiple_operation" 3121 [(set (match_operand:DI 1 "s_operand" "=S") 3122 (match_operand:DI 2 "register_operand" "r"))])] 3123 "reload_completed && TARGET_ZARCH" 3124 { 3125 int words = XVECLEN (operands[0], 0); 3126 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); 3127 return "stmg\t%2,%0,%S1"; 3128 } 3129 [(set_attr "op_type" "RSY") 3130 (set_attr "type" "stm")]) 3131 3132 3133 (define_insn "*store_multiple_si" 3134 [(match_parallel 0 "store_multiple_operation" 3135 [(set (match_operand:SI 1 "s_operand" "=Q,S") 3136 (match_operand:SI 2 "register_operand" "r,r"))])] 3137 "reload_completed" 3138 { 3139 int words = XVECLEN (operands[0], 0); 3140 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); 3141 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; 3142 } 3143 [(set_attr "op_type" "RS,RSY") 3144 (set_attr "cpu_facility" "*,longdisp") 3145 (set_attr "type" "stm")]) 3146 3147 ;; 3148 ;; String instructions. 3149 ;; 3150 3151 (define_insn "*execute_rl" 3152 [(match_parallel 0 "execute_operation" 3153 [(unspec [(match_operand 1 "register_operand" "a") 3154 (match_operand 2 "" "") 3155 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] 3156 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT 3157 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" 3158 "exrl\t%1,%3" 3159 [(set_attr "op_type" "RIL") 3160 (set_attr "type" "cs") 3161 (set_attr "relative_long" "yes")]) 3162 3163 (define_insn "*execute" 3164 [(match_parallel 0 "execute_operation" 3165 [(unspec [(match_operand 1 "register_operand" "a") 3166 (match_operand:BLK 2 "memory_operand" "R") 3167 (match_operand 3 "" "")] UNSPEC_EXECUTE)])] 3168 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT 3169 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" 3170 "ex\t%1,%2" 3171 [(set_attr "op_type" "RX") 3172 (set_attr "type" "cs")]) 3173 3174 3175 ; 3176 ; strlenM instruction pattern(s). 3177 ; 3178 3179 (define_expand "strlen<mode>" 3180 [(match_operand:P 0 "register_operand" "") ; result 3181 (match_operand:BLK 1 "memory_operand" "") ; input string 3182 (match_operand:SI 2 "immediate_operand" "") ; search character 3183 (match_operand:SI 3 "immediate_operand" "")] ; known alignment 3184 "" 3185 { 3186 if (!TARGET_VX || operands[2] != const0_rtx) 3187 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], 3188 operands[2], operands[3])); 3189 else 3190 s390_expand_vec_strlen (operands[0], operands[1], operands[3]); 3191 3192 DONE; 3193 }) 3194 3195 (define_expand "strlen_srst<mode>" 3196 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) 3197 (parallel 3198 [(set (match_dup 4) 3199 (unspec:P [(const_int 0) 3200 (match_operand:BLK 1 "memory_operand" "") 3201 (reg:SI 0) 3202 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) 3203 (clobber (scratch:P)) 3204 (clobber (reg:CC CC_REGNUM))]) 3205 (parallel 3206 [(set (match_operand:P 0 "register_operand" "") 3207 (minus:P (match_dup 4) (match_dup 5))) 3208 (clobber (reg:CC CC_REGNUM))])] 3209 "" 3210 { 3211 operands[4] = gen_reg_rtx (Pmode); 3212 operands[5] = gen_reg_rtx (Pmode); 3213 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); 3214 operands[1] = replace_equiv_address (operands[1], operands[5]); 3215 }) 3216 3217 (define_insn "*strlen<mode>" 3218 [(set (match_operand:P 0 "register_operand" "=a") 3219 (unspec:P [(match_operand:P 2 "general_operand" "0") 3220 (mem:BLK (match_operand:P 3 "register_operand" "1")) 3221 (reg:SI 0) 3222 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) 3223 (clobber (match_scratch:P 1 "=a")) 3224 (clobber (reg:CC CC_REGNUM))] 3225 "" 3226 "srst\t%0,%1\;jo\t.-4" 3227 [(set_attr "length" "8") 3228 (set_attr "type" "vs")]) 3229 3230 ; 3231 ; cmpstrM instruction pattern(s). 3232 ; 3233 3234 (define_expand "cmpstrsi" 3235 [(set (reg:SI 0) (const_int 0)) 3236 (parallel 3237 [(clobber (match_operand 3 "" "")) 3238 (clobber (match_dup 4)) 3239 (set (reg:CCU CC_REGNUM) 3240 (compare:CCU (match_operand:BLK 1 "memory_operand" "") 3241 (match_operand:BLK 2 "memory_operand" ""))) 3242 (use (reg:SI 0))]) 3243 (parallel 3244 [(set (match_operand:SI 0 "register_operand" "=d") 3245 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) 3246 (clobber (reg:CC CC_REGNUM))])] 3247 "" 3248 { 3249 /* As the result of CMPINT is inverted compared to what we need, 3250 we have to swap the operands. */ 3251 rtx op1 = operands[2]; 3252 rtx op2 = operands[1]; 3253 rtx addr1 = gen_reg_rtx (Pmode); 3254 rtx addr2 = gen_reg_rtx (Pmode); 3255 3256 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); 3257 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); 3258 operands[1] = replace_equiv_address_nv (op1, addr1); 3259 operands[2] = replace_equiv_address_nv (op2, addr2); 3260 operands[3] = addr1; 3261 operands[4] = addr2; 3262 }) 3263 3264 (define_insn "*cmpstr<mode>" 3265 [(clobber (match_operand:P 0 "register_operand" "=d")) 3266 (clobber (match_operand:P 1 "register_operand" "=d")) 3267 (set (reg:CCU CC_REGNUM) 3268 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) 3269 (mem:BLK (match_operand:P 3 "register_operand" "1")))) 3270 (use (reg:SI 0))] 3271 "" 3272 "clst\t%0,%1\;jo\t.-4" 3273 [(set_attr "length" "8") 3274 (set_attr "type" "vs")]) 3275 3276 ; 3277 ; movstr instruction pattern. 3278 ; 3279 3280 (define_expand "movstr" 3281 [(match_operand 0 "register_operand" "") 3282 (match_operand 1 "memory_operand" "") 3283 (match_operand 2 "memory_operand" "")] 3284 "" 3285 { 3286 if (TARGET_64BIT) 3287 emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); 3288 else 3289 emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); 3290 DONE; 3291 }) 3292 3293 (define_expand "movstr<P:mode>" 3294 [(set (reg:SI 0) (const_int 0)) 3295 (parallel 3296 [(clobber (match_dup 3)) 3297 (set (match_operand:BLK 1 "memory_operand" "") 3298 (match_operand:BLK 2 "memory_operand" "")) 3299 (set (match_operand:P 0 "register_operand" "") 3300 (unspec:P [(match_dup 1) 3301 (match_dup 2) 3302 (reg:SI 0)] UNSPEC_MVST)) 3303 (clobber (reg:CC CC_REGNUM))])] 3304 "" 3305 { 3306 rtx addr1, addr2; 3307 3308 if (TARGET_VX && optimize_function_for_speed_p (cfun)) 3309 { 3310 s390_expand_vec_movstr (operands[0], operands[1], operands[2]); 3311 DONE; 3312 } 3313 3314 addr1 = gen_reg_rtx (Pmode); 3315 addr2 = gen_reg_rtx (Pmode); 3316 3317 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3318 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); 3319 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3320 operands[2] = replace_equiv_address_nv (operands[2], addr2); 3321 operands[3] = addr2; 3322 }) 3323 3324 (define_insn "*movstr" 3325 [(clobber (match_operand:P 2 "register_operand" "=d")) 3326 (set (mem:BLK (match_operand:P 1 "register_operand" "0")) 3327 (mem:BLK (match_operand:P 3 "register_operand" "2"))) 3328 (set (match_operand:P 0 "register_operand" "=d") 3329 (unspec:P [(mem:BLK (match_dup 1)) 3330 (mem:BLK (match_dup 3)) 3331 (reg:SI 0)] UNSPEC_MVST)) 3332 (clobber (reg:CC CC_REGNUM))] 3333 "" 3334 "mvst\t%1,%2\;jo\t.-4" 3335 [(set_attr "length" "8") 3336 (set_attr "type" "vs")]) 3337 3338 3339 ; 3340 ; cpymemM instruction pattern(s). 3341 ; 3342 3343 (define_expand "cpymem<mode>" 3344 [(set (match_operand:BLK 0 "memory_operand" "") ; destination 3345 (match_operand:BLK 1 "memory_operand" "")) ; source 3346 (use (match_operand:GPR 2 "general_operand" "")) ; count 3347 (match_operand 3 "" "")] 3348 "" 3349 { 3350 if (s390_expand_cpymem (operands[0], operands[1], operands[2])) 3351 DONE; 3352 else 3353 FAIL; 3354 }) 3355 3356 ; Move a block that is up to 256 bytes in length. 3357 ; The block length is taken as (operands[2] % 256) + 1. 3358 3359 (define_expand "cpymem_short" 3360 [(parallel 3361 [(set (match_operand:BLK 0 "memory_operand" "") 3362 (match_operand:BLK 1 "memory_operand" "")) 3363 (use (match_operand 2 "nonmemory_operand" "")) 3364 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3365 (clobber (match_dup 3))])] 3366 "" 3367 "operands[3] = gen_rtx_SCRATCH (Pmode);") 3368 3369 (define_insn "*cpymem_short" 3370 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") 3371 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) 3372 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) 3373 (use (match_operand 3 "immediate_operand" "X,R,X,X")) 3374 (clobber (match_scratch:P 4 "=X,X,X,&a"))] 3375 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" 3376 "#" 3377 [(set_attr "type" "cs") 3378 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3379 3380 (define_split 3381 [(set (match_operand:BLK 0 "memory_operand" "") 3382 (match_operand:BLK 1 "memory_operand" "")) 3383 (use (match_operand 2 "const_int_operand" "")) 3384 (use (match_operand 3 "immediate_operand" "")) 3385 (clobber (match_scratch 4))] 3386 "reload_completed" 3387 [(parallel 3388 [(set (match_dup 0) (match_dup 1)) 3389 (use (match_dup 2))])] 3390 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") 3391 3392 (define_split 3393 [(set (match_operand:BLK 0 "memory_operand" "") 3394 (match_operand:BLK 1 "memory_operand" "")) 3395 (use (match_operand 2 "register_operand" "")) 3396 (use (match_operand 3 "memory_operand" "")) 3397 (clobber (match_scratch 4))] 3398 "reload_completed" 3399 [(parallel 3400 [(unspec [(match_dup 2) (match_dup 3) 3401 (const_int 0)] UNSPEC_EXECUTE) 3402 (set (match_dup 0) (match_dup 1)) 3403 (use (const_int 1))])] 3404 "") 3405 3406 (define_split 3407 [(set (match_operand:BLK 0 "memory_operand" "") 3408 (match_operand:BLK 1 "memory_operand" "")) 3409 (use (match_operand 2 "register_operand" "")) 3410 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3411 (clobber (match_scratch 3))] 3412 "TARGET_Z10 && reload_completed" 3413 [(parallel 3414 [(unspec [(match_dup 2) (const_int 0) 3415 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3416 (set (match_dup 0) (match_dup 1)) 3417 (use (const_int 1))])] 3418 "operands[4] = gen_label_rtx ();") 3419 3420 (define_split 3421 [(set (match_operand:BLK 0 "memory_operand" "") 3422 (match_operand:BLK 1 "memory_operand" "")) 3423 (use (match_operand 2 "register_operand" "")) 3424 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3425 (clobber (match_operand 3 "register_operand" ""))] 3426 "reload_completed" 3427 [(set (match_dup 3) (label_ref (match_dup 4))) 3428 (parallel 3429 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 3430 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3431 (set (match_dup 0) (match_dup 1)) 3432 (use (const_int 1))])] 3433 "operands[4] = gen_label_rtx ();") 3434 3435 ; Move a block of arbitrary length. 3436 3437 (define_expand "cpymem_long" 3438 [(parallel 3439 [(clobber (match_dup 2)) 3440 (clobber (match_dup 3)) 3441 (set (match_operand:BLK 0 "memory_operand" "") 3442 (match_operand:BLK 1 "memory_operand" "")) 3443 (use (match_operand 2 "general_operand" "")) 3444 (use (match_dup 3)) 3445 (clobber (reg:CC CC_REGNUM))])] 3446 "" 3447 { 3448 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3449 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3450 rtx reg0 = gen_reg_rtx (dreg_mode); 3451 rtx reg1 = gen_reg_rtx (dreg_mode); 3452 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3453 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); 3454 rtx len0 = gen_lowpart (Pmode, reg0); 3455 rtx len1 = gen_lowpart (Pmode, reg1); 3456 3457 emit_clobber (reg0); 3458 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3459 emit_move_insn (len0, operands[2]); 3460 3461 emit_clobber (reg1); 3462 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3463 emit_move_insn (len1, operands[2]); 3464 3465 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3466 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3467 operands[2] = reg0; 3468 operands[3] = reg1; 3469 }) 3470 3471 (define_insn "*cpymem_long" 3472 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3473 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) 3474 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 3475 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) 3476 (use (match_dup 2)) 3477 (use (match_dup 3)) 3478 (clobber (reg:CC CC_REGNUM))] 3479 "TARGET_64BIT || !TARGET_ZARCH" 3480 "mvcle\t%0,%1,0\;jo\t.-4" 3481 [(set_attr "length" "8") 3482 (set_attr "type" "vs")]) 3483 3484 (define_insn "*cpymem_long_31z" 3485 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3486 (clobber (match_operand:TI 1 "register_operand" "=d")) 3487 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) 3488 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) 3489 (use (match_dup 2)) 3490 (use (match_dup 3)) 3491 (clobber (reg:CC CC_REGNUM))] 3492 "!TARGET_64BIT && TARGET_ZARCH" 3493 "mvcle\t%0,%1,0\;jo\t.-4" 3494 [(set_attr "length" "8") 3495 (set_attr "type" "vs")]) 3496 3497 3498 ; 3499 ; Test data class. 3500 ; 3501 3502 (define_expand "signbit<mode>2<tf_fpr>" 3503 [(set (reg:CCZ CC_REGNUM) 3504 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") 3505 (match_dup 2)] 3506 UNSPEC_TDC_INSN)) 3507 (set (match_operand:SI 0 "register_operand" "=d") 3508 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] 3509 "TARGET_HARD_FLOAT" 3510 { 3511 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); 3512 }) 3513 3514 (define_expand "isinf<mode>2<tf_fpr>" 3515 [(set (reg:CCZ CC_REGNUM) 3516 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") 3517 (match_dup 2)] 3518 UNSPEC_TDC_INSN)) 3519 (set (match_operand:SI 0 "register_operand" "=d") 3520 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] 3521 "TARGET_HARD_FLOAT" 3522 { 3523 operands[2] = GEN_INT (S390_TDC_INFINITY); 3524 }) 3525 3526 ; This extracts CC into a GPR properly shifted. The actual IPM 3527 ; instruction will be issued by reload. The constraint of operand 1 3528 ; forces reload to use a GPR. So reload will issue a movcc insn for 3529 ; copying CC into a GPR first. 3530 (define_insn_and_split "*cc_to_int" 3531 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3532 (unspec:SI [(match_operand 1 "register_operand" "0")] 3533 UNSPEC_CC_TO_INT))] 3534 "" 3535 "#" 3536 "reload_completed" 3537 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) 3538 3539 ; This insn is used to generate all variants of the Test Data Class 3540 ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand 3541 ; is the register to be tested and the second one is the bit mask 3542 ; specifying the required test(s). 3543 ; 3544 ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet 3545 (define_insn "*TDC_insn_<mode>" 3546 [(set (reg:CCZ CC_REGNUM) 3547 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") 3548 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] 3549 "TARGET_HARD_FLOAT" 3550 "t<_d>c<xde><bt>\t%0,%1" 3551 [(set_attr "op_type" "RXE") 3552 (set_attr "type" "fsimp<type>")]) 3553 3554 3555 3556 ; 3557 ; setmemM instruction pattern(s). 3558 ; 3559 3560 (define_expand "setmem<mode>" 3561 [(set (match_operand:BLK 0 "memory_operand" "") 3562 (match_operand:QI 2 "general_operand" "")) 3563 (use (match_operand:GPR 1 "general_operand" "")) 3564 (match_operand 3 "" "")] 3565 "" 3566 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") 3567 3568 ; Clear a block that is up to 256 bytes in length. 3569 ; The block length is taken as (operands[1] % 256) + 1. 3570 3571 (define_expand "clrmem_short" 3572 [(parallel 3573 [(set (match_operand:BLK 0 "memory_operand" "") 3574 (const_int 0)) 3575 (use (match_operand 1 "nonmemory_operand" "")) 3576 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3577 (clobber (match_dup 2)) 3578 (clobber (reg:CC CC_REGNUM))])] 3579 "" 3580 "operands[2] = gen_rtx_SCRATCH (Pmode);") 3581 3582 (define_insn "*clrmem_short" 3583 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") 3584 (const_int 0)) 3585 (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) 3586 (use (match_operand 2 "immediate_operand" "X,R,X,X")) 3587 (clobber (match_scratch:P 3 "=X,X,X,&a")) 3588 (clobber (reg:CC CC_REGNUM))] 3589 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" 3590 "#" 3591 [(set_attr "type" "cs") 3592 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3593 3594 (define_split 3595 [(set (match_operand:BLK 0 "memory_operand" "") 3596 (const_int 0)) 3597 (use (match_operand 1 "const_int_operand" "")) 3598 (use (match_operand 2 "immediate_operand" "")) 3599 (clobber (match_scratch 3)) 3600 (clobber (reg:CC CC_REGNUM))] 3601 "reload_completed" 3602 [(parallel 3603 [(set (match_dup 0) (const_int 0)) 3604 (use (match_dup 1)) 3605 (clobber (reg:CC CC_REGNUM))])] 3606 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") 3607 3608 (define_split 3609 [(set (match_operand:BLK 0 "memory_operand" "") 3610 (const_int 0)) 3611 (use (match_operand 1 "register_operand" "")) 3612 (use (match_operand 2 "memory_operand" "")) 3613 (clobber (match_scratch 3)) 3614 (clobber (reg:CC CC_REGNUM))] 3615 "reload_completed" 3616 [(parallel 3617 [(unspec [(match_dup 1) (match_dup 2) 3618 (const_int 0)] UNSPEC_EXECUTE) 3619 (set (match_dup 0) (const_int 0)) 3620 (use (const_int 1)) 3621 (clobber (reg:CC CC_REGNUM))])] 3622 "") 3623 3624 (define_split 3625 [(set (match_operand:BLK 0 "memory_operand" "") 3626 (const_int 0)) 3627 (use (match_operand 1 "register_operand" "")) 3628 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3629 (clobber (match_scratch 2)) 3630 (clobber (reg:CC CC_REGNUM))] 3631 "TARGET_Z10 && reload_completed" 3632 [(parallel 3633 [(unspec [(match_dup 1) (const_int 0) 3634 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3635 (set (match_dup 0) (const_int 0)) 3636 (use (const_int 1)) 3637 (clobber (reg:CC CC_REGNUM))])] 3638 "operands[3] = gen_label_rtx ();") 3639 3640 (define_split 3641 [(set (match_operand:BLK 0 "memory_operand" "") 3642 (const_int 0)) 3643 (use (match_operand 1 "register_operand" "")) 3644 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3645 (clobber (match_operand 2 "register_operand" "")) 3646 (clobber (reg:CC CC_REGNUM))] 3647 "reload_completed" 3648 [(set (match_dup 2) (label_ref (match_dup 3))) 3649 (parallel 3650 [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) 3651 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3652 (set (match_dup 0) (const_int 0)) 3653 (use (const_int 1)) 3654 (clobber (reg:CC CC_REGNUM))])] 3655 "operands[3] = gen_label_rtx ();") 3656 3657 ; Initialize a block of arbitrary length with (operands[2] % 256). 3658 3659 (define_expand "setmem_long_<P:mode>" 3660 [(parallel 3661 [(clobber (match_dup 1)) 3662 (set (match_operand:BLK 0 "memory_operand" "") 3663 (unspec:BLK [(match_operand:P 2 "setmem_operand" "") 3664 (match_dup 4)] UNSPEC_REPLICATE_BYTE)) 3665 (use (match_dup 3)) 3666 (clobber (reg:CC CC_REGNUM))])] 3667 "" 3668 { 3669 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3670 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3671 rtx reg0 = gen_reg_rtx (dreg_mode); 3672 rtx reg1 = gen_reg_rtx (dreg_mode); 3673 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3674 rtx len0 = gen_lowpart (Pmode, reg0); 3675 3676 emit_clobber (reg0); 3677 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3678 emit_move_insn (len0, operands[1]); 3679 3680 emit_move_insn (reg1, const0_rtx); 3681 3682 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3683 operands[1] = reg0; 3684 operands[3] = reg1; 3685 operands[4] = gen_lowpart (Pmode, operands[1]); 3686 }) 3687 3688 ; Patterns for 31 bit + Esa and 64 bit + Zarch. 3689 3690 (define_insn "*setmem_long" 3691 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3692 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) 3693 (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") 3694 (subreg:P (match_dup 3) <modesize>)] 3695 UNSPEC_REPLICATE_BYTE)) 3696 (use (match_operand:<DBL> 1 "register_operand" "d")) 3697 (clobber (reg:CC CC_REGNUM))] 3698 "TARGET_64BIT || !TARGET_ZARCH" 3699 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3700 [(set_attr "length" "8") 3701 (set_attr "type" "vs")]) 3702 3703 (define_insn "*setmem_long_and" 3704 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3705 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) 3706 (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) 3707 (subreg:P (match_dup 3) <modesize>)] 3708 UNSPEC_REPLICATE_BYTE)) 3709 (use (match_operand:<DBL> 1 "register_operand" "d")) 3710 (clobber (reg:CC CC_REGNUM))] 3711 "(TARGET_64BIT || !TARGET_ZARCH)" 3712 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3713 [(set_attr "length" "8") 3714 (set_attr "type" "vs")]) 3715 3716 ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets 3717 ; of the SImode subregs. 3718 3719 (define_insn "*setmem_long_31z" 3720 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3721 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) 3722 (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") 3723 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) 3724 (use (match_operand:TI 1 "register_operand" "d")) 3725 (clobber (reg:CC CC_REGNUM))] 3726 "!TARGET_64BIT && TARGET_ZARCH" 3727 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3728 [(set_attr "length" "8") 3729 (set_attr "type" "vs")]) 3730 3731 (define_insn "*setmem_long_and_31z" 3732 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3733 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) 3734 (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) 3735 (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) 3736 (use (match_operand:TI 1 "register_operand" "d")) 3737 (clobber (reg:CC CC_REGNUM))] 3738 "(!TARGET_64BIT && TARGET_ZARCH)" 3739 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3740 [(set_attr "length" "8") 3741 (set_attr "type" "vs")]) 3742 3743 ; 3744 ; cmpmemM instruction pattern(s). 3745 ; 3746 3747 (define_expand "cmpmemsi" 3748 [(set (match_operand:SI 0 "register_operand" "") 3749 (compare:SI (match_operand:BLK 1 "memory_operand" "") 3750 (match_operand:BLK 2 "memory_operand" "") ) ) 3751 (use (match_operand:SI 3 "general_operand" "")) 3752 (use (match_operand:SI 4 "" ""))] 3753 "" 3754 { 3755 if (s390_expand_cmpmem (operands[0], operands[1], 3756 operands[2], operands[3])) 3757 DONE; 3758 else 3759 FAIL; 3760 }) 3761 3762 ; Compare a block that is up to 256 bytes in length. 3763 ; The block length is taken as (operands[2] % 256) + 1. 3764 3765 (define_expand "cmpmem_short" 3766 [(parallel 3767 [(set (reg:CCU CC_REGNUM) 3768 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3769 (match_operand:BLK 1 "memory_operand" ""))) 3770 (use (match_operand 2 "nonmemory_operand" "")) 3771 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3772 (clobber (match_dup 3))])] 3773 "" 3774 "operands[3] = gen_rtx_SCRATCH (Pmode);") 3775 3776 (define_insn "*cmpmem_short" 3777 [(set (reg:CCU CC_REGNUM) 3778 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") 3779 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) 3780 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) 3781 (use (match_operand 3 "immediate_operand" "X,R,X,X")) 3782 (clobber (match_scratch:P 4 "=X,X,X,&a"))] 3783 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" 3784 "#" 3785 [(set_attr "type" "cs") 3786 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3787 3788 (define_split 3789 [(set (reg:CCU CC_REGNUM) 3790 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3791 (match_operand:BLK 1 "memory_operand" ""))) 3792 (use (match_operand 2 "const_int_operand" "")) 3793 (use (match_operand 3 "immediate_operand" "")) 3794 (clobber (match_scratch 4))] 3795 "reload_completed" 3796 [(parallel 3797 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3798 (use (match_dup 2))])] 3799 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") 3800 3801 (define_split 3802 [(set (reg:CCU CC_REGNUM) 3803 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3804 (match_operand:BLK 1 "memory_operand" ""))) 3805 (use (match_operand 2 "register_operand" "")) 3806 (use (match_operand 3 "memory_operand" "")) 3807 (clobber (match_scratch 4))] 3808 "reload_completed" 3809 [(parallel 3810 [(unspec [(match_dup 2) (match_dup 3) 3811 (const_int 0)] UNSPEC_EXECUTE) 3812 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3813 (use (const_int 1))])] 3814 "") 3815 3816 (define_split 3817 [(set (reg:CCU CC_REGNUM) 3818 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3819 (match_operand:BLK 1 "memory_operand" ""))) 3820 (use (match_operand 2 "register_operand" "")) 3821 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3822 (clobber (match_scratch 3))] 3823 "TARGET_Z10 && reload_completed" 3824 [(parallel 3825 [(unspec [(match_dup 2) (const_int 0) 3826 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3827 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3828 (use (const_int 1))])] 3829 "operands[4] = gen_label_rtx ();") 3830 3831 (define_split 3832 [(set (reg:CCU CC_REGNUM) 3833 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3834 (match_operand:BLK 1 "memory_operand" ""))) 3835 (use (match_operand 2 "register_operand" "")) 3836 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3837 (clobber (match_operand 3 "register_operand" ""))] 3838 "reload_completed" 3839 [(set (match_dup 3) (label_ref (match_dup 4))) 3840 (parallel 3841 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 3842 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3843 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3844 (use (const_int 1))])] 3845 "operands[4] = gen_label_rtx ();") 3846 3847 ; Compare a block of arbitrary length. 3848 3849 (define_expand "cmpmem_long" 3850 [(parallel 3851 [(clobber (match_dup 2)) 3852 (clobber (match_dup 3)) 3853 (set (reg:CCU CC_REGNUM) 3854 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3855 (match_operand:BLK 1 "memory_operand" ""))) 3856 (use (match_operand 2 "general_operand" "")) 3857 (use (match_dup 3))])] 3858 "" 3859 { 3860 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3861 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3862 rtx reg0 = gen_reg_rtx (dreg_mode); 3863 rtx reg1 = gen_reg_rtx (dreg_mode); 3864 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3865 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); 3866 rtx len0 = gen_lowpart (Pmode, reg0); 3867 rtx len1 = gen_lowpart (Pmode, reg1); 3868 3869 emit_clobber (reg0); 3870 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3871 emit_move_insn (len0, operands[2]); 3872 3873 emit_clobber (reg1); 3874 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3875 emit_move_insn (len1, operands[2]); 3876 3877 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3878 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3879 operands[2] = reg0; 3880 operands[3] = reg1; 3881 }) 3882 3883 (define_insn "*cmpmem_long" 3884 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3885 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) 3886 (set (reg:CCU CC_REGNUM) 3887 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 3888 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) 3889 (use (match_dup 2)) 3890 (use (match_dup 3))] 3891 "TARGET_64BIT || !TARGET_ZARCH" 3892 "clcle\t%0,%1,0\;jo\t.-4" 3893 [(set_attr "length" "8") 3894 (set_attr "type" "vs")]) 3895 3896 (define_insn "*cmpmem_long_31z" 3897 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3898 (clobber (match_operand:TI 1 "register_operand" "=d")) 3899 (set (reg:CCU CC_REGNUM) 3900 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) 3901 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) 3902 (use (match_dup 2)) 3903 (use (match_dup 3))] 3904 "!TARGET_64BIT && TARGET_ZARCH" 3905 "clcle\t%0,%1,0\;jo\t.-4" 3906 [(set_attr "op_type" "NN") 3907 (set_attr "type" "vs") 3908 (set_attr "length" "8")]) 3909 3910 ; Convert CCUmode condition code to integer. 3911 ; Result is zero if EQ, positive if LTU, negative if GTU. 3912 3913 (define_insn_and_split "cmpint" 3914 [(set (match_operand:SI 0 "register_operand" "=d") 3915 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3916 UNSPEC_STRCMPCC_TO_INT)) 3917 (clobber (reg:CC CC_REGNUM))] 3918 "" 3919 "#" 3920 "reload_completed" 3921 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) 3922 (parallel 3923 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) 3924 (clobber (reg:CC CC_REGNUM))])]) 3925 3926 (define_insn_and_split "*cmpint_cc" 3927 [(set (reg CC_REGNUM) 3928 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3929 UNSPEC_STRCMPCC_TO_INT) 3930 (const_int 0))) 3931 (set (match_operand:SI 0 "register_operand" "=d") 3932 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] 3933 "s390_match_ccmode (insn, CCSmode)" 3934 "#" 3935 "&& reload_completed" 3936 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) 3937 (parallel 3938 [(set (match_dup 2) (match_dup 3)) 3939 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] 3940 { 3941 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); 3942 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); 3943 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); 3944 }) 3945 3946 (define_insn_and_split "*cmpint_sign" 3947 [(set (match_operand:DI 0 "register_operand" "=d") 3948 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3949 UNSPEC_STRCMPCC_TO_INT))) 3950 (clobber (reg:CC CC_REGNUM))] 3951 "TARGET_ZARCH" 3952 "#" 3953 "&& reload_completed" 3954 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3955 (parallel 3956 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) 3957 (clobber (reg:CC CC_REGNUM))])]) 3958 3959 (define_insn_and_split "*cmpint_sign_cc" 3960 [(set (reg CC_REGNUM) 3961 (compare (ashiftrt:DI (ashift:DI (subreg:DI 3962 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3963 UNSPEC_STRCMPCC_TO_INT) 0) 3964 (const_int 32)) (const_int 32)) 3965 (const_int 0))) 3966 (set (match_operand:DI 0 "register_operand" "=d") 3967 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] 3968 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" 3969 "#" 3970 "&& reload_completed" 3971 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3972 (parallel 3973 [(set (match_dup 2) (match_dup 3)) 3974 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] 3975 { 3976 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); 3977 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); 3978 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); 3979 }) 3980 3981 3982 ;; 3983 ;;- Conversion instructions. 3984 ;; 3985 3986 (define_insn "*sethighpartsi" 3987 [(set (match_operand:SI 0 "register_operand" "=d,d") 3988 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") 3989 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) 3990 (clobber (reg:CC CC_REGNUM))] 3991 "" 3992 "@ 3993 icm\t%0,%2,%S1 3994 icmy\t%0,%2,%S1" 3995 [(set_attr "op_type" "RS,RSY") 3996 (set_attr "cpu_facility" "*,longdisp") 3997 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 3998 3999 (define_insn "*sethighpartdi_64" 4000 [(set (match_operand:DI 0 "register_operand" "=d") 4001 (unspec:DI [(match_operand:BLK 1 "s_operand" "S") 4002 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) 4003 (clobber (reg:CC CC_REGNUM))] 4004 "TARGET_ZARCH" 4005 "icmh\t%0,%2,%S1" 4006 [(set_attr "op_type" "RSY") 4007 (set_attr "z10prop" "z10_super")]) 4008 4009 (define_insn "*sethighpartdi_31" 4010 [(set (match_operand:DI 0 "register_operand" "=d,d") 4011 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") 4012 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) 4013 (clobber (reg:CC CC_REGNUM))] 4014 "!TARGET_ZARCH" 4015 "@ 4016 icm\t%0,%2,%S1 4017 icmy\t%0,%2,%S1" 4018 [(set_attr "op_type" "RS,RSY") 4019 (set_attr "cpu_facility" "*,longdisp") 4020 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4021 4022 ; 4023 ; extv instruction patterns 4024 ; 4025 4026 ; FIXME: This expander needs to be converted from DI to GPR as well 4027 ; after resolving some issues with it. 4028 4029 (define_expand "extzv" 4030 [(parallel 4031 [(set (match_operand:DI 0 "register_operand" "=d") 4032 (zero_extract:DI 4033 (match_operand:DI 1 "register_operand" "d") 4034 (match_operand 2 "const_int_operand" "") ; size 4035 (match_operand 3 "const_int_operand" ""))) ; start 4036 (clobber (reg:CC CC_REGNUM))])] 4037 "TARGET_Z10" 4038 { 4039 if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) 4040 FAIL; 4041 /* Starting with zEC12 there is risbgn not clobbering CC. */ 4042 if (TARGET_ZEC12) 4043 { 4044 emit_move_insn (operands[0], 4045 gen_rtx_ZERO_EXTRACT (DImode, 4046 operands[1], 4047 operands[2], 4048 operands[3])); 4049 DONE; 4050 } 4051 }) 4052 4053 (define_insn "*extzv<mode><clobbercc_or_nocc>" 4054 [(set (match_operand:GPR 0 "register_operand" "=d") 4055 (zero_extract:GPR 4056 (match_operand:GPR 1 "register_operand" "d") 4057 (match_operand 2 "const_int_operand" "") ; size 4058 (match_operand 3 "const_int_operand" ""))) ; start 4059 ] 4060 "<z10_or_zEC12_cond> 4061 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 4062 GET_MODE_BITSIZE (<MODE>mode))" 4063 "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift 4064 [(set_attr "op_type" "RIE") 4065 (set_attr "z10prop" "z10_super_E1")]) 4066 4067 ; 64 bit: (a & -16) | ((b >> 8) & 15) 4068 (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" 4069 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 4070 (match_operand 1 "const_int_operand" "") ; size 4071 (match_operand 2 "const_int_operand" "")) ; start 4072 (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") 4073 (match_operand:DI 4 "nonzero_shift_count_operand" "")))] 4074 "<z10_or_zEC12_cond> 4075 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) 4076 && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" 4077 "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" 4078 [(set_attr "op_type" "RIE") 4079 (set_attr "z10prop" "z10_super_E1")]) 4080 4081 ; (a & -16) | ((b >> 8) & 15) 4082 (define_insn "*<risbg_n>_ior_and_sr_ze<mode>" 4083 [(set (match_operand:DSI 0 "register_operand" "=d") 4084 (ior:DSI (and:DSI 4085 (match_operand:DSI 1 "register_operand" "0") 4086 (match_operand:DSI 2 "const_int_operand" "")) 4087 (zero_extract:DSI 4088 (match_operand:DSI 3 "register_operand" "d") 4089 (match_operand 4 "const_int_operand" "") ; size 4090 (match_operand 5 "const_int_operand" "")) ; start 4091 ))] 4092 "<z10_or_zEC12_cond> 4093 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), <DSI:bitsize>) 4094 && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << UINTVAL (operands[4]))" 4095 "<risbg_n>\t%0,%3,64-%4,63,(64-<DSI:bitsize>)+%4+%5" 4096 [(set_attr "op_type" "RIE") 4097 (set_attr "z10prop" "z10_super_E1")]) 4098 4099 ; ((int)foo >> 10) & 1; 4100 (define_insn "*extract1bitdi<clobbercc_or_nocc>" 4101 [(set (match_operand:DI 0 "register_operand" "=d") 4102 (ne:DI (zero_extract:DI 4103 (match_operand:DI 1 "register_operand" "d") 4104 (const_int 1) ; size 4105 (match_operand 2 "const_int_operand" "")) ; start 4106 (const_int 0)))] 4107 "<z10_or_zEC12_cond> 4108 && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" 4109 "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift 4110 [(set_attr "op_type" "RIE") 4111 (set_attr "z10prop" "z10_super_E1")]) 4112 4113 (define_insn "*<risbg_n>_and_subregdi_rotr" 4114 [(set (match_operand:DI 0 "register_operand" "=d") 4115 (and:DI (subreg:DI 4116 (rotate:SINT (match_operand:SINT 1 "register_operand" "d") 4117 (match_operand:SINT 2 "const_int_operand" "")) 0) 4118 (match_operand:DI 3 "contiguous_bitmask_operand" "")))] 4119 "<z10_or_zEC12_cond> 4120 && (UINTVAL (operands[3]) 4121 < (HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)))" 4122 "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift 4123 [(set_attr "op_type" "RIE") 4124 (set_attr "z10prop" "z10_super_E1")]) 4125 4126 (define_insn "*<risbg_n>_and_subregdi_rotl" 4127 [(set (match_operand:DI 0 "register_operand" "=d") 4128 (and:DI (subreg:DI 4129 (rotate:SINT (match_operand:SINT 1 "register_operand" "d") 4130 (match_operand:SINT 2 "const_int_operand" "")) 0) 4131 (match_operand:DI 3 "contiguous_bitmask_operand" "")))] 4132 "<z10_or_zEC12_cond> 4133 && !(UINTVAL (operands[3]) 4134 & ((HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)) - 1))" 4135 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift 4136 [(set_attr "op_type" "RIE") 4137 (set_attr "z10prop" "z10_super_E1")]) 4138 4139 (define_insn "*<risbg_n>_di_and_rot" 4140 [(set (match_operand:DI 0 "register_operand" "=d") 4141 (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") 4142 (match_operand:DI 2 "const_int_operand" "")) 4143 (match_operand:DI 3 "contiguous_bitmask_operand" "")))] 4144 "<z10_or_zEC12_cond>" 4145 "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift 4146 [(set_attr "op_type" "RIE") 4147 (set_attr "z10prop" "z10_super_E1")]) 4148 4149 (define_insn_and_split "*pre_z10_extzv<mode>" 4150 [(set (match_operand:GPR 0 "register_operand" "=d") 4151 (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") 4152 (match_operand 2 "nonzero_shift_count_operand" "") 4153 (const_int 0))) 4154 (clobber (reg:CC CC_REGNUM))] 4155 "!TARGET_Z10" 4156 "#" 4157 "&& reload_completed" 4158 [(parallel 4159 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) 4160 (clobber (reg:CC CC_REGNUM))]) 4161 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] 4162 { 4163 int bitsize = INTVAL (operands[2]); 4164 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ 4165 unsigned HOST_WIDE_INT mask 4166 = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); 4167 4168 operands[1] = adjust_address (operands[1], BLKmode, 0); 4169 set_mem_size (operands[1], size); 4170 operands[2] = GEN_INT (<GPR:bitsize> - bitsize); 4171 operands[3] = GEN_INT (mask); 4172 }) 4173 4174 (define_insn_and_split "*pre_z10_extv<mode>" 4175 [(set (match_operand:GPR 0 "register_operand" "=d") 4176 (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") 4177 (match_operand 2 "nonzero_shift_count_operand" "") 4178 (const_int 0))) 4179 (clobber (reg:CC CC_REGNUM))] 4180 "" 4181 "#" 4182 "&& reload_completed" 4183 [(parallel 4184 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) 4185 (clobber (reg:CC CC_REGNUM))]) 4186 (parallel 4187 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) 4188 (clobber (reg:CC CC_REGNUM))])] 4189 { 4190 int bitsize = INTVAL (operands[2]); 4191 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ 4192 unsigned HOST_WIDE_INT mask 4193 = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); 4194 4195 operands[1] = adjust_address (operands[1], BLKmode, 0); 4196 set_mem_size (operands[1], size); 4197 operands[2] = GEN_INT (<GPR:bitsize> - bitsize); 4198 operands[3] = GEN_INT (mask); 4199 }) 4200 4201 ; 4202 ; insv instruction patterns 4203 ; 4204 4205 (define_expand "insv" 4206 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") 4207 (match_operand 1 "const_int_operand" "") 4208 (match_operand 2 "const_int_operand" "")) 4209 (match_operand 3 "general_operand" ""))] 4210 "" 4211 { 4212 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) 4213 DONE; 4214 FAIL; 4215 }) 4216 4217 4218 ; The normal RTL expansion will never generate a zero_extract where 4219 ; the location operand isn't word mode. However, we do this in the 4220 ; back-end when generating atomic operations. See s390_two_part_insv. 4221 (define_insn "*insv<mode><clobbercc_or_nocc>" 4222 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") 4223 (match_operand 1 "const_int_operand" "I") ; size 4224 (match_operand 2 "const_int_operand" "I")) ; pos 4225 (match_operand:GPR 3 "nonimmediate_operand" "d"))] 4226 "<z10_or_zEC12_cond> 4227 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 4228 GET_MODE_BITSIZE (<MODE>mode)) 4229 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" 4230 "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" 4231 [(set_attr "op_type" "RIE") 4232 (set_attr "z10prop" "z10_super_E1")]) 4233 4234 ; and op1 with a mask being 1 for the selected bits and 0 for the rest 4235 ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest 4236 (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" 4237 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") 4238 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") 4239 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 4240 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") 4241 (match_operand:GPR 4 "const_int_operand" ""))))] 4242 "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" 4243 "@ 4244 <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 4245 <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" 4246 [(set_attr "op_type" "RIE") 4247 (set_attr "z10prop" "z10_super_E1")]) 4248 4249 (define_insn "*insv_z10_noshift_cc" 4250 [(set (reg CC_REGNUM) 4251 (compare 4252 (ior:DI 4253 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") 4254 (match_operand:DI 2 "contiguous_bitmask_operand" "")) 4255 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") 4256 (match_operand:DI 4 "const_int_operand" ""))) 4257 (const_int 0))) 4258 (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") 4259 (ior:DI (and:DI (match_dup 1) (match_dup 2)) 4260 (and:DI (match_dup 3) (match_dup 4))))] 4261 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) 4262 && INTVAL (operands[2]) == ~INTVAL (operands[4])" 4263 "@ 4264 risbg\t%0,%1,%s2,%e2,0 4265 risbg\t%0,%3,%s4,%e4,0" 4266 [(set_attr "op_type" "RIE") 4267 (set_attr "z10prop" "z10_super_E1")]) 4268 4269 (define_insn "*insv_z10_noshift_cconly" 4270 [(set 4271 (reg CC_REGNUM) 4272 (compare 4273 (ior:DI 4274 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") 4275 (match_operand:DI 2 "contiguous_bitmask_operand" "")) 4276 (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") 4277 (match_operand:DI 4 "const_int_operand" ""))) 4278 (const_int 0))) 4279 (clobber (match_scratch:DI 0 "=d,d"))] 4280 "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) 4281 && INTVAL (operands[2]) == ~INTVAL (operands[4])" 4282 "@ 4283 risbg\t%0,%1,%s2,%e2,0 4284 risbg\t%0,%3,%s4,%e4,0" 4285 [(set_attr "op_type" "RIE") 4286 (set_attr "z10prop" "z10_super_E1")]) 4287 4288 ; Implement appending Y on the left of S bits of X 4289 ; x = (y << s) | (x & ((1 << s) - 1)) 4290 (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" 4291 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4292 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") 4293 (match_operand:GPR 2 "immediate_operand" "")) 4294 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") 4295 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] 4296 "<z10_or_zEC12_cond> 4297 && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1" 4298 "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" 4299 [(set_attr "op_type" "RIE") 4300 (set_attr "z10prop" "z10_super_E1")]) 4301 4302 ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) 4303 (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" 4304 [(set (match_operand:GPR 0 "register_operand" "=d") 4305 (ior:GPR (and:GPR 4306 (match_operand:GPR 1 "register_operand" "0") 4307 (match_operand:GPR 2 "const_int_operand" "")) 4308 (lshiftrt:GPR 4309 (match_operand:GPR 3 "register_operand" "d") 4310 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] 4311 "<z10_or_zEC12_cond> && UINTVAL (operands[2]) 4312 == (HOST_WIDE_INT_M1U 4313 << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" 4314 "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" 4315 [(set_attr "op_type" "RIE") 4316 (set_attr "z10prop" "z10_super_E1")]) 4317 4318 ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); 4319 (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" 4320 [(set (match_operand:SI 0 "register_operand" "=d") 4321 (ior:SI (and:SI 4322 (match_operand:SI 1 "register_operand" "0") 4323 (match_operand:SI 2 "const_int_operand" "")) 4324 (subreg:SI 4325 (lshiftrt:DI 4326 (match_operand:DI 3 "register_operand" "d") 4327 (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] 4328 "<z10_or_zEC12_cond> 4329 && UINTVAL (operands[2]) == ~(HOST_WIDE_INT_M1U >> UINTVAL (operands[4]))" 4330 "<risbg_n>\t%0,%3,%4,63,64-%4" 4331 [(set_attr "op_type" "RIE") 4332 (set_attr "z10prop" "z10_super_E1")]) 4333 4334 ; (ui32)(((ui64)x) >> 12) & -4 4335 (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" 4336 [(set (match_operand:SI 0 "register_operand" "=d") 4337 (and:SI 4338 (subreg:SI (lshiftrt:DI 4339 (match_operand:DI 1 "register_operand" "d") 4340 (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) 4341 (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] 4342 "<z10_or_zEC12_cond>" 4343 "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" 4344 [(set_attr "op_type" "RIE") 4345 (set_attr "z10prop" "z10_super_E1")]) 4346 4347 ; (ui32)(((ui64)x) >> 12) & -4 4348 (define_insn "*trunc_sidi_and_subreg_ze<clobbercc_or_nocc>" 4349 [(set (match_operand:SI 0 "register_operand" "=d") 4350 (and:SI 4351 (subreg:SI (zero_extract:DI 4352 (match_operand:DI 1 "register_operand" "d") 4353 (const_int 32) 4354 (match_operand:SI 2 "nonzero_shift_count_operand" "")) 4) 4355 (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] 4356 "<z10_or_zEC12_cond>" 4357 "<risbg_n>\t%0,%1,%t3,128+%f3,32+%2" 4358 [(set_attr "op_type" "RIE") 4359 (set_attr "z10prop" "z10_super_E1")]) 4360 4361 ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting 4362 ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) 4363 ; -> z = y >> d; z = risbg; 4364 4365 (define_split 4366 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 4367 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") 4368 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4369 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") 4370 (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] 4371 "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" 4372 [(set (match_dup 6) 4373 (lshiftrt:GPR (match_dup 1) (match_dup 2))) 4374 (set (match_dup 0) 4375 (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) 4376 (ashift:GPR (match_dup 3) (match_dup 4))))] 4377 { 4378 operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); 4379 if (reg_overlap_mentioned_p (operands[0], operands[3])) 4380 { 4381 if (!can_create_pseudo_p ()) 4382 FAIL; 4383 operands[6] = gen_reg_rtx (<MODE>mode); 4384 } 4385 else 4386 operands[6] = operands[0]; 4387 }) 4388 4389 (define_split 4390 [(parallel 4391 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 4392 (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") 4393 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4394 (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") 4395 (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) 4396 (clobber (reg:CC CC_REGNUM))])] 4397 "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" 4398 [(set (match_dup 6) 4399 (lshiftrt:GPR (match_dup 1) (match_dup 2))) 4400 (parallel 4401 [(set (match_dup 0) 4402 (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) 4403 (ashift:GPR (match_dup 3) (match_dup 4)))) 4404 (clobber (reg:CC CC_REGNUM))])] 4405 { 4406 operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); 4407 if (reg_overlap_mentioned_p (operands[0], operands[3])) 4408 { 4409 if (!can_create_pseudo_p ()) 4410 FAIL; 4411 operands[6] = gen_reg_rtx (<MODE>mode); 4412 } 4413 else 4414 operands[6] = operands[0]; 4415 }) 4416 4417 ; rosbg, rxsbg 4418 (define_insn "*r<noxa>sbg_<mode>_noshift" 4419 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4420 (IXOR:GPR 4421 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") 4422 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 4423 (match_operand:GPR 3 "nonimmediate_operand" "0"))) 4424 (clobber (reg:CC CC_REGNUM))] 4425 "TARGET_Z10" 4426 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" 4427 [(set_attr "op_type" "RIE")]) 4428 4429 ; rosbg, rxsbg 4430 (define_insn "*r<noxa>sbg_di_rotl" 4431 [(set (match_operand:DI 0 "nonimmediate_operand" "=d") 4432 (IXOR:DI 4433 (and:DI 4434 (rotate:DI 4435 (match_operand:DI 1 "nonimmediate_operand" "d") 4436 (match_operand:DI 3 "const_int_operand" "")) 4437 (match_operand:DI 2 "contiguous_bitmask_operand" "")) 4438 (match_operand:DI 4 "nonimmediate_operand" "0"))) 4439 (clobber (reg:CC CC_REGNUM))] 4440 "TARGET_Z10" 4441 "r<noxa>sbg\t%0,%1,%s2,%e2,%b3" 4442 [(set_attr "op_type" "RIE")]) 4443 4444 ; rosbg, rxsbg 4445 (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" 4446 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4447 (IXOR:GPR 4448 (and:GPR 4449 (lshiftrt:GPR 4450 (match_operand:GPR 1 "nonimmediate_operand" "d") 4451 (match_operand:GPR 3 "nonzero_shift_count_operand" "")) 4452 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) 4453 (match_operand:GPR 4 "nonimmediate_operand" "0"))) 4454 (clobber (reg:CC CC_REGNUM))] 4455 "TARGET_Z10 4456 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), 4457 INTVAL (operands[2]))" 4458 { 4459 operands[3] = GEN_INT (64 - INTVAL (operands[3])); 4460 return "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"; 4461 } 4462 [(set_attr "op_type" "RIE")]) 4463 4464 ; rosbg, rxsbg 4465 (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" 4466 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4467 (IXOR:GPR 4468 (and:GPR 4469 (ashift:GPR 4470 (match_operand:GPR 1 "nonimmediate_operand" "d") 4471 (match_operand:GPR 3 "nonzero_shift_count_operand" "")) 4472 (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) 4473 (match_operand:GPR 4 "nonimmediate_operand" "0"))) 4474 (clobber (reg:CC CC_REGNUM))] 4475 "TARGET_Z10 4476 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), 4477 INTVAL (operands[2]))" 4478 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" 4479 [(set_attr "op_type" "RIE")]) 4480 4481 ;; unsigned {int,long} a, b 4482 ;; a = a | (b << const_int) 4483 ;; a = a ^ (b << const_int) 4484 ; rosbg, rxsbg 4485 (define_insn "*r<noxa>sbg_<mode>_sll" 4486 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4487 (IXOR:GPR 4488 (ashift:GPR 4489 (match_operand:GPR 1 "nonimmediate_operand" "d") 4490 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4491 (match_operand:GPR 3 "nonimmediate_operand" "0"))) 4492 (clobber (reg:CC CC_REGNUM))] 4493 "TARGET_Z10" 4494 { 4495 operands[3] = GEN_INT (63 - INTVAL (operands[2])); 4496 return "r<noxa>sbg\t%0,%1,<bitoff>,%3,%2"; 4497 } 4498 [(set_attr "op_type" "RIE")]) 4499 4500 ;; unsigned {int,long} a, b 4501 ;; a = a | (b >> const_int) 4502 ;; a = a ^ (b >> const_int) 4503 ; rosbg, rxsbg 4504 (define_insn "*r<noxa>sbg_<mode>_srl" 4505 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 4506 (IXOR:GPR 4507 (lshiftrt:GPR 4508 (match_operand:GPR 1 "nonimmediate_operand" "d") 4509 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 4510 (match_operand:GPR 3 "nonimmediate_operand" "0"))) 4511 (clobber (reg:CC CC_REGNUM))] 4512 "TARGET_Z10" 4513 { 4514 operands[3] = GEN_INT (64 - INTVAL (operands[2])); 4515 operands[2] = GEN_INT (<bitoff_plus> INTVAL (operands[2])); 4516 return "r<noxa>sbg\t%0,%1,%2,63,%3"; 4517 } 4518 [(set_attr "op_type" "RIE")]) 4519 4520 ; rosbg, rxsbg 4521 (define_insn "*r<noxa>sbg_sidi_srl" 4522 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 4523 (IXOR:SI 4524 (subreg:SI 4525 (zero_extract:DI 4526 (match_operand:DI 1 "nonimmediate_operand" "d") 4527 (const_int 32) 4528 (match_operand:DI 2 "immediate_operand" "")) 4529 4) 4530 (match_operand:SI 3 "nonimmediate_operand" "0"))) 4531 (clobber (reg:CC CC_REGNUM))] 4532 "TARGET_Z10" 4533 { 4534 operands[2] = GEN_INT (32 + INTVAL (operands[2])); 4535 return "r<noxa>sbg\t%0,%1,32,63,%2"; 4536 } 4537 [(set_attr "op_type" "RIE")]) 4538 4539 ;; These two are generated by combine for s.bf &= val. 4540 ;; ??? For bitfields smaller than 32-bits, we wind up with SImode 4541 ;; shifts and ands, which results in some truly awful patterns 4542 ;; including subregs of operations. Rather unnecessisarily, IMO. 4543 ;; Instead of 4544 ;; 4545 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) 4546 ;; (const_int 24 [0x18]) 4547 ;; (const_int 0 [0])) 4548 ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) 4549 ;; (const_int 40 [0x28])) 4) 4550 ;; (reg:SI 4 %r4 [ y+4 ])) 0)) 4551 ;; 4552 ;; we should instead generate 4553 ;; 4554 ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) 4555 ;; (const_int 24 [0x18]) 4556 ;; (const_int 0 [0])) 4557 ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) 4558 ;; (const_int 40 [0x28])) 4559 ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) 4560 ;; 4561 ;; by noticing that we can push down the outer paradoxical subreg 4562 ;; into the operation. 4563 4564 (define_insn "*insv_rnsbg_noshift" 4565 [(set (zero_extract:DI 4566 (match_operand:DI 0 "nonimmediate_operand" "+d") 4567 (match_operand 1 "const_int_operand" "") 4568 (match_operand 2 "const_int_operand" "")) 4569 (and:DI 4570 (match_dup 0) 4571 (match_operand:DI 3 "nonimmediate_operand" "d"))) 4572 (clobber (reg:CC CC_REGNUM))] 4573 "TARGET_Z10 4574 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) 4575 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" 4576 "rnsbg\t%0,%3,%2,63,0" 4577 [(set_attr "op_type" "RIE")]) 4578 4579 (define_insn "*insv_rnsbg_srl" 4580 [(set (zero_extract:DI 4581 (match_operand:DI 0 "nonimmediate_operand" "+d") 4582 (match_operand 1 "const_int_operand" "") 4583 (match_operand 2 "const_int_operand" "")) 4584 (and:DI 4585 (lshiftrt:DI 4586 (match_dup 0) 4587 (match_operand 3 "const_int_operand" "")) 4588 (match_operand:DI 4 "nonimmediate_operand" "d"))) 4589 (clobber (reg:CC CC_REGNUM))] 4590 "TARGET_Z10 4591 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) 4592 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" 4593 "rnsbg\t%0,%4,%2,%2+%1-1,%3" 4594 [(set_attr "op_type" "RIE")]) 4595 4596 (define_insn "*insv<mode>_mem_reg" 4597 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") 4598 (match_operand 1 "const_int_operand" "n,n") 4599 (const_int 0)) 4600 (match_operand:W 2 "register_operand" "d,d"))] 4601 "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) 4602 && INTVAL (operands[1]) > 0 4603 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 4604 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 4605 { 4606 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 4607 4608 operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); 4609 return (which_alternative == 0) ? "stcm\t%2,%1,%S0" 4610 : "stcmy\t%2,%1,%S0"; 4611 } 4612 [(set_attr "op_type" "RS,RSY") 4613 (set_attr "cpu_facility" "*,longdisp") 4614 (set_attr "z10prop" "z10_super,z10_super")]) 4615 4616 (define_insn "*insvdi_mem_reghigh" 4617 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") 4618 (match_operand 1 "const_int_operand" "n") 4619 (const_int 0)) 4620 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") 4621 (const_int 32)))] 4622 "TARGET_ZARCH 4623 && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) 4624 && INTVAL (operands[1]) > 0 4625 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 4626 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 4627 { 4628 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 4629 4630 operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); 4631 return "stcmh\t%2,%1,%S0"; 4632 } 4633 [(set_attr "op_type" "RSY") 4634 (set_attr "z10prop" "z10_super")]) 4635 4636 (define_insn "*insvdi_reg_imm" 4637 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 4638 (const_int 16) 4639 (match_operand 1 "const_int_operand" "n")) 4640 (match_operand:DI 2 "const_int_operand" "n"))] 4641 "TARGET_ZARCH 4642 && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) 4643 && INTVAL (operands[1]) >= 0 4644 && INTVAL (operands[1]) < BITS_PER_WORD 4645 && INTVAL (operands[1]) % 16 == 0" 4646 { 4647 switch (BITS_PER_WORD - INTVAL (operands[1])) 4648 { 4649 case 64: return "iihh\t%0,%x2"; break; 4650 case 48: return "iihl\t%0,%x2"; break; 4651 case 32: return "iilh\t%0,%x2"; break; 4652 case 16: return "iill\t%0,%x2"; break; 4653 default: gcc_unreachable(); 4654 } 4655 } 4656 [(set_attr "op_type" "RI") 4657 (set_attr "z10prop" "z10_super_E1")]) 4658 4659 ; Update the left-most 32 bit of a DI. 4660 (define_insn "*insv_h_di_reg_extimm" 4661 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 4662 (const_int 32) 4663 (const_int 0)) 4664 (match_operand:DI 1 "const_int_operand" "n"))] 4665 "TARGET_EXTIMM" 4666 "iihf\t%0,%o1" 4667 [(set_attr "op_type" "RIL") 4668 (set_attr "z10prop" "z10_fwd_E1")]) 4669 4670 ; Update the right-most 32 bit of a DI. 4671 (define_insn "*insv_l_di_reg_extimm" 4672 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 4673 (const_int 32) 4674 (const_int 32)) 4675 (match_operand:DI 1 "const_int_operand" "n"))] 4676 "TARGET_EXTIMM" 4677 "iilf\t%0,%o1" 4678 [(set_attr "op_type" "RIL") 4679 (set_attr "z10prop" "z10_fwd_A1")]) 4680 4681 ; 4682 ; extendsidi2 instruction pattern(s). 4683 ; 4684 4685 (define_expand "extendsidi2" 4686 [(set (match_operand:DI 0 "register_operand" "") 4687 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 4688 "" 4689 { 4690 if (!TARGET_ZARCH) 4691 { 4692 emit_clobber (operands[0]); 4693 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); 4694 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); 4695 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); 4696 DONE; 4697 } 4698 }) 4699 4700 (define_insn "*extendsidi2" 4701 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4702 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] 4703 "TARGET_ZARCH" 4704 "@ 4705 lgfr\t%0,%1 4706 lgf\t%0,%1 4707 lgfrl\t%0,%1" 4708 [(set_attr "op_type" "RRE,RXY,RIL") 4709 (set_attr "type" "*,*,larl") 4710 (set_attr "cpu_facility" "*,*,z10") 4711 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") 4712 (set_attr "relative_long" "*,*,yes")]) 4713 4714 ; 4715 ; extend(hi|qi)(si|di)2 instruction pattern(s). 4716 ; 4717 4718 (define_expand "extend<HQI:mode><DSI:mode>2" 4719 [(set (match_operand:DSI 0 "register_operand" "") 4720 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4721 "" 4722 { 4723 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) 4724 { 4725 rtx tmp = gen_reg_rtx (SImode); 4726 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); 4727 emit_insn (gen_extendsidi2 (operands[0], tmp)); 4728 DONE; 4729 } 4730 else if (!TARGET_EXTIMM) 4731 { 4732 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); 4733 4734 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); 4735 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); 4736 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); 4737 DONE; 4738 } 4739 }) 4740 4741 ; 4742 ; extendhidi2 instruction pattern(s). 4743 ; 4744 4745 (define_insn "*extendhidi2_extimm" 4746 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4747 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] 4748 "TARGET_ZARCH && TARGET_EXTIMM" 4749 "@ 4750 lghr\t%0,%1 4751 lgh\t%0,%1 4752 lghrl\t%0,%1" 4753 [(set_attr "op_type" "RRE,RXY,RIL") 4754 (set_attr "type" "*,*,larl") 4755 (set_attr "cpu_facility" "extimm,extimm,z10") 4756 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") 4757 (set_attr "relative_long" "*,*,yes")]) 4758 4759 (define_insn "*extendhidi2" 4760 [(set (match_operand:DI 0 "register_operand" "=d") 4761 (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] 4762 "TARGET_ZARCH" 4763 "lgh\t%0,%1" 4764 [(set_attr "op_type" "RXY") 4765 (set_attr "z10prop" "z10_super_E1")]) 4766 4767 ; 4768 ; extendhisi2 instruction pattern(s). 4769 ; 4770 4771 (define_insn "*extendhisi2_extimm" 4772 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 4773 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] 4774 "TARGET_EXTIMM" 4775 "@ 4776 lhr\t%0,%1 4777 lh\t%0,%1 4778 lhy\t%0,%1 4779 lhrl\t%0,%1" 4780 [(set_attr "op_type" "RRE,RX,RXY,RIL") 4781 (set_attr "type" "*,*,*,larl") 4782 (set_attr "cpu_facility" "extimm,extimm,extimm,z10") 4783 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1") 4784 (set_attr "relative_long" "*,*,*,yes")]) 4785 4786 (define_insn "*extendhisi2" 4787 [(set (match_operand:SI 0 "register_operand" "=d,d") 4788 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] 4789 "!TARGET_EXTIMM" 4790 "@ 4791 lh\t%0,%1 4792 lhy\t%0,%1" 4793 [(set_attr "op_type" "RX,RXY") 4794 (set_attr "cpu_facility" "*,longdisp") 4795 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4796 4797 ; 4798 ; extendqi(si|di)2 instruction pattern(s). 4799 ; 4800 4801 ; lbr, lgbr, lb, lgb 4802 (define_insn "*extendqi<mode>2_extimm" 4803 [(set (match_operand:GPR 0 "register_operand" "=d,d") 4804 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] 4805 "TARGET_EXTIMM" 4806 "@ 4807 l<g>br\t%0,%1 4808 l<g>b\t%0,%1" 4809 [(set_attr "op_type" "RRE,RXY") 4810 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4811 4812 ; lb, lgb 4813 (define_insn "*extendqi<mode>2" 4814 [(set (match_operand:GPR 0 "register_operand" "=d") 4815 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] 4816 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" 4817 "l<g>b\t%0,%1" 4818 [(set_attr "op_type" "RXY") 4819 (set_attr "z10prop" "z10_super_E1")]) 4820 4821 (define_insn_and_split "*extendqi<mode>2_short_displ" 4822 [(set (match_operand:GPR 0 "register_operand" "=d") 4823 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) 4824 (clobber (reg:CC CC_REGNUM))] 4825 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" 4826 "#" 4827 "&& reload_completed" 4828 [(parallel 4829 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) 4830 (clobber (reg:CC CC_REGNUM))]) 4831 (parallel 4832 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) 4833 (clobber (reg:CC CC_REGNUM))])] 4834 { 4835 operands[1] = adjust_address (operands[1], BLKmode, 0); 4836 set_mem_size (operands[1], GET_MODE_SIZE (QImode)); 4837 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); 4838 }) 4839 4840 ; 4841 ; zero_extendsidi2 instruction pattern(s). 4842 ; 4843 4844 (define_expand "zero_extendsidi2" 4845 [(set (match_operand:DI 0 "register_operand" "") 4846 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 4847 "" 4848 { 4849 if (!TARGET_ZARCH) 4850 { 4851 emit_clobber (operands[0]); 4852 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); 4853 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); 4854 DONE; 4855 } 4856 }) 4857 4858 (define_insn "*zero_extendsidi2" 4859 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4860 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] 4861 "TARGET_ZARCH" 4862 "@ 4863 llgfr\t%0,%1 4864 llgf\t%0,%1 4865 llgfrl\t%0,%1" 4866 [(set_attr "op_type" "RRE,RXY,RIL") 4867 (set_attr "type" "*,*,larl") 4868 (set_attr "cpu_facility" "*,*,z10") 4869 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3") 4870 (set_attr "relative_long" "*,*,yes")]) 4871 4872 ; 4873 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). 4874 ; 4875 4876 (define_insn "*llgt_sidi" 4877 [(set (match_operand:DI 0 "register_operand" "=d") 4878 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) 4879 (const_int 2147483647)))] 4880 "TARGET_ZARCH" 4881 "llgt\t%0,%1" 4882 [(set_attr "op_type" "RXE") 4883 (set_attr "z10prop" "z10_super_E1")]) 4884 4885 (define_insn_and_split "*llgt_sidi_split" 4886 [(set (match_operand:DI 0 "register_operand" "=d") 4887 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) 4888 (const_int 2147483647))) 4889 (clobber (reg:CC CC_REGNUM))] 4890 "TARGET_ZARCH" 4891 "#" 4892 "&& reload_completed" 4893 [(set (match_dup 0) 4894 (and:DI (subreg:DI (match_dup 1) 0) 4895 (const_int 2147483647)))] 4896 "") 4897 4898 (define_insn "*llgt_sisi" 4899 [(set (match_operand:SI 0 "register_operand" "=d,d") 4900 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") 4901 (const_int 2147483647)))] 4902 "TARGET_ZARCH" 4903 "@ 4904 llgtr\t%0,%1 4905 llgt\t%0,%1" 4906 [(set_attr "op_type" "RRE,RXE") 4907 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4908 4909 (define_insn "*llgt_didi" 4910 [(set (match_operand:DI 0 "register_operand" "=d,d") 4911 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") 4912 (const_int 2147483647)))] 4913 "TARGET_ZARCH" 4914 "@ 4915 llgtr\t%0,%1 4916 llgt\t%0,%N1" 4917 [(set_attr "op_type" "RRE,RXE") 4918 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4919 4920 (define_split 4921 [(set (match_operand:DSI 0 "register_operand" "") 4922 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") 4923 (const_int 2147483647))) 4924 (clobber (reg:CC CC_REGNUM))] 4925 "TARGET_ZARCH && reload_completed" 4926 [(set (match_dup 0) 4927 (and:DSI (match_dup 1) 4928 (const_int 2147483647)))] 4929 "") 4930 4931 ; 4932 ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). 4933 ; 4934 4935 (define_expand "zero_extend<mode>di2" 4936 [(set (match_operand:DI 0 "register_operand" "") 4937 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4938 "" 4939 { 4940 if (!TARGET_ZARCH) 4941 { 4942 rtx tmp = gen_reg_rtx (SImode); 4943 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); 4944 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 4945 DONE; 4946 } 4947 else if (!TARGET_EXTIMM) 4948 { 4949 rtx bitcount = GEN_INT (64 - <HQI:bitsize>); 4950 operands[1] = gen_lowpart (DImode, operands[1]); 4951 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); 4952 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); 4953 DONE; 4954 } 4955 }) 4956 4957 (define_expand "zero_extend<mode>si2" 4958 [(set (match_operand:SI 0 "register_operand" "") 4959 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4960 "" 4961 { 4962 if (!TARGET_EXTIMM) 4963 { 4964 operands[1] = gen_lowpart (SImode, operands[1]); 4965 emit_insn (gen_andsi3 (operands[0], operands[1], 4966 GEN_INT ((1 << <HQI:bitsize>) - 1))); 4967 DONE; 4968 } 4969 }) 4970 4971 ; llhrl, llghrl 4972 (define_insn "*zero_extendhi<mode>2_z10" 4973 [(set (match_operand:GPR 0 "register_operand" "=d,d,d") 4974 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] 4975 "TARGET_Z10" 4976 "@ 4977 ll<g>hr\t%0,%1 4978 ll<g>h\t%0,%1 4979 ll<g>hrl\t%0,%1" 4980 [(set_attr "op_type" "RXY,RRE,RIL") 4981 (set_attr "type" "*,*,larl") 4982 (set_attr "cpu_facility" "*,*,z10") 4983 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3") 4984 (set_attr "relative_long" "*,*,yes")]) 4985 4986 ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc 4987 (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" 4988 [(set (match_operand:GPR 0 "register_operand" "=d,d") 4989 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] 4990 "TARGET_EXTIMM" 4991 "@ 4992 ll<g><hc>r\t%0,%1 4993 ll<g><hc>\t%0,%1" 4994 [(set_attr "op_type" "RRE,RXY") 4995 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) 4996 4997 ; llgh, llgc 4998 (define_insn "*zero_extend<HQI:mode><GPR:mode>2" 4999 [(set (match_operand:GPR 0 "register_operand" "=d") 5000 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] 5001 "TARGET_ZARCH && !TARGET_EXTIMM" 5002 "llg<hc>\t%0,%1" 5003 [(set_attr "op_type" "RXY") 5004 (set_attr "z10prop" "z10_fwd_A3")]) 5005 5006 (define_insn_and_split "*zero_extendhisi2_31" 5007 [(set (match_operand:SI 0 "register_operand" "=&d") 5008 (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) 5009 (clobber (reg:CC CC_REGNUM))] 5010 "!TARGET_ZARCH" 5011 "#" 5012 "&& reload_completed" 5013 [(set (match_dup 0) (const_int 0)) 5014 (parallel 5015 [(set (strict_low_part (match_dup 2)) (match_dup 1)) 5016 (clobber (reg:CC CC_REGNUM))])] 5017 "operands[2] = gen_lowpart (HImode, operands[0]);") 5018 5019 (define_insn_and_split "*zero_extendqisi2_31" 5020 [(set (match_operand:SI 0 "register_operand" "=&d") 5021 (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] 5022 "!TARGET_ZARCH" 5023 "#" 5024 "&& reload_completed" 5025 [(set (match_dup 0) (const_int 0)) 5026 (set (strict_low_part (match_dup 2)) (match_dup 1))] 5027 "operands[2] = gen_lowpart (QImode, operands[0]);") 5028 5029 ; 5030 ; zero_extendqihi2 instruction pattern(s). 5031 ; 5032 5033 (define_expand "zero_extendqihi2" 5034 [(set (match_operand:HI 0 "register_operand" "") 5035 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] 5036 "TARGET_ZARCH && !TARGET_EXTIMM" 5037 { 5038 operands[1] = gen_lowpart (HImode, operands[1]); 5039 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); 5040 DONE; 5041 }) 5042 5043 (define_insn "*zero_extendqihi2_64" 5044 [(set (match_operand:HI 0 "register_operand" "=d") 5045 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] 5046 "TARGET_ZARCH && !TARGET_EXTIMM" 5047 "llgc\t%0,%1" 5048 [(set_attr "op_type" "RXY") 5049 (set_attr "z10prop" "z10_fwd_A3")]) 5050 5051 (define_insn_and_split "*zero_extendqihi2_31" 5052 [(set (match_operand:HI 0 "register_operand" "=&d") 5053 (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] 5054 "!TARGET_ZARCH" 5055 "#" 5056 "&& reload_completed" 5057 [(set (match_dup 0) (const_int 0)) 5058 (set (strict_low_part (match_dup 2)) (match_dup 1))] 5059 "operands[2] = gen_lowpart (QImode, operands[0]);") 5060 5061 ; 5062 ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander 5063 ; 5064 5065 ; This is the only entry point for fixuns_trunc. It multiplexes the 5066 ; expansion to either the *_emu expanders below for pre z196 machines 5067 ; or emits the default pattern otherwise. 5068 (define_expand "fixuns_trunc<FP:mode><GPR:mode>2<FP:tf_fpr>" 5069 [(parallel 5070 [(set (match_operand:GPR 0 "register_operand" "") 5071 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) 5072 (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) 5073 (clobber (reg:CC CC_REGNUM))])] 5074 "TARGET_HARD_FLOAT" 5075 { 5076 if (!TARGET_Z196) 5077 { 5078 /* We don't provide emulation for TD|DD->SI. */ 5079 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT 5080 && <GPR:MODE>mode == SImode) 5081 FAIL; 5082 emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], 5083 operands[1])); 5084 DONE; 5085 } 5086 5087 if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) 5088 operands[2] = GEN_INT (DFP_RND_TOWARD_0); 5089 else 5090 operands[2] = GEN_INT (BFP_RND_TOWARD_0); 5091 }) 5092 5093 ; (sf|df|tf)->unsigned (si|di) 5094 5095 ; Emulate the unsigned conversion with the signed version for pre z196 5096 ; machines. 5097 (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" 5098 [(parallel 5099 [(set (match_operand:GPR 0 "register_operand" "") 5100 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) 5101 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) 5102 (clobber (reg:CC CC_REGNUM))])] 5103 "!TARGET_Z196 && TARGET_HARD_FLOAT" 5104 { 5105 rtx_code_label *label1 = gen_label_rtx (); 5106 rtx_code_label *label2 = gen_label_rtx (); 5107 rtx temp = gen_reg_rtx (<BFP:MODE>mode); 5108 REAL_VALUE_TYPE cmp, sub; 5109 5110 operands[1] = force_reg (<BFP:MODE>mode, operands[1]); 5111 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); 5112 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); 5113 5114 emit_cmp_and_jump_insns (operands[1], 5115 const_double_from_real_value (cmp, <BFP:MODE>mode), 5116 LT, NULL_RTX, VOIDmode, 0, label1); 5117 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], 5118 const_double_from_real_value (sub, <BFP:MODE>mode))); 5119 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, 5120 GEN_INT (BFP_RND_TOWARD_MINF))); 5121 emit_jump (label2); 5122 5123 emit_label (label1); 5124 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], 5125 operands[1], 5126 GEN_INT (BFP_RND_TOWARD_0))); 5127 emit_label (label2); 5128 DONE; 5129 }) 5130 5131 ; dd->unsigned di 5132 5133 ; Emulate the unsigned conversion with the signed version for pre z196 5134 ; machines. 5135 (define_expand "fixuns_truncdddi2_emu" 5136 [(parallel 5137 [(set (match_operand:DI 0 "register_operand" "") 5138 (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) 5139 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) 5140 (clobber (reg:CC CC_REGNUM))])] 5141 5142 "!TARGET_Z196 && TARGET_HARD_DFP" 5143 { 5144 rtx_code_label *label1 = gen_label_rtx (); 5145 rtx_code_label *label2 = gen_label_rtx (); 5146 rtx temp = gen_reg_rtx (TDmode); 5147 REAL_VALUE_TYPE cmp, sub; 5148 5149 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ 5150 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ 5151 5152 /* 2^63 can't be represented as 64bit DFP number with full precision. The 5153 solution is doing the check and the subtraction in TD mode and using a 5154 TD -> DI convert afterwards. */ 5155 emit_insn (gen_extendddtd2 (temp, operands[1])); 5156 temp = force_reg (TDmode, temp); 5157 emit_cmp_and_jump_insns (temp, 5158 const_double_from_real_value (cmp, TDmode), 5159 LT, NULL_RTX, VOIDmode, 0, label1); 5160 emit_insn (gen_subtd3 (temp, temp, 5161 const_double_from_real_value (sub, TDmode))); 5162 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, 5163 GEN_INT (DFP_RND_TOWARD_MINF))); 5164 emit_jump (label2); 5165 5166 emit_label (label1); 5167 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], 5168 GEN_INT (DFP_RND_TOWARD_0))); 5169 emit_label (label2); 5170 DONE; 5171 }) 5172 5173 ; td->unsigned di 5174 5175 ; Emulate the unsigned conversion with the signed version for pre z196 5176 ; machines. 5177 (define_expand "fixuns_trunctddi2_emu" 5178 [(parallel 5179 [(set (match_operand:DI 0 "register_operand" "") 5180 (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) 5181 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) 5182 (clobber (reg:CC CC_REGNUM))])] 5183 5184 "!TARGET_Z196 && TARGET_HARD_DFP" 5185 { 5186 rtx_code_label *label1 = gen_label_rtx (); 5187 rtx_code_label *label2 = gen_label_rtx (); 5188 rtx temp = gen_reg_rtx (TDmode); 5189 REAL_VALUE_TYPE cmp, sub; 5190 5191 operands[1] = force_reg (TDmode, operands[1]); 5192 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ 5193 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ 5194 5195 emit_cmp_and_jump_insns (operands[1], 5196 const_double_from_real_value (cmp, TDmode), 5197 LT, NULL_RTX, VOIDmode, 0, label1); 5198 emit_insn (gen_subtd3 (temp, operands[1], 5199 const_double_from_real_value (sub, TDmode))); 5200 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, 5201 GEN_INT (DFP_RND_TOWARD_MINF))); 5202 emit_jump (label2); 5203 5204 emit_label (label1); 5205 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], 5206 GEN_INT (DFP_RND_TOWARD_0))); 5207 emit_label (label2); 5208 DONE; 5209 }) 5210 5211 ; Just a dummy to make the code in the first expander a bit easier. 5212 (define_expand "fixuns_trunc<mode>si2_emu" 5213 [(parallel 5214 [(set (match_operand:SI 0 "register_operand" "") 5215 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) 5216 (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) 5217 (clobber (reg:CC CC_REGNUM))])] 5218 5219 "!TARGET_Z196 && TARGET_HARD_DFP" 5220 { 5221 FAIL; 5222 }) 5223 5224 5225 ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. 5226 5227 ; df -> unsigned di, vxe2: sf -> unsigned si 5228 ; clgdbr, clfebr, wclgdb, wclfeb 5229 (define_insn "*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13" 5230 [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") 5231 (unsigned_fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) 5232 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) 5233 (clobber (reg:CC CC_REGNUM))] 5234 "TARGET_VX && TARGET_HARD_FLOAT 5235 && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" 5236 "@ 5237 cl<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1,0 5238 wcl<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" 5239 [(set_attr "op_type" "RRF,VRR") 5240 (set_attr "type" "ftoi")]) 5241 5242 ; (dd|td|sf|df|tf)->unsigned (di|si) 5243 ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr 5244 ; clfdtr, clfxtr, clgdtr, clgxtr 5245 (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" 5246 [(set (match_operand:GPR 0 "register_operand" "=d") 5247 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) 5248 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 5249 (clobber (reg:CC CC_REGNUM))] 5250 "TARGET_Z196 && TARGET_HARD_FLOAT 5251 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" 5252 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" 5253 [(set_attr "op_type" "RRF") 5254 (set_attr "type" "ftoi")]) 5255 5256 (define_expand "fix_trunc<DSF:mode><GPR:mode>2" 5257 [(set (match_operand:GPR 0 "register_operand" "") 5258 (fix:GPR (match_operand:DSF 1 "register_operand" "")))] 5259 "TARGET_HARD_FLOAT" 5260 { 5261 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], 5262 GEN_INT (BFP_RND_TOWARD_0))); 5263 DONE; 5264 }) 5265 5266 ; df -> signed di, vxe2: sf -> signed si 5267 ; cgdbr, cfebr, wcgdb, wcfeb 5268 (define_insn "*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13" 5269 [(set (match_operand:VX_CONV_INT 0 "register_operand" "=d,v") 5270 (fix:VX_CONV_INT (match_operand:VX_CONV_BFP 1 "register_operand" "f,v"))) 5271 (unspec:VX_CONV_INT [(match_operand:VX_CONV_INT 2 "immediate_operand" "K,K")] UNSPEC_ROUND) 5272 (clobber (reg:CC CC_REGNUM))] 5273 "TARGET_VX && TARGET_HARD_FLOAT 5274 && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" 5275 "@ 5276 c<VX_CONV_INT:gf><VX_CONV_BFP:xde>br\t%0,%h2,%1 5277 wc<VX_CONV_INT:gf><VX_CONV_BFP:xde>b\t%v0,%v1,0,%h2" 5278 [(set_attr "op_type" "RRE,VRR") 5279 (set_attr "type" "ftoi")]) 5280 5281 ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr 5282 (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" 5283 [(set (match_operand:GPR 0 "register_operand" "=d") 5284 (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) 5285 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 5286 (clobber (reg:CC CC_REGNUM))] 5287 "TARGET_HARD_FLOAT 5288 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" 5289 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" 5290 [(set_attr "op_type" "RRE") 5291 (set_attr "type" "ftoi")]) 5292 5293 (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" 5294 [(parallel 5295 [(set (match_operand:GPR 0 "register_operand" "=d") 5296 (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) 5297 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 5298 (clobber (reg:CC CC_REGNUM))])] 5299 "TARGET_HARD_FLOAT") 5300 ; 5301 ; fix_trunc(td|dd)di2 instruction pattern(s). 5302 ; 5303 5304 (define_expand "fix_trunc<mode>di2" 5305 [(set (match_operand:DI 0 "register_operand" "") 5306 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] 5307 "TARGET_ZARCH && TARGET_HARD_DFP" 5308 { 5309 operands[1] = force_reg (<MODE>mode, operands[1]); 5310 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], 5311 GEN_INT (DFP_RND_TOWARD_0))); 5312 DONE; 5313 }) 5314 5315 ; cgxtr, cgdtr 5316 (define_insn "fix_trunc<DFP:mode>di2_dfp" 5317 [(set (match_operand:DI 0 "register_operand" "=d") 5318 (fix:DI (match_operand:DFP 1 "register_operand" "f"))) 5319 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) 5320 (clobber (reg:CC CC_REGNUM))] 5321 "TARGET_ZARCH && TARGET_HARD_DFP" 5322 "cg<DFP:xde>tr\t%0,%h2,%1" 5323 [(set_attr "op_type" "RRF") 5324 (set_attr "type" "ftoidfp")]) 5325 5326 5327 ; 5328 ; fix_trunctf(si|di)2 instruction pattern(s). 5329 ; 5330 5331 (define_expand "fix_trunctf<mode>2_fpr" 5332 [(parallel [(set (match_operand:GPR 0 "register_operand" "") 5333 (fix:GPR (match_operand:TF 1 "register_operand" ""))) 5334 (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) 5335 (clobber (reg:CC CC_REGNUM))])] 5336 "TARGET_HARD_FLOAT && !TARGET_VXE" 5337 "") 5338 5339 5340 ; 5341 ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). 5342 ; 5343 5344 ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr 5345 (define_insn "floatdi<mode>2<tf_fpr>" 5346 [(set (match_operand:FP 0 "register_operand" "=f,v") 5347 (float:FP (match_operand:DI 1 "register_operand" "d,v")))] 5348 "TARGET_ZARCH && TARGET_HARD_FLOAT" 5349 "@ 5350 c<xde>g<bt>r\t%0,%1 5351 wcdgb\t%v0,%v1,0,0" 5352 [(set_attr "op_type" "RRE,VRR") 5353 (set_attr "type" "itof<type>" ) 5354 (set_attr "cpu_facility" "*,vx") 5355 (set_attr "enabled" "*,<DFDI>")]) 5356 5357 ; cxfbr, cdfbr, cefbr, wcefb 5358 (define_insn "floatsi<mode>2<tf_fpr>" 5359 [(set (match_operand:BFP 0 "register_operand" "=f,v") 5360 (float:BFP (match_operand:SI 1 "register_operand" "d,v")))] 5361 "TARGET_HARD_FLOAT" 5362 "@ 5363 c<xde>fbr\t%0,%1 5364 wcefb\t%v0,%v1,0,0" 5365 [(set_attr "op_type" "RRE,VRR") 5366 (set_attr "type" "itof<type>" ) 5367 (set_attr "cpu_facility" "*,vxe2") 5368 (set_attr "enabled" "*,<SFSI>")]) 5369 5370 ; cxftr, cdftr 5371 (define_insn "floatsi<mode>2" 5372 [(set (match_operand:DFP 0 "register_operand" "=f") 5373 (float:DFP (match_operand:SI 1 "register_operand" "d")))] 5374 "TARGET_Z196 && TARGET_HARD_FLOAT" 5375 "c<xde>ftr\t%0,0,%1,0" 5376 [(set_attr "op_type" "RRE") 5377 (set_attr "type" "itof<type>")]) 5378 5379 ; 5380 ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). 5381 ; 5382 5383 (define_insn "*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13" 5384 [(set (match_operand:VX_CONV_BFP 0 "register_operand" "=f,v") 5385 (unsigned_float:VX_CONV_BFP (match_operand:VX_CONV_INT 1 "register_operand" "d,v")))] 5386 "TARGET_VX && TARGET_HARD_FLOAT 5387 && GET_MODE_SIZE (<VX_CONV_INT:MODE>mode) == GET_MODE_SIZE (<VX_CONV_BFP:MODE>mode)" 5388 "@ 5389 c<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>br\t%0,0,%1,0 5390 wc<VX_CONV_BFP:xde>l<VX_CONV_INT:gf>b\t%v0,%v1,0,0" 5391 [(set_attr "op_type" "RRE,VRR") 5392 (set_attr "type" "itofdf")]) 5393 5394 ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr 5395 ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr 5396 (define_insn "*floatuns<GPR:mode><FP:mode>2" 5397 [(set (match_operand:FP 0 "register_operand" "=f") 5398 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] 5399 "TARGET_Z196 && TARGET_HARD_FLOAT 5400 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" 5401 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" 5402 [(set_attr "op_type" "RRE") 5403 (set_attr "type" "itof<FP:type>")]) 5404 5405 (define_expand "floatuns<GPR:mode><FP:mode>2<tf_fpr>" 5406 [(set (match_operand:FP 0 "register_operand" "") 5407 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] 5408 "TARGET_Z196 && TARGET_HARD_FLOAT") 5409 5410 ; 5411 ; truncdfsf2 instruction pattern(s). 5412 ; 5413 5414 (define_insn "truncdfsf2" 5415 [(set (match_operand:SF 0 "register_operand" "=f,v") 5416 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] 5417 "TARGET_HARD_FLOAT" 5418 "@ 5419 ledbr\t%0,%1 5420 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed 5421 ; According to BFP rounding mode 5422 [(set_attr "op_type" "RRE,VRR") 5423 (set_attr "type" "ftruncdf") 5424 (set_attr "cpu_facility" "*,vx")]) 5425 5426 ; 5427 ; trunctf(df|sf)2 instruction pattern(s). 5428 ; 5429 5430 ; ldxbr, lexbr 5431 (define_insn "trunctf<mode>2_fpr" 5432 [(set (match_operand:DSF 0 "register_operand" "=f") 5433 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) 5434 (clobber (match_scratch:TF 2 "=f"))] 5435 "TARGET_HARD_FLOAT" 5436 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" 5437 [(set_attr "length" "6") 5438 (set_attr "type" "ftrunctf")]) 5439 5440 ; 5441 ; trunctddd2 and truncddsd2 instruction pattern(s). 5442 ; 5443 5444 5445 (define_expand "trunctddd2" 5446 [(parallel 5447 [(set (match_operand:DD 0 "register_operand" "") 5448 (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) 5449 (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) 5450 (clobber (scratch:TD))])] 5451 "TARGET_HARD_DFP") 5452 5453 (define_insn "*trunctddd2" 5454 [(set (match_operand:DD 0 "register_operand" "=f") 5455 (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) 5456 (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) 5457 (clobber (match_scratch:TD 3 "=f"))] 5458 "TARGET_HARD_DFP" 5459 "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" 5460 [(set_attr "length" "6") 5461 (set_attr "type" "ftruncdd")]) 5462 5463 (define_insn "truncddsd2" 5464 [(set (match_operand:SD 0 "register_operand" "=f") 5465 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] 5466 "TARGET_HARD_DFP" 5467 "ledtr\t%0,0,%1,0" 5468 [(set_attr "op_type" "RRF") 5469 (set_attr "type" "ftruncsd")]) 5470 5471 (define_expand "trunctdsd2" 5472 [(parallel 5473 [(set (match_dup 2) 5474 (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) 5475 (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) 5476 (clobber (match_scratch:TD 3 ""))]) 5477 (set (match_operand:SD 0 "register_operand" "") 5478 (float_truncate:SD (match_dup 2)))] 5479 "TARGET_HARD_DFP" 5480 { 5481 operands[2] = gen_reg_rtx (DDmode); 5482 }) 5483 5484 ; 5485 ; extend(sf|df)(df|tf)2 instruction pattern(s). 5486 ; 5487 5488 ; wflls 5489 (define_insn "*extendsfdf2_z13" 5490 [(set (match_operand:DF 0 "register_operand" "=f,f,v") 5491 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] 5492 "TARGET_VX && TARGET_HARD_FLOAT" 5493 "@ 5494 ldebr\t%0,%1 5495 ldeb\t%0,%1 5496 wldeb\t%v0,%v1" 5497 [(set_attr "op_type" "RRE,RXE,VRR") 5498 (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) 5499 5500 ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb 5501 (define_insn "*extend<DSF:mode><BFP:mode>2" 5502 [(set (match_operand:BFP 0 "register_operand" "=f,f") 5503 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] 5504 "TARGET_HARD_FLOAT 5505 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) 5506 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" 5507 "@ 5508 l<BFP:xde><DSF:xde>br\t%0,%1 5509 l<BFP:xde><DSF:xde>b\t%0,%1" 5510 [(set_attr "op_type" "RRE,RXE") 5511 (set_attr "type" "fsimp<BFP:type>, fload<BFP:type>")]) 5512 5513 (define_expand "extend<DSF:mode><BFP:mode>2<BFP:tf_fpr>" 5514 [(set (match_operand:BFP 0 "register_operand" "") 5515 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] 5516 "TARGET_HARD_FLOAT 5517 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") 5518 5519 ; 5520 ; extendddtd2 and extendsddd2 instruction pattern(s). 5521 ; 5522 5523 (define_insn "extendddtd2" 5524 [(set (match_operand:TD 0 "register_operand" "=f") 5525 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] 5526 "TARGET_HARD_DFP" 5527 "lxdtr\t%0,%1,0" 5528 [(set_attr "op_type" "RRF") 5529 (set_attr "type" "fsimptf")]) 5530 5531 (define_insn "extendsddd2" 5532 [(set (match_operand:DD 0 "register_operand" "=f") 5533 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] 5534 "TARGET_HARD_DFP" 5535 "ldetr\t%0,%1,0" 5536 [(set_attr "op_type" "RRF") 5537 (set_attr "type" "fsimptf")]) 5538 5539 (define_expand "extendsdtd2" 5540 [(set (match_dup 2) 5541 (float_extend:DD (match_operand:SD 1 "register_operand" ""))) 5542 (set (match_operand:TD 0 "register_operand" "") 5543 (float_extend:TD (match_dup 2)))] 5544 "TARGET_HARD_DFP" 5545 { 5546 operands[2] = gen_reg_rtx (DDmode); 5547 }) 5548 5549 ; Binary Floating Point - load fp integer 5550 5551 ; Expanders for: floor, btrunc, round, ceil, and nearbyint 5552 ; For all of them the inexact exceptions are suppressed. 5553 5554 ; fiebra, fidbra, fixbra 5555 (define_insn "<FPINT:fpint_name><BFP:mode>2<BFP:tf_fpr>" 5556 [(set (match_operand:BFP 0 "register_operand" "=f") 5557 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] 5558 FPINT))] 5559 "TARGET_Z196" 5560 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" 5561 [(set_attr "op_type" "RRF") 5562 (set_attr "type" "fsimp<BFP:type>")]) 5563 5564 ; rint is supposed to raise an inexact exception so we can use the 5565 ; older instructions. 5566 5567 ; fiebr, fidbr, fixbr 5568 (define_insn "rint<BFP:mode>2<BFP:tf_fpr>" 5569 [(set (match_operand:BFP 0 "register_operand" "=f") 5570 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] 5571 UNSPEC_FPINT_RINT))] 5572 "" 5573 "fi<BFP:xde>br\t%0,0,%1" 5574 [(set_attr "op_type" "RRF") 5575 (set_attr "type" "fsimp<BFP:type>")]) 5576 5577 5578 ; Decimal Floating Point - load fp integer 5579 5580 ; fidtr, fixtr 5581 (define_insn "<FPINT:fpint_name><DFP:mode>2" 5582 [(set (match_operand:DFP 0 "register_operand" "=f") 5583 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] 5584 FPINT))] 5585 "TARGET_HARD_DFP" 5586 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" 5587 [(set_attr "op_type" "RRF") 5588 (set_attr "type" "fsimp<DFP:type>")]) 5589 5590 ; fidtr, fixtr 5591 (define_insn "rint<DFP:mode>2" 5592 [(set (match_operand:DFP 0 "register_operand" "=f") 5593 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] 5594 UNSPEC_FPINT_RINT))] 5595 "TARGET_HARD_DFP" 5596 "fi<DFP:xde>tr\t%0,0,%1,0" 5597 [(set_attr "op_type" "RRF") 5598 (set_attr "type" "fsimp<DFP:type>")]) 5599 5600 ; 5601 ; Binary <-> Decimal floating point trunc patterns 5602 ; 5603 5604 (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" 5605 [(set (reg:DFP_ALL FPR0_REGNUM) 5606 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) 5607 (use (reg:SI GPR0_REGNUM)) 5608 (clobber (reg:CC CC_REGNUM)) 5609 (clobber (reg:SI GPR1_REGNUM))] 5610 "TARGET_HARD_DFP" 5611 "pfpo") 5612 5613 (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" 5614 [(set (reg:BFP FPR0_REGNUM) 5615 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) 5616 (use (reg:SI GPR0_REGNUM)) 5617 (clobber (reg:CC CC_REGNUM)) 5618 (clobber (reg:SI GPR1_REGNUM))] 5619 "TARGET_HARD_DFP" 5620 "pfpo") 5621 5622 (define_expand "trunc<BFP:mode><DFP_ALL:mode>2<BFP:tf_fpr>" 5623 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) 5624 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5625 (parallel 5626 [(set (reg:DFP_ALL FPR0_REGNUM) 5627 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) 5628 (use (reg:SI GPR0_REGNUM)) 5629 (clobber (reg:CC CC_REGNUM)) 5630 (clobber (reg:SI GPR1_REGNUM))]) 5631 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") 5632 (reg:DFP_ALL FPR0_REGNUM))] 5633 "TARGET_HARD_DFP 5634 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" 5635 { 5636 HOST_WIDE_INT flags; 5637 5638 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5639 rounding mode of the target format needs to be used. */ 5640 5641 flags = (PFPO_CONVERT | 5642 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | 5643 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | 5644 PFPO_RND_MODE_DFP); 5645 5646 operands[2] = GEN_INT (flags); 5647 }) 5648 5649 (define_expand "trunc<DFP_ALL:mode><BFP:mode>2<BFP:tf_fpr>" 5650 [(set (reg:DFP_ALL FPR4_REGNUM) 5651 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) 5652 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5653 (parallel 5654 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) 5655 (use (reg:SI GPR0_REGNUM)) 5656 (clobber (reg:CC CC_REGNUM)) 5657 (clobber (reg:SI GPR1_REGNUM))]) 5658 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] 5659 "TARGET_HARD_DFP 5660 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" 5661 { 5662 HOST_WIDE_INT flags; 5663 5664 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5665 rounding mode of the target format needs to be used. */ 5666 5667 flags = (PFPO_CONVERT | 5668 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | 5669 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | 5670 PFPO_RND_MODE_BFP); 5671 5672 operands[2] = GEN_INT (flags); 5673 }) 5674 5675 ; 5676 ; Binary <-> Decimal floating point extend patterns 5677 ; 5678 5679 (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" 5680 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) 5681 (use (reg:SI GPR0_REGNUM)) 5682 (clobber (reg:CC CC_REGNUM)) 5683 (clobber (reg:SI GPR1_REGNUM))] 5684 "TARGET_HARD_DFP" 5685 "pfpo") 5686 5687 (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" 5688 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) 5689 (use (reg:SI GPR0_REGNUM)) 5690 (clobber (reg:CC CC_REGNUM)) 5691 (clobber (reg:SI GPR1_REGNUM))] 5692 "TARGET_HARD_DFP" 5693 "pfpo") 5694 5695 (define_expand "extend<BFP:mode><DFP_ALL:mode>2<BFP:tf_fpr>" 5696 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) 5697 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5698 (parallel 5699 [(set (reg:DFP_ALL FPR0_REGNUM) 5700 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) 5701 (use (reg:SI GPR0_REGNUM)) 5702 (clobber (reg:CC CC_REGNUM)) 5703 (clobber (reg:SI GPR1_REGNUM))]) 5704 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") 5705 (reg:DFP_ALL FPR0_REGNUM))] 5706 "TARGET_HARD_DFP 5707 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" 5708 { 5709 HOST_WIDE_INT flags; 5710 5711 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5712 rounding mode of the target format needs to be used. */ 5713 5714 flags = (PFPO_CONVERT | 5715 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | 5716 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | 5717 PFPO_RND_MODE_DFP); 5718 5719 operands[2] = GEN_INT (flags); 5720 }) 5721 5722 (define_expand "extend<DFP_ALL:mode><BFP:mode>2<BFP:tf_fpr>" 5723 [(set (reg:DFP_ALL FPR4_REGNUM) 5724 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) 5725 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 5726 (parallel 5727 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) 5728 (use (reg:SI GPR0_REGNUM)) 5729 (clobber (reg:CC CC_REGNUM)) 5730 (clobber (reg:SI GPR1_REGNUM))]) 5731 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] 5732 "TARGET_HARD_DFP 5733 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" 5734 { 5735 HOST_WIDE_INT flags; 5736 5737 /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the 5738 rounding mode of the target format needs to be used. */ 5739 5740 flags = (PFPO_CONVERT | 5741 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | 5742 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | 5743 PFPO_RND_MODE_BFP); 5744 5745 operands[2] = GEN_INT (flags); 5746 }) 5747 5748 5749 ;; 5750 ;; ARITHMETIC OPERATIONS 5751 ;; 5752 ; arithmetic operations set the ConditionCode, 5753 ; because of unpredictable Bits in Register for Halfword and Byte 5754 ; the ConditionCode can be set wrong in operations for Halfword and Byte 5755 5756 ;; 5757 ;;- Add instructions. 5758 ;; 5759 5760 ; 5761 ; addti3 instruction pattern(s). 5762 ; 5763 5764 (define_expand "addti3" 5765 [(parallel 5766 [(set (match_operand:TI 0 "register_operand" "") 5767 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") 5768 (match_operand:TI 2 "general_operand" "") ) ) 5769 (clobber (reg:CC CC_REGNUM))])] 5770 "TARGET_ZARCH" 5771 { 5772 /* For z13 we have vaq which doesn't set CC. */ 5773 if (TARGET_VX) 5774 { 5775 emit_insn (gen_rtx_SET (operands[0], 5776 gen_rtx_PLUS (TImode, 5777 copy_to_mode_reg (TImode, operands[1]), 5778 copy_to_mode_reg (TImode, operands[2])))); 5779 DONE; 5780 } 5781 }) 5782 5783 (define_insn_and_split "*addti3" 5784 [(set (match_operand:TI 0 "register_operand" "=&d") 5785 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 5786 (match_operand:TI 2 "general_operand" "do") ) ) 5787 (clobber (reg:CC CC_REGNUM))] 5788 "TARGET_ZARCH" 5789 "#" 5790 "&& reload_completed" 5791 [(parallel 5792 [(set (reg:CCL1 CC_REGNUM) 5793 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) 5794 (match_dup 7))) 5795 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) 5796 (parallel 5797 [(set (match_dup 3) (plus:DI 5798 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) 5799 (match_dup 4)) (match_dup 5))) 5800 (clobber (reg:CC CC_REGNUM))])] 5801 "operands[3] = operand_subword (operands[0], 0, 0, TImode); 5802 operands[4] = operand_subword (operands[1], 0, 0, TImode); 5803 operands[5] = operand_subword (operands[2], 0, 0, TImode); 5804 operands[6] = operand_subword (operands[0], 1, 0, TImode); 5805 operands[7] = operand_subword (operands[1], 1, 0, TImode); 5806 operands[8] = operand_subword (operands[2], 1, 0, TImode);" 5807 [(set_attr "op_type" "*") 5808 (set_attr "cpu_facility" "*")]) 5809 5810 ; 5811 ; adddi3 instruction pattern(s). 5812 ; 5813 5814 (define_expand "adddi3" 5815 [(parallel 5816 [(set (match_operand:DI 0 "nonimmediate_operand" "") 5817 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") 5818 (match_operand:DI 2 "general_operand" ""))) 5819 (clobber (reg:CC CC_REGNUM))])] 5820 "" 5821 "") 5822 5823 (define_insn "*adddi3_sign" 5824 [(set (match_operand:DI 0 "register_operand" "=d,d") 5825 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5826 (match_operand:DI 1 "register_operand" "0,0"))) 5827 (clobber (reg:CC CC_REGNUM))] 5828 "TARGET_ZARCH" 5829 "@ 5830 agfr\t%0,%2 5831 agf\t%0,%2" 5832 [(set_attr "op_type" "RRE,RXY") 5833 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 5834 5835 (define_insn "*adddi3_zero_cc" 5836 [(set (reg CC_REGNUM) 5837 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5838 (match_operand:DI 1 "register_operand" "0,0")) 5839 (const_int 0))) 5840 (set (match_operand:DI 0 "register_operand" "=d,d") 5841 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] 5842 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5843 "@ 5844 algfr\t%0,%2 5845 algf\t%0,%2" 5846 [(set_attr "op_type" "RRE,RXY") 5847 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5848 5849 (define_insn "*adddi3_zero_cconly" 5850 [(set (reg CC_REGNUM) 5851 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5852 (match_operand:DI 1 "register_operand" "0,0")) 5853 (const_int 0))) 5854 (clobber (match_scratch:DI 0 "=d,d"))] 5855 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5856 "@ 5857 algfr\t%0,%2 5858 algf\t%0,%2" 5859 [(set_attr "op_type" "RRE,RXY") 5860 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5861 5862 (define_insn "*adddi3_zero" 5863 [(set (match_operand:DI 0 "register_operand" "=d,d") 5864 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 5865 (match_operand:DI 1 "register_operand" "0,0"))) 5866 (clobber (reg:CC CC_REGNUM))] 5867 "TARGET_ZARCH" 5868 "@ 5869 algfr\t%0,%2 5870 algf\t%0,%2" 5871 [(set_attr "op_type" "RRE,RXY") 5872 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5873 5874 (define_insn_and_split "*adddi3_31z" 5875 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") 5876 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 5877 (match_operand:DI 2 "general_operand" "do") ) ) 5878 (clobber (reg:CC CC_REGNUM))] 5879 "!TARGET_ZARCH" 5880 "#" 5881 "&& reload_completed" 5882 [(parallel 5883 [(set (reg:CCL1 CC_REGNUM) 5884 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 5885 (match_dup 7))) 5886 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 5887 (parallel 5888 [(set (match_dup 3) (plus:SI 5889 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) 5890 (match_dup 4)) (match_dup 5))) 5891 (clobber (reg:CC CC_REGNUM))])] 5892 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 5893 operands[4] = operand_subword (operands[1], 0, 0, DImode); 5894 operands[5] = operand_subword (operands[2], 0, 0, DImode); 5895 operands[6] = operand_subword (operands[0], 1, 0, DImode); 5896 operands[7] = operand_subword (operands[1], 1, 0, DImode); 5897 operands[8] = operand_subword (operands[2], 1, 0, DImode);") 5898 5899 ; 5900 ; addsi3 instruction pattern(s). 5901 ; 5902 5903 (define_expand "addsi3" 5904 [(parallel 5905 [(set (match_operand:SI 0 "nonimmediate_operand" "") 5906 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") 5907 (match_operand:SI 2 "general_operand" ""))) 5908 (clobber (reg:CC CC_REGNUM))])] 5909 "" 5910 "") 5911 5912 (define_insn "*addsi3_sign" 5913 [(set (match_operand:SI 0 "register_operand" "=d,d") 5914 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) 5915 (match_operand:SI 1 "register_operand" "0,0"))) 5916 (clobber (reg:CC CC_REGNUM))] 5917 "" 5918 "@ 5919 ah\t%0,%2 5920 ahy\t%0,%2" 5921 [(set_attr "op_type" "RX,RXY") 5922 (set_attr "cpu_facility" "*,longdisp") 5923 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 5924 5925 ; 5926 ; add(di|si)3 instruction pattern(s). 5927 ; 5928 5929 ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi 5930 (define_insn "*add<mode>3" 5931 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") 5932 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") 5933 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) 5934 (clobber (reg:CC CC_REGNUM))] 5935 "" 5936 "@ 5937 a<g>r\t%0,%2 5938 a<g>rk\t%0,%1,%2 5939 a<g>hi\t%0,%h2 5940 a<g>hik\t%0,%1,%h2 5941 al<g>fi\t%0,%2 5942 sl<g>fi\t%0,%n2 5943 a<g>\t%0,%2 5944 a<y>\t%0,%2 5945 a<g>si\t%0,%c2" 5946 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") 5947 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") 5948 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, 5949 z10_super_E1,z10_super_E1,z10_super_E1")]) 5950 5951 ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik 5952 (define_insn "*add<mode>3_carry1_cc" 5953 [(set (reg CC_REGNUM) 5954 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") 5955 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) 5956 (match_dup 1))) 5957 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") 5958 (plus:GPR (match_dup 1) (match_dup 2)))] 5959 "s390_match_ccmode (insn, CCL1mode)" 5960 "@ 5961 al<g>r\t%0,%2 5962 al<g>rk\t%0,%1,%2 5963 al<g>fi\t%0,%2 5964 sl<g>fi\t%0,%n2 5965 al<g>hsik\t%0,%1,%h2 5966 al<g>\t%0,%2 5967 al<y>\t%0,%2 5968 al<g>si\t%0,%c2" 5969 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 5970 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") 5971 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, 5972 z10_super_E1,z10_super_E1,z10_super_E1")]) 5973 5974 ; alr, al, aly, algr, alg, alrk, algrk 5975 (define_insn "*add<mode>3_carry1_cconly" 5976 [(set (reg CC_REGNUM) 5977 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5978 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5979 (match_dup 1))) 5980 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5981 "s390_match_ccmode (insn, CCL1mode)" 5982 "@ 5983 al<g>r\t%0,%2 5984 al<g>rk\t%0,%1,%2 5985 al<g>\t%0,%2 5986 al<y>\t%0,%2" 5987 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5988 (set_attr "cpu_facility" "*,z196,*,longdisp") 5989 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5990 5991 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik 5992 (define_insn "*add<mode>3_carry2_cc" 5993 [(set (reg CC_REGNUM) 5994 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") 5995 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) 5996 (match_dup 2))) 5997 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") 5998 (plus:GPR (match_dup 1) (match_dup 2)))] 5999 "s390_match_ccmode (insn, CCL1mode)" 6000 "@ 6001 al<g>r\t%0,%2 6002 al<g>rk\t%0,%1,%2 6003 al<g>fi\t%0,%2 6004 sl<g>fi\t%0,%n2 6005 al<g>hsik\t%0,%1,%h2 6006 al<g>\t%0,%2 6007 al<y>\t%0,%2 6008 al<g>si\t%0,%c2" 6009 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 6010 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") 6011 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, 6012 z10_super_E1,z10_super_E1,z10_super_E1")]) 6013 6014 ; alr, al, aly, algr, alg, alrk, algrk 6015 (define_insn "*add<mode>3_carry2_cconly" 6016 [(set (reg CC_REGNUM) 6017 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 6018 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6019 (match_dup 2))) 6020 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6021 "s390_match_ccmode (insn, CCL1mode)" 6022 "@ 6023 al<g>r\t%0,%2 6024 al<g>rk\t%0,%1,%2 6025 al<g>\t%0,%2 6026 al<y>\t%0,%2" 6027 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6028 (set_attr "cpu_facility" "*,z196,*,longdisp") 6029 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 6030 6031 ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik 6032 (define_insn "*add<mode>3_cc" 6033 [(set (reg CC_REGNUM) 6034 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") 6035 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) 6036 (const_int 0))) 6037 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") 6038 (plus:GPR (match_dup 1) (match_dup 2)))] 6039 "s390_match_ccmode (insn, CCLmode)" 6040 "@ 6041 al<g>r\t%0,%2 6042 al<g>rk\t%0,%1,%2 6043 al<g>fi\t%0,%2 6044 sl<g>fi\t%0,%n2 6045 al<g>hsik\t%0,%1,%h2 6046 al<g>\t%0,%2 6047 al<y>\t%0,%2 6048 al<g>si\t%0,%c2" 6049 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 6050 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") 6051 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, 6052 *,z10_super_E1,z10_super_E1,z10_super_E1")]) 6053 6054 ; alr, al, aly, algr, alg, alrk, algrk 6055 (define_insn "*add<mode>3_cconly" 6056 [(set (reg CC_REGNUM) 6057 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 6058 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6059 (const_int 0))) 6060 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6061 "s390_match_ccmode (insn, CCLmode)" 6062 "@ 6063 al<g>r\t%0,%2 6064 al<g>rk\t%0,%1,%2 6065 al<g>\t%0,%2 6066 al<y>\t%0,%2" 6067 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6068 (set_attr "cpu_facility" "*,z196,*,longdisp") 6069 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 6070 6071 ; alr, al, aly, algr, alg, alrk, algrk 6072 (define_insn "*add<mode>3_cconly2" 6073 [(set (reg CC_REGNUM) 6074 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 6075 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) 6076 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6077 "s390_match_ccmode(insn, CCLmode)" 6078 "@ 6079 al<g>r\t%0,%2 6080 al<g>rk\t%0,%1,%2 6081 al<g>\t%0,%2 6082 al<y>\t%0,%2" 6083 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6084 (set_attr "cpu_facility" "*,z196,*,longdisp") 6085 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 6086 6087 ; ahi, afi, aghi, agfi, asi, agsi 6088 (define_insn "*add<mode>3_imm_cc" 6089 [(set (reg CC_REGNUM) 6090 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") 6091 (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) 6092 (const_int 0))) 6093 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") 6094 (plus:GPR (match_dup 1) (match_dup 2)))] 6095 "s390_match_ccmode (insn, CCAmode) 6096 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") 6097 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") 6098 /* Avoid INT32_MIN on 32 bit. */ 6099 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" 6100 "@ 6101 a<g>hi\t%0,%h2 6102 a<g>hik\t%0,%1,%h2 6103 a<g>fi\t%0,%2 6104 a<g>si\t%0,%c2" 6105 [(set_attr "op_type" "RI,RIE,RIL,SIY") 6106 (set_attr "cpu_facility" "*,z196,extimm,z10") 6107 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 6108 6109 (define_insn "*adddi3_sign" 6110 [(set (match_operand:DI 0 "register_operand" "=d") 6111 (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) 6112 (match_operand:DI 1 "register_operand" "0"))) 6113 (clobber (reg:CC CC_REGNUM))] 6114 "TARGET_Z14" 6115 "agh\t%0,%2" 6116 [(set_attr "op_type" "RXY")]) 6117 6118 6119 ; Jump to label OP3 if OP1 + OP2 results in a signed overflow 6120 6121 ; addv_const_operand accepts all constants which can be handled 6122 ; without reloads. These will be handled primarily by 6123 ; "*addv<mode>3_ccoverflow_const" which doesn't provide a register 6124 ; alternative. Hence we have to match the operand exactly. 6125 ; For immediates we have to avoid the SIGN_EXTEND around OP2. 6126 (define_expand "addv<mode>4" 6127 [(parallel 6128 [(set (reg:CCO CC_REGNUM) 6129 (compare:CCO (plus:<DBL> 6130 (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) 6131 (match_dup 4)) 6132 (sign_extend:<DBL> (plus:GPR (match_dup 1) 6133 (match_operand:GPR 2 "general_operand"))))) 6134 (set (match_operand:GPR 0 "nonimmediate_operand") 6135 (plus:GPR (match_dup 1) (match_dup 2)))]) 6136 (set (pc) 6137 (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) 6138 (label_ref (match_operand 3)) 6139 (pc)))] 6140 "" 6141 { 6142 if (CONSTANT_P (operands[2]) 6143 && !addv_const_operand (operands[2], GET_MODE (operands[2]))) 6144 operands[2] = force_reg (<GPR:MODE>mode, operands[2]); 6145 6146 if (GET_MODE (operands[2]) != VOIDmode) 6147 operands[4] = gen_rtx_SIGN_EXTEND (<DBL>mode, operands[2]); 6148 else 6149 /* This is what CSE does when propagating a constant into the pattern. */ 6150 operands[4] = simplify_unary_operation (SIGN_EXTEND, <GPR:DBL>mode, operands[2], <GPR:MODE>mode); 6151 }) 6152 6153 ; ark, agrk, ar, ahi, ahik, aghik, a, ay, agr, aghi, ag, asi, agsi 6154 (define_insn "*addv<mode>3_ccoverflow" 6155 [(set (reg CC_REGNUM) 6156 (compare (plus:<DBL> 6157 (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d,0,0,0")) 6158 (sign_extend:<DBL> (match_operand:GPR 2 "general_operand" " d,d,K,K,R,T,C"))) 6159 (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) 6160 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S") 6161 (plus:GPR (match_dup 1) (match_dup 2)))] 6162 "s390_match_ccmode (insn, CCOmode)" 6163 "@ 6164 a<g>r\t%0,%2 6165 a<g>rk\t%0,%1,%2 6166 a<g>hi\t%0,%h2 6167 a<g>hik\t%0,%1,%h2 6168 a<g>\t%0,%2 6169 a<y>\t%0,%2 6170 a<g>si\t%0,%c2" 6171 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RX<Y>,RXY,SIY") 6172 (set_attr "cpu_facility" "*,z196,*,z196,*,longdisp,z10") 6173 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*, 6174 z10_super_E1,z10_super_E1,z10_super_E1")]) 6175 6176 ; ahi, aghi, ahik, aghik, asi, agsi 6177 (define_insn "*addv<mode>3_ccoverflow_const" 6178 [(set (reg CC_REGNUM) 6179 (compare (plus:<DBL> 6180 (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0")) 6181 (match_operand:<DBL> 2 "addv_const_operand" "K,K,C")) 6182 (sign_extend:<DBL> (plus:GPR (match_dup 1) (match_dup 2))))) 6183 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,S") 6184 (plus:GPR (match_dup 1) (match_dup 2)))] 6185 "s390_match_ccmode (insn, CCOmode)" 6186 "@ 6187 a<g>hi\t%0,%h2 6188 a<g>hik\t%0,%1,%h2 6189 a<g>si\t%0,%c2" 6190 [(set_attr "op_type" "RI,RIE,SIY") 6191 (set_attr "cpu_facility" "*,z196,z10") 6192 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 6193 6194 6195 ; 6196 ; add(tf|df|sf|td|dd)3 instruction pattern(s). 6197 ; 6198 6199 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 6200 ; FIXME: wfadb does not clobber cc 6201 (define_insn "add<mode>3<tf_fpr>" 6202 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 6203 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") 6204 (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) 6205 (clobber (reg:CC CC_REGNUM))] 6206 "TARGET_HARD_FLOAT" 6207 "@ 6208 a<xde>tr\t%0,%1,%2 6209 a<xde>br\t%0,%2 6210 a<xde>b\t%0,%2 6211 wfadb\t%v0,%v1,%v2 6212 wfasb\t%v0,%v1,%v2" 6213 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 6214 (set_attr "type" "fsimp<type>") 6215 (set_attr "cpu_facility" "*,*,*,vx,vxe") 6216 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 6217 6218 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 6219 (define_insn "*add<mode>3_cc" 6220 [(set (reg CC_REGNUM) 6221 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") 6222 (match_operand:FP 2 "general_operand" "f,f,R")) 6223 (match_operand:FP 3 "const0_operand" ""))) 6224 (set (match_operand:FP 0 "register_operand" "=f,f,f") 6225 (plus:FP (match_dup 1) (match_dup 2)))] 6226 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 6227 "@ 6228 a<xde>tr\t%0,%1,%2 6229 a<xde>br\t%0,%2 6230 a<xde>b\t%0,%2" 6231 [(set_attr "op_type" "RRF,RRE,RXE") 6232 (set_attr "type" "fsimp<type>") 6233 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 6234 6235 ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 6236 (define_insn "*add<mode>3_cconly" 6237 [(set (reg CC_REGNUM) 6238 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") 6239 (match_operand:FP 2 "general_operand" "f,f,R")) 6240 (match_operand:FP 3 "const0_operand" ""))) 6241 (clobber (match_scratch:FP 0 "=f,f,f"))] 6242 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 6243 "@ 6244 a<xde>tr\t%0,%1,%2 6245 a<xde>br\t%0,%2 6246 a<xde>b\t%0,%2" 6247 [(set_attr "op_type" "RRF,RRE,RXE") 6248 (set_attr "type" "fsimp<type>") 6249 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 6250 6251 ; 6252 ; Pointer add instruction patterns 6253 ; 6254 6255 ; This will match "*la_64" 6256 (define_expand "addptrdi3" 6257 [(set (match_operand:DI 0 "register_operand" "") 6258 (plus:DI (match_operand:DI 1 "register_operand" "") 6259 (match_operand:DI 2 "nonmemory_operand" "")))] 6260 "TARGET_64BIT" 6261 { 6262 if (GET_CODE (operands[2]) == CONST_INT) 6263 { 6264 HOST_WIDE_INT c = INTVAL (operands[2]); 6265 6266 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") 6267 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) 6268 { 6269 operands[2] = force_const_mem (DImode, operands[2]); 6270 operands[2] = force_reg (DImode, operands[2]); 6271 } 6272 else if (!DISP_IN_RANGE (INTVAL (operands[2]))) 6273 operands[2] = force_reg (DImode, operands[2]); 6274 } 6275 }) 6276 6277 ; For 31 bit we have to prevent the generated pattern from matching 6278 ; normal ADDs since la only does a 31 bit add. This is supposed to 6279 ; match "force_la_31". 6280 (define_expand "addptrsi3" 6281 [(parallel 6282 [(set (match_operand:SI 0 "register_operand" "") 6283 (plus:SI (match_operand:SI 1 "register_operand" "") 6284 (match_operand:SI 2 "nonmemory_operand" ""))) 6285 (use (const_int 0))])] 6286 "!TARGET_64BIT" 6287 { 6288 if (GET_CODE (operands[2]) == CONST_INT) 6289 { 6290 HOST_WIDE_INT c = INTVAL (operands[2]); 6291 6292 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") 6293 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) 6294 { 6295 operands[2] = force_const_mem (SImode, operands[2]); 6296 operands[2] = force_reg (SImode, operands[2]); 6297 } 6298 else if (!DISP_IN_RANGE (INTVAL (operands[2]))) 6299 operands[2] = force_reg (SImode, operands[2]); 6300 } 6301 }) 6302 6303 ;; 6304 ;;- Subtract instructions. 6305 ;; 6306 6307 ; 6308 ; subti3 instruction pattern(s). 6309 ; 6310 6311 (define_expand "subti3" 6312 [(parallel 6313 [(set (match_operand:TI 0 "register_operand" "") 6314 (minus:TI (match_operand:TI 1 "register_operand" "") 6315 (match_operand:TI 2 "general_operand" "") ) ) 6316 (clobber (reg:CC CC_REGNUM))])] 6317 "TARGET_ZARCH" 6318 { 6319 /* For z13 we have vsq which doesn't set CC. */ 6320 if (TARGET_VX) 6321 { 6322 emit_insn (gen_rtx_SET (operands[0], 6323 gen_rtx_MINUS (TImode, 6324 operands[1], 6325 copy_to_mode_reg (TImode, operands[2])))); 6326 DONE; 6327 } 6328 }) 6329 6330 (define_insn_and_split "*subti3" 6331 [(set (match_operand:TI 0 "register_operand" "=&d") 6332 (minus:TI (match_operand:TI 1 "register_operand" "0") 6333 (match_operand:TI 2 "general_operand" "do") ) ) 6334 (clobber (reg:CC CC_REGNUM))] 6335 "TARGET_ZARCH" 6336 "#" 6337 "&& reload_completed" 6338 [(parallel 6339 [(set (reg:CCL2 CC_REGNUM) 6340 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) 6341 (match_dup 7))) 6342 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) 6343 (parallel 6344 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) 6345 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) 6346 (clobber (reg:CC CC_REGNUM))])] 6347 "operands[3] = operand_subword (operands[0], 0, 0, TImode); 6348 operands[4] = operand_subword (operands[1], 0, 0, TImode); 6349 operands[5] = operand_subword (operands[2], 0, 0, TImode); 6350 operands[6] = operand_subword (operands[0], 1, 0, TImode); 6351 operands[7] = operand_subword (operands[1], 1, 0, TImode); 6352 operands[8] = operand_subword (operands[2], 1, 0, TImode);" 6353 [(set_attr "op_type" "*") 6354 (set_attr "cpu_facility" "*")]) 6355 6356 ; 6357 ; subdi3 instruction pattern(s). 6358 ; 6359 6360 (define_expand "subdi3" 6361 [(parallel 6362 [(set (match_operand:DI 0 "register_operand" "") 6363 (minus:DI (match_operand:DI 1 "register_operand" "") 6364 (match_operand:DI 2 "general_operand" ""))) 6365 (clobber (reg:CC CC_REGNUM))])] 6366 "" 6367 "") 6368 6369 (define_insn "*subdi3_sign" 6370 [(set (match_operand:DI 0 "register_operand" "=d,d") 6371 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6372 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) 6373 (clobber (reg:CC CC_REGNUM))] 6374 "TARGET_ZARCH" 6375 "@ 6376 sgfr\t%0,%2 6377 sgf\t%0,%2" 6378 [(set_attr "op_type" "RRE,RXY") 6379 (set_attr "z10prop" "z10_c,*") 6380 (set_attr "z196prop" "z196_cracked")]) 6381 6382 (define_insn "*subdi3_zero_cc" 6383 [(set (reg CC_REGNUM) 6384 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6385 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) 6386 (const_int 0))) 6387 (set (match_operand:DI 0 "register_operand" "=d,d") 6388 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] 6389 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 6390 "@ 6391 slgfr\t%0,%2 6392 slgf\t%0,%2" 6393 [(set_attr "op_type" "RRE,RXY") 6394 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 6395 6396 (define_insn "*subdi3_zero_cconly" 6397 [(set (reg CC_REGNUM) 6398 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6399 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) 6400 (const_int 0))) 6401 (clobber (match_scratch:DI 0 "=d,d"))] 6402 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 6403 "@ 6404 slgfr\t%0,%2 6405 slgf\t%0,%2" 6406 [(set_attr "op_type" "RRE,RXY") 6407 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 6408 6409 (define_insn "*subdi3_zero" 6410 [(set (match_operand:DI 0 "register_operand" "=d,d") 6411 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 6412 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) 6413 (clobber (reg:CC CC_REGNUM))] 6414 "TARGET_ZARCH" 6415 "@ 6416 slgfr\t%0,%2 6417 slgf\t%0,%2" 6418 [(set_attr "op_type" "RRE,RXY") 6419 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 6420 6421 (define_insn_and_split "*subdi3_31z" 6422 [(set (match_operand:DI 0 "register_operand" "=&d") 6423 (minus:DI (match_operand:DI 1 "register_operand" "0") 6424 (match_operand:DI 2 "general_operand" "do") ) ) 6425 (clobber (reg:CC CC_REGNUM))] 6426 "!TARGET_ZARCH" 6427 "#" 6428 "&& reload_completed" 6429 [(parallel 6430 [(set (reg:CCL2 CC_REGNUM) 6431 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 6432 (match_dup 7))) 6433 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 6434 (parallel 6435 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) 6436 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) 6437 (clobber (reg:CC CC_REGNUM))])] 6438 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 6439 operands[4] = operand_subword (operands[1], 0, 0, DImode); 6440 operands[5] = operand_subword (operands[2], 0, 0, DImode); 6441 operands[6] = operand_subword (operands[0], 1, 0, DImode); 6442 operands[7] = operand_subword (operands[1], 1, 0, DImode); 6443 operands[8] = operand_subword (operands[2], 1, 0, DImode);") 6444 6445 ; 6446 ; subsi3 instruction pattern(s). 6447 ; 6448 6449 (define_expand "subsi3" 6450 [(parallel 6451 [(set (match_operand:SI 0 "register_operand" "") 6452 (minus:SI (match_operand:SI 1 "register_operand" "") 6453 (match_operand:SI 2 "general_operand" ""))) 6454 (clobber (reg:CC CC_REGNUM))])] 6455 "" 6456 "") 6457 6458 (define_insn "*subsi3_sign" 6459 [(set (match_operand:SI 0 "register_operand" "=d,d") 6460 (minus:SI (match_operand:SI 1 "register_operand" "0,0") 6461 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) 6462 (clobber (reg:CC CC_REGNUM))] 6463 "" 6464 "@ 6465 sh\t%0,%2 6466 shy\t%0,%2" 6467 [(set_attr "op_type" "RX,RXY") 6468 (set_attr "cpu_facility" "*,longdisp") 6469 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 6470 6471 ; 6472 ; sub(di|si)3 instruction pattern(s). 6473 ; 6474 6475 ; sr, s, sy, sgr, sg, srk, sgrk 6476 (define_insn "*sub<mode>3" 6477 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6478 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6479 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) 6480 (clobber (reg:CC CC_REGNUM))] 6481 "" 6482 "@ 6483 s<g>r\t%0,%2 6484 s<g>rk\t%0,%1,%2 6485 s<g>\t%0,%2 6486 s<y>\t%0,%2" 6487 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6488 (set_attr "cpu_facility" "*,z196,*,longdisp") 6489 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6490 6491 ; slr, sl, sly, slgr, slg, slrk, slgrk 6492 (define_insn "*sub<mode>3_borrow_cc" 6493 [(set (reg CC_REGNUM) 6494 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6495 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6496 (match_dup 1))) 6497 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6498 (minus:GPR (match_dup 1) (match_dup 2)))] 6499 "s390_match_ccmode (insn, CCL2mode)" 6500 "@ 6501 sl<g>r\t%0,%2 6502 sl<g>rk\t%0,%1,%2 6503 sl<g>\t%0,%2 6504 sl<y>\t%0,%2" 6505 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6506 (set_attr "cpu_facility" "*,z196,*,longdisp") 6507 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6508 6509 ; slr, sl, sly, slgr, slg, slrk, slgrk 6510 (define_insn "*sub<mode>3_borrow_cconly" 6511 [(set (reg CC_REGNUM) 6512 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6513 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6514 (match_dup 1))) 6515 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6516 "s390_match_ccmode (insn, CCL2mode)" 6517 "@ 6518 sl<g>r\t%0,%2 6519 sl<g>rk\t%0,%1,%2 6520 sl<g>\t%0,%2 6521 sl<y>\t%0,%2" 6522 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6523 (set_attr "cpu_facility" "*,z196,*,longdisp") 6524 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6525 6526 ; slr, sl, sly, slgr, slg, slrk, slgrk 6527 (define_insn "*sub<mode>3_cc" 6528 [(set (reg CC_REGNUM) 6529 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6530 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6531 (const_int 0))) 6532 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6533 (minus:GPR (match_dup 1) (match_dup 2)))] 6534 "s390_match_ccmode (insn, CCLmode)" 6535 "@ 6536 sl<g>r\t%0,%2 6537 sl<g>rk\t%0,%1,%2 6538 sl<g>\t%0,%2 6539 sl<y>\t%0,%2" 6540 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6541 (set_attr "cpu_facility" "*,z196,*,longdisp") 6542 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6543 6544 ; slr, sl, sly, slgr, slg, slrk, slgrk 6545 (define_insn "*sub<mode>3_cc2" 6546 [(set (reg CC_REGNUM) 6547 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") 6548 (match_operand:GPR 2 "general_operand" "d,d,R,T"))) 6549 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6550 (minus:GPR (match_dup 1) (match_dup 2)))] 6551 "s390_match_ccmode (insn, CCL3mode)" 6552 "@ 6553 sl<g>r\t%0,%2 6554 sl<g>rk\t%0,%1,%2 6555 sl<g>\t%0,%2 6556 sl<y>\t%0,%2" 6557 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6558 (set_attr "cpu_facility" "*,z196,*,longdisp") 6559 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6560 6561 ; slr, sl, sly, slgr, slg, slrk, slgrk 6562 (define_insn "*sub<mode>3_cconly" 6563 [(set (reg CC_REGNUM) 6564 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 6565 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 6566 (const_int 0))) 6567 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6568 "s390_match_ccmode (insn, CCLmode)" 6569 "@ 6570 sl<g>r\t%0,%2 6571 sl<g>rk\t%0,%1,%2 6572 sl<g>\t%0,%2 6573 sl<y>\t%0,%2" 6574 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6575 (set_attr "cpu_facility" "*,z196,*,longdisp") 6576 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6577 6578 6579 ; slr, sl, sly, slgr, slg, slrk, slgrk 6580 (define_insn "*sub<mode>3_cconly2" 6581 [(set (reg CC_REGNUM) 6582 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") 6583 (match_operand:GPR 2 "general_operand" "d,d,R,T"))) 6584 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 6585 "s390_match_ccmode (insn, CCL3mode)" 6586 "@ 6587 sl<g>r\t%0,%2 6588 sl<g>rk\t%0,%1,%2 6589 sl<g>\t%0,%2 6590 sl<y>\t%0,%2" 6591 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6592 (set_attr "cpu_facility" "*,z196,*,longdisp") 6593 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6594 6595 (define_insn "*subdi3_sign" 6596 [(set (match_operand:DI 0 "register_operand" "=d") 6597 (minus:DI (match_operand:DI 1 "register_operand" "0") 6598 (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) 6599 (clobber (reg:CC CC_REGNUM))] 6600 "TARGET_Z14" 6601 "sgh\t%0,%2" 6602 [(set_attr "op_type" "RXY")]) 6603 6604 ; Jump to label OP3 if OP1 - OP2 results in a signed overflow 6605 (define_expand "subv<mode>4" 6606 [(parallel 6607 [(set (reg:CCO CC_REGNUM) 6608 (compare:CCO (minus:<DBL> 6609 (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand")) 6610 (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) 6611 (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) 6612 (set (match_operand:GPR 0 "nonimmediate_operand") 6613 (minus:GPR (match_dup 1) (match_dup 2)))]) 6614 (set (pc) 6615 (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) 6616 (label_ref (match_operand 3)) 6617 (pc)))] 6618 "") 6619 6620 ; sr, s, sy, sgr, sg, srk, sgrk 6621 (define_insn "*subv<mode>3_ccoverflow" 6622 [(set (reg CC_REGNUM) 6623 (compare (minus:<DBL> 6624 (sign_extend:<DBL> (match_operand:GPR 1 "nonimmediate_operand" "0,d,0,0")) 6625 (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" "d,d,R,T"))) 6626 (sign_extend:<DBL> (minus:GPR (match_dup 1) (match_dup 2))))) 6627 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 6628 (minus:GPR (match_dup 1) (match_dup 2)))] 6629 "s390_match_ccmode (insn, CCOmode)" 6630 "@ 6631 s<g>r\t%0,%2 6632 s<g>rk\t%0,%1,%2 6633 s<g>\t%0,%2 6634 s<y>\t%0,%2" 6635 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 6636 (set_attr "cpu_facility" "*,z196,*,longdisp") 6637 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 6638 6639 6640 ; 6641 ; sub(tf|df|sf|td|dd)3 instruction pattern(s). 6642 ; 6643 6644 ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? 6645 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 6646 (define_insn "sub<mode>3<tf_fpr>" 6647 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 6648 (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") 6649 (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) 6650 (clobber (reg:CC CC_REGNUM))] 6651 "TARGET_HARD_FLOAT" 6652 "@ 6653 s<xde>tr\t%0,%1,%2 6654 s<xde>br\t%0,%2 6655 s<xde>b\t%0,%2 6656 wfsdb\t%v0,%v1,%v2 6657 wfssb\t%v0,%v1,%v2" 6658 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 6659 (set_attr "type" "fsimp<type>") 6660 (set_attr "cpu_facility" "*,*,*,vx,vxe") 6661 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 6662 6663 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 6664 (define_insn "*sub<mode>3_cc" 6665 [(set (reg CC_REGNUM) 6666 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") 6667 (match_operand:FP 2 "general_operand" "f,f,R")) 6668 (match_operand:FP 3 "const0_operand" ""))) 6669 (set (match_operand:FP 0 "register_operand" "=f,f,f") 6670 (minus:FP (match_dup 1) (match_dup 2)))] 6671 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 6672 "@ 6673 s<xde>tr\t%0,%1,%2 6674 s<xde>br\t%0,%2 6675 s<xde>b\t%0,%2" 6676 [(set_attr "op_type" "RRF,RRE,RXE") 6677 (set_attr "type" "fsimp<type>") 6678 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 6679 6680 ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 6681 (define_insn "*sub<mode>3_cconly" 6682 [(set (reg CC_REGNUM) 6683 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") 6684 (match_operand:FP 2 "general_operand" "f,f,R")) 6685 (match_operand:FP 3 "const0_operand" ""))) 6686 (clobber (match_scratch:FP 0 "=f,f,f"))] 6687 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 6688 "@ 6689 s<xde>tr\t%0,%1,%2 6690 s<xde>br\t%0,%2 6691 s<xde>b\t%0,%2" 6692 [(set_attr "op_type" "RRF,RRE,RXE") 6693 (set_attr "type" "fsimp<type>") 6694 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) 6695 6696 6697 ;; 6698 ;;- Conditional add/subtract instructions. 6699 ;; 6700 6701 ; 6702 ; add(di|si)cc instruction pattern(s). 6703 ; 6704 6705 ; the following 4 patterns are used when the result of an add with 6706 ; carry is checked for an overflow condition 6707 6708 ; op1 + op2 + c < op1 6709 6710 ; alcr, alc, alcgr, alcg 6711 (define_insn "*add<mode>3_alc_carry1_cc" 6712 [(set (reg CC_REGNUM) 6713 (compare 6714 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6715 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6716 (match_operand:GPR 2 "general_operand" "d,T")) 6717 (match_dup 1))) 6718 (set (match_operand:GPR 0 "register_operand" "=d,d") 6719 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 6720 "s390_match_ccmode (insn, CCL1mode)" 6721 "@ 6722 alc<g>r\t%0,%2 6723 alc<g>\t%0,%2" 6724 [(set_attr "op_type" "RRE,RXY") 6725 (set_attr "z196prop" "z196_alone,z196_alone")]) 6726 6727 ; alcr, alc, alcgr, alcg 6728 (define_insn "*add<mode>3_alc_carry1_cconly" 6729 [(set (reg CC_REGNUM) 6730 (compare 6731 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6732 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6733 (match_operand:GPR 2 "general_operand" "d,T")) 6734 (match_dup 1))) 6735 (clobber (match_scratch:GPR 0 "=d,d"))] 6736 "s390_match_ccmode (insn, CCL1mode)" 6737 "@ 6738 alc<g>r\t%0,%2 6739 alc<g>\t%0,%2" 6740 [(set_attr "op_type" "RRE,RXY") 6741 (set_attr "z196prop" "z196_alone,z196_alone")]) 6742 6743 ; op1 + op2 + c < op2 6744 6745 ; alcr, alc, alcgr, alcg 6746 (define_insn "*add<mode>3_alc_carry2_cc" 6747 [(set (reg CC_REGNUM) 6748 (compare 6749 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6750 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6751 (match_operand:GPR 2 "general_operand" "d,T")) 6752 (match_dup 2))) 6753 (set (match_operand:GPR 0 "register_operand" "=d,d") 6754 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 6755 "s390_match_ccmode (insn, CCL1mode)" 6756 "@ 6757 alc<g>r\t%0,%2 6758 alc<g>\t%0,%2" 6759 [(set_attr "op_type" "RRE,RXY")]) 6760 6761 ; alcr, alc, alcgr, alcg 6762 (define_insn "*add<mode>3_alc_carry2_cconly" 6763 [(set (reg CC_REGNUM) 6764 (compare 6765 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6766 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6767 (match_operand:GPR 2 "general_operand" "d,T")) 6768 (match_dup 2))) 6769 (clobber (match_scratch:GPR 0 "=d,d"))] 6770 "s390_match_ccmode (insn, CCL1mode)" 6771 "@ 6772 alc<g>r\t%0,%2 6773 alc<g>\t%0,%2" 6774 [(set_attr "op_type" "RRE,RXY")]) 6775 6776 ; alcr, alc, alcgr, alcg 6777 (define_insn "*add<mode>3_alc_cc" 6778 [(set (reg CC_REGNUM) 6779 (compare 6780 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6781 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6782 (match_operand:GPR 2 "general_operand" "d,T")) 6783 (const_int 0))) 6784 (set (match_operand:GPR 0 "register_operand" "=d,d") 6785 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 6786 "s390_match_ccmode (insn, CCLmode)" 6787 "@ 6788 alc<g>r\t%0,%2 6789 alc<g>\t%0,%2" 6790 [(set_attr "op_type" "RRE,RXY")]) 6791 6792 ; alcr, alc, alcgr, alcg 6793 (define_insn "*add<mode>3_alc" 6794 [(set (match_operand:GPR 0 "register_operand" "=d,d") 6795 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 6796 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 6797 (match_operand:GPR 2 "general_operand" "d,T"))) 6798 (clobber (reg:CC CC_REGNUM))] 6799 "" 6800 "@ 6801 alc<g>r\t%0,%2 6802 alc<g>\t%0,%2" 6803 [(set_attr "op_type" "RRE,RXY")]) 6804 6805 ; slbr, slb, slbgr, slbg 6806 (define_insn "*sub<mode>3_slb_cc" 6807 [(set (reg CC_REGNUM) 6808 (compare 6809 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") 6810 (match_operand:GPR 2 "general_operand" "d,T")) 6811 (match_operand:GPR 3 "s390_slb_comparison" "")) 6812 (const_int 0))) 6813 (set (match_operand:GPR 0 "register_operand" "=d,d") 6814 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] 6815 "s390_match_ccmode (insn, CCLmode)" 6816 "@ 6817 slb<g>r\t%0,%2 6818 slb<g>\t%0,%2" 6819 [(set_attr "op_type" "RRE,RXY") 6820 (set_attr "z10prop" "z10_c,*")]) 6821 6822 ; slbr, slb, slbgr, slbg 6823 (define_insn "*sub<mode>3_slb" 6824 [(set (match_operand:GPR 0 "register_operand" "=d,d") 6825 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") 6826 (match_operand:GPR 2 "general_operand" "d,T")) 6827 (match_operand:GPR 3 "s390_slb_comparison" ""))) 6828 (clobber (reg:CC CC_REGNUM))] 6829 "" 6830 "@ 6831 slb<g>r\t%0,%2 6832 slb<g>\t%0,%2" 6833 [(set_attr "op_type" "RRE,RXY") 6834 (set_attr "z10prop" "z10_c,*")]) 6835 6836 (define_expand "add<mode>cc" 6837 [(match_operand:GPR 0 "register_operand" "") 6838 (match_operand 1 "comparison_operator" "") 6839 (match_operand:GPR 2 "register_operand" "") 6840 (match_operand:GPR 3 "const_int_operand" "")] 6841 "" 6842 "if (!s390_expand_addcc (GET_CODE (operands[1]), 6843 XEXP (operands[1], 0), XEXP (operands[1], 1), 6844 operands[0], operands[2], 6845 operands[3])) FAIL; DONE;") 6846 6847 ; 6848 ; scond instruction pattern(s). 6849 ; 6850 6851 (define_insn_and_split "*scond<mode>" 6852 [(set (match_operand:GPR 0 "register_operand" "=&d") 6853 (match_operand:GPR 1 "s390_alc_comparison" "")) 6854 (clobber (reg:CC CC_REGNUM))] 6855 "" 6856 "#" 6857 "&& reload_completed" 6858 [(set (match_dup 0) (const_int 0)) 6859 (parallel 6860 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) 6861 (match_dup 0))) 6862 (clobber (reg:CC CC_REGNUM))])] 6863 "") 6864 6865 (define_insn_and_split "*scond<mode>_neg" 6866 [(set (match_operand:GPR 0 "register_operand" "=&d") 6867 (match_operand:GPR 1 "s390_slb_comparison" "")) 6868 (clobber (reg:CC CC_REGNUM))] 6869 "" 6870 "#" 6871 "&& reload_completed" 6872 [(set (match_dup 0) (const_int 0)) 6873 (parallel 6874 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) 6875 (match_dup 1))) 6876 (clobber (reg:CC CC_REGNUM))]) 6877 (parallel 6878 [(set (match_dup 0) (neg:GPR (match_dup 0))) 6879 (clobber (reg:CC CC_REGNUM))])] 6880 "") 6881 6882 6883 (define_expand "cstore<mode>4" 6884 [(set (match_operand:SI 0 "register_operand" "") 6885 (match_operator:SI 1 "s390_scond_operator" 6886 [(match_operand:GPR 2 "register_operand" "") 6887 (match_operand:GPR 3 "general_operand" "")]))] 6888 "" 6889 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], 6890 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") 6891 6892 (define_expand "cstorecc4" 6893 [(parallel 6894 [(set (match_operand:SI 0 "register_operand" "") 6895 (match_operator:SI 1 "s390_eqne_operator" 6896 [(match_operand 2 "cc_reg_operand") 6897 (match_operand 3 "const0_operand")])) 6898 (clobber (reg:CC CC_REGNUM))])] 6899 "" 6900 "machine_mode mode = GET_MODE (operands[2]); 6901 if (TARGET_Z196) 6902 { 6903 rtx cond, ite; 6904 6905 if (GET_CODE (operands[1]) == NE) 6906 cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); 6907 else 6908 cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); 6909 ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); 6910 emit_insn (gen_rtx_SET (operands[0], ite)); 6911 } 6912 else 6913 { 6914 if (mode != CCZ1mode) 6915 FAIL; 6916 emit_insn (gen_sne (operands[0], operands[2])); 6917 if (GET_CODE (operands[1]) == EQ) 6918 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); 6919 } 6920 DONE;") 6921 6922 (define_insn_and_split "sne" 6923 [(set (match_operand:SI 0 "register_operand" "=d") 6924 (ne:SI (match_operand:CCZ1 1 "register_operand" "0") 6925 (const_int 0))) 6926 (clobber (reg:CC CC_REGNUM))] 6927 "" 6928 "#" 6929 "reload_completed" 6930 [(parallel 6931 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) 6932 (clobber (reg:CC CC_REGNUM))])]) 6933 6934 ; Such patterns get directly emitted by noce_emit_store_flag. 6935 (define_insn_and_split "*cstorecc<mode>_z13" 6936 [(set (match_operand:GPR 0 "register_operand" "=&d") 6937 (match_operator:GPR 1 "s390_comparison" 6938 [(match_operand 2 "cc_reg_operand" "c") 6939 (match_operand 3 "const_int_operand" "")]))] 6940 "TARGET_Z13" 6941 "#" 6942 "reload_completed" 6943 [(set (match_dup 0) (const_int 0)) 6944 (set (match_dup 0) 6945 (if_then_else:GPR 6946 (match_op_dup 1 [(match_dup 2) (match_dup 3)]) 6947 (const_int 1) 6948 (match_dup 0)))]) 6949 6950 ;; 6951 ;; - Conditional move instructions (introduced with z196) 6952 ;; 6953 6954 (define_expand "mov<mode>cc" 6955 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 6956 (if_then_else:GPR (match_operand 1 "comparison_operator" "") 6957 (match_operand:GPR 2 "loc_operand" "") 6958 (match_operand:GPR 3 "loc_operand" "")))] 6959 "TARGET_Z196" 6960 { 6961 if (!TARGET_Z13 && CONSTANT_P (operands[2])) 6962 operands[2] = force_reg (<MODE>mode, operands[2]); 6963 6964 if (!TARGET_Z13 && CONSTANT_P (operands[3])) 6965 operands[3] = force_reg (<MODE>mode, operands[3]); 6966 6967 /* Emit the comparison insn in case we do not already have a comparison result. */ 6968 if (!s390_comparison (operands[1], VOIDmode)) 6969 operands[1] = s390_emit_compare (GET_CODE (operands[1]), 6970 XEXP (operands[1], 0), 6971 XEXP (operands[1], 1)); 6972 }) 6973 6974 ;; 6975 ;; - We do not have instructions for QImode or HImode but still 6976 ;; enable load on condition/if conversion for them. 6977 (define_expand "mov<mode>cc" 6978 [(set (match_operand:HQI 0 "nonimmediate_operand" "") 6979 (if_then_else:HQI (match_operand 1 "comparison_operator" "") 6980 (match_operand:HQI 2 "loc_operand" "") 6981 (match_operand:HQI 3 "loc_operand" "")))] 6982 "TARGET_Z196" 6983 { 6984 /* Emit the comparison insn in case we do not already have a comparison 6985 result. */ 6986 if (!s390_comparison (operands[1], VOIDmode)) 6987 operands[1] = s390_emit_compare (GET_CODE (operands[1]), 6988 XEXP (operands[1], 0), 6989 XEXP (operands[1], 1)); 6990 6991 rtx then = operands[2]; 6992 rtx els = operands[3]; 6993 6994 if ((!TARGET_Z13 && CONSTANT_P (then)) || MEM_P (then)) 6995 then = force_reg (<MODE>mode, then); 6996 if ((!TARGET_Z13 && CONSTANT_P (els)) || MEM_P (els)) 6997 els = force_reg (<MODE>mode, els); 6998 6999 if (!CONSTANT_P (then)) 7000 then = simplify_gen_subreg (E_SImode, then, <MODE>mode, 0); 7001 if (!CONSTANT_P (els)) 7002 els = simplify_gen_subreg (E_SImode, els, <MODE>mode, 0); 7003 7004 rtx tmp_target = simplify_gen_subreg (E_SImode, operands[0], <MODE>mode, 0); 7005 7006 emit_insn (gen_movsicc (tmp_target, operands[1], then, els)); 7007 DONE; 7008 }) 7009 7010 7011 7012 ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi, selr, selgr 7013 (define_insn "*mov<mode>cc" 7014 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,S,S") 7015 (if_then_else:GPR 7016 (match_operator 1 "s390_comparison" 7017 [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c") 7018 (match_operand 5 "const_int_operand" "")]) 7019 (match_operand:GPR 3 "loc_operand" " d,0,d,S,0,K,0,d,0") 7020 (match_operand:GPR 4 "loc_operand" " 0,d,d,0,S,0,K,0,d")))] 7021 "TARGET_Z196" 7022 "@ 7023 loc<g>r%C1\t%0,%3 7024 loc<g>r%D1\t%0,%4 7025 sel<g>r%C1\t%0,%3,%4 7026 loc<g>%C1\t%0,%3 7027 loc<g>%D1\t%0,%4 7028 loc<g>hi%C1\t%0,%h3 7029 loc<g>hi%D1\t%0,%h4 7030 stoc<g>%C1\t%3,%0 7031 stoc<g>%D1\t%4,%0" 7032 [(set_attr "op_type" "RRF,RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") 7033 (set_attr "cpu_facility" "*,*,z15,*,*,z13,z13,*,*")]) 7034 7035 ;; 7036 ;;- Multiply instructions. 7037 ;; 7038 7039 ; 7040 ; muldi3 instruction pattern(s). 7041 ; 7042 7043 (define_expand "muldi3" 7044 [(parallel 7045 [(set (match_operand:DI 0 "register_operand") 7046 (mult:DI (match_operand:DI 1 "nonimmediate_operand") 7047 (match_operand:DI 2 "general_operand"))) 7048 (clobber (reg:CC CC_REGNUM))])] 7049 "TARGET_ZARCH") 7050 7051 (define_insn "*muldi3_sign" 7052 [(set (match_operand:DI 0 "register_operand" "=d,d") 7053 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) 7054 (match_operand:DI 1 "register_operand" "0,0")))] 7055 "TARGET_ZARCH" 7056 "@ 7057 msgfr\t%0,%2 7058 msgf\t%0,%2" 7059 [(set_attr "op_type" "RRE,RXY") 7060 (set_attr "type" "imuldi")]) 7061 7062 (define_insn "*muldi3" 7063 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") 7064 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") 7065 (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) 7066 (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] 7067 "TARGET_ZARCH" 7068 "@ 7069 msgr\t%0,%2 7070 msgrkc\t%0,%1,%2 7071 mghi\t%0,%h2 7072 msg\t%0,%2 7073 msgfi\t%0,%2" 7074 [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") 7075 (set_attr "type" "imuldi") 7076 (set_attr "cpu_facility" "*,z14,*,*,z10")]) 7077 7078 (define_insn "mulditi3" 7079 [(set (match_operand:TI 0 "register_operand" "=d,d") 7080 (mult:TI (sign_extend:TI 7081 (match_operand:DI 1 "register_operand" "%d,0")) 7082 (sign_extend:TI 7083 (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] 7084 "TARGET_Z14" 7085 "@ 7086 mgrk\t%0,%1,%2 7087 mg\t%0,%2" 7088 [(set_attr "op_type" "RRF,RXY")]) 7089 7090 ; Combine likes op1 and op2 to be swapped sometimes. 7091 (define_insn "mulditi3_2" 7092 [(set (match_operand:TI 0 "register_operand" "=d,d") 7093 (mult:TI (sign_extend:TI 7094 (match_operand:DI 1 "nonimmediate_operand" "%d,T")) 7095 (sign_extend:TI 7096 (match_operand:DI 2 "register_operand" " d,0"))))] 7097 "TARGET_Z14" 7098 "@ 7099 mgrk\t%0,%1,%2 7100 mg\t%0,%1" 7101 [(set_attr "op_type" "RRF,RXY")]) 7102 7103 (define_insn "*muldi3_sign" 7104 [(set (match_operand:DI 0 "register_operand" "=d") 7105 (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) 7106 (match_operand:DI 1 "register_operand" "0")))] 7107 "TARGET_Z14" 7108 "mgh\t%0,%2" 7109 [(set_attr "op_type" "RXY")]) 7110 7111 7112 ; 7113 ; mulsi3 instruction pattern(s). 7114 ; 7115 7116 (define_expand "mulsi3" 7117 [(parallel 7118 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") 7119 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 7120 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) 7121 (clobber (reg:CC CC_REGNUM))])] 7122 "") 7123 7124 (define_insn "*mulsi3_sign" 7125 [(set (match_operand:SI 0 "register_operand" "=d,d") 7126 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) 7127 (match_operand:SI 1 "register_operand" "0,0")))] 7128 "" 7129 "@ 7130 mh\t%0,%2 7131 mhy\t%0,%2" 7132 [(set_attr "op_type" "RX,RXY") 7133 (set_attr "type" "imulhi") 7134 (set_attr "cpu_facility" "*,z10")]) 7135 7136 (define_insn "*mulsi3" 7137 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") 7138 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 7139 (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) 7140 (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] 7141 "" 7142 "@ 7143 msr\t%0,%2 7144 msrkc\t%0,%1,%2 7145 mhi\t%0,%h2 7146 ms\t%0,%2 7147 msy\t%0,%2 7148 msfi\t%0,%2" 7149 [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") 7150 (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") 7151 (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")]) 7152 7153 ; 7154 ; mulsidi3 instruction pattern(s). 7155 ; 7156 7157 (define_insn "mulsidi3" 7158 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 7159 (mult:DI (sign_extend:DI 7160 (match_operand:SI 1 "register_operand" "%0,0,0")) 7161 (sign_extend:DI 7162 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] 7163 "!TARGET_ZARCH" 7164 "@ 7165 mr\t%0,%2 7166 m\t%0,%2 7167 mfy\t%0,%2" 7168 [(set_attr "op_type" "RR,RX,RXY") 7169 (set_attr "type" "imulsi") 7170 (set_attr "cpu_facility" "*,*,z10")]) 7171 7172 ; Jump to label OP3 if OP1 * OP2 results in a signed overflow 7173 (define_expand "mulv<mode>4" 7174 [(parallel 7175 [(set (reg:CCO CC_REGNUM) 7176 (compare:CCO (mult:<DBL> 7177 (sign_extend:<DBL> (match_operand:GPR 1 "register_operand")) 7178 (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand"))) 7179 (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) 7180 (set (match_operand:GPR 0 "register_operand") 7181 (mult:GPR (match_dup 1) (match_dup 2)))]) 7182 (set (pc) 7183 (if_then_else (ne (reg:CCO CC_REGNUM) (const_int 0)) 7184 (label_ref (match_operand 3)) 7185 (pc)))] 7186 "TARGET_Z14") 7187 7188 ; msrkc, msc, msgrkc, msgc 7189 (define_insn "*mulv<mode>3_ccoverflow" 7190 [(set (reg CC_REGNUM) 7191 (compare (mult:<DBL> 7192 (sign_extend:<DBL> (match_operand:GPR 1 "register_operand" "%d,0")) 7193 (sign_extend:<DBL> (match_operand:GPR 2 "nonimmediate_operand" " d,T"))) 7194 (sign_extend:<DBL> (mult:GPR (match_dup 1) (match_dup 2))))) 7195 (set (match_operand:GPR 0 "register_operand" "=d,d") 7196 (mult:GPR (match_dup 1) (match_dup 2)))] 7197 "s390_match_ccmode (insn, CCOmode) && TARGET_Z14" 7198 "@ 7199 ms<g>rkc\t%0,%1,%2 7200 ms<g>c\t%0,%2" 7201 [(set_attr "op_type" "RRF,RXY")]) 7202 7203 7204 ; 7205 ; umul instruction pattern(s). 7206 ; 7207 7208 ; mlr, ml, mlgr, mlg 7209 (define_insn "umul<dwh><mode>3" 7210 [(set (match_operand:DW 0 "register_operand" "=d,d") 7211 (mult:DW (zero_extend:DW 7212 (match_operand:<DWH> 1 "register_operand" "%0,0")) 7213 (zero_extend:DW 7214 (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] 7215 "" 7216 "@ 7217 ml<tg>r\t%0,%2 7218 ml<tg>\t%0,%2" 7219 [(set_attr "op_type" "RRE,RXY") 7220 (set_attr "type" "imul<dwh>")]) 7221 7222 ; 7223 ; mul(tf|df|sf|td|dd)3 instruction pattern(s). 7224 ; 7225 7226 ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr 7227 (define_insn "mul<mode>3<tf_fpr>" 7228 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 7229 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") 7230 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] 7231 "TARGET_HARD_FLOAT" 7232 "@ 7233 m<xdee>tr\t%0,%1,%2 7234 m<xdee>br\t%0,%2 7235 m<xdee>b\t%0,%2 7236 wfmdb\t%v0,%v1,%v2 7237 wfmsb\t%v0,%v1,%v2" 7238 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 7239 (set_attr "type" "fmul<type>") 7240 (set_attr "cpu_facility" "*,*,*,vx,vxe") 7241 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 7242 7243 ; madbr, maebr, maxb, madb, maeb 7244 (define_insn "fma<mode>4" 7245 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") 7246 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") 7247 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") 7248 (match_operand:DSF 3 "register_operand" "0,0,v,v")))] 7249 "TARGET_HARD_FLOAT && s390_fma_allowed_p (<MODE>mode)" 7250 "@ 7251 ma<xde>br\t%0,%1,%2 7252 ma<xde>b\t%0,%1,%2 7253 wfmadb\t%v0,%v1,%v2,%v3 7254 wfmasb\t%v0,%v1,%v2,%v3" 7255 [(set_attr "op_type" "RRE,RXE,VRR,VRR") 7256 (set_attr "type" "fmadd<mode>") 7257 (set_attr "cpu_facility" "*,*,vx,vxe") 7258 (set_attr "enabled" "*,*,<DF>,<SF>")]) 7259 7260 ; msxbr, msdbr, msebr, msxb, msdb, mseb 7261 (define_insn "fms<mode>4" 7262 [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") 7263 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") 7264 (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") 7265 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] 7266 "TARGET_HARD_FLOAT && s390_fma_allowed_p (<MODE>mode)" 7267 "@ 7268 ms<xde>br\t%0,%1,%2 7269 ms<xde>b\t%0,%1,%2 7270 wfmsdb\t%v0,%v1,%v2,%v3 7271 wfmssb\t%v0,%v1,%v2,%v3" 7272 [(set_attr "op_type" "RRE,RXE,VRR,VRR") 7273 (set_attr "type" "fmadd<mode>") 7274 (set_attr "cpu_facility" "*,*,vx,vxe") 7275 (set_attr "enabled" "*,*,<DF>,<SF>")]) 7276 7277 ;; 7278 ;;- Divide and modulo instructions. 7279 ;; 7280 7281 ; 7282 ; divmoddi4 instruction pattern(s). 7283 ; 7284 7285 (define_expand "divmoddi4" 7286 [(parallel [(set (match_operand:DI 0 "general_operand" "") 7287 (div:DI (match_operand:DI 1 "register_operand" "") 7288 (match_operand:DI 2 "general_operand" ""))) 7289 (set (match_operand:DI 3 "general_operand" "") 7290 (mod:DI (match_dup 1) (match_dup 2)))]) 7291 (clobber (match_dup 4))] 7292 "TARGET_ZARCH" 7293 { 7294 rtx div_equal, mod_equal; 7295 rtx_insn *insn; 7296 7297 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); 7298 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); 7299 7300 operands[4] = gen_reg_rtx(TImode); 7301 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); 7302 7303 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 7304 set_unique_reg_note (insn, REG_EQUAL, div_equal); 7305 7306 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 7307 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 7308 7309 DONE; 7310 }) 7311 7312 (define_insn "divmodtidi3" 7313 [(set (match_operand:TI 0 "register_operand" "=d,d") 7314 (ior:TI 7315 (ashift:TI 7316 (zero_extend:TI 7317 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 7318 (match_operand:DI 2 "general_operand" "d,T"))) 7319 (const_int 64)) 7320 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] 7321 "TARGET_ZARCH" 7322 "@ 7323 dsgr\t%0,%2 7324 dsg\t%0,%2" 7325 [(set_attr "op_type" "RRE,RXY") 7326 (set_attr "type" "idiv")]) 7327 7328 (define_insn "divmodtisi3" 7329 [(set (match_operand:TI 0 "register_operand" "=d,d") 7330 (ior:TI 7331 (ashift:TI 7332 (zero_extend:TI 7333 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 7334 (sign_extend:DI 7335 (match_operand:SI 2 "nonimmediate_operand" "d,T")))) 7336 (const_int 64)) 7337 (zero_extend:TI 7338 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] 7339 "TARGET_ZARCH" 7340 "@ 7341 dsgfr\t%0,%2 7342 dsgf\t%0,%2" 7343 [(set_attr "op_type" "RRE,RXY") 7344 (set_attr "type" "idiv")]) 7345 7346 ; 7347 ; udivmoddi4 instruction pattern(s). 7348 ; 7349 7350 (define_expand "udivmoddi4" 7351 [(parallel [(set (match_operand:DI 0 "general_operand" "") 7352 (udiv:DI (match_operand:DI 1 "general_operand" "") 7353 (match_operand:DI 2 "nonimmediate_operand" ""))) 7354 (set (match_operand:DI 3 "general_operand" "") 7355 (umod:DI (match_dup 1) (match_dup 2)))]) 7356 (clobber (match_dup 4))] 7357 "TARGET_ZARCH" 7358 { 7359 rtx div_equal, mod_equal, equal; 7360 rtx_insn *insn; 7361 7362 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); 7363 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); 7364 equal = gen_rtx_IOR (TImode, 7365 gen_rtx_ASHIFT (TImode, 7366 gen_rtx_ZERO_EXTEND (TImode, mod_equal), 7367 GEN_INT (64)), 7368 gen_rtx_ZERO_EXTEND (TImode, div_equal)); 7369 7370 operands[4] = gen_reg_rtx(TImode); 7371 emit_clobber (operands[4]); 7372 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); 7373 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); 7374 7375 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); 7376 set_unique_reg_note (insn, REG_EQUAL, equal); 7377 7378 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 7379 set_unique_reg_note (insn, REG_EQUAL, div_equal); 7380 7381 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 7382 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 7383 7384 DONE; 7385 }) 7386 7387 (define_insn "udivmodtidi3" 7388 [(set (match_operand:TI 0 "register_operand" "=d,d") 7389 (ior:TI 7390 (ashift:TI 7391 (zero_extend:TI 7392 (truncate:DI 7393 (umod:TI (match_operand:TI 1 "register_operand" "0,0") 7394 (zero_extend:TI 7395 (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) 7396 (const_int 64)) 7397 (zero_extend:TI 7398 (truncate:DI 7399 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] 7400 "TARGET_ZARCH" 7401 "@ 7402 dlgr\t%0,%2 7403 dlg\t%0,%2" 7404 [(set_attr "op_type" "RRE,RXY") 7405 (set_attr "type" "idiv")]) 7406 7407 ; 7408 ; divmodsi4 instruction pattern(s). 7409 ; 7410 7411 (define_expand "divmodsi4" 7412 [(parallel [(set (match_operand:SI 0 "general_operand" "") 7413 (div:SI (match_operand:SI 1 "general_operand" "") 7414 (match_operand:SI 2 "nonimmediate_operand" ""))) 7415 (set (match_operand:SI 3 "general_operand" "") 7416 (mod:SI (match_dup 1) (match_dup 2)))]) 7417 (clobber (match_dup 4))] 7418 "!TARGET_ZARCH" 7419 { 7420 rtx div_equal, mod_equal, equal; 7421 rtx_insn *insn; 7422 7423 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); 7424 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); 7425 equal = gen_rtx_IOR (DImode, 7426 gen_rtx_ASHIFT (DImode, 7427 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 7428 GEN_INT (32)), 7429 gen_rtx_ZERO_EXTEND (DImode, div_equal)); 7430 7431 operands[4] = gen_reg_rtx(DImode); 7432 emit_insn (gen_extendsidi2 (operands[4], operands[1])); 7433 7434 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); 7435 set_unique_reg_note (insn, REG_EQUAL, equal); 7436 7437 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 7438 set_unique_reg_note (insn, REG_EQUAL, div_equal); 7439 7440 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 7441 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 7442 7443 DONE; 7444 }) 7445 7446 (define_insn "divmoddisi3" 7447 [(set (match_operand:DI 0 "register_operand" "=d,d") 7448 (ior:DI 7449 (ashift:DI 7450 (zero_extend:DI 7451 (truncate:SI 7452 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 7453 (sign_extend:DI 7454 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) 7455 (const_int 32)) 7456 (zero_extend:DI 7457 (truncate:SI 7458 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] 7459 "!TARGET_ZARCH" 7460 "@ 7461 dr\t%0,%2 7462 d\t%0,%2" 7463 [(set_attr "op_type" "RR,RX") 7464 (set_attr "type" "idiv")]) 7465 7466 ; 7467 ; udivsi3 and umodsi3 instruction pattern(s). 7468 ; 7469 7470 (define_expand "udivmodsi4" 7471 [(parallel [(set (match_operand:SI 0 "general_operand" "") 7472 (udiv:SI (match_operand:SI 1 "general_operand" "") 7473 (match_operand:SI 2 "nonimmediate_operand" ""))) 7474 (set (match_operand:SI 3 "general_operand" "") 7475 (umod:SI (match_dup 1) (match_dup 2)))]) 7476 (clobber (match_dup 4))] 7477 "!TARGET_ZARCH" 7478 { 7479 rtx div_equal, mod_equal, equal; 7480 rtx_insn *insn; 7481 7482 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 7483 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 7484 equal = gen_rtx_IOR (DImode, 7485 gen_rtx_ASHIFT (DImode, 7486 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 7487 GEN_INT (32)), 7488 gen_rtx_ZERO_EXTEND (DImode, div_equal)); 7489 7490 operands[4] = gen_reg_rtx(DImode); 7491 emit_clobber (operands[4]); 7492 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); 7493 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); 7494 7495 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); 7496 set_unique_reg_note (insn, REG_EQUAL, equal); 7497 7498 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 7499 set_unique_reg_note (insn, REG_EQUAL, div_equal); 7500 7501 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 7502 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 7503 7504 DONE; 7505 }) 7506 7507 (define_insn "udivmoddisi3" 7508 [(set (match_operand:DI 0 "register_operand" "=d,d") 7509 (ior:DI 7510 (ashift:DI 7511 (zero_extend:DI 7512 (truncate:SI 7513 (umod:DI (match_operand:DI 1 "register_operand" "0,0") 7514 (zero_extend:DI 7515 (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) 7516 (const_int 32)) 7517 (zero_extend:DI 7518 (truncate:SI 7519 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] 7520 "!TARGET_ZARCH" 7521 "@ 7522 dlr\t%0,%2 7523 dl\t%0,%2" 7524 [(set_attr "op_type" "RRE,RXY") 7525 (set_attr "type" "idiv")]) 7526 7527 ; 7528 ; div(df|sf)3 instruction pattern(s). 7529 ; 7530 7531 ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr 7532 (define_insn "div<mode>3<tf_fpr>" 7533 [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") 7534 (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") 7535 (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] 7536 "TARGET_HARD_FLOAT" 7537 "@ 7538 d<xde>tr\t%0,%1,%2 7539 d<xde>br\t%0,%2 7540 d<xde>b\t%0,%2 7541 wfddb\t%v0,%v1,%v2 7542 wfdsb\t%v0,%v1,%v2" 7543 [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") 7544 (set_attr "type" "fdiv<type>") 7545 (set_attr "cpu_facility" "*,*,*,vx,vxe") 7546 (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) 7547 7548 7549 ;; 7550 ;;- And instructions. 7551 ;; 7552 7553 (define_expand "and<mode>3" 7554 [(set (match_operand:INT 0 "nonimmediate_operand" "") 7555 (and:INT (match_operand:INT 1 "nonimmediate_operand" "") 7556 (match_operand:INT 2 "general_operand" ""))) 7557 (clobber (reg:CC CC_REGNUM))] 7558 "" 7559 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") 7560 7561 ; 7562 ; anddi3 instruction pattern(s). 7563 ; 7564 7565 (define_insn "*anddi3_cc" 7566 [(set (reg CC_REGNUM) 7567 (compare 7568 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") 7569 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) 7570 (const_int 0))) 7571 (set (match_operand:DI 0 "register_operand" "=d,d,d, d") 7572 (and:DI (match_dup 1) (match_dup 2)))] 7573 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" 7574 "@ 7575 ngr\t%0,%2 7576 ngrk\t%0,%1,%2 7577 ng\t%0,%2 7578 risbg\t%0,%1,%s2,128+%e2,0" 7579 [(set_attr "op_type" "RRE,RRF,RXY,RIE") 7580 (set_attr "cpu_facility" "*,z196,*,z10") 7581 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7582 7583 (define_insn "*anddi3_cconly" 7584 [(set (reg CC_REGNUM) 7585 (compare 7586 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") 7587 (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) 7588 (const_int 0))) 7589 (clobber (match_scratch:DI 0 "=d,d,d, d"))] 7590 "TARGET_ZARCH 7591 && s390_match_ccmode(insn, CCTmode) 7592 /* Do not steal TM patterns. */ 7593 && s390_single_part (operands[2], DImode, HImode, 0) < 0" 7594 "@ 7595 ngr\t%0,%2 7596 ngrk\t%0,%1,%2 7597 ng\t%0,%2 7598 risbg\t%0,%1,%s2,128+%e2,0" 7599 [(set_attr "op_type" "RRE,RRF,RXY,RIE") 7600 (set_attr "cpu_facility" "*,z196,*,z10") 7601 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7602 7603 (define_insn "*anddi3" 7604 [(set (match_operand:DI 0 "nonimmediate_operand" 7605 "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") 7606 (and:DI 7607 (match_operand:DI 1 "nonimmediate_operand" 7608 "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") 7609 (match_operand:DI 2 "general_operand" 7610 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) 7611 (clobber (reg:CC CC_REGNUM))] 7612 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7613 "@ 7614 # 7615 # 7616 nihh\t%0,%j2 7617 nihl\t%0,%j2 7618 nilh\t%0,%j2 7619 nill\t%0,%j2 7620 nihf\t%0,%m2 7621 nilf\t%0,%m2 7622 ngr\t%0,%2 7623 ngrk\t%0,%1,%2 7624 ng\t%0,%2 7625 risbg\t%0,%1,%s2,128+%e2,0 7626 # 7627 #" 7628 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") 7629 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") 7630 (set_attr "z10prop" "*, 7631 *, 7632 z10_super_E1, 7633 z10_super_E1, 7634 z10_super_E1, 7635 z10_super_E1, 7636 z10_super_E1, 7637 z10_super_E1, 7638 z10_super_E1, 7639 *, 7640 z10_super_E1, 7641 z10_super_E1, 7642 *, 7643 *")]) 7644 7645 (define_split 7646 [(set (match_operand:DI 0 "s_operand" "") 7647 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 7648 (clobber (reg:CC CC_REGNUM))] 7649 "reload_completed" 7650 [(parallel 7651 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 7652 (clobber (reg:CC CC_REGNUM))])] 7653 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 7654 7655 ;; These two are what combine generates for (ashift (zero_extract)). 7656 (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" 7657 [(set (match_operand:GPR 0 "register_operand" "=d") 7658 (and:GPR (lshiftrt:GPR 7659 (match_operand:GPR 1 "register_operand" "d") 7660 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 7661 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] 7662 "<z10_or_zEC12_cond> 7663 /* Note that even for the SImode pattern, the rotate is always DImode. */ 7664 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), 7665 INTVAL (operands[3]))" 7666 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" 7667 [(set_attr "op_type" "RIE") 7668 (set_attr "z10prop" "z10_super_E1")]) 7669 7670 (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" 7671 [(set (match_operand:GPR 0 "register_operand" "=d") 7672 (and:GPR (ashift:GPR 7673 (match_operand:GPR 1 "register_operand" "d") 7674 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 7675 (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] 7676 "<z10_or_zEC12_cond> 7677 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), 7678 INTVAL (operands[3]))" 7679 "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" 7680 [(set_attr "op_type" "RIE") 7681 (set_attr "z10prop" "z10_super_E1")]) 7682 7683 7684 ; 7685 ; andsi3 instruction pattern(s). 7686 ; 7687 7688 (define_insn "*andsi3_cc" 7689 [(set (reg CC_REGNUM) 7690 (compare 7691 (and:SI 7692 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") 7693 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) 7694 (const_int 0))) 7695 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") 7696 (and:SI (match_dup 1) (match_dup 2)))] 7697 "s390_match_ccmode(insn, CCTmode)" 7698 "@ 7699 nilf\t%0,%o2 7700 nr\t%0,%2 7701 nrk\t%0,%1,%2 7702 n\t%0,%2 7703 ny\t%0,%2 7704 risbg\t%0,%1,%t2,128+%f2,0" 7705 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") 7706 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") 7707 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 7708 z10_super_E1,z10_super_E1,z10_super_E1")]) 7709 7710 (define_insn "*andsi3_cconly" 7711 [(set (reg CC_REGNUM) 7712 (compare 7713 (and:SI 7714 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") 7715 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) 7716 (const_int 0))) 7717 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] 7718 "s390_match_ccmode(insn, CCTmode) 7719 /* Do not steal TM patterns. */ 7720 && s390_single_part (operands[2], SImode, HImode, 0) < 0" 7721 "@ 7722 nilf\t%0,%o2 7723 nr\t%0,%2 7724 nrk\t%0,%1,%2 7725 n\t%0,%2 7726 ny\t%0,%2 7727 risbg\t%0,%1,%t2,128+%f2,0" 7728 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") 7729 (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") 7730 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 7731 z10_super_E1,z10_super_E1,z10_super_E1")]) 7732 7733 (define_insn "*andsi3_zarch" 7734 [(set (match_operand:SI 0 "nonimmediate_operand" 7735 "=d,d, d, d, d,d,d,d,d, d, AQ,Q") 7736 (and:SI (match_operand:SI 1 "nonimmediate_operand" 7737 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") 7738 (match_operand:SI 2 "general_operand" 7739 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) 7740 (clobber (reg:CC CC_REGNUM))] 7741 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7742 "@ 7743 # 7744 # 7745 nilh\t%0,%j2 7746 nill\t%0,%j2 7747 nilf\t%0,%o2 7748 nr\t%0,%2 7749 nrk\t%0,%1,%2 7750 n\t%0,%2 7751 ny\t%0,%2 7752 risbg\t%0,%1,%t2,128+%f2,0 7753 # 7754 #" 7755 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") 7756 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") 7757 (set_attr "z10prop" "*, 7758 *, 7759 z10_super_E1, 7760 z10_super_E1, 7761 z10_super_E1, 7762 z10_super_E1, 7763 *, 7764 z10_super_E1, 7765 z10_super_E1, 7766 z10_super_E1, 7767 *, 7768 *")]) 7769 7770 (define_insn "*andsi3_esa" 7771 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") 7772 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") 7773 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) 7774 (clobber (reg:CC CC_REGNUM))] 7775 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7776 "@ 7777 nr\t%0,%2 7778 n\t%0,%2 7779 # 7780 #" 7781 [(set_attr "op_type" "RR,RX,SI,SS") 7782 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) 7783 7784 7785 (define_split 7786 [(set (match_operand:SI 0 "s_operand" "") 7787 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 7788 (clobber (reg:CC CC_REGNUM))] 7789 "reload_completed" 7790 [(parallel 7791 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 7792 (clobber (reg:CC CC_REGNUM))])] 7793 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 7794 7795 ; 7796 ; andhi3 instruction pattern(s). 7797 ; 7798 7799 (define_insn "*andhi3_zarch" 7800 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 7801 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") 7802 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) 7803 (clobber (reg:CC CC_REGNUM))] 7804 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7805 "@ 7806 nr\t%0,%2 7807 nrk\t%0,%1,%2 7808 nill\t%0,%x2 7809 # 7810 #" 7811 [(set_attr "op_type" "RR,RRF,RI,SI,SS") 7812 (set_attr "cpu_facility" "*,z196,*,*,*") 7813 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") 7814 ]) 7815 7816 (define_insn "*andhi3_esa" 7817 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") 7818 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") 7819 (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) 7820 (clobber (reg:CC CC_REGNUM))] 7821 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7822 "@ 7823 nr\t%0,%2 7824 # 7825 #" 7826 [(set_attr "op_type" "RR,SI,SS") 7827 (set_attr "z10prop" "z10_super_E1,*,*") 7828 ]) 7829 7830 (define_split 7831 [(set (match_operand:HI 0 "s_operand" "") 7832 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 7833 (clobber (reg:CC CC_REGNUM))] 7834 "reload_completed" 7835 [(parallel 7836 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 7837 (clobber (reg:CC CC_REGNUM))])] 7838 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 7839 7840 ; 7841 ; andqi3 instruction pattern(s). 7842 ; 7843 7844 (define_insn "*andqi3_zarch" 7845 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 7846 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 7847 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) 7848 (clobber (reg:CC CC_REGNUM))] 7849 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7850 "@ 7851 nr\t%0,%2 7852 nrk\t%0,%1,%2 7853 nill\t%0,%b2 7854 ni\t%S0,%b2 7855 niy\t%S0,%b2 7856 #" 7857 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") 7858 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") 7859 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) 7860 7861 (define_insn "*andqi3_esa" 7862 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") 7863 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 7864 (match_operand:QI 2 "general_operand" "d,n,Q"))) 7865 (clobber (reg:CC CC_REGNUM))] 7866 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7867 "@ 7868 nr\t%0,%2 7869 ni\t%S0,%b2 7870 #" 7871 [(set_attr "op_type" "RR,SI,SS") 7872 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) 7873 7874 ; 7875 ; And with complement 7876 ; 7877 ; c = ~b & a = (b & a) ^ a 7878 7879 (define_insn_and_split "*andc_split_<mode>" 7880 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 7881 (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) 7882 (match_operand:GPR 2 "general_operand" ""))) 7883 (clobber (reg:CC CC_REGNUM))] 7884 "!TARGET_Z15 7885 && ! reload_completed 7886 && (GET_CODE (operands[0]) != MEM 7887 /* Ensure that s390_logical_operator_ok_p will succeed even 7888 on the split xor if (b & a) is stored into a pseudo. */ 7889 || rtx_equal_p (operands[0], operands[2]))" 7890 "#" 7891 "&& 1" 7892 [ 7893 (parallel 7894 [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) 7895 (clobber (reg:CC CC_REGNUM))]) 7896 (parallel 7897 [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) 7898 (clobber (reg:CC CC_REGNUM))])] 7899 { 7900 if (reg_overlap_mentioned_p (operands[0], operands[2])) 7901 operands[3] = gen_reg_rtx (<MODE>mode); 7902 else 7903 operands[3] = operands[0]; 7904 }) 7905 7906 ; 7907 ; Block and (NC) patterns. 7908 ; 7909 7910 (define_insn "*nc" 7911 [(set (match_operand:BLK 0 "memory_operand" "=Q") 7912 (and:BLK (match_dup 0) 7913 (match_operand:BLK 1 "memory_operand" "Q"))) 7914 (use (match_operand 2 "const_int_operand" "n")) 7915 (clobber (reg:CC CC_REGNUM))] 7916 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 7917 "nc\t%O0(%2,%R0),%S1" 7918 [(set_attr "op_type" "SS") 7919 (set_attr "z196prop" "z196_cracked")]) 7920 7921 (define_split 7922 [(set (match_operand 0 "memory_operand" "") 7923 (and (match_dup 0) 7924 (match_operand 1 "memory_operand" ""))) 7925 (clobber (reg:CC CC_REGNUM))] 7926 "reload_completed 7927 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 7928 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 7929 [(parallel 7930 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) 7931 (use (match_dup 2)) 7932 (clobber (reg:CC CC_REGNUM))])] 7933 { 7934 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 7935 operands[0] = adjust_address (operands[0], BLKmode, 0); 7936 operands[1] = adjust_address (operands[1], BLKmode, 0); 7937 }) 7938 7939 (define_peephole2 7940 [(parallel 7941 [(set (match_operand:BLK 0 "memory_operand" "") 7942 (and:BLK (match_dup 0) 7943 (match_operand:BLK 1 "memory_operand" ""))) 7944 (use (match_operand 2 "const_int_operand" "")) 7945 (clobber (reg:CC CC_REGNUM))]) 7946 (parallel 7947 [(set (match_operand:BLK 3 "memory_operand" "") 7948 (and:BLK (match_dup 3) 7949 (match_operand:BLK 4 "memory_operand" ""))) 7950 (use (match_operand 5 "const_int_operand" "")) 7951 (clobber (reg:CC CC_REGNUM))])] 7952 "s390_offset_p (operands[0], operands[3], operands[2]) 7953 && s390_offset_p (operands[1], operands[4], operands[2]) 7954 && !s390_overlap_p (operands[0], operands[1], 7955 INTVAL (operands[2]) + INTVAL (operands[5])) 7956 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 7957 [(parallel 7958 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) 7959 (use (match_dup 8)) 7960 (clobber (reg:CC CC_REGNUM))])] 7961 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 7962 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 7963 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 7964 7965 7966 ;; 7967 ;;- Bit set (inclusive or) instructions. 7968 ;; 7969 7970 (define_expand "ior<mode>3" 7971 [(set (match_operand:INT 0 "nonimmediate_operand" "") 7972 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") 7973 (match_operand:INT 2 "general_operand" ""))) 7974 (clobber (reg:CC CC_REGNUM))] 7975 "" 7976 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") 7977 7978 ; 7979 ; iordi3 instruction pattern(s). 7980 ; 7981 7982 (define_insn "*iordi3_cc" 7983 [(set (reg CC_REGNUM) 7984 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 7985 (match_operand:DI 2 "general_operand" " d,d,T")) 7986 (const_int 0))) 7987 (set (match_operand:DI 0 "register_operand" "=d,d,d") 7988 (ior:DI (match_dup 1) (match_dup 2)))] 7989 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 7990 "@ 7991 ogr\t%0,%2 7992 ogrk\t%0,%1,%2 7993 og\t%0,%2" 7994 [(set_attr "op_type" "RRE,RRF,RXY") 7995 (set_attr "cpu_facility" "*,z196,*") 7996 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 7997 7998 (define_insn "*iordi3_cconly" 7999 [(set (reg CC_REGNUM) 8000 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 8001 (match_operand:DI 2 "general_operand" " d,d,T")) 8002 (const_int 0))) 8003 (clobber (match_scratch:DI 0 "=d,d,d"))] 8004 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 8005 "@ 8006 ogr\t%0,%2 8007 ogrk\t%0,%1,%2 8008 og\t%0,%2" 8009 [(set_attr "op_type" "RRE,RRF,RXY") 8010 (set_attr "cpu_facility" "*,z196,*") 8011 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 8012 8013 (define_insn "*iordi3" 8014 [(set (match_operand:DI 0 "nonimmediate_operand" 8015 "=d, d, d, d, d, d,d,d,d, AQ,Q") 8016 (ior:DI (match_operand:DI 1 "nonimmediate_operand" 8017 " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") 8018 (match_operand:DI 2 "general_operand" 8019 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) 8020 (clobber (reg:CC CC_REGNUM))] 8021 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8022 "@ 8023 oihh\t%0,%i2 8024 oihl\t%0,%i2 8025 oilh\t%0,%i2 8026 oill\t%0,%i2 8027 oihf\t%0,%k2 8028 oilf\t%0,%k2 8029 ogr\t%0,%2 8030 ogrk\t%0,%1,%2 8031 og\t%0,%2 8032 # 8033 #" 8034 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") 8035 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") 8036 (set_attr "z10prop" "z10_super_E1, 8037 z10_super_E1, 8038 z10_super_E1, 8039 z10_super_E1, 8040 z10_super_E1, 8041 z10_super_E1, 8042 z10_super_E1, 8043 *, 8044 z10_super_E1, 8045 *, 8046 *")]) 8047 8048 (define_split 8049 [(set (match_operand:DI 0 "s_operand" "") 8050 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 8051 (clobber (reg:CC CC_REGNUM))] 8052 "reload_completed" 8053 [(parallel 8054 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 8055 (clobber (reg:CC CC_REGNUM))])] 8056 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 8057 8058 ; 8059 ; iorsi3 instruction pattern(s). 8060 ; 8061 8062 (define_insn "*iorsi3_cc" 8063 [(set (reg CC_REGNUM) 8064 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 8065 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 8066 (const_int 0))) 8067 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 8068 (ior:SI (match_dup 1) (match_dup 2)))] 8069 "s390_match_ccmode(insn, CCTmode)" 8070 "@ 8071 oilf\t%0,%o2 8072 or\t%0,%2 8073 ork\t%0,%1,%2 8074 o\t%0,%2 8075 oy\t%0,%2" 8076 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 8077 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 8078 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) 8079 8080 (define_insn "*iorsi3_cconly" 8081 [(set (reg CC_REGNUM) 8082 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 8083 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 8084 (const_int 0))) 8085 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] 8086 "s390_match_ccmode(insn, CCTmode)" 8087 "@ 8088 oilf\t%0,%o2 8089 or\t%0,%2 8090 ork\t%0,%1,%2 8091 o\t%0,%2 8092 oy\t%0,%2" 8093 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 8094 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 8095 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) 8096 8097 (define_insn "*iorsi3_zarch" 8098 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") 8099 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") 8100 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) 8101 (clobber (reg:CC CC_REGNUM))] 8102 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8103 "@ 8104 oilh\t%0,%i2 8105 oill\t%0,%i2 8106 oilf\t%0,%o2 8107 or\t%0,%2 8108 ork\t%0,%1,%2 8109 o\t%0,%2 8110 oy\t%0,%2 8111 # 8112 #" 8113 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") 8114 (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") 8115 (set_attr "z10prop" "z10_super_E1, 8116 z10_super_E1, 8117 z10_super_E1, 8118 z10_super_E1, 8119 *, 8120 z10_super_E1, 8121 z10_super_E1, 8122 *, 8123 *")]) 8124 8125 (define_insn "*iorsi3_esa" 8126 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") 8127 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") 8128 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) 8129 (clobber (reg:CC CC_REGNUM))] 8130 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8131 "@ 8132 or\t%0,%2 8133 o\t%0,%2 8134 # 8135 #" 8136 [(set_attr "op_type" "RR,RX,SI,SS") 8137 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) 8138 8139 (define_split 8140 [(set (match_operand:SI 0 "s_operand" "") 8141 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 8142 (clobber (reg:CC CC_REGNUM))] 8143 "reload_completed" 8144 [(parallel 8145 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 8146 (clobber (reg:CC CC_REGNUM))])] 8147 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 8148 8149 ; 8150 ; iorhi3 instruction pattern(s). 8151 ; 8152 8153 (define_insn "*iorhi3_zarch" 8154 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 8155 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") 8156 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) 8157 (clobber (reg:CC CC_REGNUM))] 8158 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8159 "@ 8160 or\t%0,%2 8161 ork\t%0,%1,%2 8162 oill\t%0,%x2 8163 # 8164 #" 8165 [(set_attr "op_type" "RR,RRF,RI,SI,SS") 8166 (set_attr "cpu_facility" "*,z196,*,*,*") 8167 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) 8168 8169 (define_insn "*iorhi3_esa" 8170 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") 8171 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") 8172 (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) 8173 (clobber (reg:CC CC_REGNUM))] 8174 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8175 "@ 8176 or\t%0,%2 8177 # 8178 #" 8179 [(set_attr "op_type" "RR,SI,SS") 8180 (set_attr "z10prop" "z10_super_E1,*,*")]) 8181 8182 (define_split 8183 [(set (match_operand:HI 0 "s_operand" "") 8184 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 8185 (clobber (reg:CC CC_REGNUM))] 8186 "reload_completed" 8187 [(parallel 8188 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 8189 (clobber (reg:CC CC_REGNUM))])] 8190 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 8191 8192 ; 8193 ; iorqi3 instruction pattern(s). 8194 ; 8195 8196 (define_insn "*iorqi3_zarch" 8197 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 8198 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 8199 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) 8200 (clobber (reg:CC CC_REGNUM))] 8201 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8202 "@ 8203 or\t%0,%2 8204 ork\t%0,%1,%2 8205 oill\t%0,%b2 8206 oi\t%S0,%b2 8207 oiy\t%S0,%b2 8208 #" 8209 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") 8210 (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") 8211 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, 8212 z10_super,z10_super,*")]) 8213 8214 (define_insn "*iorqi3_esa" 8215 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") 8216 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 8217 (match_operand:QI 2 "general_operand" "d,n,Q"))) 8218 (clobber (reg:CC CC_REGNUM))] 8219 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8220 "@ 8221 or\t%0,%2 8222 oi\t%S0,%b2 8223 #" 8224 [(set_attr "op_type" "RR,SI,SS") 8225 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) 8226 8227 ; 8228 ; And/Or with complement 8229 ; 8230 8231 ; ncrk, ncgrk, ocrk, ocgrk 8232 (define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cc" 8233 [(set (reg CC_REGNUM) 8234 (compare 8235 (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 8236 (match_operand:GPR 2 "register_operand" "d")) 8237 (const_int 0))) 8238 (set (match_operand:GPR 0 "register_operand" "=d") 8239 (ANDOR:GPR (not:GPR (match_dup 1)) 8240 (match_dup 2)))] 8241 "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" 8242 "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" 8243 [(set_attr "op_type" "RRF")]) 8244 8245 ; ncrk, ncgrk, ocrk, ocgrk 8246 (define_insn "*<ANDOR:bitops_name>c<GPR:mode>_cconly" 8247 [(set (reg CC_REGNUM) 8248 (compare 8249 (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 8250 (match_operand:GPR 2 "register_operand" "d")) 8251 (const_int 0))) 8252 (clobber (match_scratch:GPR 0 "=d"))] 8253 "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" 8254 "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" 8255 [(set_attr "op_type" "RRF")]) 8256 8257 ; ncrk, ncgrk, ocrk, ocgrk 8258 (define_insn "*<ANDOR:bitops_name>c<GPR:mode>" 8259 [(set (match_operand:GPR 0 "register_operand" "=d") 8260 (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 8261 (match_operand:GPR 2 "register_operand" "d"))) 8262 (clobber (reg:CC CC_REGNUM))] 8263 "TARGET_Z15" 8264 "<ANDOR:noxa>c<GPR:g>rk\t%0,%2,%1" 8265 [(set_attr "op_type" "RRF")]) 8266 8267 ; 8268 ;- Nand/Nor instructions. 8269 ; 8270 8271 ; nnrk, nngrk, nork, nogrk 8272 (define_insn "*n<ANDOR:inv_bitops_name><GPR:mode>_cc" 8273 [(set (reg CC_REGNUM) 8274 (compare 8275 (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 8276 (not:GPR (match_operand:GPR 2 "register_operand" "d"))) 8277 (const_int 0))) 8278 (set (match_operand:GPR 0 "register_operand" "=d") 8279 (ANDOR:GPR (not:GPR (match_dup 1)) 8280 (not:GPR (match_dup 2))))] 8281 "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" 8282 "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" 8283 [(set_attr "op_type" "RRF")]) 8284 8285 ; nnrk, nngrk, nork, nogrk 8286 (define_insn "*n<ANDOR:inv_bitops_name><mode>_cconly" 8287 [(set (reg CC_REGNUM) 8288 (compare 8289 (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 8290 (not:GPR (match_operand:GPR 2 "register_operand" "d"))) 8291 (const_int 0))) 8292 (clobber (match_scratch:GPR 0 "=d"))] 8293 "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" 8294 "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" 8295 [(set_attr "op_type" "RRF")]) 8296 8297 ; nnrk, nngrk, nork, nogrk 8298 (define_insn "*n<ANDOR:inv_bitops_name><mode>" 8299 [(set (match_operand:GPR 0 "register_operand" "=d") 8300 (ANDOR:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d")) 8301 (not:GPR (match_operand:GPR 2 "register_operand" "d")))) 8302 (clobber (reg:CC CC_REGNUM))] 8303 "TARGET_Z15" 8304 "n<ANDOR:inv_no><GPR:g>rk\t%0,%1,%2" 8305 [(set_attr "op_type" "RRF")]) 8306 8307 8308 ; 8309 ; Block inclusive or (OC) patterns. 8310 ; 8311 8312 (define_insn "*oc" 8313 [(set (match_operand:BLK 0 "memory_operand" "=Q") 8314 (ior:BLK (match_dup 0) 8315 (match_operand:BLK 1 "memory_operand" "Q"))) 8316 (use (match_operand 2 "const_int_operand" "n")) 8317 (clobber (reg:CC CC_REGNUM))] 8318 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 8319 "oc\t%O0(%2,%R0),%S1" 8320 [(set_attr "op_type" "SS") 8321 (set_attr "z196prop" "z196_cracked")]) 8322 8323 (define_split 8324 [(set (match_operand 0 "memory_operand" "") 8325 (ior (match_dup 0) 8326 (match_operand 1 "memory_operand" ""))) 8327 (clobber (reg:CC CC_REGNUM))] 8328 "reload_completed 8329 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 8330 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 8331 [(parallel 8332 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) 8333 (use (match_dup 2)) 8334 (clobber (reg:CC CC_REGNUM))])] 8335 { 8336 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 8337 operands[0] = adjust_address (operands[0], BLKmode, 0); 8338 operands[1] = adjust_address (operands[1], BLKmode, 0); 8339 }) 8340 8341 (define_peephole2 8342 [(parallel 8343 [(set (match_operand:BLK 0 "memory_operand" "") 8344 (ior:BLK (match_dup 0) 8345 (match_operand:BLK 1 "memory_operand" ""))) 8346 (use (match_operand 2 "const_int_operand" "")) 8347 (clobber (reg:CC CC_REGNUM))]) 8348 (parallel 8349 [(set (match_operand:BLK 3 "memory_operand" "") 8350 (ior:BLK (match_dup 3) 8351 (match_operand:BLK 4 "memory_operand" ""))) 8352 (use (match_operand 5 "const_int_operand" "")) 8353 (clobber (reg:CC CC_REGNUM))])] 8354 "s390_offset_p (operands[0], operands[3], operands[2]) 8355 && s390_offset_p (operands[1], operands[4], operands[2]) 8356 && !s390_overlap_p (operands[0], operands[1], 8357 INTVAL (operands[2]) + INTVAL (operands[5])) 8358 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 8359 [(parallel 8360 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) 8361 (use (match_dup 8)) 8362 (clobber (reg:CC CC_REGNUM))])] 8363 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 8364 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 8365 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 8366 8367 8368 ;; 8369 ;;- Xor instructions. 8370 ;; 8371 8372 (define_expand "xor<mode>3" 8373 [(set (match_operand:INT 0 "nonimmediate_operand" "") 8374 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") 8375 (match_operand:INT 2 "general_operand" ""))) 8376 (clobber (reg:CC CC_REGNUM))] 8377 "" 8378 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") 8379 8380 ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing 8381 ; simplifications. So its better to have something matching. 8382 (define_split 8383 [(set (match_operand:INT 0 "nonimmediate_operand" "") 8384 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] 8385 "" 8386 [(parallel 8387 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) 8388 (clobber (reg:CC CC_REGNUM))])] 8389 { 8390 operands[2] = constm1_rtx; 8391 if (!s390_logical_operator_ok_p (operands)) 8392 FAIL; 8393 }) 8394 8395 ; 8396 ; xordi3 instruction pattern(s). 8397 ; 8398 8399 (define_insn "*xordi3_cc" 8400 [(set (reg CC_REGNUM) 8401 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 8402 (match_operand:DI 2 "general_operand" " d,d,T")) 8403 (const_int 0))) 8404 (set (match_operand:DI 0 "register_operand" "=d,d,d") 8405 (xor:DI (match_dup 1) (match_dup 2)))] 8406 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 8407 "@ 8408 xgr\t%0,%2 8409 xgrk\t%0,%1,%2 8410 xg\t%0,%2" 8411 [(set_attr "op_type" "RRE,RRF,RXY") 8412 (set_attr "cpu_facility" "*,z196,*") 8413 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 8414 8415 (define_insn "*xordi3_cconly" 8416 [(set (reg CC_REGNUM) 8417 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 8418 (match_operand:DI 2 "general_operand" " d,d,T")) 8419 (const_int 0))) 8420 (clobber (match_scratch:DI 0 "=d,d,d"))] 8421 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 8422 "@ 8423 xgr\t%0,%2 8424 xgrk\t%0,%1,%2 8425 xg\t%0,%2" 8426 [(set_attr "op_type" "RRE,RRF,RXY") 8427 (set_attr "cpu_facility" "*,z196,*") 8428 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 8429 8430 (define_insn "*xordi3" 8431 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") 8432 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") 8433 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) 8434 (clobber (reg:CC CC_REGNUM))] 8435 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 8436 "@ 8437 xihf\t%0,%k2 8438 xilf\t%0,%k2 8439 xgr\t%0,%2 8440 xgrk\t%0,%1,%2 8441 xg\t%0,%2 8442 # 8443 #" 8444 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") 8445 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") 8446 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, 8447 *,z10_super_E1,*,*")]) 8448 8449 (define_split 8450 [(set (match_operand:DI 0 "s_operand" "") 8451 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 8452 (clobber (reg:CC CC_REGNUM))] 8453 "reload_completed" 8454 [(parallel 8455 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 8456 (clobber (reg:CC CC_REGNUM))])] 8457 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 8458 8459 ; 8460 ; xorsi3 instruction pattern(s). 8461 ; 8462 8463 (define_insn "*xorsi3_cc" 8464 [(set (reg CC_REGNUM) 8465 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 8466 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 8467 (const_int 0))) 8468 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 8469 (xor:SI (match_dup 1) (match_dup 2)))] 8470 "s390_match_ccmode(insn, CCTmode)" 8471 "@ 8472 xilf\t%0,%o2 8473 xr\t%0,%2 8474 xrk\t%0,%1,%2 8475 x\t%0,%2 8476 xy\t%0,%2" 8477 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 8478 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 8479 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 8480 z10_super_E1,z10_super_E1")]) 8481 8482 (define_insn "*xorsi3_cconly" 8483 [(set (reg CC_REGNUM) 8484 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 8485 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 8486 (const_int 0))) 8487 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] 8488 "s390_match_ccmode(insn, CCTmode)" 8489 "@ 8490 xilf\t%0,%o2 8491 xr\t%0,%2 8492 xrk\t%0,%1,%2 8493 x\t%0,%2 8494 xy\t%0,%2" 8495 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 8496 (set_attr "cpu_facility" "*,*,z196,*,longdisp") 8497 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 8498 z10_super_E1,z10_super_E1")]) 8499 8500 (define_insn "*xorsi3" 8501 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") 8502 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") 8503 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) 8504 (clobber (reg:CC CC_REGNUM))] 8505 "s390_logical_operator_ok_p (operands)" 8506 "@ 8507 xilf\t%0,%o2 8508 xr\t%0,%2 8509 xrk\t%0,%1,%2 8510 x\t%0,%2 8511 xy\t%0,%2 8512 # 8513 #" 8514 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") 8515 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") 8516 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 8517 z10_super_E1,z10_super_E1,*,*")]) 8518 8519 (define_split 8520 [(set (match_operand:SI 0 "s_operand" "") 8521 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 8522 (clobber (reg:CC CC_REGNUM))] 8523 "reload_completed" 8524 [(parallel 8525 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 8526 (clobber (reg:CC CC_REGNUM))])] 8527 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 8528 8529 ; 8530 ; xorhi3 instruction pattern(s). 8531 ; 8532 8533 (define_insn "*xorhi3" 8534 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 8535 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") 8536 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) 8537 (clobber (reg:CC CC_REGNUM))] 8538 "s390_logical_operator_ok_p (operands)" 8539 "@ 8540 xilf\t%0,%x2 8541 xr\t%0,%2 8542 xrk\t%0,%1,%2 8543 # 8544 #" 8545 [(set_attr "op_type" "RIL,RR,RRF,SI,SS") 8546 (set_attr "cpu_facility" "*,*,z196,*,*") 8547 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) 8548 8549 (define_split 8550 [(set (match_operand:HI 0 "s_operand" "") 8551 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 8552 (clobber (reg:CC CC_REGNUM))] 8553 "reload_completed" 8554 [(parallel 8555 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 8556 (clobber (reg:CC CC_REGNUM))])] 8557 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 8558 8559 ; 8560 ; xorqi3 instruction pattern(s). 8561 ; 8562 8563 (define_insn "*xorqi3" 8564 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 8565 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") 8566 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) 8567 (clobber (reg:CC CC_REGNUM))] 8568 "s390_logical_operator_ok_p (operands)" 8569 "@ 8570 xilf\t%0,%b2 8571 xr\t%0,%2 8572 xrk\t%0,%1,%2 8573 xi\t%S0,%b2 8574 xiy\t%S0,%b2 8575 #" 8576 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") 8577 (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") 8578 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) 8579 8580 8581 ; 8582 ; Block exclusive or (XC) patterns. 8583 ; 8584 8585 (define_insn "*xc" 8586 [(set (match_operand:BLK 0 "memory_operand" "=Q") 8587 (xor:BLK (match_dup 0) 8588 (match_operand:BLK 1 "memory_operand" "Q"))) 8589 (use (match_operand 2 "const_int_operand" "n")) 8590 (clobber (reg:CC CC_REGNUM))] 8591 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 8592 "xc\t%O0(%2,%R0),%S1" 8593 [(set_attr "op_type" "SS")]) 8594 8595 (define_split 8596 [(set (match_operand 0 "memory_operand" "") 8597 (xor (match_dup 0) 8598 (match_operand 1 "memory_operand" ""))) 8599 (clobber (reg:CC CC_REGNUM))] 8600 "reload_completed 8601 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 8602 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 8603 [(parallel 8604 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) 8605 (use (match_dup 2)) 8606 (clobber (reg:CC CC_REGNUM))])] 8607 { 8608 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 8609 operands[0] = adjust_address (operands[0], BLKmode, 0); 8610 operands[1] = adjust_address (operands[1], BLKmode, 0); 8611 }) 8612 8613 (define_peephole2 8614 [(parallel 8615 [(set (match_operand:BLK 0 "memory_operand" "") 8616 (xor:BLK (match_dup 0) 8617 (match_operand:BLK 1 "memory_operand" ""))) 8618 (use (match_operand 2 "const_int_operand" "")) 8619 (clobber (reg:CC CC_REGNUM))]) 8620 (parallel 8621 [(set (match_operand:BLK 3 "memory_operand" "") 8622 (xor:BLK (match_dup 3) 8623 (match_operand:BLK 4 "memory_operand" ""))) 8624 (use (match_operand 5 "const_int_operand" "")) 8625 (clobber (reg:CC CC_REGNUM))])] 8626 "s390_offset_p (operands[0], operands[3], operands[2]) 8627 && s390_offset_p (operands[1], operands[4], operands[2]) 8628 && !s390_overlap_p (operands[0], operands[1], 8629 INTVAL (operands[2]) + INTVAL (operands[5])) 8630 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 8631 [(parallel 8632 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) 8633 (use (match_dup 8)) 8634 (clobber (reg:CC CC_REGNUM))])] 8635 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 8636 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 8637 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 8638 8639 ; 8640 ; Block xor (XC) patterns with src == dest. 8641 ; 8642 8643 (define_insn "*xc_zero" 8644 [(set (match_operand:BLK 0 "memory_operand" "=Q") 8645 (const_int 0)) 8646 (use (match_operand 1 "const_int_operand" "n")) 8647 (clobber (reg:CC CC_REGNUM))] 8648 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" 8649 "xc\t%O0(%1,%R0),%S0" 8650 [(set_attr "op_type" "SS") 8651 (set_attr "z196prop" "z196_cracked")]) 8652 8653 (define_peephole2 8654 [(parallel 8655 [(set (match_operand:BLK 0 "memory_operand" "") 8656 (const_int 0)) 8657 (use (match_operand 1 "const_int_operand" "")) 8658 (clobber (reg:CC CC_REGNUM))]) 8659 (parallel 8660 [(set (match_operand:BLK 2 "memory_operand" "") 8661 (const_int 0)) 8662 (use (match_operand 3 "const_int_operand" "")) 8663 (clobber (reg:CC CC_REGNUM))])] 8664 "s390_offset_p (operands[0], operands[2], operands[1]) 8665 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" 8666 [(parallel 8667 [(set (match_dup 4) (const_int 0)) 8668 (use (match_dup 5)) 8669 (clobber (reg:CC CC_REGNUM))])] 8670 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 8671 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") 8672 8673 ; 8674 ;- Nxor instructions. 8675 ; 8676 8677 ; nxrk, nxgrk 8678 (define_insn "*nxor<GPR:mode>_cc" 8679 [(set (reg CC_REGNUM) 8680 (compare 8681 (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") 8682 (match_operand:GPR 2 "register_operand" "d"))) 8683 (const_int 0))) 8684 (set (match_operand:GPR 0 "register_operand" "=d") 8685 (xor:GPR (not:GPR (match_dup 1)) 8686 (match_dup 2)))] 8687 "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" 8688 "nx<GPR:g>rk\t%0,%1,%2" 8689 [(set_attr "op_type" "RRF")]) 8690 8691 ; nxrk, nxgrk 8692 (define_insn "*nxor<mode>_cconly" 8693 [(set (reg CC_REGNUM) 8694 (compare 8695 (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") 8696 (match_operand:GPR 2 "register_operand" "d"))) 8697 (const_int 0))) 8698 (clobber (match_scratch:GPR 0 "=d"))] 8699 "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" 8700 "nx<GPR:g>rk\t%0,%1,%2" 8701 [(set_attr "op_type" "RRF")]) 8702 8703 ; nxrk, nxgrk 8704 (define_insn "*nxor<mode>" 8705 [(set (match_operand:GPR 0 "register_operand" "=d") 8706 (not:GPR (xor:GPR (match_operand:GPR 1 "register_operand" "d") 8707 (match_operand:GPR 2 "register_operand" "d")))) 8708 (clobber (reg:CC CC_REGNUM))] 8709 "TARGET_Z15" 8710 "nx<GPR:g>rk\t%0,%1,%2" 8711 [(set_attr "op_type" "RRF")]) 8712 8713 ;; 8714 ;;- Negate instructions. 8715 ;; 8716 8717 ; 8718 ; neg(di|si)2 instruction pattern(s). 8719 ; 8720 8721 (define_expand "neg<mode>2" 8722 [(parallel 8723 [(set (match_operand:DSI 0 "register_operand" "=d") 8724 (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) 8725 (clobber (reg:CC CC_REGNUM))])] 8726 "" 8727 "") 8728 8729 (define_insn "*negdi2_sign_cc" 8730 [(set (reg CC_REGNUM) 8731 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI 8732 (match_operand:SI 1 "register_operand" "d") 0) 8733 (const_int 32)) (const_int 32))) 8734 (const_int 0))) 8735 (set (match_operand:DI 0 "register_operand" "=d") 8736 (neg:DI (sign_extend:DI (match_dup 1))))] 8737 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 8738 "lcgfr\t%0,%1" 8739 [(set_attr "op_type" "RRE") 8740 (set_attr "z10prop" "z10_c")]) 8741 8742 (define_insn "*negdi2_sign" 8743 [(set (match_operand:DI 0 "register_operand" "=d") 8744 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 8745 (clobber (reg:CC CC_REGNUM))] 8746 "TARGET_ZARCH" 8747 "lcgfr\t%0,%1" 8748 [(set_attr "op_type" "RRE") 8749 (set_attr "z10prop" "z10_c")]) 8750 8751 ; lcr, lcgr 8752 (define_insn "*neg<mode>2_cc" 8753 [(set (reg CC_REGNUM) 8754 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) 8755 (const_int 0))) 8756 (set (match_operand:GPR 0 "register_operand" "=d") 8757 (neg:GPR (match_dup 1)))] 8758 "s390_match_ccmode (insn, CCAmode)" 8759 "lc<g>r\t%0,%1" 8760 [(set_attr "op_type" "RR<E>") 8761 (set_attr "z10prop" "z10_super_c_E1")]) 8762 8763 ; lcr, lcgr 8764 (define_insn "*neg<mode>2_cconly" 8765 [(set (reg CC_REGNUM) 8766 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) 8767 (const_int 0))) 8768 (clobber (match_scratch:GPR 0 "=d"))] 8769 "s390_match_ccmode (insn, CCAmode)" 8770 "lc<g>r\t%0,%1" 8771 [(set_attr "op_type" "RR<E>") 8772 (set_attr "z10prop" "z10_super_c_E1")]) 8773 8774 ; lcr, lcgr 8775 (define_insn "*neg<mode>2" 8776 [(set (match_operand:GPR 0 "register_operand" "=d") 8777 (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) 8778 (clobber (reg:CC CC_REGNUM))] 8779 "" 8780 "lc<g>r\t%0,%1" 8781 [(set_attr "op_type" "RR<E>") 8782 (set_attr "z10prop" "z10_super_c_E1")]) 8783 8784 (define_insn "*negdi2_31" 8785 [(set (match_operand:DI 0 "register_operand" "=d") 8786 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 8787 (clobber (reg:CC CC_REGNUM))] 8788 "!TARGET_ZARCH" 8789 "#") 8790 8791 ; Split a DImode NEG on 31bit into 2 SImode NEGs 8792 8793 ; Doing the twos complement separately on the SImode parts does an 8794 ; unwanted +1 on the high part which needs to be subtracted afterwards 8795 ; ... unless the +1 on the low part created an overflow. 8796 8797 (define_split 8798 [(set (match_operand:DI 0 "register_operand" "") 8799 (neg:DI (match_operand:DI 1 "register_operand" ""))) 8800 (clobber (reg:CC CC_REGNUM))] 8801 "!TARGET_ZARCH 8802 && (REGNO (operands[0]) == REGNO (operands[1]) 8803 || s390_split_ok_p (operands[0], operands[1], DImode, 0)) 8804 && reload_completed" 8805 [(parallel 8806 [(set (match_dup 2) (neg:SI (match_dup 3))) 8807 (clobber (reg:CC CC_REGNUM))]) 8808 (parallel 8809 [(set (reg:CCAP CC_REGNUM) 8810 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) 8811 (set (match_dup 4) (neg:SI (match_dup 5)))]) 8812 (set (pc) 8813 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) 8814 (pc) 8815 (label_ref (match_dup 6)))) 8816 (parallel 8817 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 8818 (clobber (reg:CC CC_REGNUM))]) 8819 (match_dup 6)] 8820 "operands[2] = operand_subword (operands[0], 0, 0, DImode); 8821 operands[3] = operand_subword (operands[1], 0, 0, DImode); 8822 operands[4] = operand_subword (operands[0], 1, 0, DImode); 8823 operands[5] = operand_subword (operands[1], 1, 0, DImode); 8824 operands[6] = gen_label_rtx ();") 8825 8826 ; Like above but first make a copy of the low part of the src operand 8827 ; since it might overlap with the high part of the destination. 8828 8829 (define_split 8830 [(set (match_operand:DI 0 "register_operand" "") 8831 (neg:DI (match_operand:DI 1 "register_operand" ""))) 8832 (clobber (reg:CC CC_REGNUM))] 8833 "!TARGET_ZARCH 8834 && s390_split_ok_p (operands[0], operands[1], DImode, 1) 8835 && reload_completed" 8836 [; Make a backup of op5 first 8837 (set (match_dup 4) (match_dup 5)) 8838 ; Setting op2 here might clobber op5 8839 (parallel 8840 [(set (match_dup 2) (neg:SI (match_dup 3))) 8841 (clobber (reg:CC CC_REGNUM))]) 8842 (parallel 8843 [(set (reg:CCAP CC_REGNUM) 8844 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) 8845 (set (match_dup 4) (neg:SI (match_dup 4)))]) 8846 (set (pc) 8847 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) 8848 (pc) 8849 (label_ref (match_dup 6)))) 8850 (parallel 8851 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 8852 (clobber (reg:CC CC_REGNUM))]) 8853 (match_dup 6)] 8854 "operands[2] = operand_subword (operands[0], 0, 0, DImode); 8855 operands[3] = operand_subword (operands[1], 0, 0, DImode); 8856 operands[4] = operand_subword (operands[0], 1, 0, DImode); 8857 operands[5] = operand_subword (operands[1], 1, 0, DImode); 8858 operands[6] = gen_label_rtx ();") 8859 8860 ; 8861 ; neg(tf|df|sf)2 instruction pattern(s). 8862 ; 8863 8864 (define_expand "neg<mode>2<tf_fpr>" 8865 [(parallel 8866 [(set (match_operand:BFP 0 "register_operand") 8867 (neg:BFP (match_operand:BFP 1 "register_operand"))) 8868 (clobber (reg:CC CC_REGNUM))])] 8869 "TARGET_HARD_FLOAT") 8870 8871 ; lcxbr, lcdbr, lcebr 8872 (define_insn "*neg<mode>2_cc" 8873 [(set (reg CC_REGNUM) 8874 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) 8875 (match_operand:BFP 2 "const0_operand" ""))) 8876 (set (match_operand:BFP 0 "register_operand" "=f") 8877 (neg:BFP (match_dup 1)))] 8878 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8879 "lc<xde>br\t%0,%1" 8880 [(set_attr "op_type" "RRE") 8881 (set_attr "type" "fsimp<type>")]) 8882 8883 ; lcxbr, lcdbr, lcebr 8884 (define_insn "*neg<mode>2_cconly" 8885 [(set (reg CC_REGNUM) 8886 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) 8887 (match_operand:BFP 2 "const0_operand" ""))) 8888 (clobber (match_scratch:BFP 0 "=f"))] 8889 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8890 "lc<xde>br\t%0,%1" 8891 [(set_attr "op_type" "RRE") 8892 (set_attr "type" "fsimp<type>")]) 8893 8894 ; lcdfr 8895 (define_insn "*neg<mode>2_nocc" 8896 [(set (match_operand:FP 0 "register_operand" "=f") 8897 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] 8898 "TARGET_DFP" 8899 "lcdfr\t%0,%1" 8900 [(set_attr "op_type" "RRE") 8901 (set_attr "type" "fsimp<type>")]) 8902 8903 ; lcxbr, lcdbr, lcebr 8904 ; FIXME: wflcdb does not clobber cc 8905 ; FIXME: Does wflcdb ever match here? 8906 (define_insn "*neg<mode>2" 8907 [(set (match_operand:BFP 0 "register_operand" "=f,v,v") 8908 (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) 8909 (clobber (reg:CC CC_REGNUM))] 8910 "TARGET_HARD_FLOAT" 8911 "@ 8912 lc<xde>br\t%0,%1 8913 wflcdb\t%0,%1 8914 wflcsb\t%0,%1" 8915 [(set_attr "op_type" "RRE,VRR,VRR") 8916 (set_attr "cpu_facility" "*,vx,vxe") 8917 (set_attr "type" "fsimp<type>,*,*") 8918 (set_attr "enabled" "*,<DF>,<SF>")]) 8919 8920 8921 ;; 8922 ;;- Absolute value instructions. 8923 ;; 8924 8925 ; 8926 ; abs(di|si)2 instruction pattern(s). 8927 ; 8928 8929 (define_insn "*absdi2_sign_cc" 8930 [(set (reg CC_REGNUM) 8931 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI 8932 (match_operand:SI 1 "register_operand" "d") 0) 8933 (const_int 32)) (const_int 32))) 8934 (const_int 0))) 8935 (set (match_operand:DI 0 "register_operand" "=d") 8936 (abs:DI (sign_extend:DI (match_dup 1))))] 8937 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 8938 "lpgfr\t%0,%1" 8939 [(set_attr "op_type" "RRE") 8940 (set_attr "z10prop" "z10_c")]) 8941 8942 (define_insn "*absdi2_sign" 8943 [(set (match_operand:DI 0 "register_operand" "=d") 8944 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 8945 (clobber (reg:CC CC_REGNUM))] 8946 "TARGET_ZARCH" 8947 "lpgfr\t%0,%1" 8948 [(set_attr "op_type" "RRE") 8949 (set_attr "z10prop" "z10_c")]) 8950 8951 ; lpr, lpgr 8952 (define_insn "*abs<mode>2_cc" 8953 [(set (reg CC_REGNUM) 8954 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) 8955 (const_int 0))) 8956 (set (match_operand:GPR 0 "register_operand" "=d") 8957 (abs:GPR (match_dup 1)))] 8958 "s390_match_ccmode (insn, CCAmode)" 8959 "lp<g>r\t%0,%1" 8960 [(set_attr "op_type" "RR<E>") 8961 (set_attr "z10prop" "z10_c")]) 8962 8963 ; lpr, lpgr 8964 (define_insn "*abs<mode>2_cconly" 8965 [(set (reg CC_REGNUM) 8966 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) 8967 (const_int 0))) 8968 (clobber (match_scratch:GPR 0 "=d"))] 8969 "s390_match_ccmode (insn, CCAmode)" 8970 "lp<g>r\t%0,%1" 8971 [(set_attr "op_type" "RR<E>") 8972 (set_attr "z10prop" "z10_c")]) 8973 8974 ; lpr, lpgr 8975 (define_insn "abs<mode>2" 8976 [(set (match_operand:GPR 0 "register_operand" "=d") 8977 (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 8978 (clobber (reg:CC CC_REGNUM))] 8979 "" 8980 "lp<g>r\t%0,%1" 8981 [(set_attr "op_type" "RR<E>") 8982 (set_attr "z10prop" "z10_c")]) 8983 8984 ; 8985 ; abs(tf|df|sf)2 instruction pattern(s). 8986 ; 8987 8988 (define_expand "abs<mode>2<tf_fpr>" 8989 [(parallel 8990 [(set (match_operand:BFP 0 "register_operand" "=f") 8991 (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 8992 (clobber (reg:CC CC_REGNUM))])] 8993 "TARGET_HARD_FLOAT" 8994 "") 8995 8996 ; lpxbr, lpdbr, lpebr 8997 (define_insn "*abs<mode>2_cc" 8998 [(set (reg CC_REGNUM) 8999 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) 9000 (match_operand:BFP 2 "const0_operand" ""))) 9001 (set (match_operand:BFP 0 "register_operand" "=f") 9002 (abs:BFP (match_dup 1)))] 9003 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 9004 "lp<xde>br\t%0,%1" 9005 [(set_attr "op_type" "RRE") 9006 (set_attr "type" "fsimp<type>")]) 9007 9008 ; lpxbr, lpdbr, lpebr 9009 (define_insn "*abs<mode>2_cconly" 9010 [(set (reg CC_REGNUM) 9011 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) 9012 (match_operand:BFP 2 "const0_operand" ""))) 9013 (clobber (match_scratch:BFP 0 "=f"))] 9014 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 9015 "lp<xde>br\t%0,%1" 9016 [(set_attr "op_type" "RRE") 9017 (set_attr "type" "fsimp<type>")]) 9018 9019 ; lpdfr 9020 (define_insn "*abs<mode>2_nocc" 9021 [(set (match_operand:FP 0 "register_operand" "=f") 9022 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] 9023 "TARGET_DFP" 9024 "lpdfr\t%0,%1" 9025 [(set_attr "op_type" "RRE") 9026 (set_attr "type" "fsimp<type>")]) 9027 9028 ; lpxbr, lpdbr, lpebr 9029 ; FIXME: wflpdb does not clobber cc 9030 (define_insn "*abs<mode>2" 9031 [(set (match_operand:BFP 0 "register_operand" "=f,v") 9032 (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) 9033 (clobber (reg:CC CC_REGNUM))] 9034 "TARGET_HARD_FLOAT" 9035 "@ 9036 lp<xde>br\t%0,%1 9037 wflpdb\t%0,%1" 9038 [(set_attr "op_type" "RRE,VRR") 9039 (set_attr "cpu_facility" "*,vx") 9040 (set_attr "type" "fsimp<type>,*") 9041 (set_attr "enabled" "*,<DFDI>")]) 9042 9043 9044 ;; 9045 ;;- Negated absolute value instructions 9046 ;; 9047 9048 ; 9049 ; Integer 9050 ; 9051 9052 (define_insn "*negabsdi2_sign_cc" 9053 [(set (reg CC_REGNUM) 9054 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI 9055 (match_operand:SI 1 "register_operand" "d") 0) 9056 (const_int 32)) (const_int 32)))) 9057 (const_int 0))) 9058 (set (match_operand:DI 0 "register_operand" "=d") 9059 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] 9060 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 9061 "lngfr\t%0,%1" 9062 [(set_attr "op_type" "RRE") 9063 (set_attr "z10prop" "z10_c")]) 9064 9065 (define_insn "*negabsdi2_sign" 9066 [(set (match_operand:DI 0 "register_operand" "=d") 9067 (neg:DI (abs:DI (sign_extend:DI 9068 (match_operand:SI 1 "register_operand" "d"))))) 9069 (clobber (reg:CC CC_REGNUM))] 9070 "TARGET_ZARCH" 9071 "lngfr\t%0,%1" 9072 [(set_attr "op_type" "RRE") 9073 (set_attr "z10prop" "z10_c")]) 9074 9075 ; lnr, lngr 9076 (define_insn "*negabs<mode>2_cc" 9077 [(set (reg CC_REGNUM) 9078 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 9079 (const_int 0))) 9080 (set (match_operand:GPR 0 "register_operand" "=d") 9081 (neg:GPR (abs:GPR (match_dup 1))))] 9082 "s390_match_ccmode (insn, CCAmode)" 9083 "ln<g>r\t%0,%1" 9084 [(set_attr "op_type" "RR<E>") 9085 (set_attr "z10prop" "z10_c")]) 9086 9087 ; lnr, lngr 9088 (define_insn "*negabs<mode>2_cconly" 9089 [(set (reg CC_REGNUM) 9090 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 9091 (const_int 0))) 9092 (clobber (match_scratch:GPR 0 "=d"))] 9093 "s390_match_ccmode (insn, CCAmode)" 9094 "ln<g>r\t%0,%1" 9095 [(set_attr "op_type" "RR<E>") 9096 (set_attr "z10prop" "z10_c")]) 9097 9098 ; lnr, lngr 9099 (define_insn "*negabs<mode>2" 9100 [(set (match_operand:GPR 0 "register_operand" "=d") 9101 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) 9102 (clobber (reg:CC CC_REGNUM))] 9103 "" 9104 "ln<g>r\t%0,%1" 9105 [(set_attr "op_type" "RR<E>") 9106 (set_attr "z10prop" "z10_c")]) 9107 9108 ; 9109 ; Floating point 9110 ; 9111 9112 ; lnxbr, lndbr, lnebr 9113 (define_insn "*negabs<mode>2_cc" 9114 [(set (reg CC_REGNUM) 9115 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 9116 (match_operand:BFP 2 "const0_operand" ""))) 9117 (set (match_operand:BFP 0 "register_operand" "=f") 9118 (neg:BFP (abs:BFP (match_dup 1))))] 9119 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 9120 "ln<xde>br\t%0,%1" 9121 [(set_attr "op_type" "RRE") 9122 (set_attr "type" "fsimp<type>")]) 9123 9124 ; lnxbr, lndbr, lnebr 9125 (define_insn "*negabs<mode>2_cconly" 9126 [(set (reg CC_REGNUM) 9127 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 9128 (match_operand:BFP 2 "const0_operand" ""))) 9129 (clobber (match_scratch:BFP 0 "=f"))] 9130 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 9131 "ln<xde>br\t%0,%1" 9132 [(set_attr "op_type" "RRE") 9133 (set_attr "type" "fsimp<type>")]) 9134 9135 ; lndfr 9136 (define_insn "*negabs<mode>2_nocc" 9137 [(set (match_operand:FP 0 "register_operand" "=f") 9138 (neg:FP (abs:FP (match_operand:FP 1 "register_operand" "<fT0>"))))] 9139 "TARGET_DFP" 9140 "lndfr\t%0,%1" 9141 [(set_attr "op_type" "RRE") 9142 (set_attr "type" "fsimp<type>")]) 9143 9144 ; lnxbr, lndbr, lnebr 9145 ; FIXME: wflndb does not clobber cc 9146 (define_insn "*negabs<mode>2" 9147 [(set (match_operand:BFP 0 "register_operand" "=f,v") 9148 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) 9149 (clobber (reg:CC CC_REGNUM))] 9150 "TARGET_HARD_FLOAT" 9151 "@ 9152 ln<xde>br\t%0,%1 9153 wflndb\t%0,%1" 9154 [(set_attr "op_type" "RRE,VRR") 9155 (set_attr "cpu_facility" "*,vx") 9156 (set_attr "type" "fsimp<type>,*") 9157 (set_attr "enabled" "*,<DFDI>")]) 9158 9159 ;; 9160 ;;- Square root instructions. 9161 ;; 9162 9163 ; 9164 ; sqrt(df|sf)2 instruction pattern(s). 9165 ; 9166 9167 ; sqxbr, sqdbr, sqebr, sqdb, sqeb 9168 (define_insn "sqrt<mode>2<tf_fpr>" 9169 [(set (match_operand:BFP 0 "register_operand" "=f,f,v") 9170 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] 9171 "TARGET_HARD_FLOAT" 9172 "@ 9173 sq<xde>br\t%0,%1 9174 sq<xde>b\t%0,%1 9175 wfsqdb\t%v0,%v1" 9176 [(set_attr "op_type" "RRE,RXE,VRR") 9177 (set_attr "type" "fsqrt<type>") 9178 (set_attr "cpu_facility" "*,*,vx") 9179 (set_attr "enabled" "*,<DSF>,<DFDI>")]) 9180 9181 9182 ;; 9183 ;;- One complement instructions. 9184 ;; 9185 9186 ; 9187 ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). 9188 ; 9189 9190 (define_expand "one_cmpl<mode>2" 9191 [(parallel 9192 [(set (match_operand:INT 0 "register_operand" "") 9193 (xor:INT (match_operand:INT 1 "register_operand" "") 9194 (const_int -1))) 9195 (clobber (reg:CC CC_REGNUM))])] 9196 "" 9197 "") 9198 9199 9200 ;; 9201 ;; Find leftmost bit instructions. 9202 ;; 9203 9204 (define_expand "clzdi2" 9205 [(set (match_operand:DI 0 "register_operand" "=d") 9206 (clz:DI (match_operand:DI 1 "register_operand" "d")))] 9207 "TARGET_EXTIMM && TARGET_ZARCH" 9208 { 9209 rtx_insn *insn; 9210 rtx clz_equal; 9211 rtx wide_reg = gen_reg_rtx (TImode); 9212 rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); 9213 9214 clz_equal = gen_rtx_CLZ (DImode, operands[1]); 9215 9216 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); 9217 9218 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); 9219 set_unique_reg_note (insn, REG_EQUAL, clz_equal); 9220 9221 DONE; 9222 }) 9223 9224 ; CLZ result is in hard reg op0 - this is the high part of the target operand 9225 ; The source with the left-most one bit cleared is in hard reg op0 + 1 - the low part 9226 (define_insn "clztidi2" 9227 [(set (match_operand:TI 0 "register_operand" "=d") 9228 (ior:TI 9229 (ashift:TI (zero_extend:TI (clz:DI (match_operand:DI 1 "register_operand" "d"))) 9230 (const_int 64)) 9231 (zero_extend:TI 9232 (xor:DI (match_dup 1) 9233 (lshiftrt (match_operand:DI 2 "const_int_operand" "") 9234 (subreg:SI (clz:DI (match_dup 1)) 4)))))) 9235 (clobber (reg:CC CC_REGNUM))] 9236 "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 9237 && TARGET_EXTIMM && TARGET_ZARCH" 9238 "flogr\t%0,%1" 9239 [(set_attr "op_type" "RRE")]) 9240 9241 9242 ;; 9243 ;;- Rotate instructions. 9244 ;; 9245 9246 ; 9247 ; rotl(di|si)3 instruction pattern(s). 9248 ; 9249 9250 (define_expand "rotl<mode>3" 9251 [(set (match_operand:GPR 0 "register_operand" "") 9252 (rotate:GPR (match_operand:GPR 1 "register_operand" "") 9253 (match_operand:QI 2 "shift_count_operand" "")))] 9254 "" 9255 "") 9256 9257 ; rll, rllg 9258 (define_insn "*rotl<mode>3" 9259 [(set (match_operand:GPR 0 "register_operand" "=d") 9260 (rotate:GPR (match_operand:GPR 1 "register_operand" "d") 9261 (match_operand:QI 2 "shift_count_operand" "jsc")))] 9262 "" 9263 "rll<g>\t%0,%1,%Y2" 9264 [(set_attr "op_type" "RSE") 9265 (set_attr "atype" "reg") 9266 (set_attr "z10prop" "z10_super_E1")]) 9267 9268 9269 ;; 9270 ;;- Shift instructions. 9271 ;; 9272 9273 ; 9274 ; (ashl|lshr)(di|si)3 instruction pattern(s). 9275 ; Left shifts and logical right shifts 9276 9277 (define_expand "<shift><mode>3" 9278 [(set (match_operand:DSI 0 "register_operand" "") 9279 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") 9280 (match_operand:QI 2 "shift_count_operand" "")))] 9281 "" 9282 "") 9283 9284 ; ESA 64 bit register pair shift with reg or imm shift count 9285 ; sldl, srdl 9286 (define_insn "*<shift>di3_31" 9287 [(set (match_operand:DI 0 "register_operand" "=d") 9288 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") 9289 (match_operand:QI 2 "shift_count_operand" "jsc")))] 9290 "!TARGET_ZARCH" 9291 "s<lr>dl\t%0,%Y2" 9292 [(set_attr "op_type" "RS") 9293 (set_attr "atype" "reg") 9294 (set_attr "z196prop" "z196_cracked")]) 9295 9296 9297 ; 64 bit register shift with reg or imm shift count 9298 ; sll, srl, sllg, srlg, sllk, srlk 9299 (define_insn "*<shift><mode>3" 9300 [(set (match_operand:GPR 0 "register_operand" "=d, d") 9301 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") 9302 (match_operand:QI 2 "shift_count_operand" "jsc,jsc")))] 9303 "" 9304 "@ 9305 s<lr>l<g>\t%0,<1>%Y2 9306 s<lr>l<gk>\t%0,%1,%Y2" 9307 [(set_attr "op_type" "RS<E>,RSY") 9308 (set_attr "atype" "reg,reg") 9309 (set_attr "cpu_facility" "*,z196") 9310 (set_attr "z10prop" "z10_super_E1,*")]) 9311 9312 9313 ; 9314 ; ashr(di|si)3 instruction pattern(s). 9315 ; Arithmetic right shifts 9316 9317 (define_expand "ashr<mode>3" 9318 [(parallel 9319 [(set (match_operand:DSI 0 "register_operand" "") 9320 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") 9321 (match_operand:QI 2 "shift_count_operand" ""))) 9322 (clobber (reg:CC CC_REGNUM))])] 9323 "" 9324 "") 9325 9326 (define_insn "*ashrdi3_31<setcc><cconly>" 9327 [(set (match_operand:DI 0 "register_operand" "=d") 9328 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 9329 (match_operand:QI 2 "shift_count_operand" "jsc"))) 9330 (clobber (reg:CC CC_REGNUM))] 9331 "!TARGET_ZARCH" 9332 "srda\t%0,%Y2" 9333 [(set_attr "op_type" "RS") 9334 (set_attr "atype" "reg")]) 9335 9336 9337 ; sra, srag 9338 (define_insn "*ashr<mode>3<setcc><cconly>" 9339 [(set (match_operand:GPR 0 "register_operand" "=d, d") 9340 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") 9341 (match_operand:QI 2 "shift_count_operand" "jsc,jsc"))) 9342 (clobber (reg:CC CC_REGNUM))] 9343 "" 9344 "@ 9345 sra<g>\t%0,<1>%Y2 9346 sra<gk>\t%0,%1,%Y2" 9347 [(set_attr "op_type" "RS<E>,RSY") 9348 (set_attr "atype" "reg") 9349 (set_attr "cpu_facility" "*,z196") 9350 (set_attr "z10prop" "z10_super_E1,*")]) 9351 9352 9353 ;; 9354 ;; Branch instruction patterns. 9355 ;; 9356 9357 (define_expand "cbranch<mode>4" 9358 [(set (pc) 9359 (if_then_else (match_operator 0 "comparison_operator" 9360 [(match_operand:GPR 1 "register_operand" "") 9361 (match_operand:GPR 2 "general_operand" "")]) 9362 (label_ref (match_operand 3 "" "")) 9363 (pc)))] 9364 "" 9365 "s390_emit_jump (operands[3], 9366 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); 9367 DONE;") 9368 9369 (define_expand "cbranch<mode>4" 9370 [(set (pc) 9371 (if_then_else (match_operator 0 "comparison_operator" 9372 [(match_operand:FP_ANYTF 1 "register_operand" "") 9373 (match_operand:FP_ANYTF 2 "general_operand" "")]) 9374 (label_ref (match_operand 3 "" "")) 9375 (pc)))] 9376 "TARGET_HARD_FLOAT" 9377 "s390_emit_jump (operands[3], 9378 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); 9379 DONE;") 9380 9381 (define_expand "cbranchcc4" 9382 [(set (pc) 9383 (if_then_else (match_operator 0 "s390_comparison" 9384 [(match_operand 1 "cc_reg_operand" "") 9385 (match_operand 2 "const_int_operand" "")]) 9386 (label_ref (match_operand 3 "" "")) 9387 (pc)))] 9388 "" 9389 "") 9390 9391 9392 ;; 9393 ;;- Conditional jump instructions. 9394 ;; 9395 9396 (define_insn "*cjump_64" 9397 [(set (pc) 9398 (if_then_else 9399 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) 9400 (match_operand 2 "const_int_operand" "")]) 9401 (label_ref (match_operand 0 "" "")) 9402 (pc)))] 9403 "" 9404 { 9405 if (get_attr_length (insn) == 4) 9406 return "j%C1\t%l0"; 9407 else 9408 return "jg%C1\t%l0"; 9409 } 9410 [(set_attr "op_type" "RI") 9411 (set_attr "type" "branch") 9412 (set (attr "length") 9413 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9414 (const_int 4) (const_int 6)))]) 9415 9416 (define_insn "*cjump_long" 9417 [(set (pc) 9418 (if_then_else 9419 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9420 (match_operand 0 "address_operand" "ZQZR") 9421 (pc)))] 9422 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" 9423 { 9424 if (get_attr_op_type (insn) == OP_TYPE_RR) 9425 return "b%C1r\t%0"; 9426 else 9427 return "b%C1\t%a0"; 9428 } 9429 [(set (attr "op_type") 9430 (if_then_else (match_operand 0 "register_operand" "") 9431 (const_string "RR") (const_string "RX"))) 9432 (set (attr "mnemonic") 9433 (if_then_else (match_operand 0 "register_operand" "") 9434 (const_string "bcr") (const_string "bc"))) 9435 (set_attr "type" "branch") 9436 (set_attr "atype" "agen")]) 9437 9438 ;; A conditional return instruction. 9439 (define_insn "*c<code>" 9440 [(set (pc) 9441 (if_then_else 9442 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9443 (ANY_RETURN) 9444 (pc)))] 9445 "s390_can_use_<code>_insn ()" 9446 { 9447 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 9448 { 9449 s390_indirect_branch_via_thunk (RETURN_REGNUM, 9450 INVALID_REGNUM, 9451 operands[0], 9452 s390_indirect_branch_type_return); 9453 return ""; 9454 } 9455 else 9456 return "b%C0r\t%%r14"; 9457 } 9458 [(set (attr "op_type") 9459 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 9460 (const_string "RIL") 9461 (const_string "RR"))) 9462 (set (attr "mnemonic") 9463 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 9464 (const_string "brcl") 9465 (const_string "bcr"))) 9466 (set_attr "type" "jsr") 9467 (set_attr "atype" "agen")]) 9468 9469 ;; 9470 ;;- Negated conditional jump instructions. 9471 ;; 9472 9473 (define_insn "*icjump_64" 9474 [(set (pc) 9475 (if_then_else 9476 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) 9477 (match_operand 2 "const_int_operand" "")]) 9478 (pc) 9479 (label_ref (match_operand 0 "" ""))))] 9480 "" 9481 { 9482 if (get_attr_length (insn) == 4) 9483 return "j%D1\t%l0"; 9484 else 9485 return "jg%D1\t%l0"; 9486 } 9487 [(set_attr "op_type" "RI") 9488 (set_attr "type" "branch") 9489 (set (attr "length") 9490 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9491 (const_int 4) (const_int 6)))]) 9492 9493 (define_insn "*icjump_long" 9494 [(set (pc) 9495 (if_then_else 9496 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 9497 (pc) 9498 (match_operand 0 "address_operand" "ZQZR")))] 9499 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" 9500 { 9501 if (get_attr_op_type (insn) == OP_TYPE_RR) 9502 return "b%D1r\t%0"; 9503 else 9504 return "b%D1\t%a0"; 9505 } 9506 [(set (attr "op_type") 9507 (if_then_else (match_operand 0 "register_operand" "") 9508 (const_string "RR") (const_string "RX"))) 9509 (set (attr "mnemonic") 9510 (if_then_else (match_operand 0 "register_operand" "") 9511 (const_string "bcr") (const_string "bc"))) 9512 (set_attr "type" "branch") 9513 (set_attr "atype" "agen")]) 9514 9515 ;; 9516 ;;- Trap instructions. 9517 ;; 9518 9519 (define_insn "trap" 9520 [(trap_if (const_int 1) (const_int 0))] 9521 "" 9522 "j\t.+2" 9523 [(set_attr "op_type" "RI") 9524 (set_attr "type" "branch")]) 9525 9526 (define_expand "ctrap<mode>4" 9527 [(trap_if (match_operator 0 "comparison_operator" 9528 [(match_operand:GPR 1 "register_operand" "") 9529 (match_operand:GPR 2 "general_operand" "")]) 9530 (match_operand 3 "const0_operand" ""))] 9531 "" 9532 { 9533 rtx cond = s390_emit_compare (GET_CODE (operands[0]), 9534 operands[1], operands[2]); 9535 emit_insn (gen_condtrap (cond, XEXP (cond, 0))); 9536 DONE; 9537 }) 9538 9539 (define_expand "ctrap<mode>4" 9540 [(trap_if (match_operator 0 "comparison_operator" 9541 [(match_operand:FP 1 "register_operand" "") 9542 (match_operand:FP 2 "general_operand" "")]) 9543 (match_operand 3 "const0_operand" ""))] 9544 "" 9545 { 9546 rtx cond = s390_emit_compare (GET_CODE (operands[0]), 9547 operands[1], operands[2]); 9548 emit_insn (gen_condtrap (cond, XEXP (cond, 0))); 9549 DONE; 9550 }) 9551 9552 (define_insn "condtrap" 9553 [(trap_if (match_operator 0 "s390_comparison" 9554 [(match_operand 1 "cc_reg_operand" "c") 9555 (const_int 0)]) 9556 (const_int 0))] 9557 "" 9558 "j%C0\t.+2"; 9559 [(set_attr "op_type" "RI") 9560 (set_attr "type" "branch")]) 9561 9562 ; crt, cgrt, cit, cgit 9563 (define_insn "*cmp_and_trap_signed_int<mode>" 9564 [(trap_if (match_operator 0 "s390_signed_integer_comparison" 9565 [(match_operand:GPR 1 "register_operand" "d,d") 9566 (match_operand:GPR 2 "nonmemory_operand" "d,K")]) 9567 (const_int 0))] 9568 "TARGET_Z10" 9569 "@ 9570 c<g>rt%C0\t%1,%2 9571 c<g>it%C0\t%1,%h2" 9572 [(set_attr "op_type" "RRF,RIE") 9573 (set_attr "type" "branch") 9574 (set_attr "z10prop" "z10_super_c,z10_super")]) 9575 9576 ; clrt, clgrt, clfit, clgit, clt, clgt 9577 (define_insn "*cmp_and_trap_unsigned_int<mode>" 9578 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" 9579 [(match_operand:GPR 1 "register_operand" "d,d,d") 9580 (match_operand:GPR 2 "general_operand" "d,D,S")]) 9581 (const_int 0))] 9582 "TARGET_Z10" 9583 "@ 9584 cl<g>rt%C0\t%1,%2 9585 cl<gf>it%C0\t%1,%x2 9586 cl<g>t%C0\t%1,%2" 9587 [(set_attr "op_type" "RRF,RIE,RSY") 9588 (set_attr "type" "branch") 9589 (set_attr "z10prop" "z10_super_c,z10_super,*") 9590 (set_attr "cpu_facility" "z10,z10,zEC12")]) 9591 9592 ; lat, lgat 9593 (define_insn "*load_and_trap<mode>" 9594 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") 9595 (const_int 0)) 9596 (const_int 0)) 9597 (set (match_operand:GPR 1 "register_operand" "=d") 9598 (match_dup 0))] 9599 "TARGET_ZEC12" 9600 "l<g>at\t%1,%0" 9601 [(set_attr "op_type" "RXY")]) 9602 9603 9604 ;; 9605 ;;- Loop instructions. 9606 ;; 9607 ;; This is all complicated by the fact that since this is a jump insn 9608 ;; we must handle our own output reloads. 9609 9610 ;; branch on index 9611 9612 ; This splitter will be matched by combine and has to add the 2 moves 9613 ; necessary to load the compare and the increment values into a 9614 ; register pair as needed by brxle. 9615 9616 (define_insn_and_split "*brx_stage1_<GPR:mode>" 9617 [(set (pc) 9618 (if_then_else 9619 (match_operator 6 "s390_brx_operator" 9620 [(plus:GPR (match_operand:GPR 1 "register_operand" "") 9621 (match_operand:GPR 2 "general_operand" "")) 9622 (match_operand:GPR 3 "register_operand" "")]) 9623 (label_ref (match_operand 0 "" "")) 9624 (pc))) 9625 (set (match_operand:GPR 4 "nonimmediate_operand" "") 9626 (plus:GPR (match_dup 1) (match_dup 2))) 9627 (clobber (match_scratch:GPR 5 ""))] 9628 "" 9629 "#" 9630 "!reload_completed && !reload_in_progress" 9631 [(set (match_dup 7) (match_dup 2)) ; the increment 9632 (set (match_dup 8) (match_dup 3)) ; the comparison value 9633 (parallel [(set (pc) 9634 (if_then_else 9635 (match_op_dup 6 9636 [(plus:GPR (match_dup 1) (match_dup 7)) 9637 (match_dup 8)]) 9638 (label_ref (match_dup 0)) 9639 (pc))) 9640 (set (match_dup 4) 9641 (plus:GPR (match_dup 1) (match_dup 7))) 9642 (clobber (match_dup 5)) 9643 (clobber (reg:CC CC_REGNUM))])] 9644 { 9645 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); 9646 operands[7] = gen_lowpart (<GPR:MODE>mode, 9647 gen_highpart (word_mode, dreg)); 9648 operands[8] = gen_lowpart (<GPR:MODE>mode, 9649 gen_lowpart (word_mode, dreg)); 9650 }) 9651 9652 ; brxlg, brxhg 9653 9654 (define_insn_and_split "*brxg_64bit" 9655 [(set (pc) 9656 (if_then_else 9657 (match_operator 5 "s390_brx_operator" 9658 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") 9659 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) 9660 (subreg:DI (match_dup 2) 8)]) 9661 (label_ref (match_operand 0 "" "")) 9662 (pc))) 9663 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") 9664 (plus:DI (match_dup 1) 9665 (subreg:DI (match_dup 2) 0))) 9666 (clobber (match_scratch:DI 4 "=X,&1,&?d")) 9667 (clobber (reg:CC CC_REGNUM))] 9668 "TARGET_ZARCH" 9669 { 9670 if (which_alternative != 0) 9671 return "#"; 9672 else if (get_attr_length (insn) == 6) 9673 return "brx%E5g\t%1,%2,%l0"; 9674 else 9675 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; 9676 } 9677 "&& reload_completed 9678 && (!REG_P (operands[3]) 9679 || !rtx_equal_p (operands[1], operands[3]))" 9680 [(set (match_dup 4) (match_dup 1)) 9681 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) 9682 (clobber (reg:CC CC_REGNUM))]) 9683 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) 9684 (set (match_dup 3) (match_dup 4)) 9685 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 9686 (label_ref (match_dup 0)) 9687 (pc)))] 9688 "" 9689 [(set_attr "op_type" "RIE") 9690 (set_attr "type" "branch") 9691 (set (attr "length") 9692 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9693 (const_int 6) (const_int 16)))]) 9694 9695 ; brxle, brxh 9696 9697 (define_insn_and_split "*brx_64bit" 9698 [(set (pc) 9699 (if_then_else 9700 (match_operator 5 "s390_brx_operator" 9701 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") 9702 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) 9703 (subreg:SI (match_dup 2) 12)]) 9704 (label_ref (match_operand 0 "" "")) 9705 (pc))) 9706 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 9707 (plus:SI (match_dup 1) 9708 (subreg:SI (match_dup 2) 4))) 9709 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 9710 (clobber (reg:CC CC_REGNUM))] 9711 "TARGET_ZARCH" 9712 { 9713 if (which_alternative != 0) 9714 return "#"; 9715 else if (get_attr_length (insn) == 6) 9716 return "brx%C5\t%1,%2,%l0"; 9717 else 9718 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; 9719 } 9720 "&& reload_completed 9721 && (!REG_P (operands[3]) 9722 || !rtx_equal_p (operands[1], operands[3]))" 9723 [(set (match_dup 4) (match_dup 1)) 9724 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) 9725 (clobber (reg:CC CC_REGNUM))]) 9726 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) 9727 (set (match_dup 3) (match_dup 4)) 9728 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 9729 (label_ref (match_dup 0)) 9730 (pc)))] 9731 "" 9732 [(set_attr "op_type" "RSI") 9733 (set_attr "type" "branch") 9734 (set (attr "length") 9735 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9736 (const_int 6) (const_int 14)))]) 9737 9738 ; brxle, brxh 9739 9740 (define_insn_and_split "*brx_31bit" 9741 [(set (pc) 9742 (if_then_else 9743 (match_operator 5 "s390_brx_operator" 9744 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") 9745 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) 9746 (subreg:SI (match_dup 2) 4)]) 9747 (label_ref (match_operand 0 "" "")) 9748 (pc))) 9749 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 9750 (plus:SI (match_dup 1) 9751 (subreg:SI (match_dup 2) 0))) 9752 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 9753 (clobber (reg:CC CC_REGNUM))] 9754 "!TARGET_ZARCH" 9755 { 9756 if (which_alternative != 0) 9757 return "#"; 9758 else if (get_attr_length (insn) == 6) 9759 return "brx%C5\t%1,%2,%l0"; 9760 else 9761 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; 9762 } 9763 "&& reload_completed 9764 && (!REG_P (operands[3]) 9765 || !rtx_equal_p (operands[1], operands[3]))" 9766 [(set (match_dup 4) (match_dup 1)) 9767 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) 9768 (clobber (reg:CC CC_REGNUM))]) 9769 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) 9770 (set (match_dup 3) (match_dup 4)) 9771 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 9772 (label_ref (match_dup 0)) 9773 (pc)))] 9774 "" 9775 [(set_attr "op_type" "RSI") 9776 (set_attr "type" "branch") 9777 (set (attr "length") 9778 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9779 (const_int 6) (const_int 14)))]) 9780 9781 9782 ;; branch on count 9783 9784 (define_expand "doloop_end" 9785 [(use (match_operand 0 "" "")) ; loop pseudo 9786 (use (match_operand 1 "" ""))] ; label 9787 "" 9788 { 9789 if (GET_MODE (operands[0]) == SImode) 9790 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); 9791 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) 9792 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); 9793 else 9794 FAIL; 9795 9796 DONE; 9797 }) 9798 9799 (define_insn_and_split "doloop_si64" 9800 [(set (pc) 9801 (if_then_else 9802 (ne (match_operand:SI 1 "register_operand" "d,d,d") 9803 (const_int 1)) 9804 (label_ref (match_operand 0 "" "")) 9805 (pc))) 9806 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") 9807 (plus:SI (match_dup 1) (const_int -1))) 9808 (clobber (match_scratch:SI 3 "=X,&1,&?d")) 9809 (clobber (reg:CC CC_REGNUM))] 9810 "" 9811 { 9812 if (which_alternative != 0) 9813 return "#"; 9814 else if (get_attr_length (insn) == 4) 9815 return "brct\t%1,%l0"; 9816 else 9817 return "ahi\t%1,-1\;jgne\t%l0"; 9818 } 9819 "&& reload_completed 9820 && (! REG_P (operands[2]) 9821 || ! rtx_equal_p (operands[1], operands[2]))" 9822 [(set (match_dup 3) (match_dup 1)) 9823 (parallel [(set (reg:CCAN CC_REGNUM) 9824 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) 9825 (const_int 0))) 9826 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 9827 (set (match_dup 2) (match_dup 3)) 9828 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9829 (label_ref (match_dup 0)) 9830 (pc)))] 9831 "" 9832 [(set_attr "op_type" "RI") 9833 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9834 ; hurt us in the (rare) case of ahi. 9835 (set_attr "z10prop" "z10_super_E1") 9836 (set_attr "type" "branch") 9837 (set (attr "length") 9838 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9839 (const_int 4) (const_int 10)))]) 9840 9841 (define_insn_and_split "doloop_di" 9842 [(set (pc) 9843 (if_then_else 9844 (ne (match_operand:DI 1 "register_operand" "d,d,d") 9845 (const_int 1)) 9846 (label_ref (match_operand 0 "" "")) 9847 (pc))) 9848 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") 9849 (plus:DI (match_dup 1) (const_int -1))) 9850 (clobber (match_scratch:DI 3 "=X,&1,&?d")) 9851 (clobber (reg:CC CC_REGNUM))] 9852 "TARGET_ZARCH" 9853 { 9854 if (which_alternative != 0) 9855 return "#"; 9856 else if (get_attr_length (insn) == 4) 9857 return "brctg\t%1,%l0"; 9858 else 9859 return "aghi\t%1,-1\;jgne\t%l0"; 9860 } 9861 "&& reload_completed 9862 && (! REG_P (operands[2]) 9863 || ! rtx_equal_p (operands[1], operands[2]))" 9864 [(set (match_dup 3) (match_dup 1)) 9865 (parallel [(set (reg:CCAN CC_REGNUM) 9866 (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) 9867 (const_int 0))) 9868 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) 9869 (set (match_dup 2) (match_dup 3)) 9870 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9871 (label_ref (match_dup 0)) 9872 (pc)))] 9873 "" 9874 [(set_attr "op_type" "RI") 9875 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9876 ; hurt us in the (rare) case of ahi. 9877 (set_attr "z10prop" "z10_super_E1") 9878 (set_attr "type" "branch") 9879 (set (attr "length") 9880 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9881 (const_int 4) (const_int 10)))]) 9882 9883 ;; 9884 ;;- Unconditional jump instructions. 9885 ;; 9886 9887 ; 9888 ; jump instruction pattern(s). 9889 ; 9890 9891 (define_expand "jump" 9892 [(match_operand 0 "" "")] 9893 "" 9894 "s390_emit_jump (operands[0], NULL_RTX); DONE;") 9895 9896 (define_insn "*jump64" 9897 [(set (pc) (label_ref (match_operand 0 "" "")))] 9898 "" 9899 { 9900 if (get_attr_length (insn) == 4) 9901 return "j\t%l0"; 9902 else 9903 return "jg\t%l0"; 9904 } 9905 [(set_attr "op_type" "RI") 9906 (set_attr "type" "branch") 9907 (set (attr "length") 9908 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9909 (const_int 4) (const_int 6)))]) 9910 9911 ; 9912 ; indirect-jump instruction pattern(s). 9913 ; 9914 9915 (define_expand "indirect_jump" 9916 [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] 9917 "" 9918 { 9919 if (address_operand (operands[0], GET_MODE (operands[0]))) 9920 ; 9921 else if (TARGET_Z14 9922 && GET_MODE (operands[0]) == Pmode 9923 && memory_operand (operands[0], Pmode)) 9924 ; 9925 else 9926 operands[0] = force_reg (Pmode, operands[0]); 9927 9928 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) 9929 { 9930 operands[0] = force_reg (Pmode, operands[0]); 9931 if (TARGET_CPU_Z10) 9932 { 9933 if (TARGET_64BIT) 9934 emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); 9935 else 9936 emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); 9937 } 9938 else 9939 { 9940 if (TARGET_64BIT) 9941 emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); 9942 else 9943 emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); 9944 } 9945 DONE; 9946 } 9947 9948 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) 9949 { 9950 operands[0] = force_reg (Pmode, operands[0]); 9951 rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); 9952 if (TARGET_CPU_Z10) 9953 { 9954 if (TARGET_64BIT) 9955 emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], 9956 label_ref)); 9957 else 9958 emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], 9959 label_ref)); 9960 } 9961 else 9962 { 9963 if (TARGET_64BIT) 9964 emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], 9965 label_ref, 9966 force_reg (Pmode, label_ref))); 9967 else 9968 emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], 9969 label_ref, 9970 force_reg (Pmode, label_ref))); 9971 } 9972 DONE; 9973 } 9974 }) 9975 9976 (define_insn "*indirect_jump" 9977 [(set (pc) 9978 (match_operand 0 "address_operand" "ZR"))] 9979 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" 9980 { 9981 if (get_attr_op_type (insn) == OP_TYPE_RR) 9982 return "br\t%0"; 9983 else 9984 return "b\t%a0"; 9985 } 9986 [(set (attr "op_type") 9987 (if_then_else (match_operand 0 "register_operand" "") 9988 (const_string "RR") (const_string "RX"))) 9989 (set (attr "mnemonic") 9990 (if_then_else (match_operand 0 "register_operand" "") 9991 (const_string "br") (const_string "b"))) 9992 (set_attr "type" "branch") 9993 (set_attr "atype" "agen")]) 9994 9995 (define_insn "indirect_jump_via_thunk<mode>_z10" 9996 [(set (pc) 9997 (match_operand:P 0 "register_operand" "a"))] 9998 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 9999 && TARGET_CPU_Z10" 10000 { 10001 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10002 INVALID_REGNUM, 10003 NULL_RTX, 10004 s390_indirect_branch_type_jump); 10005 return ""; 10006 } 10007 [(set_attr "op_type" "RIL") 10008 (set_attr "mnemonic" "jg") 10009 (set_attr "type" "branch") 10010 (set_attr "atype" "agen")]) 10011 10012 (define_insn "indirect_jump_via_thunk<mode>" 10013 [(set (pc) 10014 (match_operand:P 0 "register_operand" " a")) 10015 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 10016 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 10017 && !TARGET_CPU_Z10" 10018 { 10019 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10020 INVALID_REGNUM, 10021 NULL_RTX, 10022 s390_indirect_branch_type_jump); 10023 return ""; 10024 } 10025 [(set_attr "op_type" "RIL") 10026 (set_attr "mnemonic" "jg") 10027 (set_attr "type" "branch") 10028 (set_attr "atype" "agen")]) 10029 10030 10031 ; The label_ref is wrapped into an if_then_else in order to hide it 10032 ; from mark_jump_label. Without this the label_ref would become the 10033 ; ONLY jump target of that jump breaking the control flow graph. 10034 (define_insn "indirect_jump_via_inlinethunk<mode>_z10" 10035 [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") 10036 (const_int 0) 10037 (const_int 0)) 10038 (const_int 0)] UNSPEC_EXECUTE_JUMP) 10039 (set (pc) (match_operand:P 0 "register_operand" "a"))] 10040 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 10041 && TARGET_CPU_Z10" 10042 { 10043 s390_indirect_branch_via_inline_thunk (operands[1]); 10044 return ""; 10045 } 10046 [(set_attr "op_type" "RIL") 10047 (set_attr "type" "branch") 10048 (set_attr "length" "10")]) 10049 10050 (define_insn "indirect_jump_via_inlinethunk<mode>" 10051 [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") 10052 (const_int 0) 10053 (const_int 0)) 10054 (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) 10055 (set (pc) (match_operand:P 0 "register_operand" "a"))] 10056 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 10057 && !TARGET_CPU_Z10" 10058 { 10059 s390_indirect_branch_via_inline_thunk (operands[2]); 10060 return ""; 10061 } 10062 [(set_attr "op_type" "RX") 10063 (set_attr "type" "branch") 10064 (set_attr "length" "8")]) 10065 10066 ; FIXME: LRA does not appear to be able to deal with MEMs being 10067 ; checked against address constraints like ZR above. So make this a 10068 ; separate pattern for now. 10069 (define_insn "*indirect2_jump" 10070 [(set (pc) 10071 (match_operand 0 "nonimmediate_operand" "a,T"))] 10072 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" 10073 "@ 10074 br\t%0 10075 bi\t%0" 10076 [(set_attr "op_type" "RR,RXY") 10077 (set_attr "type" "branch") 10078 (set_attr "atype" "agen") 10079 (set_attr "cpu_facility" "*,z14")]) 10080 10081 ; 10082 ; casesi instruction pattern(s). 10083 ; 10084 10085 (define_expand "casesi_jump" 10086 [(parallel 10087 [(set (pc) (match_operand 0 "address_operand")) 10088 (use (label_ref (match_operand 1 "")))])] 10089 "" 10090 { 10091 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) 10092 { 10093 operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); 10094 10095 if (TARGET_CPU_Z10) 10096 { 10097 if (TARGET_64BIT) 10098 emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], 10099 operands[1])); 10100 else 10101 emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], 10102 operands[1])); 10103 } 10104 else 10105 { 10106 if (TARGET_64BIT) 10107 emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], 10108 operands[1])); 10109 else 10110 emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], 10111 operands[1])); 10112 } 10113 DONE; 10114 } 10115 10116 if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) 10117 { 10118 operands[0] = force_reg (Pmode, operands[0]); 10119 rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); 10120 if (TARGET_CPU_Z10) 10121 { 10122 if (TARGET_64BIT) 10123 emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], 10124 operands[1], 10125 label_ref)); 10126 else 10127 emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], 10128 operands[1], 10129 label_ref)); 10130 } 10131 else 10132 { 10133 if (TARGET_64BIT) 10134 emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], 10135 operands[1], 10136 label_ref, 10137 force_reg (Pmode, label_ref))); 10138 else 10139 emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], 10140 operands[1], 10141 label_ref, 10142 force_reg (Pmode, label_ref))); 10143 } 10144 DONE; 10145 } 10146 }) 10147 10148 (define_insn "*casesi_jump" 10149 [(set (pc) (match_operand 0 "address_operand" "ZR")) 10150 (use (label_ref (match_operand 1 "" "")))] 10151 "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" 10152 { 10153 if (get_attr_op_type (insn) == OP_TYPE_RR) 10154 return "br\t%0"; 10155 else 10156 return "b\t%a0"; 10157 } 10158 [(set (attr "op_type") 10159 (if_then_else (match_operand 0 "register_operand" "") 10160 (const_string "RR") (const_string "RX"))) 10161 (set (attr "mnemonic") 10162 (if_then_else (match_operand 0 "register_operand" "") 10163 (const_string "br") (const_string "b"))) 10164 (set_attr "type" "branch") 10165 (set_attr "atype" "agen")]) 10166 10167 (define_insn "casesi_jump_via_thunk<mode>_z10" 10168 [(set (pc) (match_operand:P 0 "register_operand" "a")) 10169 (use (label_ref (match_operand 1 "" "")))] 10170 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 10171 && TARGET_CPU_Z10" 10172 { 10173 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10174 INVALID_REGNUM, 10175 NULL_RTX, 10176 s390_indirect_branch_type_jump); 10177 return ""; 10178 } 10179 [(set_attr "op_type" "RIL") 10180 (set_attr "mnemonic" "jg") 10181 (set_attr "type" "branch") 10182 (set_attr "atype" "agen")]) 10183 10184 (define_insn "casesi_jump_via_thunk<mode>" 10185 [(set (pc) (match_operand:P 0 "register_operand" "a")) 10186 (use (label_ref (match_operand 1 "" ""))) 10187 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 10188 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK 10189 && !TARGET_CPU_Z10" 10190 { 10191 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10192 INVALID_REGNUM, 10193 NULL_RTX, 10194 s390_indirect_branch_type_jump); 10195 return ""; 10196 } 10197 [(set_attr "op_type" "RIL") 10198 (set_attr "mnemonic" "jg") 10199 (set_attr "type" "branch") 10200 (set_attr "atype" "agen")]) 10201 10202 10203 ; The label_ref is wrapped into an if_then_else in order to hide it 10204 ; from mark_jump_label. Without this the label_ref would become the 10205 ; ONLY jump target of that jump breaking the control flow graph. 10206 (define_insn "casesi_jump_via_inlinethunk<mode>_z10" 10207 [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") 10208 (const_int 0) 10209 (const_int 0)) 10210 (const_int 0)] UNSPEC_EXECUTE_JUMP) 10211 (set (pc) (match_operand:P 0 "register_operand" "a")) 10212 (use (label_ref (match_operand 1 "" "")))] 10213 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 10214 && TARGET_CPU_Z10" 10215 { 10216 s390_indirect_branch_via_inline_thunk (operands[2]); 10217 return ""; 10218 } 10219 [(set_attr "op_type" "RIL") 10220 (set_attr "type" "cs") 10221 (set_attr "length" "10")]) 10222 10223 (define_insn "casesi_jump_via_inlinethunk<mode>" 10224 [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") 10225 (const_int 0) 10226 (const_int 0)) 10227 (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) 10228 (set (pc) (match_operand:P 0 "register_operand" "a")) 10229 (use (label_ref (match_operand 1 "" "")))] 10230 "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK 10231 && !TARGET_CPU_Z10" 10232 { 10233 s390_indirect_branch_via_inline_thunk (operands[3]); 10234 return ""; 10235 } 10236 [(set_attr "op_type" "RX") 10237 (set_attr "type" "cs") 10238 (set_attr "length" "8")]) 10239 10240 (define_expand "casesi" 10241 [(match_operand:SI 0 "general_operand" "") 10242 (match_operand:SI 1 "general_operand" "") 10243 (match_operand:SI 2 "general_operand" "") 10244 (label_ref (match_operand 3 "" "")) 10245 (label_ref (match_operand 4 "" ""))] 10246 "" 10247 { 10248 rtx index = gen_reg_rtx (SImode); 10249 rtx base = gen_reg_rtx (Pmode); 10250 rtx target = gen_reg_rtx (Pmode); 10251 10252 emit_move_insn (index, operands[0]); 10253 emit_insn (gen_subsi3 (index, index, operands[1])); 10254 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, 10255 operands[4]); 10256 10257 if (Pmode != SImode) 10258 index = convert_to_mode (Pmode, index, 1); 10259 if (GET_CODE (index) != REG) 10260 index = copy_to_mode_reg (Pmode, index); 10261 10262 if (TARGET_64BIT) 10263 emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); 10264 else 10265 emit_insn (gen_ashlsi3 (index, index, const2_rtx)); 10266 10267 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); 10268 10269 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); 10270 emit_move_insn (target, index); 10271 10272 if (flag_pic) 10273 target = gen_rtx_PLUS (Pmode, base, target); 10274 emit_jump_insn (gen_casesi_jump (target, operands[3])); 10275 10276 DONE; 10277 }) 10278 10279 10280 ;; 10281 ;;- Jump to subroutine. 10282 ;; 10283 ;; 10284 10285 ; 10286 ; untyped call instruction pattern(s). 10287 ; 10288 10289 ;; Call subroutine returning any type. 10290 (define_expand "untyped_call" 10291 [(parallel [(call (match_operand 0 "" "") 10292 (const_int 0)) 10293 (match_operand 1 "" "") 10294 (match_operand 2 "" "")])] 10295 "" 10296 { 10297 int i; 10298 10299 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); 10300 10301 for (i = 0; i < XVECLEN (operands[2], 0); i++) 10302 { 10303 rtx set = XVECEXP (operands[2], 0, i); 10304 emit_move_insn (SET_DEST (set), SET_SRC (set)); 10305 } 10306 10307 /* The optimizer does not know that the call sets the function value 10308 registers we stored in the result block. We avoid problems by 10309 claiming that all hard registers are used and clobbered at this 10310 point. */ 10311 emit_insn (gen_blockage ()); 10312 10313 DONE; 10314 }) 10315 10316 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 10317 ;; all of memory. This blocks insns from being moved across this point. 10318 10319 (define_insn "blockage" 10320 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 10321 "" 10322 "" 10323 [(set_attr "type" "none") 10324 (set_attr "length" "0")]) 10325 10326 ; 10327 ; sibcall patterns 10328 ; 10329 10330 (define_expand "sibcall" 10331 [(call (match_operand 0 "" "") 10332 (match_operand 1 "" ""))] 10333 "" 10334 { 10335 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); 10336 DONE; 10337 }) 10338 10339 (define_insn "*sibcall_br" 10340 [(call (mem:QI (reg SIBCALL_REGNUM)) 10341 (match_operand 0 "const_int_operand" "n"))] 10342 "SIBLING_CALL_P (insn) 10343 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" 10344 { 10345 if (TARGET_INDIRECT_BRANCH_NOBP_CALL) 10346 { 10347 gcc_assert (TARGET_CPU_Z10); 10348 s390_indirect_branch_via_thunk (SIBCALL_REGNUM, 10349 INVALID_REGNUM, 10350 NULL_RTX, 10351 s390_indirect_branch_type_call); 10352 return ""; 10353 } 10354 else 10355 return "br\t%%r1"; 10356 } 10357 [(set (attr "op_type") 10358 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10359 (const_string "RIL") 10360 (const_string "RR"))) 10361 (set (attr "mnemonic") 10362 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10363 (const_string "jg") 10364 (const_string "br"))) 10365 (set_attr "type" "branch") 10366 (set_attr "atype" "agen")]) 10367 10368 (define_insn "*sibcall_brc" 10369 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10370 (match_operand 1 "const_int_operand" "n"))] 10371 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" 10372 "j\t%0%K0" 10373 [(set_attr "op_type" "RI") 10374 (set_attr "type" "branch")]) 10375 10376 (define_insn "*sibcall_brcl" 10377 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10378 (match_operand 1 "const_int_operand" "n"))] 10379 "SIBLING_CALL_P (insn)" 10380 "jg\t%0%K0" 10381 [(set_attr "op_type" "RIL") 10382 (set_attr "type" "branch")]) 10383 10384 ; 10385 ; sibcall_value patterns 10386 ; 10387 10388 (define_expand "sibcall_value" 10389 [(set (match_operand 0 "" "") 10390 (call (match_operand 1 "" "") 10391 (match_operand 2 "" "")))] 10392 "" 10393 { 10394 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); 10395 DONE; 10396 }) 10397 10398 (define_insn "*sibcall_value_br" 10399 [(set (match_operand 0 "" "") 10400 (call (mem:QI (reg SIBCALL_REGNUM)) 10401 (match_operand 1 "const_int_operand" "n")))] 10402 "SIBLING_CALL_P (insn) 10403 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" 10404 { 10405 if (TARGET_INDIRECT_BRANCH_NOBP_CALL) 10406 { 10407 gcc_assert (TARGET_CPU_Z10); 10408 s390_indirect_branch_via_thunk (SIBCALL_REGNUM, 10409 INVALID_REGNUM, 10410 NULL_RTX, 10411 s390_indirect_branch_type_call); 10412 return ""; 10413 } 10414 else 10415 return "br\t%%r1"; 10416 } 10417 [(set (attr "op_type") 10418 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10419 (const_string "RIL") 10420 (const_string "RR"))) 10421 (set (attr "mnemonic") 10422 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") 10423 (const_string "jg") 10424 (const_string "br"))) 10425 (set_attr "type" "branch") 10426 (set_attr "atype" "agen")]) 10427 10428 (define_insn "*sibcall_value_brc" 10429 [(set (match_operand 0 "" "") 10430 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10431 (match_operand 2 "const_int_operand" "n")))] 10432 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" 10433 "j\t%1%K1" 10434 [(set_attr "op_type" "RI") 10435 (set_attr "type" "branch")]) 10436 10437 (define_insn "*sibcall_value_brcl" 10438 [(set (match_operand 0 "" "") 10439 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10440 (match_operand 2 "const_int_operand" "n")))] 10441 "SIBLING_CALL_P (insn)" 10442 "jg\t%1%K1" 10443 [(set_attr "op_type" "RIL") 10444 (set_attr "type" "branch")]) 10445 10446 10447 ; 10448 ; call instruction pattern(s). 10449 ; 10450 10451 (define_expand "call" 10452 [(call (match_operand 0 "" "") 10453 (match_operand 1 "" "")) 10454 (use (match_operand 2 "" ""))] 10455 "" 10456 { 10457 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, 10458 gen_rtx_REG (Pmode, RETURN_REGNUM)); 10459 DONE; 10460 }) 10461 10462 (define_insn "*bras" 10463 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10464 (match_operand 1 "const_int_operand" "n")) 10465 (clobber (match_operand 2 "register_operand" "=r"))] 10466 "!SIBLING_CALL_P (insn) 10467 && TARGET_SMALL_EXEC 10468 && GET_MODE (operands[2]) == Pmode" 10469 "bras\t%2,%0%K0" 10470 [(set_attr "op_type" "RI") 10471 (set_attr "type" "jsr") 10472 (set_attr "z196prop" "z196_cracked")]) 10473 10474 (define_insn "*brasl" 10475 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 10476 (match_operand 1 "const_int_operand" "n")) 10477 (clobber (match_operand 2 "register_operand" "=r"))] 10478 "!SIBLING_CALL_P (insn) 10479 10480 && GET_MODE (operands[2]) == Pmode" 10481 "brasl\t%2,%0%K0" 10482 [(set_attr "op_type" "RIL") 10483 (set_attr "type" "jsr") 10484 (set_attr "z196prop" "z196_cracked") 10485 (set_attr "relative_long" "yes")]) 10486 10487 (define_insn "*basr" 10488 [(call (mem:QI (match_operand 0 "address_operand" "ZR")) 10489 (match_operand 1 "const_int_operand" "n")) 10490 (clobber (match_operand 2 "register_operand" "=r"))] 10491 "!TARGET_INDIRECT_BRANCH_NOBP_CALL 10492 && !SIBLING_CALL_P (insn) 10493 && GET_MODE (operands[2]) == Pmode" 10494 { 10495 if (get_attr_op_type (insn) == OP_TYPE_RR) 10496 return "basr\t%2,%0"; 10497 else 10498 return "bas\t%2,%a0"; 10499 } 10500 [(set (attr "op_type") 10501 (if_then_else (match_operand 0 "register_operand" "") 10502 (const_string "RR") (const_string "RX"))) 10503 (set (attr "mnemonic") 10504 (if_then_else (match_operand 0 "register_operand" "") 10505 (const_string "basr") (const_string "bas"))) 10506 (set_attr "type" "jsr") 10507 (set_attr "atype" "agen") 10508 (set_attr "z196prop" "z196_cracked")]) 10509 10510 (define_insn "*basr_via_thunk<mode>_z10" 10511 [(call (mem:QI (match_operand:P 0 "register_operand" "a")) 10512 (match_operand 1 "const_int_operand" "n")) 10513 (clobber (match_operand:P 2 "register_operand" "=&r"))] 10514 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10515 && TARGET_CPU_Z10 10516 && !SIBLING_CALL_P (insn)" 10517 { 10518 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10519 REGNO (operands[2]), 10520 NULL_RTX, 10521 s390_indirect_branch_type_call); 10522 return ""; 10523 } 10524 [(set_attr "op_type" "RIL") 10525 (set_attr "mnemonic" "brasl") 10526 (set_attr "type" "jsr") 10527 (set_attr "atype" "agen") 10528 (set_attr "z196prop" "z196_cracked")]) 10529 10530 (define_insn "*basr_via_thunk<mode>" 10531 [(call (mem:QI (match_operand:P 0 "register_operand" "a")) 10532 (match_operand 1 "const_int_operand" "n")) 10533 (clobber (match_operand:P 2 "register_operand" "=&r")) 10534 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 10535 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10536 && !TARGET_CPU_Z10 10537 && !SIBLING_CALL_P (insn)" 10538 { 10539 s390_indirect_branch_via_thunk (REGNO (operands[0]), 10540 REGNO (operands[2]), 10541 NULL_RTX, 10542 s390_indirect_branch_type_call); 10543 return ""; 10544 } 10545 [(set_attr "op_type" "RIL") 10546 (set_attr "mnemonic" "brasl") 10547 (set_attr "type" "jsr") 10548 (set_attr "atype" "agen") 10549 (set_attr "z196prop" "z196_cracked")]) 10550 10551 ; 10552 ; call_value instruction pattern(s). 10553 ; 10554 10555 (define_expand "call_value" 10556 [(set (match_operand 0 "" "") 10557 (call (match_operand 1 "" "") 10558 (match_operand 2 "" ""))) 10559 (use (match_operand 3 "" ""))] 10560 "" 10561 { 10562 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], 10563 gen_rtx_REG (Pmode, RETURN_REGNUM)); 10564 DONE; 10565 }) 10566 10567 (define_insn "*bras_r" 10568 [(set (match_operand 0 "" "") 10569 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10570 (match_operand:SI 2 "const_int_operand" "n"))) 10571 (clobber (match_operand 3 "register_operand" "=r"))] 10572 "!SIBLING_CALL_P (insn) 10573 && TARGET_SMALL_EXEC 10574 && GET_MODE (operands[3]) == Pmode" 10575 "bras\t%3,%1%K1" 10576 [(set_attr "op_type" "RI") 10577 (set_attr "type" "jsr") 10578 (set_attr "z196prop" "z196_cracked")]) 10579 10580 (define_insn "*brasl_r" 10581 [(set (match_operand 0 "" "") 10582 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10583 (match_operand 2 "const_int_operand" "n"))) 10584 (clobber (match_operand 3 "register_operand" "=r"))] 10585 "!SIBLING_CALL_P (insn) 10586 10587 && GET_MODE (operands[3]) == Pmode" 10588 "brasl\t%3,%1%K1" 10589 [(set_attr "op_type" "RIL") 10590 (set_attr "type" "jsr") 10591 (set_attr "z196prop" "z196_cracked") 10592 (set_attr "relative_long" "yes")]) 10593 10594 (define_insn "*basr_r" 10595 [(set (match_operand 0 "" "") 10596 (call (mem:QI (match_operand 1 "address_operand" "ZR")) 10597 (match_operand 2 "const_int_operand" "n"))) 10598 (clobber (match_operand 3 "register_operand" "=r"))] 10599 "!TARGET_INDIRECT_BRANCH_NOBP_CALL 10600 && !SIBLING_CALL_P (insn) 10601 && GET_MODE (operands[3]) == Pmode" 10602 { 10603 if (get_attr_op_type (insn) == OP_TYPE_RR) 10604 return "basr\t%3,%1"; 10605 else 10606 return "bas\t%3,%a1"; 10607 } 10608 [(set (attr "op_type") 10609 (if_then_else (match_operand 1 "register_operand" "") 10610 (const_string "RR") (const_string "RX"))) 10611 (set (attr "mnemonic") 10612 (if_then_else (match_operand 1 "register_operand" "") 10613 (const_string "basr") (const_string "bas"))) 10614 (set_attr "type" "jsr") 10615 (set_attr "atype" "agen") 10616 (set_attr "z196prop" "z196_cracked")]) 10617 10618 (define_insn "*basr_r_via_thunk_z10" 10619 [(set (match_operand 0 "" "") 10620 (call (mem:QI (match_operand 1 "register_operand" "a")) 10621 (match_operand 2 "const_int_operand" "n"))) 10622 (clobber (match_operand 3 "register_operand" "=&r"))] 10623 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10624 && TARGET_CPU_Z10 10625 && !SIBLING_CALL_P (insn) 10626 && GET_MODE (operands[3]) == Pmode" 10627 { 10628 s390_indirect_branch_via_thunk (REGNO (operands[1]), 10629 REGNO (operands[3]), 10630 NULL_RTX, 10631 s390_indirect_branch_type_call); 10632 return ""; 10633 } 10634 [(set_attr "op_type" "RIL") 10635 (set_attr "mnemonic" "brasl") 10636 (set_attr "type" "jsr") 10637 (set_attr "atype" "agen") 10638 (set_attr "z196prop" "z196_cracked")]) 10639 10640 (define_insn "*basr_r_via_thunk" 10641 [(set (match_operand 0 "" "") 10642 (call (mem:QI (match_operand 1 "register_operand" "a")) 10643 (match_operand 2 "const_int_operand" "n"))) 10644 (clobber (match_operand 3 "register_operand" "=&r")) 10645 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 10646 "TARGET_INDIRECT_BRANCH_NOBP_CALL 10647 && !TARGET_CPU_Z10 10648 && !SIBLING_CALL_P (insn) 10649 && GET_MODE (operands[3]) == Pmode" 10650 { 10651 s390_indirect_branch_via_thunk (REGNO (operands[1]), 10652 REGNO (operands[3]), 10653 NULL_RTX, 10654 s390_indirect_branch_type_call); 10655 return ""; 10656 } 10657 [(set_attr "op_type" "RIL") 10658 (set_attr "mnemonic" "brasl") 10659 (set_attr "type" "jsr") 10660 (set_attr "atype" "agen") 10661 (set_attr "z196prop" "z196_cracked")]) 10662 10663 ;; 10664 ;;- Thread-local storage support. 10665 ;; 10666 10667 (define_expand "@get_thread_pointer<mode>" 10668 [(set (match_operand:P 0 "nonimmediate_operand" "") 10669 (unspec:P [(reg:P TP_REGNUM)] UNSPEC_GET_TP))] 10670 "" 10671 "") 10672 10673 (define_expand "set_thread_pointer<mode>" 10674 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) 10675 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] 10676 "" 10677 "") 10678 10679 (define_insn "*set_tp" 10680 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] 10681 "" 10682 "" 10683 [(set_attr "type" "none") 10684 (set_attr "length" "0")]) 10685 10686 (define_insn "*tls_load_64" 10687 [(set (match_operand:DI 0 "register_operand" "=d") 10688 (unspec:DI [(match_operand:DI 1 "memory_operand" "T") 10689 (match_operand:DI 2 "" "")] 10690 UNSPEC_TLS_LOAD))] 10691 "TARGET_64BIT" 10692 "lg\t%0,%1%J2" 10693 [(set_attr "op_type" "RXE") 10694 (set_attr "z10prop" "z10_fwd_A3")]) 10695 10696 (define_insn "*tls_load_31" 10697 [(set (match_operand:SI 0 "register_operand" "=d,d") 10698 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") 10699 (match_operand:SI 2 "" "")] 10700 UNSPEC_TLS_LOAD))] 10701 "!TARGET_64BIT" 10702 "@ 10703 l\t%0,%1%J2 10704 ly\t%0,%1%J2" 10705 [(set_attr "op_type" "RX,RXY") 10706 (set_attr "type" "load") 10707 (set_attr "cpu_facility" "*,longdisp") 10708 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) 10709 10710 (define_insn "*bras_tls" 10711 [(set (match_operand 0 "" "") 10712 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10713 (match_operand 2 "const_int_operand" "n"))) 10714 (clobber (match_operand 3 "register_operand" "=r")) 10715 (use (match_operand 4 "" ""))] 10716 "!SIBLING_CALL_P (insn) 10717 && TARGET_SMALL_EXEC 10718 && GET_MODE (operands[3]) == Pmode" 10719 "bras\t%3,%1%K1%J4" 10720 [(set_attr "op_type" "RI") 10721 (set_attr "type" "jsr") 10722 (set_attr "z196prop" "z196_cracked")]) 10723 10724 (define_insn "*brasl_tls" 10725 [(set (match_operand 0 "" "") 10726 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 10727 (match_operand 2 "const_int_operand" "n"))) 10728 (clobber (match_operand 3 "register_operand" "=r")) 10729 (use (match_operand 4 "" ""))] 10730 "!SIBLING_CALL_P (insn) 10731 10732 && GET_MODE (operands[3]) == Pmode" 10733 "brasl\t%3,%1%K1%J4" 10734 [(set_attr "op_type" "RIL") 10735 (set_attr "type" "jsr") 10736 (set_attr "z196prop" "z196_cracked") 10737 (set_attr "relative_long" "yes")]) 10738 10739 (define_insn "*basr_tls" 10740 [(set (match_operand 0 "" "") 10741 (call (mem:QI (match_operand 1 "address_operand" "ZR")) 10742 (match_operand 2 "const_int_operand" "n"))) 10743 (clobber (match_operand 3 "register_operand" "=r")) 10744 (use (match_operand 4 "" ""))] 10745 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" 10746 { 10747 if (get_attr_op_type (insn) == OP_TYPE_RR) 10748 return "basr\t%3,%1%J4"; 10749 else 10750 return "bas\t%3,%a1%J4"; 10751 } 10752 [(set (attr "op_type") 10753 (if_then_else (match_operand 1 "register_operand" "") 10754 (const_string "RR") (const_string "RX"))) 10755 (set_attr "type" "jsr") 10756 (set_attr "atype" "agen") 10757 (set_attr "z196prop" "z196_cracked")]) 10758 10759 ;; 10760 ;;- Atomic operations 10761 ;; 10762 10763 ; 10764 ; memory barrier patterns. 10765 ; 10766 10767 (define_expand "mem_thread_fence" 10768 [(match_operand:SI 0 "const_int_operand")] ;; model 10769 "" 10770 { 10771 /* Unless this is a SEQ_CST fence, the s390 memory model is strong 10772 enough not to require barriers of any kind. */ 10773 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) 10774 { 10775 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 10776 MEM_VOLATILE_P (mem) = 1; 10777 emit_insn (gen_mem_thread_fence_1 (mem)); 10778 } 10779 DONE; 10780 }) 10781 10782 ; Although bcr is superscalar on Z10, this variant will never 10783 ; become part of an execution group. 10784 ; With z196 we can make use of the fast-BCR-serialization facility. 10785 ; This allows for a slightly faster sync which is sufficient for our 10786 ; purposes. 10787 (define_insn "mem_thread_fence_1" 10788 [(set (match_operand:BLK 0 "" "") 10789 (unspec:BLK [(match_dup 0)] UNSPEC_MB))] 10790 "" 10791 { 10792 if (TARGET_Z196) 10793 return "bcr\t14,0"; 10794 else 10795 return "bcr\t15,0"; 10796 } 10797 [(set_attr "op_type" "RR") 10798 (set_attr "mnemonic" "bcr_flush") 10799 (set_attr "z196prop" "z196_alone")]) 10800 10801 ; 10802 ; atomic load/store operations 10803 ; 10804 10805 ; Atomic loads need not examine the memory model at all. 10806 (define_expand "atomic_load<mode>" 10807 [(match_operand:DINT 0 "register_operand") ;; output 10808 (match_operand:DINT 1 "memory_operand") ;; memory 10809 (match_operand:SI 2 "const_int_operand")] ;; model 10810 "" 10811 { 10812 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) 10813 FAIL; 10814 10815 if (<MODE>mode == TImode) 10816 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); 10817 else if (<MODE>mode == DImode && !TARGET_ZARCH) 10818 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); 10819 else 10820 emit_move_insn (operands[0], operands[1]); 10821 DONE; 10822 }) 10823 10824 ; Different from movdi_31 in that we want no splitters. 10825 (define_insn "atomic_loaddi_1" 10826 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") 10827 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] 10828 UNSPEC_MOVA))] 10829 "!TARGET_ZARCH" 10830 "@ 10831 lm\t%0,%M0,%S1 10832 lmy\t%0,%M0,%S1 10833 ld\t%0,%1 10834 ldy\t%0,%1" 10835 [(set_attr "op_type" "RS,RSY,RS,RSY") 10836 (set_attr "cpu_facility" "*,longdisp,*,longdisp") 10837 (set_attr "type" "lm,lm,floaddf,floaddf")]) 10838 10839 (define_insn "atomic_loadti_1" 10840 [(set (match_operand:TI 0 "register_operand" "=r") 10841 (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] 10842 UNSPEC_MOVA))] 10843 "TARGET_ZARCH" 10844 "lpq\t%0,%1" 10845 [(set_attr "op_type" "RXY") 10846 (set_attr "type" "other")]) 10847 10848 ; Atomic stores must(?) enforce sequential consistency. 10849 (define_expand "atomic_store<mode>" 10850 [(match_operand:DINT 0 "memory_operand") ;; memory 10851 (match_operand:DINT 1 "register_operand") ;; input 10852 (match_operand:SI 2 "const_int_operand")] ;; model 10853 "" 10854 { 10855 enum memmodel model = memmodel_from_int (INTVAL (operands[2])); 10856 10857 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) 10858 FAIL; 10859 10860 if (<MODE>mode == TImode) 10861 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); 10862 else if (<MODE>mode == DImode && !TARGET_ZARCH) 10863 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); 10864 else 10865 emit_move_insn (operands[0], operands[1]); 10866 if (is_mm_seq_cst (model)) 10867 emit_insn (gen_mem_thread_fence (operands[2])); 10868 DONE; 10869 }) 10870 10871 ; Different from movdi_31 in that we want no splitters. 10872 (define_insn "atomic_storedi_1" 10873 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") 10874 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] 10875 UNSPEC_MOVA))] 10876 "!TARGET_ZARCH" 10877 "@ 10878 stm\t%1,%N1,%S0 10879 stmy\t%1,%N1,%S0 10880 std %1,%0 10881 stdy %1,%0" 10882 [(set_attr "op_type" "RS,RSY,RS,RSY") 10883 (set_attr "cpu_facility" "*,longdisp,*,longdisp") 10884 (set_attr "type" "stm,stm,fstoredf,fstoredf")]) 10885 10886 (define_insn "atomic_storeti_1" 10887 [(set (match_operand:TI 0 "memory_operand" "=T") 10888 (unspec:TI [(match_operand:TI 1 "register_operand" "r")] 10889 UNSPEC_MOVA))] 10890 "TARGET_ZARCH" 10891 "stpq\t%1,%0" 10892 [(set_attr "op_type" "RXY") 10893 (set_attr "type" "other")]) 10894 10895 ; 10896 ; compare and swap patterns. 10897 ; 10898 10899 (define_expand "atomic_compare_and_swap<mode>" 10900 [(match_operand:SI 0 "register_operand") ;; bool success output 10901 (match_operand:DINT 1 "nonimmediate_operand");; oldval output 10902 (match_operand:DINT 2 "s_operand") ;; memory 10903 (match_operand:DINT 3 "general_operand") ;; expected intput 10904 (match_operand:DINT 4 "general_operand") ;; newval intput 10905 (match_operand:SI 5 "const_int_operand") ;; is_weak 10906 (match_operand:SI 6 "const_int_operand") ;; success model 10907 (match_operand:SI 7 "const_int_operand")] ;; failure model 10908 "" 10909 { 10910 if (GET_MODE_BITSIZE (<MODE>mode) >= 16 10911 && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) 10912 FAIL; 10913 10914 s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], 10915 operands[3], operands[4], INTVAL (operands[5])); 10916 DONE;}) 10917 10918 (define_expand "atomic_compare_and_swap<mode>_internal" 10919 [(parallel 10920 [(set (match_operand:DGPR 0 "register_operand") 10921 (match_operand:DGPR 1 "s_operand")) 10922 (set (match_dup 1) 10923 (unspec_volatile:DGPR 10924 [(match_dup 1) 10925 (match_operand:DGPR 2 "register_operand") 10926 (match_operand:DGPR 3 "register_operand")] 10927 UNSPECV_CAS)) 10928 (set (match_operand 4 "cc_reg_operand") 10929 (match_dup 5))])] 10930 "GET_MODE (operands[4]) == CCZmode 10931 || GET_MODE (operands[4]) == CCZ1mode" 10932 { 10933 operands[5] 10934 = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); 10935 }) 10936 10937 ; cdsg, csg 10938 (define_insn "*atomic_compare_and_swap<mode>_1" 10939 [(set (match_operand:TDI 0 "register_operand" "=r") 10940 (match_operand:TDI 1 "nonsym_memory_operand" "+S")) 10941 (set (match_dup 1) 10942 (unspec_volatile:TDI 10943 [(match_dup 1) 10944 (match_operand:TDI 2 "register_operand" "0") 10945 (match_operand:TDI 3 "register_operand" "r")] 10946 UNSPECV_CAS)) 10947 (set (reg CC_REGNUM) 10948 (compare (match_dup 1) (match_dup 2)))] 10949 "TARGET_ZARCH 10950 && s390_match_ccmode (insn, CCZ1mode)" 10951 "c<td>sg\t%0,%3,%S1" 10952 [(set_attr "op_type" "RSY") 10953 (set_attr "type" "sem")]) 10954 10955 ; cds, cdsy 10956 (define_insn "*atomic_compare_and_swapdi_2" 10957 [(set (match_operand:DI 0 "register_operand" "=r,r") 10958 (match_operand:DI 1 "nonsym_memory_operand" "+Q,S")) 10959 (set (match_dup 1) 10960 (unspec_volatile:DI 10961 [(match_dup 1) 10962 (match_operand:DI 2 "register_operand" "0,0") 10963 (match_operand:DI 3 "register_operand" "r,r")] 10964 UNSPECV_CAS)) 10965 (set (reg CC_REGNUM) 10966 (compare (match_dup 1) (match_dup 2)))] 10967 "!TARGET_ZARCH 10968 && s390_match_ccmode (insn, CCZ1mode)" 10969 "@ 10970 cds\t%0,%3,%S1 10971 cdsy\t%0,%3,%S1" 10972 [(set_attr "op_type" "RS,RSY") 10973 (set_attr "cpu_facility" "*,longdisp") 10974 (set_attr "type" "sem")]) 10975 10976 ; cs, csy 10977 (define_insn "*atomic_compare_and_swapsi_3" 10978 [(set (match_operand:SI 0 "register_operand" "=r,r") 10979 (match_operand:SI 1 "nonsym_memory_operand" "+Q,S")) 10980 (set (match_dup 1) 10981 (unspec_volatile:SI 10982 [(match_dup 1) 10983 (match_operand:SI 2 "register_operand" "0,0") 10984 (match_operand:SI 3 "register_operand" "r,r")] 10985 UNSPECV_CAS)) 10986 (set (reg CC_REGNUM) 10987 (compare (match_dup 1) (match_dup 2)))] 10988 "s390_match_ccmode (insn, CCZ1mode)" 10989 "@ 10990 cs\t%0,%3,%S1 10991 csy\t%0,%3,%S1" 10992 [(set_attr "op_type" "RS,RSY") 10993 (set_attr "cpu_facility" "*,longdisp") 10994 (set_attr "type" "sem")]) 10995 10996 ; 10997 ; Other atomic instruction patterns. 10998 ; 10999 11000 ; z196 load and add, xor, or and and instructions 11001 11002 (define_expand "atomic_fetch_<atomic><mode>" 11003 [(match_operand:GPR 0 "register_operand") ;; val out 11004 (ATOMIC_Z196:GPR 11005 (match_operand:GPR 1 "memory_operand") ;; memory 11006 (match_operand:GPR 2 "register_operand")) ;; val in 11007 (match_operand:SI 3 "const_int_operand")] ;; model 11008 "TARGET_Z196" 11009 { 11010 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) 11011 FAIL; 11012 11013 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf 11014 (operands[0], operands[1], operands[2])); 11015 DONE; 11016 }) 11017 11018 ; lan, lang, lao, laog, lax, laxg, laa, laag 11019 (define_insn "atomic_fetch_<atomic><mode>_iaf" 11020 [(set (match_operand:GPR 0 "register_operand" "=d") 11021 (match_operand:GPR 1 "memory_operand" "+S")) 11022 (set (match_dup 1) 11023 (unspec_volatile:GPR 11024 [(ATOMIC_Z196:GPR (match_dup 1) 11025 (match_operand:GPR 2 "general_operand" "d"))] 11026 UNSPECV_ATOMIC_OP)) 11027 (clobber (reg:CC CC_REGNUM))] 11028 "TARGET_Z196" 11029 "la<noxa><g>\t%0,%2,%1" 11030 [(set_attr "op_type" "RSY") 11031 (set_attr "type" "sem")]) 11032 11033 ;; For SImode and larger, the optabs.cc code will do just fine in 11034 ;; expanding a compare-and-swap loop. For QI/HImode, we can do 11035 ;; better by expanding our own loop. 11036 11037 (define_expand "atomic_<atomic><mode>" 11038 [(ATOMIC:HQI 11039 (match_operand:HQI 0 "memory_operand") ;; memory 11040 (match_operand:HQI 1 "general_operand")) ;; val in 11041 (match_operand:SI 2 "const_int_operand")] ;; model 11042 "" 11043 { 11044 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], 11045 operands[1], false); 11046 DONE; 11047 }) 11048 11049 (define_expand "atomic_fetch_<atomic><mode>" 11050 [(match_operand:HQI 0 "register_operand") ;; val out 11051 (ATOMIC:HQI 11052 (match_operand:HQI 1 "memory_operand") ;; memory 11053 (match_operand:HQI 2 "general_operand")) ;; val in 11054 (match_operand:SI 3 "const_int_operand")] ;; model 11055 "" 11056 { 11057 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 11058 operands[2], false); 11059 DONE; 11060 }) 11061 11062 (define_expand "atomic_<atomic>_fetch<mode>" 11063 [(match_operand:HQI 0 "register_operand") ;; val out 11064 (ATOMIC:HQI 11065 (match_operand:HQI 1 "memory_operand") ;; memory 11066 (match_operand:HQI 2 "general_operand")) ;; val in 11067 (match_operand:SI 3 "const_int_operand")] ;; model 11068 "" 11069 { 11070 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 11071 operands[2], true); 11072 DONE; 11073 }) 11074 11075 ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code 11076 ;; generated by the middleend is not good. 11077 (define_expand "atomic_exchange<mode>" 11078 [(match_operand:DINT 0 "register_operand") ;; val out 11079 (match_operand:DINT 1 "s_operand") ;; memory 11080 (match_operand:DINT 2 "general_operand") ;; val in 11081 (match_operand:SI 3 "const_int_operand")] ;; model 11082 "" 11083 { 11084 if (<MODE>mode != QImode 11085 && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) 11086 FAIL; 11087 if (<MODE>mode == HImode || <MODE>mode == QImode) 11088 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], 11089 false); 11090 else if (<MODE>mode == SImode || TARGET_ZARCH) 11091 s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); 11092 else 11093 FAIL; 11094 DONE; 11095 }) 11096 11097 ;; 11098 ;;- Miscellaneous instructions. 11099 ;; 11100 11101 ; 11102 ; allocate stack instruction pattern(s). 11103 ; 11104 11105 (define_expand "allocate_stack" 11106 [(match_operand 0 "general_operand" "") 11107 (match_operand 1 "general_operand" "")] 11108 "TARGET_BACKCHAIN" 11109 { 11110 rtx temp = gen_reg_rtx (Pmode); 11111 11112 emit_move_insn (temp, s390_back_chain_rtx ()); 11113 11114 if (flag_stack_clash_protection) 11115 anti_adjust_stack_and_probe_stack_clash (operands[1]); 11116 else 11117 anti_adjust_stack (operands[1]); 11118 11119 emit_move_insn (s390_back_chain_rtx (), temp); 11120 11121 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 11122 DONE; 11123 }) 11124 11125 (define_expand "@probe_stack2<mode>" 11126 [(set (reg:CCZ CC_REGNUM) 11127 (compare:CCZ (reg:W 0) 11128 (match_operand:W 0 "memory_operand"))) 11129 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 11130 "") 11131 11132 (define_expand "probe_stack" 11133 [(match_operand 0 "memory_operand")] 11134 "" 11135 { 11136 emit_insn (gen_probe_stack2 (word_mode, operands[0])); 11137 DONE; 11138 }) 11139 11140 ; 11141 ; setjmp instruction pattern. 11142 ; 11143 11144 (define_expand "builtin_setjmp_receiver" 11145 [(match_operand 0 "" "")] 11146 "flag_pic" 11147 { 11148 emit_insn (s390_load_got ()); 11149 emit_use (pic_offset_table_rtx); 11150 DONE; 11151 }) 11152 11153 ;; These patterns say how to save and restore the stack pointer. We need not 11154 ;; save the stack pointer at function level since we are careful to 11155 ;; preserve the backchain. At block level, we have to restore the backchain 11156 ;; when we restore the stack pointer. 11157 ;; 11158 ;; For nonlocal gotos, we must save both the stack pointer and its 11159 ;; backchain and restore both. Note that in the nonlocal case, the 11160 ;; save area is a memory location. 11161 11162 (define_expand "save_stack_function" 11163 [(match_operand 0 "general_operand" "") 11164 (match_operand 1 "general_operand" "")] 11165 "" 11166 "DONE;") 11167 11168 (define_expand "restore_stack_function" 11169 [(match_operand 0 "general_operand" "") 11170 (match_operand 1 "general_operand" "")] 11171 "" 11172 "DONE;") 11173 11174 (define_expand "restore_stack_block" 11175 [(match_operand 0 "register_operand" "") 11176 (match_operand 1 "register_operand" "")] 11177 "TARGET_BACKCHAIN" 11178 { 11179 rtx temp = gen_reg_rtx (Pmode); 11180 11181 emit_move_insn (temp, s390_back_chain_rtx ()); 11182 emit_move_insn (operands[0], operands[1]); 11183 emit_move_insn (s390_back_chain_rtx (), temp); 11184 11185 DONE; 11186 }) 11187 11188 (define_expand "save_stack_nonlocal" 11189 [(match_operand 0 "memory_operand" "") 11190 (match_operand 1 "register_operand" "")] 11191 "" 11192 { 11193 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 11194 11195 /* Copy the backchain to the first word, sp to the second and the 11196 literal pool base to the third. */ 11197 11198 rtx save_bc = adjust_address (operands[0], Pmode, 0); 11199 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); 11200 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); 11201 11202 if (TARGET_BACKCHAIN) 11203 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); 11204 11205 emit_move_insn (save_sp, operands[1]); 11206 emit_move_insn (save_bp, base); 11207 11208 DONE; 11209 }) 11210 11211 (define_expand "restore_stack_nonlocal" 11212 [(match_operand 0 "register_operand" "") 11213 (match_operand 1 "memory_operand" "")] 11214 "" 11215 { 11216 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 11217 rtx temp = NULL_RTX; 11218 11219 /* Restore the backchain from the first word, sp from the second and the 11220 literal pool base from the third. */ 11221 11222 rtx save_bc = adjust_address (operands[1], Pmode, 0); 11223 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); 11224 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); 11225 11226 if (TARGET_BACKCHAIN) 11227 temp = force_reg (Pmode, save_bc); 11228 11229 emit_move_insn (base, save_bp); 11230 emit_move_insn (operands[0], save_sp); 11231 11232 if (temp) 11233 emit_move_insn (s390_back_chain_rtx (), temp); 11234 11235 emit_use (base); 11236 DONE; 11237 }) 11238 11239 (define_expand "exception_receiver" 11240 [(const_int 0)] 11241 "" 11242 { 11243 s390_set_has_landing_pad_p (true); 11244 DONE; 11245 }) 11246 11247 ; 11248 ; nop instruction pattern(s). 11249 ; 11250 11251 (define_insn "nop" 11252 [(const_int 0)] 11253 "" 11254 "nopr\t%%r0" 11255 [(set_attr "op_type" "RR")]) 11256 11257 ; non-branch NOPs required for optimizing compare-and-branch patterns 11258 ; on z10 11259 11260 (define_insn "nop_lr0" 11261 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] 11262 "" 11263 "lr\t0,0" 11264 [(set_attr "op_type" "RR") 11265 (set_attr "z10prop" "z10_fr_E1")]) 11266 11267 (define_insn "nop_lr1" 11268 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] 11269 "" 11270 "lr\t1,1" 11271 [(set_attr "op_type" "RR")]) 11272 11273 ;;- Undeletable nops (used for hotpatching) 11274 11275 (define_insn "nop_2_byte" 11276 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] 11277 "" 11278 "nopr\t%%r0" 11279 [(set_attr "op_type" "RR")]) 11280 11281 (define_insn "nop_4_byte" 11282 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] 11283 "" 11284 "nop\t0" 11285 [(set_attr "op_type" "RX")]) 11286 11287 (define_insn "nop_6_byte" 11288 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] 11289 "" 11290 "brcl\t0, 0" 11291 [(set_attr "op_type" "RIL") 11292 (set_attr "relative_long" "yes")]) 11293 11294 11295 ; 11296 ; Special literal pool access instruction pattern(s). 11297 ; 11298 11299 (define_insn "*pool_entry" 11300 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] 11301 UNSPECV_POOL_ENTRY)] 11302 "" 11303 { 11304 machine_mode mode = GET_MODE (PATTERN (insn)); 11305 unsigned int align = GET_MODE_BITSIZE (mode); 11306 s390_output_pool_entry (operands[0], mode, align); 11307 return ""; 11308 } 11309 [(set (attr "length") 11310 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) 11311 11312 (define_insn "pool_align" 11313 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 11314 UNSPECV_POOL_ALIGN)] 11315 "" 11316 ".align\t%0" 11317 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 11318 11319 (define_insn "pool_section_start" 11320 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] 11321 "" 11322 { 11323 switch_to_section (targetm.asm_out.function_rodata_section 11324 (current_function_decl, false)); 11325 return ""; 11326 } 11327 [(set_attr "length" "0")]) 11328 11329 (define_insn "pool_section_end" 11330 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] 11331 "" 11332 { 11333 switch_to_section (current_function_section ()); 11334 return ""; 11335 } 11336 [(set_attr "length" "0")]) 11337 11338 (define_insn "main_base_64" 11339 [(set (match_operand 0 "register_operand" "=a") 11340 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] 11341 "GET_MODE (operands[0]) == Pmode" 11342 "larl\t%0,%1%K1" 11343 [(set_attr "op_type" "RIL") 11344 (set_attr "type" "larl") 11345 (set_attr "z10prop" "z10_fwd_A1") 11346 (set_attr "relative_long" "yes")]) 11347 11348 (define_insn "main_pool" 11349 [(set (match_operand 0 "register_operand" "=a") 11350 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] 11351 "GET_MODE (operands[0]) == Pmode" 11352 { 11353 gcc_unreachable (); 11354 } 11355 [(set (attr "type") 11356 (const_string "larl"))]) 11357 11358 (define_insn "reload_base_64" 11359 [(set (match_operand 0 "register_operand" "=a") 11360 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] 11361 "GET_MODE (operands[0]) == Pmode" 11362 "larl\t%0,%1%K1" 11363 [(set_attr "op_type" "RIL") 11364 (set_attr "type" "larl") 11365 (set_attr "z10prop" "z10_fwd_A1")]) 11366 11367 (define_insn "pool" 11368 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] 11369 "" 11370 { 11371 gcc_unreachable (); 11372 } 11373 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 11374 11375 ;; 11376 ;; Insns related to generating the function prologue and epilogue. 11377 ;; 11378 11379 11380 (define_expand "prologue" 11381 [(use (const_int 0))] 11382 "" 11383 "s390_emit_prologue (); DONE;") 11384 11385 (define_expand "epilogue" 11386 [(use (const_int 1))] 11387 "" 11388 "s390_emit_epilogue (false); DONE;") 11389 11390 (define_expand "sibcall_epilogue" 11391 [(use (const_int 0))] 11392 "" 11393 "s390_emit_epilogue (true); DONE;") 11394 11395 ;; A direct return instruction, without using an epilogue. 11396 (define_insn "<code>" 11397 [(ANY_RETURN)] 11398 "s390_can_use_<code>_insn ()" 11399 { 11400 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 11401 { 11402 /* The target is always r14 so there is no clobber 11403 of r1 needed for pre z10 targets. */ 11404 s390_indirect_branch_via_thunk (RETURN_REGNUM, 11405 INVALID_REGNUM, 11406 NULL_RTX, 11407 s390_indirect_branch_type_return); 11408 return ""; 11409 } 11410 else 11411 return "br\t%%r14"; 11412 } 11413 [(set (attr "op_type") 11414 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11415 (const_string "RIL") 11416 (const_string "RR"))) 11417 (set (attr "mnemonic") 11418 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11419 (const_string "jg") 11420 (const_string "br"))) 11421 (set_attr "type" "jsr") 11422 (set_attr "atype" "agen")]) 11423 11424 11425 (define_expand "return_use" 11426 [(parallel 11427 [(return) 11428 (use (match_operand 0 "register_operand" "a"))])] 11429 "" 11430 { 11431 if (!TARGET_CPU_Z10 11432 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) 11433 { 11434 if (TARGET_64BIT) 11435 emit_jump_insn (gen_returndi_prez10 (operands[0])); 11436 else 11437 emit_jump_insn (gen_returnsi_prez10 (operands[0])); 11438 DONE; 11439 } 11440 }) 11441 11442 (define_insn "*return<mode>" 11443 [(return) 11444 (use (match_operand:P 0 "register_operand" "a"))] 11445 "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" 11446 { 11447 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 11448 { 11449 s390_indirect_branch_via_thunk (REGNO (operands[0]), 11450 INVALID_REGNUM, 11451 NULL_RTX, 11452 s390_indirect_branch_type_return); 11453 return ""; 11454 } 11455 else 11456 return "br\t%0"; 11457 } 11458 [(set (attr "op_type") 11459 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11460 (const_string "RIL") 11461 (const_string "RR"))) 11462 (set (attr "mnemonic") 11463 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11464 (const_string "jg") 11465 (const_string "br"))) 11466 (set_attr "type" "jsr") 11467 (set_attr "atype" "agen")]) 11468 11469 (define_insn "return<mode>_prez10" 11470 [(return) 11471 (use (match_operand:P 0 "register_operand" "a")) 11472 (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] 11473 "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" 11474 { 11475 if (TARGET_INDIRECT_BRANCH_NOBP_RET) 11476 { 11477 s390_indirect_branch_via_thunk (REGNO (operands[0]), 11478 INVALID_REGNUM, 11479 NULL_RTX, 11480 s390_indirect_branch_type_return); 11481 return ""; 11482 } 11483 else 11484 return "br\t%0"; 11485 } 11486 [(set (attr "op_type") 11487 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11488 (const_string "RIL") 11489 (const_string "RR"))) 11490 (set (attr "mnemonic") 11491 (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") 11492 (const_string "jg") 11493 (const_string "br"))) 11494 (set_attr "type" "jsr") 11495 (set_attr "atype" "agen")]) 11496 11497 11498 ;; Instruction definition to extend a 31-bit pointer into a 64-bit 11499 ;; pointer. This is used for compatibility. 11500 11501 (define_expand "ptr_extend" 11502 [(set (match_operand:DI 0 "register_operand" "=r") 11503 (match_operand:SI 1 "register_operand" "r"))] 11504 "TARGET_64BIT" 11505 { 11506 emit_insn (gen_anddi3 (operands[0], 11507 gen_lowpart (DImode, operands[1]), 11508 GEN_INT (0x7fffffff))); 11509 DONE; 11510 }) 11511 11512 ;; Instruction definition to expand eh_return macro to support 11513 ;; swapping in special linkage return addresses. 11514 11515 (define_expand "eh_return" 11516 [(use (match_operand 0 "register_operand" ""))] 11517 "TARGET_TPF" 11518 { 11519 s390_emit_tpf_eh_return (operands[0]); 11520 DONE; 11521 }) 11522 11523 ; 11524 ; Stack Protector Patterns 11525 ; 11526 11527 (define_expand "stack_protect_set" 11528 [(set (match_operand 0 "memory_operand" "") 11529 (match_operand 1 "memory_operand" ""))] 11530 "" 11531 { 11532 #ifdef TARGET_THREAD_SSP_OFFSET 11533 operands[1] 11534 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), 11535 GEN_INT (TARGET_THREAD_SSP_OFFSET))); 11536 #endif 11537 if (TARGET_64BIT) 11538 emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); 11539 else 11540 emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); 11541 11542 DONE; 11543 }) 11544 11545 (define_insn "stack_protect_set<mode>" 11546 [(set (match_operand:DSI 0 "memory_operand" "=Q") 11547 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] 11548 "" 11549 "mvc\t%O0(%G0,%R0),%S1" 11550 [(set_attr "op_type" "SS")]) 11551 11552 (define_expand "stack_protect_test" 11553 [(set (reg:CC CC_REGNUM) 11554 (compare (match_operand 0 "memory_operand" "") 11555 (match_operand 1 "memory_operand" ""))) 11556 (match_operand 2 "" "")] 11557 "" 11558 { 11559 rtx cc_reg, test; 11560 #ifdef TARGET_THREAD_SSP_OFFSET 11561 operands[1] 11562 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), 11563 GEN_INT (TARGET_THREAD_SSP_OFFSET))); 11564 #endif 11565 if (TARGET_64BIT) 11566 emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); 11567 else 11568 emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); 11569 11570 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); 11571 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); 11572 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); 11573 DONE; 11574 }) 11575 11576 (define_insn "stack_protect_test<mode>" 11577 [(set (reg:CCZ CC_REGNUM) 11578 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") 11579 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] 11580 "" 11581 "clc\t%O0(%G0,%R0),%S1" 11582 [(set_attr "op_type" "SS")]) 11583 11584 ; This is used in s390_emit_prologue in order to prevent insns 11585 ; adjusting the stack pointer to be moved over insns writing stack 11586 ; slots using a copy of the stack pointer in a different register. 11587 (define_insn "stack_tie" 11588 [(set (match_operand:BLK 0 "memory_operand" "+m") 11589 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] 11590 "" 11591 "" 11592 [(set_attr "length" "0")]) 11593 11594 11595 (define_insn "stack_restore_from_fpr" 11596 [(set (reg:DI STACK_REGNUM) 11597 (match_operand:DI 0 "register_operand" "f")) 11598 (clobber (mem:BLK (scratch)))] 11599 "TARGET_Z10" 11600 "lgdr\t%%r15,%0" 11601 [(set_attr "op_type" "RRE")]) 11602 11603 ; 11604 ; Data prefetch patterns 11605 ; 11606 11607 (define_insn "prefetch" 11608 [(prefetch (match_operand 0 "address_operand" "ZT,X") 11609 (match_operand:SI 1 "const_int_operand" " n,n") 11610 (match_operand:SI 2 "const_int_operand" " n,n"))] 11611 "TARGET_Z10" 11612 { 11613 switch (which_alternative) 11614 { 11615 case 0: 11616 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; 11617 case 1: 11618 if (larl_operand (operands[0], Pmode)) 11619 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; 11620 /* fallthrough */ 11621 default: 11622 11623 /* This might be reached for symbolic operands with an odd 11624 addend. We simply omit the prefetch for such rare cases. */ 11625 11626 return ""; 11627 } 11628 } 11629 [(set_attr "type" "load,larl") 11630 (set_attr "op_type" "RXY,RIL") 11631 (set_attr "z10prop" "z10_super") 11632 (set_attr "z196prop" "z196_alone") 11633 (set_attr "relative_long" "yes")]) 11634 11635 11636 ; 11637 ; Byte swap instructions 11638 ; 11639 11640 ; FIXME: There is also mvcin but we cannot use it since src and target 11641 ; may overlap. 11642 ; lrvr, lrv, strv, lrvgr, lrvg, strvg 11643 (define_insn "bswap<mode>2" 11644 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") 11645 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] 11646 "" 11647 "@ 11648 lrv<g>r\t%0,%1 11649 lrv<g>\t%0,%1 11650 strv<g>\t%1,%0" 11651 [(set_attr "type" "*,load,store") 11652 (set_attr "op_type" "RRE,RXY,RXY") 11653 (set_attr "z10prop" "z10_super")]) 11654 11655 (define_insn "bswaphi2" 11656 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") 11657 (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] 11658 "" 11659 "@ 11660 # 11661 lrvh\t%0,%1 11662 strvh\t%1,%0" 11663 [(set_attr "type" "*,load,store") 11664 (set_attr "op_type" "RRE,RXY,RXY") 11665 (set_attr "z10prop" "z10_super")]) 11666 11667 (define_split 11668 [(set (match_operand:HI 0 "register_operand" "") 11669 (bswap:HI (match_operand:HI 1 "register_operand" "")))] 11670 "" 11671 [(set (match_dup 2) (bswap:SI (match_dup 3))) 11672 (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] 11673 { 11674 operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); 11675 operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); 11676 }) 11677 11678 11679 ; 11680 ; Population count instruction 11681 ; 11682 11683 (define_insn "*popcountdi_z15_cc" 11684 [(set (reg CC_REGNUM) 11685 (compare (popcount:DI (match_operand:DI 1 "register_operand" "d")) 11686 (const_int 0))) 11687 (set (match_operand:DI 0 "register_operand" "=d") 11688 (match_dup 1))] 11689 "TARGET_Z15 && s390_match_ccmode (insn, CCTmode)" 11690 "popcnt\t%0,%1,8" 11691 [(set_attr "op_type" "RRF")]) 11692 11693 (define_insn "*popcountdi_z15_cconly" 11694 [(set (reg CC_REGNUM) 11695 (compare (popcount:DI (match_operand:DI 1 "register_operand" "d")) 11696 (const_int 0))) 11697 (clobber (match_scratch:DI 0 "=d"))] 11698 "TARGET_Z15 && s390_match_ccmode(insn, CCTmode)" 11699 "popcnt\t%0,%1,8" 11700 [(set_attr "op_type" "RRF")]) 11701 11702 (define_insn "*popcountdi_z15" 11703 [(set (match_operand:DI 0 "register_operand" "=d") 11704 (popcount:DI (match_operand:DI 1 "register_operand" "d"))) 11705 (clobber (reg:CC CC_REGNUM))] 11706 "TARGET_Z15" 11707 "popcnt\t%0,%1,8" 11708 [(set_attr "op_type" "RRF")]) 11709 11710 ; The pre-z15 popcount instruction counts the bits of op1 in 8 byte 11711 ; portions and stores the result in the corresponding bytes in op0. 11712 (define_insn "*popcount<mode>_z196" 11713 [(set (match_operand:INT 0 "register_operand" "=d") 11714 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) 11715 (clobber (reg:CC CC_REGNUM))] 11716 "TARGET_Z196" 11717 "popcnt\t%0,%1" 11718 [(set_attr "op_type" "RRE")]) 11719 11720 (define_expand "popcountdi2_z196" 11721 [; popcnt op0, op1 11722 (parallel [(set (match_operand:DI 0 "register_operand" "") 11723 (unspec:DI [(match_operand:DI 1 "register_operand")] 11724 UNSPEC_POPCNT)) 11725 (clobber (reg:CC CC_REGNUM))]) 11726 ; sllg op2, op0, 32 11727 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) 11728 ; agr op0, op2 11729 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 11730 (clobber (reg:CC CC_REGNUM))]) 11731 ; sllg op2, op0, 16 11732 (set (match_dup 2) 11733 (ashift:DI (match_dup 0) (const_int 16))) 11734 ; agr op0, op2 11735 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 11736 (clobber (reg:CC CC_REGNUM))]) 11737 ; sllg op2, op0, 8 11738 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) 11739 ; agr op0, op2 11740 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 11741 (clobber (reg:CC CC_REGNUM))]) 11742 ; srlg op0, op0, 56 11743 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] 11744 "TARGET_Z196" 11745 "operands[2] = gen_reg_rtx (DImode);") 11746 11747 (define_expand "popcountdi2" 11748 [(parallel 11749 [(set (match_operand:DI 0 "register_operand" "") 11750 (popcount:DI (match_operand:DI 1 "register_operand"))) 11751 (clobber (reg:CC CC_REGNUM))])] 11752 "TARGET_Z196" 11753 { 11754 if (!TARGET_Z15) 11755 { 11756 emit_insn (gen_popcountdi2_z196 (operands[0], operands[1])); 11757 DONE; 11758 } 11759 }) 11760 11761 (define_expand "popcountsi2_z196" 11762 [; popcnt op0, op1 11763 (parallel [(set (match_operand:SI 0 "register_operand" "") 11764 (unspec:SI [(match_operand:SI 1 "register_operand")] 11765 UNSPEC_POPCNT)) 11766 (clobber (reg:CC CC_REGNUM))]) 11767 ; sllk op2, op0, 16 11768 (set (match_dup 2) 11769 (ashift:SI (match_dup 0) (const_int 16))) 11770 ; ar op0, op2 11771 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 11772 (clobber (reg:CC CC_REGNUM))]) 11773 ; sllk op2, op0, 8 11774 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) 11775 ; ar op0, op2 11776 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 11777 (clobber (reg:CC CC_REGNUM))]) 11778 ; srl op0, op0, 24 11779 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] 11780 "TARGET_Z196" 11781 "operands[2] = gen_reg_rtx (SImode);") 11782 11783 ; popcount always counts on the full 64 bit. With the z196 version 11784 ; counting bits per byte we just ignore the upper 4 bytes. With the 11785 ; z15 version we have to zero out the upper 32 bits first. 11786 (define_expand "popcountsi2" 11787 [(set (match_dup 2) 11788 (zero_extend:DI (match_operand:SI 1 "register_operand"))) 11789 (parallel [(set (match_dup 3) (popcount:DI (match_dup 2))) 11790 (clobber (reg:CC CC_REGNUM))]) 11791 (set (match_operand:SI 0 "register_operand") 11792 (subreg:SI (match_dup 3) 4))] 11793 "TARGET_Z196" 11794 { 11795 if (!TARGET_Z15) 11796 { 11797 emit_insn (gen_popcountsi2_z196 (operands[0], operands[1])); 11798 DONE; 11799 } 11800 else 11801 { 11802 operands[2] = gen_reg_rtx (DImode); 11803 operands[3] = gen_reg_rtx (DImode); 11804 } 11805 }) 11806 11807 (define_expand "popcounthi2_z196" 11808 [; popcnt op2, op1 11809 (parallel [(set (match_dup 2) 11810 (unspec:HI [(match_operand:HI 1 "register_operand")] 11811 UNSPEC_POPCNT)) 11812 (clobber (reg:CC CC_REGNUM))]) 11813 ; lr op3, op2 11814 (set (match_dup 3) (subreg:SI (match_dup 2) 0)) 11815 ; srl op4, op3, 8 11816 (set (match_dup 4) (lshiftrt:SI (match_dup 3) (const_int 8))) 11817 ; ar op3, op4 11818 (parallel [(set (match_dup 3) (plus:SI (match_dup 3) (match_dup 4))) 11819 (clobber (reg:CC CC_REGNUM))]) 11820 ; llgc op0, op3 11821 (parallel [(set (match_operand:HI 0 "register_operand" "") 11822 (and:HI (subreg:HI (match_dup 3) 2) (const_int 255))) 11823 (clobber (reg:CC CC_REGNUM))])] 11824 "TARGET_Z196" 11825 { 11826 operands[2] = gen_reg_rtx (HImode); 11827 operands[3] = gen_reg_rtx (SImode); 11828 operands[4] = gen_reg_rtx (SImode); 11829 }) 11830 11831 (define_expand "popcounthi2" 11832 [(set (match_dup 2) 11833 (zero_extend:DI (match_operand:HI 1 "register_operand"))) 11834 (parallel [(set (match_dup 3) (popcount:DI (match_dup 2))) 11835 (clobber (reg:CC CC_REGNUM))]) 11836 (set (match_operand:HI 0 "register_operand") 11837 (subreg:HI (match_dup 3) 6))] 11838 "TARGET_Z196" 11839 { 11840 if (!TARGET_Z15) 11841 { 11842 emit_insn (gen_popcounthi2_z196 (operands[0], operands[1])); 11843 DONE; 11844 } 11845 else 11846 { 11847 operands[2] = gen_reg_rtx (DImode); 11848 operands[3] = gen_reg_rtx (DImode); 11849 } 11850 }) 11851 11852 ; For popcount on a single byte the old z196 style popcount 11853 ; instruction is ideal. Since it anyway does a byte-wise popcount we 11854 ; just use it instead of zero extending the QImode input to DImode and 11855 ; using the z15 popcount variant. 11856 (define_expand "popcountqi2" 11857 [; popcnt op0, op1 11858 (parallel [(set (match_operand:QI 0 "register_operand" "") 11859 (unspec:QI [(match_operand:QI 1 "register_operand")] 11860 UNSPEC_POPCNT)) 11861 (clobber (reg:CC CC_REGNUM))])] 11862 "TARGET_Z196" 11863 "") 11864 11865 ;; 11866 ;;- Copy sign instructions 11867 ;; 11868 11869 (define_insn "copysign<mode>3<tf_fpr>" 11870 [(set (match_operand:FP 0 "register_operand" "=f") 11871 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") 11872 (match_operand:FP 2 "register_operand" "f")] 11873 UNSPEC_COPYSIGN))] 11874 "TARGET_Z196" 11875 "cpsdr\t%0,%2,%1" 11876 [(set_attr "op_type" "RRF") 11877 (set_attr "type" "fsimp<type>")]) 11878 11879 11880 ;; 11881 ;;- Transactional execution instructions 11882 ;; 11883 11884 ; This splitter helps combine to make use of CC directly when 11885 ; comparing the integer result of a tbegin builtin with a constant. 11886 ; The unspec is already removed by canonicalize_comparison. So this 11887 ; splitters only job is to turn the PARALLEL into separate insns 11888 ; again. Unfortunately this only works with the very first cc/int 11889 ; compare since combine is not able to deal with data flow across 11890 ; basic block boundaries. 11891 11892 ; It needs to be an insn pattern as well since combine does not apply 11893 ; the splitter directly. Combine would only use it if it actually 11894 ; would reduce the number of instructions. 11895 (define_insn_and_split "*ccraw_to_int" 11896 [(set (pc) 11897 (if_then_else 11898 (match_operator 0 "s390_eqne_operator" 11899 [(reg:CCRAW CC_REGNUM) 11900 (match_operand 1 "const_int_operand" "")]) 11901 (label_ref (match_operand 2 "" "")) 11902 (pc))) 11903 (set (match_operand:SI 3 "register_operand" "=d") 11904 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] 11905 "" 11906 "#" 11907 "" 11908 [(set (match_dup 3) 11909 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) 11910 (set (pc) 11911 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) 11912 (label_ref (match_dup 2)) 11913 (pc)))] 11914 "") 11915 11916 ; Non-constrained transaction begin 11917 11918 (define_expand "tbegin" 11919 [(match_operand:SI 0 "register_operand" "") 11920 (match_operand:BLK 1 "memory_operand" "")] 11921 "TARGET_HTM" 11922 { 11923 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); 11924 DONE; 11925 }) 11926 11927 (define_expand "tbegin_nofloat" 11928 [(match_operand:SI 0 "register_operand" "") 11929 (match_operand:BLK 1 "memory_operand" "")] 11930 "TARGET_HTM" 11931 { 11932 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); 11933 DONE; 11934 }) 11935 11936 (define_expand "tbegin_retry" 11937 [(match_operand:SI 0 "register_operand" "") 11938 (match_operand:BLK 1 "memory_operand" "") 11939 (match_operand:SI 2 "general_operand" "")] 11940 "TARGET_HTM" 11941 { 11942 s390_expand_tbegin (operands[0], operands[1], operands[2], true); 11943 DONE; 11944 }) 11945 11946 (define_expand "tbegin_retry_nofloat" 11947 [(match_operand:SI 0 "register_operand" "") 11948 (match_operand:BLK 1 "memory_operand" "") 11949 (match_operand:SI 2 "general_operand" "")] 11950 "TARGET_HTM" 11951 { 11952 s390_expand_tbegin (operands[0], operands[1], operands[2], false); 11953 DONE; 11954 }) 11955 11956 ; Clobber VRs since they don't get restored 11957 (define_insn "tbegin_1_z13" 11958 [(set (reg:CCRAW CC_REGNUM) 11959 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 11960 UNSPECV_TBEGIN)) 11961 (set (match_operand:BLK 1 "memory_operand" "=Q") 11962 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) 11963 (clobber (reg:TI 16)) (clobber (reg:TI 38)) 11964 (clobber (reg:TI 17)) (clobber (reg:TI 39)) 11965 (clobber (reg:TI 18)) (clobber (reg:TI 40)) 11966 (clobber (reg:TI 19)) (clobber (reg:TI 41)) 11967 (clobber (reg:TI 20)) (clobber (reg:TI 42)) 11968 (clobber (reg:TI 21)) (clobber (reg:TI 43)) 11969 (clobber (reg:TI 22)) (clobber (reg:TI 44)) 11970 (clobber (reg:TI 23)) (clobber (reg:TI 45)) 11971 (clobber (reg:TI 24)) (clobber (reg:TI 46)) 11972 (clobber (reg:TI 25)) (clobber (reg:TI 47)) 11973 (clobber (reg:TI 26)) (clobber (reg:TI 48)) 11974 (clobber (reg:TI 27)) (clobber (reg:TI 49)) 11975 (clobber (reg:TI 28)) (clobber (reg:TI 50)) 11976 (clobber (reg:TI 29)) (clobber (reg:TI 51)) 11977 (clobber (reg:TI 30)) (clobber (reg:TI 52)) 11978 (clobber (reg:TI 31)) (clobber (reg:TI 53))] 11979 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is 11980 ; not supposed to be used for immediates (see genpreds.cc). 11981 "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 11982 "tbegin\t%1,%x0" 11983 [(set_attr "op_type" "SIL")]) 11984 11985 (define_insn "tbegin_1" 11986 [(set (reg:CCRAW CC_REGNUM) 11987 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 11988 UNSPECV_TBEGIN)) 11989 (set (match_operand:BLK 1 "memory_operand" "=Q") 11990 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) 11991 (clobber (reg:DF 16)) 11992 (clobber (reg:DF 17)) 11993 (clobber (reg:DF 18)) 11994 (clobber (reg:DF 19)) 11995 (clobber (reg:DF 20)) 11996 (clobber (reg:DF 21)) 11997 (clobber (reg:DF 22)) 11998 (clobber (reg:DF 23)) 11999 (clobber (reg:DF 24)) 12000 (clobber (reg:DF 25)) 12001 (clobber (reg:DF 26)) 12002 (clobber (reg:DF 27)) 12003 (clobber (reg:DF 28)) 12004 (clobber (reg:DF 29)) 12005 (clobber (reg:DF 30)) 12006 (clobber (reg:DF 31))] 12007 ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is 12008 ; not supposed to be used for immediates (see genpreds.cc). 12009 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 12010 "tbegin\t%1,%x0" 12011 [(set_attr "op_type" "SIL")]) 12012 12013 ; Same as above but without the FPR clobbers 12014 (define_insn "tbegin_nofloat_1" 12015 [(set (reg:CCRAW CC_REGNUM) 12016 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 12017 UNSPECV_TBEGIN)) 12018 (set (match_operand:BLK 1 "memory_operand" "=Q") 12019 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] 12020 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 12021 "tbegin\t%1,%x0" 12022 [(set_attr "op_type" "SIL")]) 12023 12024 12025 ; Constrained transaction begin 12026 12027 (define_expand "tbeginc" 12028 [(set (reg:CCRAW CC_REGNUM) 12029 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] 12030 UNSPECV_TBEGINC))] 12031 "TARGET_HTM" 12032 "") 12033 12034 (define_insn "*tbeginc_1" 12035 [(set (reg:CCRAW CC_REGNUM) 12036 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] 12037 UNSPECV_TBEGINC))] 12038 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 12039 "tbeginc\t0,%x0" 12040 [(set_attr "op_type" "SIL")]) 12041 12042 ; Transaction end 12043 12044 (define_expand "tend" 12045 [(set (reg:CCRAW CC_REGNUM) 12046 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) 12047 (set (match_operand:SI 0 "register_operand" "") 12048 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] 12049 "TARGET_HTM" 12050 "") 12051 12052 (define_insn "*tend_1" 12053 [(set (reg:CCRAW CC_REGNUM) 12054 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] 12055 "TARGET_HTM" 12056 "tend" 12057 [(set_attr "op_type" "S")]) 12058 12059 ; Transaction abort 12060 12061 (define_expand "tabort" 12062 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] 12063 UNSPECV_TABORT)] 12064 "TARGET_HTM" 12065 { 12066 if (CONST_INT_P (operands[0]) 12067 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) 12068 { 12069 error ("invalid transaction abort code: %wd (values in range 0 " 12070 "through 255 are reserved)", INTVAL (operands[0])); 12071 FAIL; 12072 } 12073 }) 12074 12075 (define_insn "*tabort_1" 12076 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] 12077 UNSPECV_TABORT)] 12078 "TARGET_HTM" 12079 "tabort\t%Y0" 12080 [(set_attr "op_type" "S")]) 12081 12082 (define_insn "*tabort_1_plus" 12083 [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") 12084 (match_operand:SI 1 "const_int_operand" "J"))] 12085 UNSPECV_TABORT)] 12086 "TARGET_HTM && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" 12087 "tabort\t%1(%0)" 12088 [(set_attr "op_type" "S")]) 12089 12090 ; Transaction extract nesting depth 12091 12092 (define_insn "etnd" 12093 [(set (match_operand:SI 0 "register_operand" "=d") 12094 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] 12095 "TARGET_HTM" 12096 "etnd\t%0" 12097 [(set_attr "op_type" "RRE")]) 12098 12099 ; Non-transactional store 12100 12101 (define_insn "ntstg" 12102 [(set (match_operand:DI 0 "memory_operand" "=T") 12103 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] 12104 UNSPECV_NTSTG))] 12105 "TARGET_HTM" 12106 "ntstg\t%1,%0" 12107 [(set_attr "op_type" "RXY")]) 12108 12109 ; Transaction perform processor assist 12110 12111 (define_expand "tx_assist" 12112 [(unspec_volatile [(match_operand:SI 0 "register_operand" "") 12113 (reg:SI GPR0_REGNUM) 12114 (const_int PPA_TX_ABORT)] 12115 UNSPECV_PPA)] 12116 "TARGET_HTM" 12117 "") 12118 12119 (define_insn "*ppa" 12120 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") 12121 (match_operand:SI 1 "register_operand" "d") 12122 (match_operand 2 "const_int_operand" "I")] 12123 UNSPECV_PPA)] 12124 "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16" 12125 "ppa\t%0,%1,%2" 12126 [(set_attr "op_type" "RRF")]) 12127 12128 12129 ; Set and get floating point control register 12130 12131 (define_insn "sfpc" 12132 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] 12133 UNSPECV_SFPC)] 12134 "TARGET_HARD_FLOAT" 12135 "sfpc\t%0") 12136 12137 (define_insn "efpc" 12138 [(set (match_operand:SI 0 "register_operand" "=d") 12139 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] 12140 "TARGET_HARD_FLOAT" 12141 "efpc\t%0") 12142 12143 12144 ; Load count to block boundary 12145 12146 (define_insn "lcbb" 12147 [(set (match_operand:SI 0 "register_operand" "=d") 12148 (unspec:SI [(match_operand 1 "address_operand" "ZR") 12149 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) 12150 (clobber (reg:CC CC_REGNUM))] 12151 "TARGET_Z13" 12152 "lcbb\t%0,%a1,%b2" 12153 [(set_attr "op_type" "VRX")]) 12154 12155 ; Handle -fsplit-stack. 12156 12157 (define_expand "split_stack_prologue" 12158 [(const_int 0)] 12159 "" 12160 { 12161 s390_expand_split_stack_prologue (); 12162 DONE; 12163 }) 12164 12165 ;; If there are operand 0 bytes available on the stack, jump to 12166 ;; operand 1. 12167 12168 (define_expand "split_stack_space_check" 12169 [(set (pc) (if_then_else 12170 (ltu (minus (reg 15) 12171 (match_operand 0 "register_operand")) 12172 (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) 12173 (label_ref (match_operand 1)) 12174 (pc)))] 12175 "" 12176 { 12177 /* Offset from thread pointer to __private_ss. */ 12178 int psso = TARGET_64BIT ? 0x38 : 0x20; 12179 rtx tp = s390_get_thread_pointer (); 12180 rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); 12181 rtx reg = gen_reg_rtx (Pmode); 12182 rtx cc; 12183 if (TARGET_64BIT) 12184 emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); 12185 else 12186 emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); 12187 cc = s390_emit_compare (GT, reg, guard); 12188 s390_emit_jump (operands[1], cc); 12189 12190 DONE; 12191 }) 12192 12193 ;; Call to __morestack used by the split stack support 12194 12195 ; The insn has 3 parts: 12196 ; 1. A jump to the call done label. The jump will be done as part of 12197 ; __morestack and will not be explicitly emitted to the insn stream. 12198 ; 2. The call of __morestack including a use for r1 which is supposed to 12199 ; point to the parameter block for __morestack. 12200 ; 3. 3 USES whose values together with the call done label will be 12201 ; used to emit the parameter block to the .rodata section. This 12202 ; needs to be tied into the same insn as 1. since the call done 12203 ; label is emitted also as part of the parm block. In order to 12204 ; allow the edge to the BB with the call done label to be 12205 ; redirected both need to make use of the same label_ref. 12206 12207 (define_insn "@split_stack_call<mode>" 12208 [(set (pc) (label_ref (match_operand 2 "" ""))) ; call done label 12209 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") 12210 (reg:P 1)] 12211 UNSPECV_SPLIT_STACK_CALL)) 12212 (use (label_ref (match_operand 1 "" "X"))) ; parm block label 12213 (use (match_operand 3 "const_int_operand" "X")) ; frame size 12214 (use (match_operand 4 "const_int_operand" "X"))] ; arg size 12215 "" 12216 { 12217 s390_output_split_stack_data (operands[1], operands[2], operands[3], operands[4]); 12218 return "jg\t%0%K0"; 12219 } 12220 [(set_attr "op_type" "RIL") 12221 (set_attr "type" "branch")]) 12222 12223 ; As above but with a conditional jump 12224 12225 (define_insn "@split_stack_cond_call<mode>" 12226 [(set (pc) 12227 (if_then_else 12228 (match_operand 5 "" "") ; condition 12229 (label_ref (match_operand 2 "" "")) ; call done label 12230 (pc))) 12231 (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") 12232 (reg:P 1)] 12233 UNSPECV_SPLIT_STACK_CALL)) 12234 (use (label_ref (match_operand 1 "" "X"))) ; parm block label 12235 (use (match_operand 3 "const_int_operand" "X")) ; frame size 12236 (use (match_operand 4 "const_int_operand" "X"))] ; arg size 12237 "" 12238 { 12239 s390_output_split_stack_data (operands[1], operands[2], operands[3], operands[4]); 12240 return "jg%C5\t%0"; 12241 } 12242 [(set_attr "op_type" "RIL") 12243 (set_attr "type" "branch")]) 12244 12245 12246 (define_insn "osc_break" 12247 [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] 12248 "" 12249 "bcr\t7,%%r0" 12250 [(set_attr "op_type" "RR")]) 12251 12252 (define_expand "speculation_barrier" 12253 [(unspec_volatile [(reg:SI GPR0_REGNUM) 12254 (reg:SI GPR0_REGNUM) 12255 (const_int PPA_OOO_BARRIER)] 12256 UNSPECV_PPA)] 12257 "TARGET_ZEC12" 12258 "") 12259 12260 (define_expand "rawmemchr<SINT:mode>" 12261 [(match_operand 0 "register_operand") 12262 (match_operand 1 "memory_operand") 12263 (match_operand:SINT 2 "const_int_operand")] 12264 "TARGET_VX" 12265 "s390_rawmemchr(<SINT:MODE>mode, operands[0], operands[1], operands[2]); DONE;") 12266
Indexes created Sat Jun 27 00:24:51 UTC 2026