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      1 ;; Scheduling description for Tilera TILEPro chip.
      2 ;; Copyright (C) 2011-2022 Free Software Foundation, Inc.
      3 ;; Contributed by Walter Lee (walt (a] tilera.com)
      4 ;;
      5 ;; This file is part of GCC.
      6 ;;
      7 ;; GCC is free software; you can redistribute it and/or modify it
      8 ;; under the terms of the GNU General Public License as published
      9 ;; by the Free Software Foundation; either version 3, or (at your
     10 ;; option) any later version.
     11 ;;
     12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
     13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     15 ;; License for more details.
     16 ;;
     17 ;; You should have received a copy of the GNU General Public License
     18 ;; along with GCC; see the file COPYING3.  If not see
     19 ;; <http://www.gnu.org/licenses/>.
     20 
     21 (define_automaton "tile")
     22 
     23 ; Make the scheduling automaton an ndfa.
     24 (automata_option "ndfa")
     25 
     26 ; Name the three pipes.
     27 (define_cpu_unit "X0" "tile")
     28 (define_cpu_unit "X1" "tile")
     29 (define_cpu_unit "Y0" "tile")
     30 (define_cpu_unit "Y1" "tile")
     31 (define_cpu_unit "Y2" "tile")
     32 
     33 (define_insn_reservation "X0" 1
     34   (eq_attr "type" "X0")
     35   "X0")
     36 
     37 (define_insn_reservation "X0_2cycle" 2
     38   (eq_attr "type" "X0_2cycle")
     39   "X0,nothing")
     40 
     41 (define_insn_reservation "X1" 1
     42   (eq_attr "type" "X1,X1_branch")
     43   "X1")
     44 
     45 (define_insn_reservation "X1_2cycle" 2
     46   (eq_attr "type" "X1_2cycle")
     47   "X1,nothing")
     48 
     49 (define_insn_reservation "X1_L2" 8
     50   (eq_attr "type" "X1_L2")
     51   "X1")
     52 
     53 (define_insn_reservation "X1_miss" 80
     54   (eq_attr "type" "X1_miss")
     55   "X1")
     56 
     57 (define_insn_reservation "X01" 1
     58   (eq_attr "type" "X01")
     59   "X0|X1")
     60 
     61 (define_insn_reservation "Y0" 1
     62   (eq_attr "type" "Y0")
     63   "Y0|X0")
     64 
     65 (define_insn_reservation "Y0_2cycle" 2
     66   (eq_attr "type" "Y0_2cycle")
     67   "Y0|X0,nothing")
     68 
     69 (define_insn_reservation "Y2" 1
     70   (eq_attr "type" "Y2")
     71   "Y2|X1")
     72 
     73 (define_insn_reservation "Y2_2cycle" 2
     74   (eq_attr "type" "Y2_2cycle")
     75   "Y2|X1,nothing")
     76 
     77 (define_insn_reservation "Y2_L2" 8
     78   (eq_attr "type" "Y2_L2")
     79   "Y2|X1")
     80 
     81 (define_insn_reservation "Y2_miss" 80
     82   (eq_attr "type" "Y2_miss")
     83   "Y2|X1")
     84 
     85 (define_insn_reservation "Y01" 1
     86   (eq_attr "type" "Y01")
     87   "Y0|Y1|X0|X1")
     88 
     89 (define_insn_reservation "nothing" 0
     90   (eq_attr "type" "nothing")
     91   "nothing")
     92 
     93 (define_insn_reservation "cannot_bundle" 1
     94   (eq_attr "type" "cannot_bundle")
     95   "X0+X1")
     96 
     97 (define_insn_reservation "cannot_bundle_3cycle" 3
     98   (eq_attr "type" "cannot_bundle_3cycle")
     99   "X0+X1")
    100 
    101 (define_insn_reservation "cannot_bundle_4cycle" 4
    102   (eq_attr "type" "cannot_bundle_4cycle")
    103   "X0+X1")
    104 
    105 
    106 ; A bundle must be in either X format or Y format.
    107 (exclusion_set "X0,X1" "Y0,Y1,Y2")
    108