Home | History | Annotate | Line # | Download | only in cpu 
      1 ; OpenRISC 1000 architecture.  -*- Scheme -*-
      2 ; Copyright 2000-2019 Free Software Foundation, Inc.
      3 ; Contributed for OR32 by Johan Rydberg, jrydberg (a] opencores.org
      4 ; Modified by Julius Baxter, juliusbaxter (a] gmail.com
      5 ; Modified by Peter Gavin, pgavin (a] gmail.com
      6 ; Modified by Andrey Bacherov, avbacherov (a] opencores.org
      7 ;
      8 ; This program is free software; you can redistribute it and/or modify
      9 ; it under the terms of the GNU General Public License as published by
     10 ; the Free Software Foundation; either version 3 of the License, or
     11 ; (at your option) any later version.
     12 ;
     13 ; This program is distributed in the hope that it will be useful,
     14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
     15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16 ; GNU General Public License for more details.
     17 ;
     18 ; You should have received a copy of the GNU General Public License
     19 ; along with this program; if not, see <http://www.gnu.org/licenses/>
     20 
     21 (include "simplify.inc")
     22 
     23 ; The OpenRISC family is a set of RISC microprocessor architectures with an
     24 ; emphasis on scalability and is targetted at embedded use.
     25 ; The CPU RTL development is a collaborative open source effort.
     26 ; http://opencores.org/or1k
     27 ; http://openrisc.net
     28 
     29 (define-arch
     30   (name or1k)
     31   (comment "OpenRISC 1000")
     32   (default-alignment aligned)
     33   (insn-lsb0? #t)
     34   (machs or32 or32nd)
     35   (isas openrisc)
     36 )
     37 
     38 ; Instruction set parameters.
     39 (define-isa
     40   ; Name of the ISA.
     41   (name openrisc)
     42   ; Base insturction length.  The insns are always 32 bits wide.
     43   (base-insn-bitsize 32)
     44   )
     45 
     46 (define-pmacro OR32-MACHS       or32,or32nd)
     47 (define-pmacro ORBIS-MACHS      or32,or32nd)
     48 (define-pmacro ORFPX32-MACHS    or32,or32nd)
     49 (define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
     50 
     51 (define-attr
     52   (for model)
     53   (type boolean)
     54   (name NO-DELAY-SLOT)
     55   (comment "does not have delay slots")
     56   )
     57 
     58 (if (keep-mach? (or32 or32nd))
     59     (begin
     60       (define-cpu
     61         (name or1k32bf)
     62         (comment "OpenRISC 1000 32-bit CPU family")
     63         (insn-endian big)
     64         (data-endian big)
     65         (word-bitsize 32)
     66         (file-transform "")
     67         )
     68 
     69       (define-mach
     70         (name or32)
     71         (comment "Generic OpenRISC 1000 32-bit CPU")
     72         (cpu or1k32bf)
     73         (bfd-name "or1k")
     74         )
     75 
     76       (define-mach
     77         (name or32nd)
     78         (comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot")
     79         (cpu or1k32bf)
     80         (bfd-name "or1knd")
     81         )
     82 
     83       ; OpenRISC 1200 - 32-bit or1k CPU implementation
     84       (define-model
     85         (name or1200) (comment "OpenRISC 1200 model")
     86         (attrs)
     87         (mach or32)
     88         (unit u-exec "Execution Unit" () 1 1 () () () ())
     89         )
     90 
     91       ; OpenRISC 1200 - 32-bit or1k CPU implementation
     92       (define-model
     93         (name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot")
     94         (attrs NO-DELAY-SLOT)
     95         (mach or32nd)
     96         (unit u-exec "Execution Unit" () 1 1 () () () ())
     97         )
     98       )
     99     )
    100 
    101 (include "or1kcommon.cpu")
    102 (include "or1korbis.cpu")
    103 (include "or1korfpx.cpu")
    104