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      1 /* Native-dependent code for GNU/Linux on LoongArch processors.
      2 
      3    Copyright (C) 2024 Free Software Foundation, Inc.
      4    Contributed by Loongson Ltd.
      5 
      6    This file is part of GDB.
      7 
      8    This program is free software; you can redistribute it and/or modify
      9    it under the terms of the GNU General Public License as published by
     10    the Free Software Foundation; either version 3 of the License, or
     11    (at your option) any later version.
     12 
     13    This program is distributed in the hope that it will be useful,
     14    but WITHOUT ANY WARRANTY; without even the implied warranty of
     15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     16    GNU General Public License for more details.
     17 
     18    You should have received a copy of the GNU General Public License
     19    along with this program.  If not, see <http://www.gnu.org/licenses/>. */
     20 
     21 #ifndef GDB_NAT_LOONGARCH_HW_POINT_H
     22 #define GDB_NAT_LOONGARCH_HW_POINT_H
     23 
     24 /* Macro definitions, data structures, and code for the hardware
     25    breakpoint and hardware watchpoint support follow.  We use the
     26    following abbreviations throughout the code:
     27 
     28    hw - hardware
     29    bp - breakpoint
     30    wp - watchpoint  */
     31 
     32 /* Maximum number of hardware breakpoint and watchpoint registers.
     33    Neither of these values may exceed the width of dr_changed_t
     34    measured in bits.  */
     35 
     36 #define LOONGARCH_HBP_MAX_NUM 8
     37 #define LOONGARCH_HWP_MAX_NUM 8
     38 
     39 
     40 /* The maximum length of a memory region that can be watched by one
     41    hardware watchpoint register.  */
     42 
     43 #define LOONGARCH_HWP_MAX_LEN_PER_REG 8
     44 #define CTRL_PLV3_ENABLE		0x10
     45 
     46 #define DR_CONTROL_ENABLED(ctrl)  ((ctrl & CTRL_PLV3_ENABLE) == CTRL_PLV3_ENABLE)
     47 
     48 /* Structure for managing the hardware breakpoint/watchpoint resources.
     49    DR_ADDR_* stores the address, DR_CTRL_* stores the control register
     50    content, and DR_REF_COUNT_* counts the numbers of references to the
     51    corresponding bp/wp, by which way the limited hardware resources
     52    are not wasted on duplicated bp/wp settings (though so far gdb has
     53    done a good job by not sending duplicated bp/wp requests).  */
     54 
     55 struct loongarch_debug_reg_state
     56 {
     57   /* hardware breakpoint */
     58   CORE_ADDR dr_addr_bp[LOONGARCH_HBP_MAX_NUM];
     59   unsigned int dr_ctrl_bp[LOONGARCH_HBP_MAX_NUM];
     60   unsigned int dr_ref_count_bp[LOONGARCH_HBP_MAX_NUM];
     61 
     62   /* hardware watchpoint */
     63   CORE_ADDR dr_addr_wp[LOONGARCH_HWP_MAX_NUM];
     64   unsigned int dr_ctrl_wp[LOONGARCH_HWP_MAX_NUM];
     65   unsigned int dr_ref_count_wp[LOONGARCH_HWP_MAX_NUM];
     66 };
     67 
     68 extern int loongarch_num_bp_regs;
     69 extern int loongarch_num_wp_regs;
     70 
     71 /* Invoked when IDXth breakpoint/watchpoint register pair needs to be
     72    updated.  */
     73 
     74 void loongarch_notify_debug_reg_change (ptid_t ptid, int is_watchpoint,
     75 				      unsigned int idx);
     76 
     77 
     78 int loongarch_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
     79 				 int len, int is_insert, ptid_t ptid,
     80 				 struct loongarch_debug_reg_state *state);
     81 
     82 int loongarch_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
     83 				 int len, int is_insert, ptid_t ptid,
     84 				 struct loongarch_debug_reg_state *state);
     85 
     86 /* Return TRUE if there are any hardware breakpoints.  If WATCHPOINT is TRUE,
     87    check hardware watchpoints instead.  */
     88 
     89 bool loongarch_any_set_debug_regs_state (loongarch_debug_reg_state *state,
     90 					 bool watchpoint);
     91 
     92 /* Print the values of the cached breakpoint/watchpoint registers.  */
     93 
     94 void loongarch_show_debug_reg_state (struct loongarch_debug_reg_state *state,
     95 				     const char *func, CORE_ADDR addr,
     96 				     int len, enum target_hw_bp_type type);
     97 
     98 /* Return true if we can watch a memory region that starts address
     99    ADDR and whose length is LEN in bytes.  */
    100 
    101 int loongarch_region_ok_for_watchpoint (CORE_ADDR addr, int len);
    102 
    103 #endif /* GDB_NAT_LOONGARCH_HW_POINT_H */
    104